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This aligns LLVM: https://llvm.org/docs/RISCVUsage.html --- bfd/elfxx-riscv.c | 5 +++++ gas/testsuite/gas/riscv/march-help.l | 1 + gas/testsuite/gas/riscv/sifive-insns.d | 3 ++- gas/testsuite/gas/riscv/sifive-insns.s | 6 ++++++ include/opcode/riscv-opc.h | 3 +++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 3 +++ 7 files changed, 21 insertions(+), 1 deletion(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index dfacb87eda0..c69a000a46e 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1470,6 +1470,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadzvamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xsfvcp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0}, + {"xsfcease", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2706,6 +2707,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xventanacondops"); case INSN_CLASS_XSFVCP: return riscv_subset_supports (rps, "xsfvcp"); + case INSN_CLASS_XSFCEASE: + return riscv_subset_supports (rps, "xsfcease"); default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); @@ -2960,6 +2963,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadvector"; case INSN_CLASS_XTHEADZVAMO: return "xtheadzvamo"; + case INSN_CLASS_XSFCEASE: + return _("xsfcease"); default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index c5754837e05..b30790bb980 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -121,3 +121,4 @@ All available -march extensions for RISC-V: xtheadzvamo 1.0 xventanacondops 1.0 xsfvcp 1.0 + xsfcease 1.0 diff --git a/gas/testsuite/gas/riscv/sifive-insns.d b/gas/testsuite/gas/riscv/sifive-insns.d index f7d63d1bce0..ad811c328cd 100644 --- a/gas/testsuite/gas/riscv/sifive-insns.d +++ b/gas/testsuite/gas/riscv/sifive-insns.d @@ -33,5 +33,6 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+ac25d05b[ ]+sf.vc.v.fvv[ ]+0x1,v0,v2,fa1 [ ]+[0-9a-f]+:[ ]+fc20805b[ ]+sf.vc.v.vvw[ ]+0x3,v0,v2,v1 [ ]+[0-9a-f]+:[ ]+fc25c05b[ ]+sf.vc.v.xvw[ ]+0x3,v0,v2,a1 -[ ]+[0-9a-f]+:[ ]+fc27b05b[ ]+sf.vc.v.ivw[ ]+0x3,v0,v2,15 +[ ]+[0-9a-f]+:[ ]+fc27b05b[ ]+sf.vc.v.ivw[ ]+0x3,v0,v2,15 [ ]+[0-9a-f]+:[ ]+fc25d05b[ ]+sf.vc.v.fvw[ ]+0x1,v0,v2,fa1 +[ ]+[0-9a-f]+:[ ]+30500073[ ]+sf.cease diff --git a/gas/testsuite/gas/riscv/sifive-insns.s b/gas/testsuite/gas/riscv/sifive-insns.s index d593692c5c0..cdf90c1b3ba 100644 --- a/gas/testsuite/gas/riscv/sifive-insns.s +++ b/gas/testsuite/gas/riscv/sifive-insns.s @@ -31,3 +31,9 @@ sf.vc.v.ivw 0x3, v0, v2, 15 sf.vc.v.fvw 0x1, v0, v2, fa1 .option pop + + # xscease + .option push + .option arch, +xsfcease1p0 + sf.cease + .option pop diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index ae14e14d427..d2d08c6526d 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3076,6 +3076,9 @@ #define MASK_SF_VC_FVW 0xfa00707f #define MATCH_SF_VC_V_FVW 0xf800505b #define MASK_SF_VC_V_FVW 0xfa00707f +/* Vendor-specific (SiFive) cease instruction. */ +#define MATCH_SF_CEASE 0x30500073 +#define MASK_SF_CEASE 0xffffffff /* Unprivileged Counter/Timers CSR addresses. */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 5f516a1026e..d6081caa0dd 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -505,6 +505,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADZVAMO, INSN_CLASS_XVENTANACONDOPS, INSN_CLASS_XSFVCP, + INSN_CLASS_XSFCEASE, }; /* This structure holds information for a particular instruction. */ diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 1ef4eaddf4d..01ced23d657 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -3041,6 +3041,9 @@ const struct riscv_opcode riscv_opcodes[] = {"sf.vc.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_FVW, MASK_SF_VC_FVW, match_opcode, 0 }, {"sf.vc.v.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S", MATCH_SF_VC_V_FVW, MASK_SF_VC_V_FVW, match_opcode, 0 }, +/* Vendor-specific (SiFive) cease instruction. */ +{"sf.cease", 0, INSN_CLASS_XSFCEASE, "", MATCH_SF_CEASE, MASK_SF_CEASE, match_opcode, 0 }, + /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} };