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UJL0ZVyu8aSRtrqmzCMygFD98gX8nMY4 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org From: Vladimir Mezentsev ChangeLog 2024-05-20 Vladimir Mezentsev * libcollector/collector.c: Use static initialization instead of memset. * libcollector/dispatcher.c: Likewise. * libcollector/hwprofile.c: Likewise. * libcollector/jprofile.c: Likewise. * libcollector/profile.c: Likewise. * libcollector/synctrace.c: Likewise. --- gprofng/libcollector/collector.c | 10 ++++----- gprofng/libcollector/dispatcher.c | 7 +++---- gprofng/libcollector/hwprofile.c | 12 +++++------ gprofng/libcollector/jprofile.c | 4 ++-- gprofng/libcollector/profile.c | 7 +++---- gprofng/libcollector/synctrace.c | 34 +++++++------------------------ 6 files changed, 24 insertions(+), 50 deletions(-) diff --git a/gprofng/libcollector/collector.c b/gprofng/libcollector/collector.c index 39529758600..3a8f27a719d 100644 --- a/gprofng/libcollector/collector.c +++ b/gprofng/libcollector/collector.c @@ -1344,10 +1344,9 @@ __collector_close_experiment () return; } - struct sigaction sa; - CALL_UTIL (memset)(&sa, 0, sizeof (struct sigaction)); + static struct sigaction sigaction_0 = {.sa_flags = SA_SIGINFO }; + struct sigaction sa = sigaction_0; sa.sa_sigaction = __collector_SIGCHLD_signal_handler; - sa.sa_flags = SA_SIGINFO; __collector_sigaction (SIGCHLD, &sa, &original_sigchld_sigaction); /* linetrace interposition takes care of unsetting Environment variables */ @@ -2319,7 +2318,6 @@ ovw_write () return 0; int fd; int res; - struct prusage usage; struct rusage rusage; hrtime_t hrt, delta; @@ -2335,9 +2333,9 @@ ovw_write () return ( hrt); } - CALL_UTIL (memset)(&usage, 0, sizeof (struct prusage)); + static struct prusage usage_0 = { .pr_count = 1 }; + struct prusage usage = usage_0; usage.pr_lwpid = getpid (); - usage.pr_count = 1; usage.pr_tstamp.tv_sec = hrt / NANOSEC; usage.pr_tstamp.tv_nsec = hrt % NANOSEC; usage.pr_create.tv_sec = starttime / NANOSEC; diff --git a/gprofng/libcollector/dispatcher.c b/gprofng/libcollector/dispatcher.c index d2a4ad0b60b..8b8ad77b5ee 100644 --- a/gprofng/libcollector/dispatcher.c +++ b/gprofng/libcollector/dispatcher.c @@ -109,6 +109,7 @@ enum DISPATCH_TST = 2 /* dispatcher installed, and enabled in testing mode */ }; +static struct sigaction sigaction_0; static int dispatch_mode = DISPATCH_NYI; /* controls SIGPROF dispatching */ static int itimer_period_requested = 0; /* dispatcher itimer period */ static int itimer_period_actual = 0; /* actual dispatcher itimer period */ @@ -263,8 +264,7 @@ __collector_sigprof_install () TprintfT (DBG_LT1, "dispatcher: __collector_ext_dispatcher_install() collector_sigprof_dispatcher already installed\n"); else { - struct sigaction c_act; - CALL_UTIL (memset)(&c_act, 0, sizeof c_act); + struct sigaction c_act = sigaction_0; sigemptyset (&c_act.sa_mask); sigaddset (&c_act.sa_mask, HWCFUNCS_SIGNAL); /* block SIGEMT delivery in handler */ c_act.sa_sigaction = collector_sigprof_dispatcher; @@ -358,8 +358,7 @@ void __collector_SIGDFL_handler (int sig) { /* remove our dispatcher, replacing it with the default disposition */ - struct sigaction act; - CALL_UTIL (memset)(&act, 0, sizeof (act)); + struct sigaction act = sigaction_0; act.sa_handler = SIG_DFL; if (__collector_sigaction (sig, &act, NULL)) { diff --git a/gprofng/libcollector/hwprofile.c b/gprofng/libcollector/hwprofile.c index 364c600968a..cfe0d84dc1e 100644 --- a/gprofng/libcollector/hwprofile.c +++ b/gprofng/libcollector/hwprofile.c @@ -32,7 +32,6 @@ #include #include "gp-defs.h" -#define _STRING_H 1 /* XXX MEZ: temporary workaround */ #include "hwcdrv.h" #include "collector_module.h" #include "gp-experiment.h" @@ -409,8 +408,8 @@ hwc_initialize_handlers (void) else { /* set our signal handler */ - struct sigaction c_act; - CALL_UTIL (memset)(&c_act, 0, sizeof c_act); + static struct sigaction c_act_0 = {.sa_flags = SA_RESTART | SA_SIGINFO}; + struct sigaction c_act = c_act_0; sigemptyset (&c_act.sa_mask); sigaddset (&c_act.sa_mask, SIGPROF); /* block SIGPROF delivery in handler */ /* XXXX should probably also block sample_sig & pause_sig */ @@ -531,8 +530,9 @@ collector_record_counter_internal (ucontext_t *ucp, int timecvt, uint64_t va, uint64_t latency, uint64_t data_source) { - MHwcntr_packet pckt; - CALL_UTIL (memset)(&pckt, 0, sizeof ( MHwcntr_packet)); + static MHwcntr_packet hwc_packet_0 = {.comm.type = HW_PCKT, + .comm.tsize = sizeof (Hwcntr_packet)}; + MHwcntr_packet pckt = hwc_packet_0; pckt.comm.tstamp = time; pckt.tag = tag; if (timecvt > 1) @@ -547,8 +547,6 @@ collector_record_counter_internal (ucontext_t *ucp, int timecvt, value *= timecvt; } pckt.interval = value; - pckt.comm.type = HW_PCKT; - pckt.comm.tsize = sizeof (Hwcntr_packet); TprintfT (DBG_LT4, "hwprofile: %llu sample %lld tag %u recorded\n", (unsigned long long) time, (long long) value, tag); if (ABS_memop == ABST_NOPC) diff --git a/gprofng/libcollector/jprofile.c b/gprofng/libcollector/jprofile.c index 2cabb1a08de..cd498bed0a3 100644 --- a/gprofng/libcollector/jprofile.c +++ b/gprofng/libcollector/jprofile.c @@ -361,8 +361,8 @@ JVM_OnLoad (JavaVM *vm, char *options, void *reserved) err = (*jvmti)->GetPotentialCapabilities (jvmti, &cpblts); if (err == JVMTI_ERROR_NONE) { - jvmtiCapabilities cpblts_set; - CALL_UTIL (memset)(&cpblts_set, 0, sizeof (cpblts_set)); + static jvmtiCapabilities cpblts_set_0; + jvmtiCapabilities cpblts_set = cpblts_set_0; /* Add only those capabilities that are among potential ones */ cpblts_set.can_get_source_file_name = cpblts.can_get_source_file_name; diff --git a/gprofng/libcollector/profile.c b/gprofng/libcollector/profile.c index 127fd6917bb..f6546235365 100644 --- a/gprofng/libcollector/profile.c +++ b/gprofng/libcollector/profile.c @@ -272,10 +272,9 @@ __collector_ext_profile_handler (siginfo_t *info, ucontext_t *context) CALL_UTIL (getcontext) (context); /* initialize dummy context */ SETFUNCTIONCONTEXT (context, &__collector_lost_profile_context); } - ClockPacket pckt; - CALL_UTIL (memset)(&pckt, 0, sizeof ( pckt)); - pckt.comm.tsize = sizeof ( pckt); - pckt.comm.type = CLOCK_TYPE; + static ClockPacket clock_pckt_0 = {.comm.type = CLOCK_TYPE, + .comm.tsize = sizeof (ClockPacket)}; + ClockPacket pckt = clock_pckt_0; pckt.lwp_id = __collector_lwp_self (); pckt.thr_id = __collector_thr_self (); pckt.cpu_id = CALL_UTIL (getcpuid)(); diff --git a/gprofng/libcollector/synctrace.c b/gprofng/libcollector/synctrace.c index a304188e396..2f3097fb4da 100644 --- a/gprofng/libcollector/synctrace.c +++ b/gprofng/libcollector/synctrace.c @@ -75,6 +75,7 @@ static unsigned sync_key = COLLECTOR_TSD_INVALID_KEY; static long sync_threshold = -1; /* calibrate the value */ static int init_thread_intf_started = 0; static int init_thread_intf_finished = 0; +static Sync_packet spacket_0 = { .comm.tsize = sizeof ( Sync_packet) }; #define CHCK_NREENTRANCE(x) (!sync_native || !sync_mode || ((x) = collector_interface->getKey( sync_key )) == NULL || (*(x) != 0)) #define RECHCK_NREENTRANCE(x) (!sync_native || !sync_mode || ((x) = collector_interface->getKey( sync_key )) == NULL || (*(x) == 0)) @@ -137,15 +138,6 @@ static int (*__real_pthread_cond_timedwait_2_0) (pthread_cond_t *restrict cond, pthread_mutex_t *restrict mutex, const struct timespec *restrict abstime) = NULL; - -static void -collector_memset (void *s, int c, size_t n) -{ - unsigned char *s1 = s; - while (n--) - *s1++ = (unsigned char) c; -} - void __collector_module_init (CollectorInterface *_collector_interface) { @@ -568,9 +560,7 @@ __collector_jsync_end (hrtime_t reqt, void *object) hrtime_t grnt = gethrtime (); if (grnt - reqt >= sync_threshold) { - Sync_packet spacket; - collector_memset (&spacket, 0, sizeof (Sync_packet)); - spacket.comm.tsize = sizeof (Sync_packet); + Sync_packet spacket = spacket_0; spacket.comm.tstamp = grnt; spacket.requested = reqt; spacket.objp = (intptr_t) object; @@ -600,9 +590,7 @@ gprofng_pthread_mutex_lock (int (real_func) (pthread_mutex_t *), hrtime_t grnt = gethrtime (); if (grnt - reqt >= sync_threshold) { - Sync_packet spacket; - collector_memset (&spacket, 0, sizeof (Sync_packet)); - spacket.comm.tsize = sizeof (Sync_packet); + Sync_packet spacket = spacket_0; spacket.comm.tstamp = grnt; spacket.requested = reqt; spacket.objp = (intptr_t) mp; @@ -647,9 +635,7 @@ gprofng_pthread_cond_wait (int(real_func) (pthread_cond_t *, pthread_mutex_t *), hrtime_t grnt = gethrtime (); if (grnt - reqt >= sync_threshold) { - Sync_packet spacket; - collector_memset (&spacket, 0, sizeof (Sync_packet)); - spacket.comm.tsize = sizeof (Sync_packet); + Sync_packet spacket = spacket_0; spacket.comm.tstamp = grnt; spacket.requested = reqt; spacket.objp = (intptr_t) mutex; @@ -697,9 +683,7 @@ gprofng_pthread_cond_timedwait (int(real_func) (pthread_cond_t *, hrtime_t grnt = gethrtime (); if (grnt - reqt >= sync_threshold) { - Sync_packet spacket; - collector_memset (&spacket, 0, sizeof (Sync_packet)); - spacket.comm.tsize = sizeof (Sync_packet); + Sync_packet spacket = spacket_0; spacket.comm.tstamp = grnt; spacket.requested = reqt; spacket.objp = (intptr_t) mutex; @@ -746,9 +730,7 @@ gprofng_pthread_join (int(real_func) (pthread_t, void **), hrtime_t grnt = gethrtime (); if (grnt - reqt >= sync_threshold) { - Sync_packet spacket; - collector_memset (&spacket, 0, sizeof (Sync_packet)); - spacket.comm.tsize = sizeof (Sync_packet); + Sync_packet spacket = spacket_0; spacket.comm.tstamp = grnt; spacket.requested = reqt; spacket.objp = (Vaddr_type) target_thread; @@ -793,9 +775,7 @@ gprofng_sem_wait (int (real_func) (sem_t *), sem_t *sp) hrtime_t grnt = gethrtime (); if (grnt - reqt >= sync_threshold) { - Sync_packet spacket; - collector_memset (&spacket, 0, sizeof (Sync_packet)); - spacket.comm.tsize = sizeof (Sync_packet); + Sync_packet spacket = spacket_0; spacket.comm.tstamp = grnt; spacket.requested = reqt; spacket.objp = (intptr_t) sp; From patchwork Tue May 21 02:27:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Mezentsev X-Patchwork-Id: 90506 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CD8213858C52 for ; Tue, 21 May 2024 02:28:30 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from 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W-W2r81FUd0eGLFsrA22dmekYqqbUHvz X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, UNWANTED_LANGUAGE_BODY, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org From: Vladimir Mezentsev ChangeLog 2024-05-20 Vladimir Mezentsev PR gprofng/31123 * common/hwctable.c: Remove hardware counter tables for Sparc machines. --- gprofng/common/hwctable.c | 1181 +------------------------------------ 1 file changed, 1 insertion(+), 1180 deletions(-) diff --git a/gprofng/common/hwctable.c b/gprofng/common/hwctable.c index 5dc8dde7d97..0b4800eadd8 100644 --- a/gprofng/common/hwctable.c +++ b/gprofng/common/hwctable.c @@ -30,10 +30,6 @@ /*---------------------------------------------------------------------------*/ /* compile options */ -#define DISALLOW_USI_USII_6357446 -/* Solaris 9/libcpc1 allows cpc_bind() to work on US-IIe processors, even - though this processor cannot generate profiling interrupts. */ - #define DISALLOW_PENTIUM_PRO_MMX_7007575 /* Solaris/libcpc2 defaults to "Pentium Pro with MMX, Pentium II" when it doesn't recognize an Intel processor. As a result, @@ -119,12 +115,6 @@ static const Hwcentry empty_ctr = {NULL, NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, {"cycles1", "cpu_clk_unhalted.ref_p", 1, NULL, PRELOAD( 910,MHZ), -(MHZ), ABST_NONE}, /*hidden*/ \ /* end of list */ -#define SPARC_CYCLES \ - {"usr_time","Cycles_user", SYSTIME_REGNOS, STXT("User CPU"), PRELOADS_75,1, ABST_NONE}, \ - {"sys_time","Cycles_user~system=1~user=0", SYSTIME_REGNOS, STXT("System CPU"), PRELOADS_75,1, ABST_NONE}, \ - /* end of list */ - - /* --- PERF_EVENTS "software" definitions --- */ #define PERF_EVENTS_SW_EVENT_ALIASES \ // none supported for now @@ -134,12 +124,7 @@ static const Hwcentry empty_ctr = {NULL, NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, /* end of list */ #endif -#define PERF_EVENTS_SW_EVENT_DEFS \ -// none supported for now -#if 0 - {"PERF_COUNT_SW_TASK_CLOCK", NULL, REGNO_ANY, NULL, PRELOADS_7, -(1000),ABST_NONE}, \ - /* end of list */ -#endif +#define PERF_EVENTS_SW_EVENT_DEFS /* * The PAPI descriptive strings used to be wrapped with STXT(), @@ -258,1136 +243,6 @@ static Hwcentry papi_generic_list[] = { {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} }; -static Hwcentry usIlist[] = { - {"cycles", "Cycle_cnt", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE}, - {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE}, - {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} -}; - -static Hwcentry usIIIlist[] = /* III, IIIi, IIIp. Note that some counters are processor-specific */{ - {"cycles", "Cycle_cnt", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE}, - {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE}, - {"icm", "IC_miss", REGNO_ANY, STXT ("I$ Misses"), PRELOADS_5, 0, ABST_NONE}, - {"dcrm", "DC_rd_miss", REGNO_ANY, STXT ("D$ Read Misses"), PRELOADS_5, 0, ABST_LOAD}, - {"dcwm", "DC_wr_miss", REGNO_ANY, STXT ("D$ Write Misses"), PRELOADS_5, 0, ABST_STORE}, - {"dcr", "DC_rd", REGNO_ANY, STXT ("D$ Read Refs"), PRELOADS_6, 0, ABST_LOAD}, - {"dcw", "DC_wr", REGNO_ANY, STXT ("D$ Write Refs"), PRELOADS_6, 0, ABST_STORE}, - {"ecref", "EC_ref", REGNO_ANY, STXT ("E$ Refs"), PRELOADS_6, 0, ABST_LDST}, - {"itlbm", "ITLB_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE}, - {"dtlbm", "DTLB_miss", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_5, 0, ABST_US_DTLBM}, - {"ecm", "EC_misses", REGNO_ANY, STXT ("E$ Misses"), PRELOADS_5, 0, ABST_LDST}, - {"ecrm", "EC_rd_miss", REGNO_ANY, STXT ("E$ Read Misses"), PRELOADS_5, 0, ABST_LOAD}, - {"ecml", "EC_miss_local", REGNO_ANY, STXT ("E$ Local Misses"), PRELOADS_5, 0, ABST_LDST}, - {"ecmr", "EC_miss_remote", REGNO_ANY, STXT ("E$ Remote Misses"), PRELOADS_5, 0, ABST_LDST}, - {"ecim", "EC_ic_miss", REGNO_ANY, STXT ("E$ Instr. Misses"), PRELOADS_5, 0, ABST_NONE}, - {"icstall", "Dispatch0_IC_miss", REGNO_ANY, STXT ("I$ Stall Cycles"), PRELOADS_6, 1, ABST_NONE}, - {"dcstall", "Re_DC_miss", REGNO_ANY, STXT ("D$ and E$ Stall Cycles"), PRELOADS_6, 1, ABST_LOAD}, - {"ecstall", "Re_EC_miss", REGNO_ANY, STXT ("E$ Stall Cycles"), PRELOADS_6, 1, ABST_LOAD}, - {"sqstall", "Rstall_storeQ", REGNO_ANY, STXT ("StoreQ Stall Cycles"), PRELOADS_6, 1, ABST_STORE}, - {"rawstall", "Re_RAW_miss", REGNO_ANY, STXT ("RAW Stall Cycles"), PRELOADS_6, 1, ABST_LOAD}, - {"dcmissov", "Re_DC_missovhd", REGNO_ANY, STXT ("DC Miss Ovhd"), PRELOADS_6, 1, ABST_LOAD}, - {"fpustall", "Re_FPU_bypass", REGNO_ANY, STXT ("FPU Stall Cycles"), PRELOADS_6, 1, ABST_NONE}, - {"fpusestall", "Rstall_FP_use", REGNO_ANY, STXT ("FPU Use Stall Cycles"), PRELOADS_6, 1, ABST_NONE}, - {"iustall", "Rstall_IU_use", REGNO_ANY, STXT ("IU Stall Cycles"), PRELOADS_6, 1, ABST_NONE}, - {"fpadd", "FA_pipe_completion", REGNO_ANY, STXT ("FP Adds"), PRELOADS_6, 0, ABST_NONE}, - {"fpmul", "FM_pipe_completion", REGNO_ANY, STXT ("FP Muls"), PRELOADS_6, 0, ABST_NONE}, - - /* explicit definitions of (hidden) entries for proper counters */ - /* Only counters that can be time converted, or are load-store need to be in this table */ - {"Cycle_cnt", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE}, - {"EC_miss_mtag_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST}, - {"DC_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"DC_wr_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"DC_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"DC_wr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"EC_ref", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST}, - {"EC_snoop_inv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/}, - {"EC_wb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"EC_wb_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"DTLB_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_US_DTLBM}, - {"EC_misses", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST}, - {"EC_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"PC_port0_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"EC_miss_local", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST}, - {"EC_miss_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST}, - {"EC_snoop_cb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/}, - {"WC_snoop_cb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/}, - {"WC_scrubbed", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"WC_wb_wo_read", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"PC_MS_misses", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"PC_soft_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"PC_hard_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"PC_port1_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"PC_snoop_inv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE /*?*/}, - {"SW_count_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_COUNT}, - {"SW_count_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_COUNT}, - {"Dispatch0_IC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Dispatch0_mispred", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Dispatch0_br_target", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Dispatch0_2nd_br", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Dispatch_rs_mispred", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Rstall_storeQ", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_STORE}, - {"Rstall_FP_use", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Rstall_IU_use", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"EC_write_hit_RTO", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"Re_RAW_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD}, - {"Re_DC_missovhd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD}, - {"Re_endian_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD}, - {"Re_FPU_bypass", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Re_DC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD}, - {"Re_EC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD}, - {"Re_PC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD}, - {"SI_snoop", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"SI_ciq_flow", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"SI_owned", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_msl_busy_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC}, - {"MC_mdb_overflow_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC}, - {"MC_page_close_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC}, - {"MC_reads_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_reads_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_reads_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_reads_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_writes_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_writes_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_writes_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_writes_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_stalls_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC}, - {"MC_stalls_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC}, - {"MC_stalls_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC}, - {"MC_stalls_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC}, - - /* additional (hidden) aliases, for convenience */ - {"cycles0", "Cycle_cnt", 0, NULL, PRELOADS_75, 1, ABST_NONE}, - {"cycles1", "Cycle_cnt", 1, NULL, PRELOADS_75, 1, ABST_NONE}, - {"insts0", "Instr_cnt", 0, NULL, PRELOADS_75, 0, ABST_NONE}, - {"insts1", "Instr_cnt", 1, NULL, PRELOADS_75, 0, ABST_NONE}, - {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} -}; - -static Hwcentry usIVplist[] = { - {"cycles", "Cycle_cnt", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE}, - {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE}, - {"icm", "IC_fill", REGNO_ANY, STXT ("I$ Misses"), PRELOADS_5, 0, ABST_NONE}, - {"dcrm", "DC_rd_miss", REGNO_ANY, STXT ("D$ Read Misses"), PRELOADS_5, 0, ABST_LOAD}, - {"dcwm", "DC_wr_miss", REGNO_ANY, STXT ("D$ Write Misses"), PRELOADS_5, 0, ABST_STORE}, - {"dcr", "DC_rd", REGNO_ANY, STXT ("D$ Read Refs"), PRELOADS_6, 0, ABST_LOAD}, - {"dcw", "DC_wr", REGNO_ANY, STXT ("D$ Write Refs"), PRELOADS_6, 0, ABST_STORE}, - {"itlbm", "ITLB_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE}, - {"dtlbm", "DTLB_miss", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_5, 0, ABST_US_DTLBM}, - {"l2ref", "L2_ref", REGNO_ANY, STXT ("L2$ Refs"), PRELOADS_5, 0, ABST_LDST}, - {"l2m", "L2_miss", REGNO_ANY, STXT ("L2$ Misses"), PRELOADS_5, 0, ABST_LDST}, - {"l2rm", "L2_rd_miss", REGNO_ANY, STXT ("L2$ Read Misses"), PRELOADS_5, 0, ABST_LOAD}, - {"l2im", "L2_IC_miss", REGNO_ANY, STXT ("L2$ Instr. Misses"), PRELOADS_5, 0, ABST_NONE}, - {"ecm", "L3_miss", REGNO_ANY, STXT ("E$ Misses"), PRELOADS_5, 0, ABST_LDST}, - {"ecrm", "L3_rd_miss", REGNO_ANY, STXT ("E$ Read Misses"), PRELOADS_5, 0, ABST_LOAD}, - {"ecml", "SSM_L3_miss_local", REGNO_ANY, STXT ("E$ Local Misses"), PRELOADS_5, 0, ABST_LDST}, - {"ecmr", "SSM_L3_miss_remote", REGNO_ANY, STXT ("E$ Remote Misses"), PRELOADS_5, 0, ABST_LDST}, - {"ecim", "L3_IC_miss", REGNO_ANY, STXT ("E$ Instr. Misses"), PRELOADS_5, 0, ABST_NONE}, - {"icstall", "Dispatch0_IC_miss", REGNO_ANY, STXT ("I$ Stall Cycles"), PRELOADS_6, 1, ABST_NONE}, - {"dcstall", "Re_DC_miss", REGNO_ANY, STXT ("D$ and E$ Stall Cycles"), PRELOADS_6, 1, ABST_LOAD}, - {"ecstall", "Re_L3_miss", REGNO_ANY, STXT ("E$ Stall Cycles"), PRELOADS_6, 1, ABST_LOAD}, - {"sqstall", "Rstall_storeQ", REGNO_ANY, STXT ("StoreQ Stall Cycles"), PRELOADS_6, 1, ABST_STORE}, - {"rawstall", "Re_RAW_miss", REGNO_ANY, STXT ("RAW Stall Cycles"), PRELOADS_6, 1, ABST_LOAD}, - {"dcmissov", "Re_DC_missovhd", REGNO_ANY, STXT ("DC Miss Ovhd"), PRELOADS_6, 1, ABST_LOAD}, - {"fpustall", "Re_FPU_bypass", REGNO_ANY, STXT ("FPU Stall Cycles"), PRELOADS_6, 1, ABST_NONE}, - {"fpusestall", "Rstall_FP_use", REGNO_ANY, STXT ("FPU Use Stall Cycles"), PRELOADS_6, 1, ABST_NONE}, - {"iustall", "Rstall_IU_use", REGNO_ANY, STXT ("IU Stall Cycles"), PRELOADS_6, 1, ABST_NONE}, - {"fpadd", "FA_pipe_completion", REGNO_ANY, STXT ("FP Adds"), PRELOADS_6, 0, ABST_NONE}, - {"fpmul", "FM_pipe_completion", REGNO_ANY, STXT ("FP Muls"), PRELOADS_6, 0, ABST_NONE}, - - /* explicit definitions of (hidden) entries for proper counters */ - /* Only counters that can be time converted, or are load-store need to be in this table */ - {"Cycle_cnt", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE}, - {"DC_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"DC_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"DC_wr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"DC_wr_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"DTLB_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_US_DTLBM}, - {"Dispatch0_2nd_br", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Dispatch0_IC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Dispatch0_other", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2L3_snoop_cb_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/}, - {"L2L3_snoop_inv_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/}, - {"L2_hit_I_state_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST /*?*/}, - {"L2_hit_other_half", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST}, - {"L2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST}, - {"L2_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"L2_ref", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST}, - {"L2_snoop_cb_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/}, - {"L2_snoop_inv_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/}, - {"L2_wb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"L2_wb_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"L2_write_hit_RTO", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"L2_write_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"L3_hit_I_state_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST}, - {"L3_hit_other_half", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST}, - {"L3_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST}, - {"L3_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"L3_wb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"L3_wb_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"L3_write_hit_RTO", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"L3_write_miss_RTO", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE}, - {"MC_reads_0_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_reads_1_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_reads_2_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_reads_3_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_stalls_0_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC}, - {"MC_stalls_1_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC}, - {"MC_stalls_2_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC}, - {"MC_stalls_3_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC}, - {"MC_writes_0_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_writes_1_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_writes_2_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"MC_writes_3_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - /*? {"PC_MS_misses", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, */ - {"PC_hard_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"PC_inv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE /*?*/}, - {"PC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"PC_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"PC_soft_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD}, - {"Re_DC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD}, - {"Re_DC_missovhd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD}, - {"Re_FPU_bypass", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Re_L2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD}, - {"Re_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD}, - {"Re_PFQ_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Re_RAW_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD}, - {"Rstall_FP_use", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Rstall_IU_use", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Rstall_storeQ", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_STORE}, - {"SI_RTO_src_data", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"SI_RTS_src_data", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"SI_ciq_flow_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC}, - {"SI_owned_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"SI_snoop_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC}, - {"ecml", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST}, - {"ecmr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST}, - {"SSM_L3_miss_local", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST /*?*/}, - {"SSM_L3_miss_mtag_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST /*?*/}, - {"SSM_L3_miss_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST /*?*/}, - {"SSM_L3_wb_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE /*?*/}, - {"SSM_new_transaction_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_TBD /*?*/}, - - /* additional (hidden) aliases, for convenience */ - {"cycles0", "Cycle_cnt", 0, NULL, PRELOADS_75, 1, ABST_NONE}, - {"cycles1", "Cycle_cnt", 1, NULL, PRELOADS_75, 1, ABST_NONE}, - {"insts0", "Instr_cnt", 0, NULL, PRELOADS_75, 0, ABST_NONE}, - {"insts1", "Instr_cnt", 1, NULL, PRELOADS_75, 0, ABST_NONE}, - {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} -}; - -static Hwcentry niagara1[] = - /* CPC_ULTRA_T1 , "UltraSPARC T1" */{ - {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE}, -#ifndef WORKAROUND_6231196_NIAGARA1_NO_CTR_0 /* since register 0 counter don't work XXX */ - {"icm", "IC_miss", REGNO_ANY, STXT ("I$ Misses"), PRELOADS_5, 0, ABST_NONE}, - {"itlbm", "ITLB_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE}, - {"ecim", "L2_imiss", REGNO_ANY, STXT ("E$ Instr. Misses"), PRELOADS_4, 0, ABST_NONE}, - {"dcm", "DC_miss", REGNO_ANY, STXT ("D$ Misses"), PRELOADS_5, 0, ABST_EXACT}, - {"dtlbm", "DTLB_miss", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_5, 0, ABST_EXACT}, - {"ecdm", "L2_dmiss_ld", REGNO_ANY, STXT ("E$ Data Misses"), PRELOADS_4, 0, ABST_EXACT}, - {"flops", "FP_instr_cnt", REGNO_ANY, STXT ("Floating-point Ops"), PRELOADS_6, 0, ABST_NONE}, - - /* explicit definitions of (hidden) entries for proper counters */ - /* Only counters that can be time converted, or are load-store need to be in this table */ - {"SB_full", NULL, REGNO_ANY, NULL, PRELOADS_6, 1, ABST_NONE}, - {"DC_miss", NULL, REGNO_ANY, NULL, PRELOADS_6, 0, ABST_EXACT}, - {"DTLB_miss", NULL, REGNO_ANY, NULL, PRELOADS_6, 0, ABST_EXACT}, - {"L2_dmiss_ld", NULL, REGNO_ANY, NULL, PRELOADS_6, 0, ABST_EXACT}, -#endif - - /* additional (hidden) aliases, for convenience */ - {"insts1", "Instr_cnt", 1, NULL, PRELOADS_75, 0, ABST_NONE}, - {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} -}; - -static Hwcentry niagara2[] = { - /* CPC_ULTRA_T2 , "UltraSPARC T2" */ - /* CPC_ULTRA_T2 , "UltraSPARC T2+" */ - {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE}, - {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT}, - {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_6, 0, ABST_EXACT}, - {"dcm", "DC_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_6, 0, ABST_EXACT}, - {"dtlbm", "DTLB_miss", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_6, 0, ABST_NONE}, - {"l2drm", "L2_dmiss_ld", REGNO_ANY, STXT ("L2 D-cache Read Misses (See Bug 15664448)"), PRELOADS_5, 0, ABST_EXACT}, - {"icm", "IC_miss", REGNO_ANY, STXT ("L1 I-cache Misses"), PRELOADS_5, 0, ABST_NONE}, - {"itlbm", "ITLB_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE}, - {"l2im", "L2_imiss", REGNO_ANY, STXT ("L2 I-cache Misses"), PRELOADS_4, 0, ABST_NONE}, - - /* explicit definitions of (hidden) entries for proper counters */ - /* Only counters that can be time converted, or are load-store need to be in this table */ - {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOADS_7, 0, ABST_EXACT}, - {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT}, - {"Atomics", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT}, - {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT}, - {"L2_dmiss_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT}, - {"DTLB_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE}, - {"DES_3DES_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"AES_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Kasumi_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"MD5_SHA-1_SHA-256_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"MA_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - /* additional (hidden) aliases, for convenience */ - {"insts1", "Instr_cnt", 1, NULL, PRELOADS_75, 0, ABST_NONE}, - {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} -}; - -static Hwcentry sparc_t4[] = { - // Identical to sparc_t5_m6 except for: l3m_spec - // when updating this table, also update sparc_t5_m6[] - // obsolete aliases marked with REGNO_INVALID (allows reading of older experiments) - {"l2l3dh", "DC_miss_L2_L3_hit_nospec", REGNO_INVALID, STXT ("L2 or L3 D-cache Hits"), PRELOADS_6, 0, ABST_EXACT}, // undercounts due to thread-hog issue - {"l3m", "DC_miss_remote_L3_hit_nospec~emask=0x6", REGNO_INVALID, STXT ("L3 D-cache Misses"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue - {"lmh", "DC_miss_local_hit_nospec", REGNO_INVALID, STXT ("Local Mem. Hits"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue - {"rmh", "DC_miss_remote_L3_hit_nospec", REGNO_INVALID, STXT ("Remote Mem. Hits"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue - {"pqs", "PQ_tag_wait", REGNO_INVALID, STXT ("Pick Queue Stalls"), PRELOADS_7, 1, ABST_NONE}, // old alias name - {"raw_stb", "RAW_hit_st_buf", REGNO_INVALID, STXT ("RAW Hazard in Store Buffer"), PRELOADS_55, 0, ABST_NONE}, // 11@full hit, 60@partial hit (in future, combine w/st_q) - {"raw_stq", "RAW_hit_st_q", REGNO_INVALID, STXT ("RAW Hazard in Store Queue"), PRELOADS_55, 0, ABST_NONE}, // 11@full hit, 60@partial hit (in future, combine w/st_buf) - {"sel_stalls", "Sel_0_ready", REGNO_INVALID, STXT ("Stalls Another Thread Selected"), PRELOADS_7, 1, ABST_NONE}, - {"icm", "IC_miss", REGNO_INVALID, STXT ("L1 I-Cache Misses"), PRELOADS_55, 0, ABST_NONE}, // 20@ l2/l3 hit (guess) - {"icm_stalls", "IC_miss", REGNO_INVALID, STXT ("L1 I-Cache Miss Est Stalls"), PRELOADS_55, 25, ABST_NONE}, // 25@ l2-20/l3-50 - - // current aliases - SPARC_CYCLES - {"cycles", "Cycles_user", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE}, - {"insts", "Instr_all", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE}, - {"c_stalls", "Commit_0", REGNO_ANY, STXT ("Stall Cycles"), PRELOADS_7, 1, ABST_NONE}, - {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT}, - {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_7, 0, ABST_EXACT}, - {"dcm", "DC_miss_nospec", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_EXACT}, - {"l3m_spec", "DC_miss_local_hit~emask=0x6", REGNO_ANY, STXT ("L3 D-cache Speculative Misses"), PRELOADS_5, 0, ABST_NONE, STXT ("Loads that speculatively missed local L3")}, // T4 encoding (430 lm, 690 rm) ~5 misses overlap on t5/pico_ile - // {"l3m_spec", "DC_miss_local_hit~emask=0x30", REGNO_ANY, STXT("L3 D-cache Speculative Misses"),PRELOADS_5,0, ABST_NONE, STXT("Loads that speculatively missed local L3")}, // T5/M6 encoding (430 lm, 690 rm) ~5 misses overlap on t5/pico_ile - {"lmh_spec", "DC_miss_local_hit", REGNO_ANY, STXT ("Local Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE}, - {"rmh_spec", "DC_miss_remote_L3_hit", REGNO_ANY, STXT ("Remote Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE}, - // - {"dtlbm", "DTLB_miss_asynch", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_55, 0, ABST_NONE}, // 10@l1 hit, 24@l2 hit, 60@l3 hit, 500@l3 miss, 5000@trap 0.001 events/cycle - {"dtlb_hwtw_stalls", "DTLB_HWTW_all", REGNO_ANY, STXT ("DTLB HWTW Est Stalls"), PRELOADS_55, 25, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss requiring a HW tablewalk")}, // l2-20, l3-50 - {"dtlb_trap_stalls", "DTLB_fill_trap", REGNO_ANY, STXT ("DTLB Trap Est Stalls"), PRELOADS_35, 5000, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss with HW tablewalk unsuccessful")}, // 5000@trap - {"rawhaz", "RAW_hit_st_q~emask=0xf", REGNO_ANY, STXT ("Read-after-write Hazards"), PRELOADS_55, 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write hazards)")}, - {"br_msp_stalls", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict Stalls"), PRELOADS_6, 24, ABST_NONE, STXT ("Estimated time stalled on Branch mispredictions")}, // 24@miss, %5 of branches is bad - {"br_msp", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict"), PRELOADS_6, 0, ABST_NONE}, // 24@miss, %5 of branches is bad - {"br_tkn", "Br_taken", REGNO_ANY, STXT ("Branch Taken"), PRELOADS_7, 0, ABST_NONE}, // 2 cycles minimum - {"br_ins", "Branches", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE}, // 24@miss, %5 of branches is bad - {"fgu", "Instr_FGU_crypto", REGNO_ANY, STXT ("FP/VIS/Crypto Instructions"), PRELOADS_7, 0, ABST_NONE}, // 1 cycle/event - - /* explicit definitions of (hidden) entries for proper counters */ - /* Counters that can be time converted, support memspace, or have a short_desc need to be in this table */ - - {"Sel_pipe_drain_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting with correct instructions when pipeline has to drain after branch misprediction")}, - {"Sel_0_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for various conditions to be resolved")}, - {"Sel_0_ready", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread was ready to have its instructions selected but another hardware thread was selected instead")}, - {"Sel_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that only 1 instruction or uop was selected")}, - {"Sel_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that 2 instructions or uops were selected")}, - - {"Pick_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Pick_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Pick_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Pick_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Pick_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"Branches", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Control transfer instructions completed, excluding trap-related transfers")}, - {"Instr_FGU_crypto", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("FP and VIS instructions completed by the Floating Point and Graphics Unit")}, - {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Load instructions completed")}, - {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Store instructions completed")}, - {"SPR_ring_ops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Specialized instructions that require internal use of SPR ring completed")}, - {"Instr_other", NULL, REGNO_ANY, NULL, PRELOAD (2, 4), 0, ABST_NONE, STXT ("Basic arithmetic and logical instructions completed")}, - {"Instr_all", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 0, ABST_NONE, STXT ("Total instructions completed")}, - - {"Br_taken", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branch instructions taken and completed")}, - {"Sw_count_intr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("SW Count instructions completed")}, - {"Atomics", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Atomic instructions, including CASA/XA, completed")}, - {"SW_prefetch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("PREFETCH and PREFETCHA instructions completed")}, - {"Block_ld_st", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Block load/store instructions completed")}, - - {"BTC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branches delayed a few extra cycles because branch target not found in Branch Target Cache")}, - - {"ITLB_fill_8KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 8K page")}, - {"ITLB_fill_64KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 64K page")}, - {"ITLB_fill_4MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 4M page")}, - {"ITLB_fill_256MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 256M page")}, - {"ITLB_fill_2GB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")}, - {"ITLB_fill_trap", NULL, REGNO_ANY, NULL, PRELOAD (1000, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk unsuccessful")}, - {"ITLB_miss_asynch", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk search done")}, - - {"Fetch_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_0_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"Instr_buffer_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"PQ_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"ROB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"ROB_LB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"ROB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"ROB_LB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"DTLB_miss_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"ITLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L2D")}, - {"ITLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L3 or neighbor L2D")}, - {"ITLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk missed all local caches")}, - {"DTLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L2D")}, - {"DTLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L3 or neighbor L2D")}, - {"DTLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk missed all local caches")}, - {"DTLB_HWTW_all", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss requiring HW tablewalk")}, - - {"DC_miss_L2_L3_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT}, - {"DC_miss_local_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_EXACT}, - {"DC_miss_remote_L3_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_EXACT}, - {"DC_miss_nospec", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT, STXT ("Loads that missed local L1D")}, - - {"DTLB_fill_8KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 8K page")}, - {"DTLB_fill_64KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 64K page")}, - {"DTLB_fill_4MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 4M page")}, - {"DTLB_fill_256MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 256M page")}, - {"DTLB_fill_2GB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")}, - {"DTLB_fill_trap", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk unsuccessful")}, - {"DTLB_miss_asynch", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk search done")}, - {"RAW_hit_st_buf", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) still in store buffer not yet committed")}, - {"RAW_hit_st_q", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) committed but in store queue not yet written to L2D")}, - - {"St_q_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"St_hit_L2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L2D")}, - {"St_hit_L3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L3")}, - - {"DC_miss_L2_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local L2D or L3")}, - {"DC_miss_local_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local memory")}, - {"DC_miss_remote_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit remote cache or remote memory")}, - {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed L1D")}, - - {"L2_pipe_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"Br_dir_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction was mispredicted")}, - {"Br_trg_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose target was mispredicted")}, - {"Br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction or target was mispredicted")}, - - {"Cycles_user", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 1, ABST_NONE, STXT ("Cycles hardware thread is active in specified mode(s)")}, - // - {"Commit_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from this hardware thread")}, - {"Commit_0_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from any hardware thread on this core")}, - {"Commit_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 uop commits from this hardware thread")}, - {"Commit_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 2 uops commit from this hardware thread")}, - {"Commit_1_or_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 or 2 uops commit from this hardware thread")}, - - /* additional (hidden) aliases, for convenience */ - {"cycles0", "Cycles_user", 0, NULL, PRELOADS_8, 1, ABST_NONE}, - {"cycles1", "Cycles_user", 1, NULL, PRELOADS_8, 1, ABST_NONE}, - {"insts0", "Instr_all", 0, NULL, PRELOADS_8, 0, ABST_NONE}, - {"insts1", "Instr_all", 1, NULL, PRELOADS_8, 0, ABST_NONE}, - {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} -}; - -static Hwcentry sparc_t5_m6[] = { - // Identical to sparc_t4 except for: l3m_spec - // when updating this table, also update sparc_t4[] - // obsolete aliases marked with REGNO_INVALID (allows reading of older experiments) - {"l2l3dh", "DC_miss_L2_L3_hit_nospec", REGNO_INVALID, STXT ("L2 or L3 D-cache Hits"), PRELOADS_6, 0, ABST_EXACT}, // undercounts due to thread-hog issue - {"l3m", "DC_miss_remote_L3_hit_nospec~emask=0x6", REGNO_INVALID, STXT ("L3 D-cache Misses"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue - {"lmh", "DC_miss_local_hit_nospec", REGNO_INVALID, STXT ("Local Mem. Hits"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue - {"rmh", "DC_miss_remote_L3_hit_nospec", REGNO_INVALID, STXT ("Remote Mem. Hits"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue - {"pqs", "PQ_tag_wait", REGNO_INVALID, STXT ("Pick Queue Stalls"), PRELOADS_7, 1, ABST_NONE}, // old alias name - {"raw_stb", "RAW_hit_st_buf", REGNO_INVALID, STXT ("RAW Hazard in Store Buffer"), PRELOADS_55, 0, ABST_NONE}, // 11@full hit, 60@partial hit (in future, combine w/st_q) - {"raw_stq", "RAW_hit_st_q", REGNO_INVALID, STXT ("RAW Hazard in Store Queue"), PRELOADS_55, 0, ABST_NONE}, // 11@full hit, 60@partial hit (in future, combine w/st_buf) - {"sel_stalls", "Sel_0_ready", REGNO_INVALID, STXT ("Stalls Another Thread Selected"), PRELOADS_7, 1, ABST_NONE}, - {"icm", "IC_miss", REGNO_INVALID, STXT ("L1 I-Cache Misses"), PRELOADS_55, 0, ABST_NONE}, // 20@ l2/l3 hit (guess) - {"icm_stalls", "IC_miss", REGNO_INVALID, STXT ("L1 I-Cache Miss Est Stalls"), PRELOADS_55, 25, ABST_NONE}, // 25@ l2-20/l3-50 - - // current aliases - SPARC_CYCLES - {"cycles", "Cycles_user", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE}, - {"insts", "Instr_all", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE}, - {"c_stalls", "Commit_0", REGNO_ANY, STXT ("Stall Cycles"), PRELOADS_7, 1, ABST_NONE}, - - {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT}, - {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_7, 0, ABST_EXACT}, - {"dcm", "DC_miss_nospec", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_EXACT}, - // {"l3m_spec", "DC_miss_local_hit~emask=0x6", REGNO_ANY, STXT("L3 D-cache Speculative Misses"),PRELOADS_5,0, ABST_NONE, STXT("Loads that speculatively missed local L3")}, // T4 encoding (430 lm, 690 rm) ~5 misses overlap on t5/pico_ile - {"l3m_spec", "DC_miss_local_hit~emask=0x30", REGNO_ANY, STXT ("L3 D-cache Speculative Misses"), PRELOADS_5, 0, ABST_NONE, STXT ("Loads that speculatively missed local L3")}, // T5/M6 encoding (430 lm, 690 rm) ~5 misses overlap on t5/pico_ile - {"lmh_spec", "DC_miss_local_hit", REGNO_ANY, STXT ("Local Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE}, - {"rmh_spec", "DC_miss_remote_L3_hit", REGNO_ANY, STXT ("Remote Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE}, - // - {"dtlbm", "DTLB_miss_asynch", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_55, 0, ABST_NONE}, // 10@l1 hit, 24@l2 hit, 60@l3 hit, 500@l3 miss, 5000@trap 0.001 events/cycle - {"dtlb_hwtw_stalls", "DTLB_HWTW_all", REGNO_ANY, STXT ("DTLB HWTW Est Stalls"), PRELOADS_55, 25, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss requiring a HW tablewalk")}, // l2-20, l3-50 - {"dtlb_trap_stalls", "DTLB_fill_trap", REGNO_ANY, STXT ("DTLB Trap Est Stalls"), PRELOADS_35, 5000, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss with HW tablewalk unsuccessful")}, // 5000@trap - {"rawhaz", "RAW_hit_st_q~emask=0xf", REGNO_ANY, STXT ("Read-after-write Hazards"), PRELOADS_55, 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write hazards)")}, - {"br_msp_stalls", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict Stalls"), PRELOADS_6, 24, ABST_NONE, STXT ("Estimated time stalled on Branch mispredictions")}, // 24@miss, %5 of branches is bad - {"br_msp", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict"), PRELOADS_6, 0, ABST_NONE}, // 24@miss, %5 of branches is bad - {"br_tkn", "Br_taken", REGNO_ANY, STXT ("Branch Taken"), PRELOADS_7, 0, ABST_NONE}, // 2 cycles minimum - {"br_ins", "Branches", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE}, // 24@miss, %5 of branches is bad - {"fgu", "Instr_FGU_crypto", REGNO_ANY, STXT ("FP/VIS/Crypto Instructions"), PRELOADS_7, 0, ABST_NONE}, // 1 cycle/event - - /* explicit definitions of (hidden) entries for proper counters */ - /* Counters that can be time converted, support memspace, or have a short_desc need to be in this table */ - - {"Sel_pipe_drain_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting with correct instructions when pipeline has to drain after branch misprediction")}, - {"Sel_0_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for various conditions to be resolved")}, - {"Sel_0_ready", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread was ready to have its instructions selected but another hardware thread was selected instead")}, - {"Sel_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that only 1 instruction or uop was selected")}, - {"Sel_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that 2 instructions or uops were selected")}, - - {"Pick_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Pick_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Pick_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Pick_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Pick_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"Branches", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Control transfer instructions completed, excluding trap-related transfers")}, - {"Instr_FGU_crypto", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("FP and VIS instructions completed by the Floating Point and Graphics Unit")}, - {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Load instructions completed")}, - {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Store instructions completed")}, - {"SPR_ring_ops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Specialized instructions that require internal use of SPR ring completed")}, - {"Instr_other", NULL, REGNO_ANY, NULL, PRELOAD (2, 4), 0, ABST_NONE, STXT ("Basic arithmetic and logical instructions completed")}, - {"Instr_all", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 0, ABST_NONE, STXT ("Total instructions completed")}, - - {"Br_taken", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branch instructions taken and completed")}, - {"Sw_count_intr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("SW Count instructions completed")}, - {"Atomics", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Atomic instructions, including CASA/XA, completed")}, - {"SW_prefetch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("PREFETCH and PREFETCHA instructions completed")}, - {"Block_ld_st", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Block load/store instructions completed")}, - - {"BTC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branches delayed a few extra cycles because branch target not found in Branch Target Cache")}, - - {"ITLB_fill_8KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 8K page")}, - {"ITLB_fill_64KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 64K page")}, - {"ITLB_fill_4MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 4M page")}, - {"ITLB_fill_256MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 256M page")}, - {"ITLB_fill_2GB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")}, - {"ITLB_fill_trap", NULL, REGNO_ANY, NULL, PRELOAD (1000, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk unsuccessful")}, - {"ITLB_miss_asynch", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk search done")}, - - {"Fetch_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_0_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"Instr_buffer_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"PQ_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"ROB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"ROB_LB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"ROB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"ROB_LB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"DTLB_miss_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"ITLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L2D")}, - {"ITLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L3 or neighbor L2D")}, - {"ITLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk missed all local caches")}, - {"DTLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L2D")}, - {"DTLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L3 or neighbor L2D")}, - {"DTLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk missed all local caches")}, - {"DTLB_HWTW_all", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss requiring HW tablewalk")}, - - {"DC_miss_L2_L3_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT}, - {"DC_miss_local_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_EXACT}, - {"DC_miss_remote_L3_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_EXACT}, - {"DC_miss_nospec", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT, STXT ("Loads that missed local L1D")}, - - {"DTLB_fill_8KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 8K page")}, - {"DTLB_fill_64KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 64K page")}, - {"DTLB_fill_4MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 4M page")}, - {"DTLB_fill_256MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 256M page")}, - {"DTLB_fill_2GB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")}, - {"DTLB_fill_trap", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk unsuccessful")}, - {"DTLB_miss_asynch", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk search done")}, - {"RAW_hit_st_buf", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) still in store buffer not yet committed")}, - {"RAW_hit_st_q", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) committed but in store queue not yet written to L2D")}, - - {"St_q_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"St_hit_L2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L2D")}, - {"St_hit_L3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L3")}, - - {"DC_miss_L2_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local L2D or L3")}, - {"DC_miss_local_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local memory")}, - {"DC_miss_remote_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit remote cache or remote memory")}, - {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed L1D")}, - - {"L2_pipe_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"Br_dir_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction was mispredicted")}, - {"Br_trg_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose target was mispredicted")}, - {"Br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction or target was mispredicted")}, - - {"Cycles_user", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 1, ABST_NONE, STXT ("Cycles hardware thread is active in specified mode(s)")}, - // - {"Commit_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from this hardware thread")}, - {"Commit_0_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from any hardware thread on this core")}, - {"Commit_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 uop commits from this hardware thread")}, - {"Commit_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 2 uops commit from this hardware thread")}, - {"Commit_1_or_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 or 2 uops commit from this hardware thread")}, - - /* additional (hidden) aliases, for convenience */ - {"cycles0", "Cycles_user", 0, NULL, PRELOADS_8, 1, ABST_NONE}, - {"cycles1", "Cycles_user", 1, NULL, PRELOADS_8, 1, ABST_NONE}, - {"insts0", "Instr_all", 0, NULL, PRELOADS_8, 0, ABST_NONE}, - {"insts1", "Instr_all", 1, NULL, PRELOADS_8, 0, ABST_NONE}, - {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} -}; - -static Hwcentry sparc_m7[] = { - // obsolete aliases marked with REGNO_INVALID (allows reading of older experiments) - {"icm", "IC_miss_commit", REGNO_INVALID, STXT ("L1 I-Cache Misses"), PRELOADS_6, 0, ABST_EXACT}, - {"raw_stb", "RAW_hit_st_buf", REGNO_INVALID, STXT ("RAW Hazard in Store Buffer"), PRELOADS_55, 0, ABST_NONE}, - {"raw_stq", "RAW_hit_st_q", REGNO_INVALID, STXT ("RAW Hazard in Store Queue"), PRELOADS_55, 0, ABST_NONE}, - {"pqs", "PQ_tag_wait_cyc", REGNO_INVALID, STXT ("Pick Queue Stalls"), PRELOADS_7, 1, ABST_NONE}, - {"sel_stalls", "Sel_0_ready_cyc", REGNO_INVALID, STXT ("Stalls Another Thread Selected"), PRELOADS_7, 1, ABST_NONE}, - - // current aliases - SPARC_CYCLES - {"cycles", "Cycles_user", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE}, - {"insts", "Instr_all", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE}, - {"c_stalls", "Commit_0_cyc", REGNO_ANY, STXT ("Stall Cycles"), PRELOADS_7, 1, ABST_NONE}, - - {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT}, - {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_6, 0, ABST_EXACT}, - {"dcm", "DC_miss_commit", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_6, 0, ABST_EXACT}, - - {"l3m_spec", "DC_miss_L3_miss", REGNO_ANY, STXT ("L3 D-cache Speculative Misses"), PRELOADS_5, 0, ABST_NONE}, - {"lmh_spec", "DC_miss_local_mem_hit", REGNO_ANY, STXT ("Local Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE}, - {"rmh_spec", "DC_miss_remote_mem_hit", REGNO_ANY, STXT ("Remote Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE}, - // - {"dtlbm", "DTLB_HWTW_search", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_55, 0, ABST_NONE}, // 10@l1 hit, 24@l2 hit, 60@l3 hit, 500@l3 miss, 5000@trap 0.001 events/cycle - {"dtlb_hwtw_stalls", "DTLB_HWTW_ref", REGNO_ANY, STXT ("DTLB HWTW Est Stalls"), PRELOADS_55, 25, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss requiring a HW tablewalk")}, // l2-20, l3-50 - {"dtlb_trap_stalls", "DTLB_HWTW_miss_trap", REGNO_ANY, STXT ("DTLB Trap Est Stalls"), PRELOADS_35, 5000, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss with HW tablewalk unsuccessful")}, // 5000@trap - {"rawhaz", "RAW_hit_st_q~emask=0xf", REGNO_ANY, STXT ("Read-after-write Hazards"), PRELOADS_55, 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write hazards)")}, - {"br_msp_stalls", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict Stalls"), PRELOADS_6, 24, ABST_NONE, STXT ("Estimated time stalled on Branch mispredictions")}, // 24@miss, %5 of branches is bad - {"br_msp", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict"), PRELOADS_6, 0, ABST_NONE}, - {"br_tkn", "Br_taken", REGNO_ANY, STXT ("Branch Taken"), PRELOADS_7, 0, ABST_NONE}, - {"br_ins", "Branches", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE}, - {"fgu", "Instr_FGU_crypto", REGNO_ANY, STXT ("FP/VIS/Crypto Instructions"), PRELOADS_7, 0, ABST_NONE}, - {"spill_fill", "Flush_arch_exception", REGNO_ANY, STXT ("Reg Window Spill/Fill Est Stalls"), PRELOAD (100, 4), 80, ABST_NONE, STXT ("Estimated time stalled on flushing pipeline due to register window spill/fill")}, - - /* explicit definitions of (hidden) entries for proper counters */ - /* Counters that can be time converted, support memspace, or have a short_desc need to be in this table */ - {"Sel_pipe_drain_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting with correct instructions when pipeline has to drain after branch misprediction")}, - {"Sel_0_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for various conditions to be resolved")}, - {"Sel_0_ready_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread was ready to have its instructions selected but another hardware thread was selected instead")}, - {"Sel_1_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that only 1 instruction or uop was selected")}, - {"Sel_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that 2 instructions or uops were selected")}, - - {"Pick_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Pick_1_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Pick_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Pick_3_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Pick_any_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"Branches", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Control transfer instructions completed, excluding trap-related transfers")}, - {"Instr_FGU_crypto", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("FP and VIS instructions completed by the Floating Point and Graphics Unit")}, - {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Load instructions completed")}, - {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Store instructions completed")}, - {"Instr_SPR_ring_ops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Specialized instructions that require internal use of SPR ring completed")}, - {"Instr_other", NULL, REGNO_ANY, NULL, PRELOAD (2, 4), 0, ABST_NONE, STXT ("Basic arithmetic and logical instructions completed")}, - {"Instr_all", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 0, ABST_NONE, STXT ("Total instructions completed")}, - - {"Br_taken", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branch instructions taken and completed")}, - {"Instr_SW_count", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("SW Count instructions completed")}, - {"Instr_atomic", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Atomic instructions, including CASA/XA, completed")}, - {"Instr_SW_prefetch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("PREFETCH and PREFETCHA instructions completed")}, - {"Instr_block_ld_st", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Block load/store instructions completed")}, - - {"Br_BTC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branches delayed a few extra cycles because branch target not found in Branch Target Cache")}, - - {"ITLB_HWTW_hit_8K", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 8K page")}, - {"ITLB_HWTW_hit_64K", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 64K page")}, - {"ITLB_HWTW_hit_4M", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 4M page")}, - {"ITLB_HWTW_hit_256M", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 256M page")}, - {"ITLB_HWTW_hit_2G_16G", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")}, - {"ITLB_HWTW_miss_trap", NULL, REGNO_ANY, NULL, PRELOAD (1000, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk unsuccessful")}, - {"ITLB_HWTW_search", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk search done")}, - - {"Fetch_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_0_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"Instr_buffer_full_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"PQ_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"ROB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"SB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"ROB_LB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"ROB_SB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LB_SB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"ROB_LB_SB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"DTLB_miss_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"ITLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L2D")}, - {"ITLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L3 or neighbor L2D")}, - {"ITLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk missed all local caches")}, - {"DTLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L2D")}, - {"DTLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L3 or neighbor L2D")}, - {"DTLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk missed all local caches")}, - {"DTLB_HWTW_ref", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss requiring HW tablewalk")}, - - {"DC_miss_L2_L3_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT}, - {"DC_miss_nbr_scc_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_EXACT}, - {"DC_miss_nbr_scc_miss_commit", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_EXACT}, - {"DC_miss_commit", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT, STXT ("Loads that missed local L1D")}, - - {"DTLB_HWTW_hit_8K", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 8K page")}, - {"DTLB_HWTW_hit_64K", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 64K page")}, - {"DTLB_HWTW_hit_4M", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 4M page")}, - {"DTLB_HWTW_hit_256M", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 256M page")}, - {"DTLB_HWTW_hit_2G_16G", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")}, - {"DTLB_HWTW_miss_trap", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk unsuccessful")}, - {"DTLB_HWTW_search", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk search done")}, - {"RAW_hit_st_buf", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) still in store buffer not yet committed")}, - {"RAW_hit_st_q", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) committed but in store queue not yet written to L2D")}, - - {"St_q_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"St_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L2D")}, - {"St_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L3")}, - - {"DC_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Loads that speculatively hit local L1D")}, - {"DC_miss_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local L2D")}, - {"DC_miss_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local L3")}, - {"DC_miss_nbr_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit neighbor L2D via local L3")}, - {"DC_miss_nbr_scc_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit neighbor L3 on same socket")}, - {"DC_miss_nbr_scc_miss", NULL, REGNO_ANY, NULL, PRELOAD (400, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed all caches on same socket")}, - {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD (10, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed local L1D")}, - {"DC_miss_L2_miss", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed local L2D")}, - {"DC_miss_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (200, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed local L3")}, - - {"DC_miss_remote_scc_hit", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit remote cache on different socket")}, - {"DC_miss_local_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local memory")}, - {"DC_miss_remote_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (1000, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit remote memory")}, - {"Br_dir_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction was mispredicted")}, - {"Br_tgt_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose target was mispredicted")}, - {"Br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction or target was mispredicted")}, - - {"Cycles_user", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 1, ABST_NONE, STXT ("Cycles hardware thread is active in specified mode(s)")}, - - {"Flush_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Pipeline flushes due to a load that misses L3 when more than 1 hardware thread is active on the core")}, - {"Flush_br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Pipeline flushes due to a branch misprediction")}, - {"Flush_arch_exception", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Pipeline flushes due to SPARC architecture exceptions and trap entry/return")}, - {"Flush_other", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Pipeline flushes due to hardware thread state change to/from halted/paused state")}, - // - {"Commit_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from this hardware thread")}, - {"Commit_0_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from any hardware thread on this core")}, - {"Commit_1_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 uop commits from this hardware thread")}, - {"Commit_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 2 uops commit from this hardware thread")}, - {"Commit_1_or_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 or 2 uops commit from this hardware thread")}, - - - /* additional (hidden) aliases, for convenience */ - {"cycles0", "Cycles_user", 0, NULL, PRELOADS_8, 1, ABST_NONE}, - {"cycles1", "Cycles_user", 1, NULL, PRELOADS_8, 1, ABST_NONE}, - {"insts0", "Instr_all", 0, NULL, PRELOADS_8, 0, ABST_NONE}, - {"insts1", "Instr_all", 1, NULL, PRELOADS_8, 0, ABST_NONE}, - {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} -}; - -static Hwcentry sparc_m8[] = { - // current aliases - SPARC_CYCLES - {"cycles", "Cycles_user", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE}, - {"insts", "Instr_all", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE}, - {"c_stalls", "Commit_0_cyc", 3, STXT ("Stall Cycles"), PRELOADS_7, 1, ABST_NONE}, // 22825776: limit to reg 3 - {"Sel_0_wait_cyc", "Sel_0_cyc~emask=0x3f", REGNO_ANY, STXT ("Select Stall Cycles"), PRELOADS_7, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for various conditions to be resolved that prevent it being selected")}, - - {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT}, - {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_6, 0, ABST_EXACT}, - {"dcm", "DC_miss_commit", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_6, 0, ABST_EXACT}, - - {"lmh_spec", "DC_miss_local_mem_hit", REGNO_ANY, STXT ("Local Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE}, - {"rmh_spec", "DC_miss_remote_mem_hit", REGNO_ANY, STXT ("Remote Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE}, - - {"dtlbm", "DTLB_HWTW", REGNO_ANY, STXT ("DTLB Misses"), PRELOAD (40, 5), 0, ABST_NONE}, // 10@l1 hit, 24@l2 hit, 60@l3 hit, 500@l3 miss, 5000@trap 0.001 events/cycle - {"dtlb_hwtw_stalls", "DTLB_HWTW", REGNO_ANY, STXT ("DTLB HWTW Est Stalls"), PRELOAD (40, 5), 25, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss requiring a HW tablewalk")}, // l2-20, l3-50 - {"dtlb_trap_stalls", "DTLB_HWTW_miss_trap", REGNO_ANY, STXT ("DTLB Trap Est Stalls"), PRELOAD (800, 5), 5000, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss with HW tablewalk unsuccessful")}, // 5000@trap - {"rawhaz", "RAW_hit", REGNO_ANY, STXT ("Read-after-write Hazards"), PRELOAD (40, 5), 0, ABST_NONE}, - {"br_msp_stalls", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict Stalls"), PRELOAD (40, 5), 24, ABST_NONE, STXT ("Estimated time stalled on Branch mispredictions")}, // 24@miss, %5 of branches is bad - {"br_msp", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict"), PRELOAD (40, 5), 0, ABST_NONE}, - {"br_tkn", "Br_taken", REGNO_ANY, STXT ("Branch Taken"), PRELOADS_7, 0, ABST_NONE}, - {"br_ins", "Branches", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE}, - {"fgu", "Instr_FGU_crypto", REGNO_ANY, STXT ("FP/VIS/Crypto Instructions"), PRELOADS_7, 0, ABST_NONE}, - {"spill_fill", "Flush_spill_fill", REGNO_ANY, STXT ("Reg Window Spill/Fill Est Stalls"), PRELOAD (100, 5), 80, ABST_NONE, STXT ("Estimated time stalled on flushing pipeline due to register window spill/fill")}, - - /* explicit definitions of (hidden) entries for proper counters */ - /* Counters that can be time converted, support memspace, or have a short_desc need to be in this table */ - //0x01 - {"Fetch_stall_IFU_reset_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_stall_IC_miss_MB_full_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_stall_IC_miss_MB_avail_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_stall_IC_miss_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_stall_ITLB_miss_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_stall_SEL_buf_full_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_ready_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_0_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - //0x02 - {"Fetch_1_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_3_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_4_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_5_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_6_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_7_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_8_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - //0x07 - {"ITLB_HWTW_hit_8K", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 8K page")}, - {"ITLB_HWTW_hit_64K", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 64K page")}, - {"ITLB_HWTW_hit_4M", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 4M page")}, - {"ITLB_HWTW_hit_256M", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 256M page")}, - {"ITLB_HWTW_hit_16G", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 16G page")}, - {"ITLB_HWTW_hit_1T", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 1T page")}, - // { "ITLB_HWTW_miss_RA2PAC", 0x0740, 0xf07ff }, - // { "ITLB_HWTW_miss_not_RA2PAC", 0x0780, 0xf07ff }, - {"ITLB_HWTW_miss_trap", NULL, REGNO_ANY, NULL, PRELOAD (1000, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk unsuccessful")}, - {"ITLB_HWTW", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk search done")}, - //0x08 - {"Br_BTC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branches delayed a few extra cycles because branch target not found in Branch Target Cache")}, - //0x09 - {"Sel_0_no_instr_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select because no instructions are available")}, - {"Sel_0_pipe_drain_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting with correct instructions when pipeline has to drain after branch misprediction")}, - {"Sel_0_postsync_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for prior instructions to commit")}, - {"Sel_0_presync_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select with instruction that cannot decode until prior instructions have committed")}, - {"Sel_0_thread_hog_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select to prevent strand monopolizing resources")}, - {"Sel_0_tag_stall_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select because no required tags are available")}, - {"Sel_0_ready_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread was ready to have its instructions selected but another hardware thread was selected instead")}, - {"Sel_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread is not selected")}, - // No direct equivalent Sel_1/2_cyc. Nearest is Decode_uop, which increments by 0-4 each cycle according to how many uops were decoded. - //0x13 - {"ITLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L2D")}, - {"ITLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L3 or neighbor L2D")}, - {"ITLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk missed all local caches")}, - {"DTLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L2D")}, - {"DTLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L3 or neighbor L2D")}, - {"DTLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk missed all local caches")}, - {"DTLB_HWTW_ref", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss requiring HW tablewalk")}, - //0x0E - {"Instr_FGU_crypto", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("FP and VIS instructions completed by the Floating Point and Graphics Unit")}, - {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Load instructions completed")}, - {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Store instructions completed")}, - {"Instr_block_ld_st", NULL, REGNO_ANY, NULL, PRELOAD (20, 5), 0, ABST_EXACT, STXT ("Block load/store instructions completed")}, - {"Instr_SPR_ring_ops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Specialized instructions that require internal use of SPR ring completed")}, - {"Instr_atomic", NULL, REGNO_ANY, NULL, PRELOAD (20, 5), 0, ABST_EXACT, STXT ("Atomic instructions, including CASA/XA, completed")}, - {"Instr_SW_prefetch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("PREFETCH and PREFETCHA instructions completed")}, - {"Instr_other", NULL, REGNO_ANY, NULL, PRELOAD (2, 5), 0, ABST_NONE, STXT ("Basic arithmetic and logical instructions completed")}, - {"Instr_all", NULL, REGNO_ANY, NULL, PRELOAD (1, 5), 0, ABST_NONE, STXT ("Total instructions completed")}, - //0x0F - {"Branches", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Control transfer instructions completed, excluding trap-related transfers")}, - //0x10 - {"Br_taken", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branch instructions taken and completed")}, - //0x11 - {"Rename_tag_wait_PQ_1_EXU_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Rename_tag_wait_PQ_0_LSU_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Rename_wait_crypto_diag_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Sel_0_wait_ROB_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Sel_0_wait_WRF_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Sel_0_wait_LB_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Sel_0_wait_SB_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - //0x12 - {"Fetch_stall_BDA_tag_unavail_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_stall_BTA_tag_unavail_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_stall_misc_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"Fetch_stall_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"MMU_TTE_buffer_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"MMU_PRQ_pool_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - //0x15 - {"L2I_request_block_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2I_thread_hog_stall_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2I_MB_full_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2I_snoop_eviction", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2I_stall_no_request_credit_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2I_stall_no_response_credit_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - //0x16 - {"Flush_thread_hog", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes to prevent thread from monopolizing resources")}, - {"Flush_br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to a branch misprediction")}, - {"Flush_arch_exception", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to SPARC architecture exceptions and trap entry/return")}, - {"Flush_evil_twin", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to detecting floating point evil twin condition")}, - {"Flush_LSU_trap", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes to refetch Next-PC")}, - {"Flush_mode_change", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to strand mode change")}, - {"Flush_misalign", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to detecting misaligned load/store requiring transition to misaligned mitigation mode")}, - {"Flush_other", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to hardware thread state change to/from halted/paused state")}, - {"Flush_all", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to any reason")}, - //0x17 - {"Flush_spill_n_normal", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to spill_n_normal exception")}, - {"Flush_spill_n_other", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to spill_n_other exception")}, - {"Flush_fill_n_normal", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to fill_n_normal exception")}, - {"Flush_fill_n_other", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to fill_n_other exception")}, - {"Flush_spill_fill", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to spill/fill exceptions")}, - {"Flush_lost_load", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to speculatively executed load violating memory order")}, - //0x21 - {"Br_dir_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Branch instructions completed whose direction was mispredicted")}, - {"Br_tgt_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Branch instructions completed whose target was mispredicted")}, - {"Br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Branch instructions completed whose direction or target was mispredicted")}, - //0x23 - {"LSU_st_q_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LSU_st_q_tag_wait_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2D_stall_no_request_credit_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2D_stall_no_response_credit_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - //0x27 - {"DC_miss_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit local L2D")}, - {"DC_miss_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit local L3")}, - {"DC_miss_L3_dirty_copyback", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit local L3 but require copyback from L2D within same CPC")}, - {"DC_miss_nbr_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit neighbor L3 on same socket")}, - {"DC_miss_remote_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (400, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit remote cache on different socket")}, - {"DC_miss_local_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit local memory")}, - {"DC_miss_remote_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (1000, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit remote memory")}, - {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD (10, 5), 0, ABST_NONE, STXT ("Loads that speculatively missed local L1D")}, - //0x28 - {"DC_sec_miss_L2_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT}, - {"DC_miss_L2_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT}, - {"DC_miss_L3_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT}, - {"DC_miss_L3_dirty_copyback_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT}, - {"DC_miss_nbr_L3_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT}, - {"DC_miss_remote_L3_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT}, - {"DC_miss_local_mem_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT}, - {"DC_miss_remote_mem_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT}, - {"DC_miss_commit", NULL, REGNO_ANY, NULL, PRELOAD (25, 5), 0, ABST_EXACT, STXT ("Loads that missed local L1D")}, - //0x29 - // {"Store_DC_sec_miss_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT("")}, - {"Store_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L2D")}, - {"Store_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L3")}, - {"Store_nbr_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in neighbor L2 on same socket")}, - {"Store_nbr_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in neighbor L3 on same socket")}, - {"Store_remote_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (400, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in remote cache on different socket")}, - {"Store_local_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local memory")}, - {"Store_remote_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (1000, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in remote memory")}, - {"Store_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was observed to be somewhere in the memory hierarchy")}, - //0x2d - {"RAW_hit_st_buf", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) still in store buffer not yet committed")}, - {"RAW_hit_st_q", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) committed but in store queue not yet written to L2D")}, - {"RAW_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write hazards)")}, - //0x2f - {"Cycles_user_non_MLA", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE}, - {"Cycles_user_MLA", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE}, - {"Cycles_user", NULL, REGNO_ANY, NULL, PRELOAD (1, 5), 1, ABST_NONE, STXT ("Cycles hardware thread is active in specified mode(s)")}, - //0x37 - {"DTLB_HWTW_hit_8K", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 8K page")}, - {"DTLB_HWTW_hit_64K", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 64K page")}, - {"DTLB_HWTW_hit_4M", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 4M page")}, - {"DTLB_HWTW_hit_256M", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 256M page")}, - {"DTLB_HWTW_hit_16G", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 16G page")}, - {"DTLB_HWTW_hit_1T", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 1T page")}, - {"DTLB_HWTW_miss_trap", NULL, REGNO_ANY, NULL, PRELOAD (800, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk unsuccessful")}, - {"DTLB_HWTW", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk search done")}, - //0x3f - {"Commit_0_cyc", /*22825776*/ NULL, 3, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from this hardware thread")}, - {"Commit_0_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from any hardware thread on this core")}, - // Similar situation to Sel_1_cyc etc. No direct equivalent, nearest is Commit_uop, which increments by 0-4 each cycle according to how many uops were committed. - - /* additional (hidden) aliases, for convenience */ - {"cycles0", "Cycles_user", 0, NULL, PRELOADS_8, 1, ABST_NONE}, - {"cycles1", "Cycles_user", 1, NULL, PRELOADS_8, 1, ABST_NONE}, - {"insts0", "Instr_all", 0, NULL, PRELOADS_8, 0, ABST_NONE}, - {"insts1", "Instr_all", 1, NULL, PRELOADS_8, 0, ABST_NONE}, - {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} -}; - -static Hwcentry usfuji_V_list[] = { - {"cycles", "cycle_counts", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE}, - {"insts", "instruction_counts", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE}, - {"flops", "floating_instructions", REGNO_ANY, STXT ("Floating-point Ops"), PRELOADS_6, 0, ABST_NONE}, - - /* explicit definitions of (hidden) entries for proper counters */ - /* Only counters that can be time converted, or are load-store need to be in this table */ - {"cycle_counts", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE}, - {"load_store_instructions", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE}, - - /* additional (hidden) aliases for convenience */ - {"cycles0", "cycle_counts", 0, NULL, PRELOADS_75, 1, ABST_NONE}, - {"cycles1", "cycle_counts", 1, NULL, PRELOADS_75, 1, ABST_NONE}, - {"insts0", "instruction_counts", 0, NULL, PRELOADS_75, 0, ABST_NONE}, - {"insts1", "instruction_counts", 1, NULL, PRELOADS_75, 0, ABST_NONE}, - {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} -}; - -static Hwcentry usfuji_VI_VII_list[] = { - {"cycles", "cycle_counts", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE}, - {"insts", "instruction_counts", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE}, - {"dcm", "op_r_iu_req_mi_go", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_6, 0, ABST_NONE}, - {"dcstall", "op_wait_all", REGNO_ANY, STXT ("L1 D-cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE}, - {"dtlbm", "write_op_uTLB", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_5, 0, ABST_NONE}, - // l2m: mem_cache_load test shows undercount of 3x, however, we don't care too much about this chip, keeping the alias for now - {"l2m", "sx_miss_count_dm", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_5, 0, ABST_NONE}, /*YXXX undercounts?*/ - {"l2wm", "dvp_count_dm", REGNO_ANY, STXT ("L2 Cache Writeback Misses"), PRELOADS_5, 0, ABST_NONE}, - {"l2ref", "sx_read_count_dm", REGNO_ANY, STXT ("L2 Cache Refs"), PRELOADS_6, 0, ABST_NONE}, - {"l2stall", "sx_miss_wait_dm", REGNO_ANY, STXT ("L2 Cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE}, - {"icm", "if_r_iu_req_mi_go", REGNO_ANY, STXT ("L1 I-cache Misses"), PRELOADS_6, 0, ABST_NONE}, - {"icstall", "if_wait_all", REGNO_ANY, STXT ("L1 I-cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE}, - {"itlbm", "write_if_uTLB", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE}, - {"flops", "floating_instructions", REGNO_ANY, STXT ("Floating-point Ops"), PRELOADS_7, 0, ABST_NONE}, - - /* explicit definitions of (hidden) entries for proper counters */ - /* Only counters that can be time converted, or are load-store need to be in this table */ - {"cycle_counts", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE}, - {"op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"load_store_instructions", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE}, - {"active_cycle_count", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"write_op_uTLB", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE}, - {"sx_miss_wait_pf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"sx_miss_wait_dm", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"sx_miss_count_dm", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE}, - {"fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_r_iu_req_mi_go", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE}, - {"sx_miss_count_dm_if", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE}, - {"op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"swpf_lbs_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE}, - {"sx_read_count_dm", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE}, - {"trap_DMMU_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE}, - {"op_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"sx_miss_count_dm_opex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE}, - {"if_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"dvp_count_dm", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE}, - {"sx_miss_count_dm_opsh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE}, - - /* additional (hidden) aliases for convenience */ - {"cycles0", "cycle_counts", 0, NULL, PRELOADS_8, 1, ABST_NONE}, - {"cycles1", "cycle_counts", 1, NULL, PRELOADS_8, 1, ABST_NONE}, - {"insts0", "instruction_counts", 0, NULL, PRELOADS_8, 0, ABST_NONE}, - {"insts1", "instruction_counts", 1, NULL, PRELOADS_8, 0, ABST_NONE}, - {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} -}; - - -static Hwcentry usfuji_X_list[] = { - {"cycles", "cycle_counts", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE}, - {"insts", "instruction_counts", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE}, - {"dcm", "L1D_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE}, - {"dcstall", "L1D_wait_all", REGNO_ANY, STXT ("L1 D-cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE}, - - /* explicit definitions of (hidden) entries for proper counters */ - /* Only counters that can be time converted, or are load-store need to be in this table */ - {"cycle_counts", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE}, - {"w_op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_pf_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_pfp_busy_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_dm_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_pf_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_dm_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"d_move_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_pfp_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_pf_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_dm_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L1D_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_pf_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"cse_priority_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_pfp_busy_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L1I_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_dm_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"single_mode_cycle_counts", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"suspend_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"sleep_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - /* additional (hidden) aliases for convenience */ - {"cycles0", "cycle_counts", 0, NULL, PRELOADS_8, 1, ABST_NONE}, - {"cycles1", "cycle_counts", 1, NULL, PRELOADS_8, 1, ABST_NONE}, - {"insts0", "instruction_counts", 0, NULL, PRELOADS_8, 0, ABST_NONE}, - {"insts1", "instruction_counts", 1, NULL, PRELOADS_8, 0, ABST_NONE}, - {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} -}; - -static Hwcentry usfuji_XII_list[] = { - {"cycles", "cycle_counts", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE}, - {"insts", "instruction_counts", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE}, - {"dcm", "L1D_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE}, - {"dcstall", "L1D_wait_all", REGNO_ANY, STXT ("L1 D-cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE}, - - /* explicit definitions of (hidden) entries for proper counters */ - /* Only counters that can be time converted, or are load-store need to be in this table */ - {"cycle_counts", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE}, - {"L1D_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L1I_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_dm_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_dm_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_dm_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_dm_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_pf_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_pf_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_pf_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"L2_miss_wait_pf_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LL_miss_wait_dm_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LL_miss_wait_dm_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LL_miss_wait_dm_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LL_miss_wait_dm_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LL_miss_wait_pf_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LL_miss_wait_pf_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LL_miss_wait_pf_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"LL_miss_wait_pf_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"cse_priority_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"d_move_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"l2_sy_miss_wait_dm_part1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"l2_sy_miss_wait_dm_part2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"msgr_reqp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"msgr_rtnp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"msgs_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_l1d_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_l1d_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_l2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_l2_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_ll_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_ll_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_pfp_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_pfp_busy_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_pfp_busy_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_l1d_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_l1d_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_l2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_l2_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_ll_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_ll_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_pfp_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_pfp_busy_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_pfp_busy_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"w_op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - {"single_mode_cycle_counts", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"suspend_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - {"sleep_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, - - /* additional (hidden) aliases for convenience */ - {"cycles0", "cycle_counts", 0, NULL, PRELOADS_8, 1, ABST_NONE}, - {"cycles1", "cycle_counts", 1, NULL, PRELOADS_8, 1, ABST_NONE}, - {"insts0", "instruction_counts", 0, NULL, PRELOADS_8, 0, ABST_NONE}, - {"insts1", "instruction_counts", 1, NULL, PRELOADS_8, 0, ABST_NONE}, - {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} -}; - /* Kernel profiling pseudo-chip, OBSOLETE (To support 12.3 and earlier, TBR) */ static Hwcentry kproflist[] = { {"kcycles", "kcycles", 0, STXT ("KCPU Cycles"), PRELOADS_5, 1, ABST_NONE}, @@ -2468,24 +1323,6 @@ typedef struct * If the string is not formatted that way, -h hi and -h lo will fail */ static cpu_list_t cputabs[] = { - {CPC_ULTRA1, usIlist, {NULL}}, /* bind will fail */ - {CPC_ULTRA2, usIlist, {NULL}}, /* bind will fail */ - {CPC_ULTRA3, usIIIlist, {"insts,,ecstall", 0}}, - {CPC_ULTRA3_PLUS, usIIIlist, {"insts,,ecstall", 0}}, - {CPC_ULTRA3_I, usIIIlist, {"insts,,ecstall", 0}}, - {CPC_ULTRA4_PLUS, usIVplist, {"insts,,ecstall", 0}}, - {CPC_ULTRA_T1, niagara1, {"insts", 0}}, - {CPC_ULTRA_T2, niagara2, {"insts,,+l2drm", 0}}, - {CPC_ULTRA_T2P, niagara2, {"insts,,+l2drm", 0}}, - {CPC_ULTRA_T3, niagara2, {"insts,,+l2drm", 0}}, - {CPC_SPARC_T4, sparc_t4, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, - {CPC_SPARC_M4, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, // renamed to m5 - {CPC_SPARC_T5, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, - {CPC_SPARC_M5, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, - {CPC_SPARC_T6, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, // no such processor - {CPC_SPARC_M6, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, - {CPC_SPARC_M7, sparc_m7, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, // includes T7 - {CPC_SPARC_M8, sparc_m8, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, {CPC_PENTIUM_PRO_MMX, pentiumIIlist, {"insts", 0}}, {CPC_PENTIUM_PRO, pentiumIIIlist, {"insts", 0}}, {CPC_PENTIUM_4, pentium4, {"insts", 0}}, @@ -2512,11 +1349,6 @@ static cpu_list_t cputabs[] = { {CPC_AMD_FAM_10H, amd_opteron_10h_11h, {"insts,,cycles,,l2dm,,l2dtlbm", 0}}, {CPC_AMD_FAM_11H, amd_opteron_10h_11h, {"insts,,cycles,,l2dm,,l2dtlbm", 0}}, {CPC_AMD_FAM_15H, amd_15h, {"insts,,cycles", 0}}, - {CPC_SPARC64_V, usfuji_V_list, {"insts,,cycles", 0}}, - {CPC_SPARC64_VI, usfuji_VI_VII_list, {"insts,,cycles,,dcstall", 0}}, - {CPC_SPARC64_VII, usfuji_VI_VII_list, {"insts,,cycles,,dcstall", 0}}, - {CPC_SPARC64_X, usfuji_X_list, {"insts,,cycles,,dcstall", 0}}, - {CPC_SPARC64_XII, usfuji_XII_list, {"insts,,cycles,,dcstall", 0}}, {CPC_KPROF, kproflist, {NULL}}, // OBSOLETE (To support 12.3 and earlier, TBR) {ARM_CPU_IMP_APM, generic_list, {"insts,,cycles", 0}}, {CPC_AMD_Authentic, generic_list, {"insts,,cycles", 0}}, @@ -2993,17 +1825,6 @@ setup_cpc_general (int skip_hwc_test) hwcdrv->hwcdrv_get_info (&cpcx_cpuver, &cpcx_cciname, &cpcx_npics, &cpcx_docref, &cpcx_support_bitmask); -#ifdef DISALLOW_USI_USII_6357446 - if (cpcx_cpuver == CPC_ULTRA1 || cpcx_cpuver == CPC_ULTRA2) - { - Tprintf (0, "hwctable: WARNING: setup_cpc(): cpu=%d" - " US-I/US-II cannot provide profile interrupts\n", cpcx_cpuver); - /* profiling interrupts don't work on US-I, US-II */ - hwcfuncs_int_logerr (GTXT ("UltraSPARC I and II cannot provide overflow interrupts\n")); - goto setup_cpc_wrapup; - } -#endif - #ifdef DISALLOW_PENTIUM_PRO_MMX_7007575 if (cpcx_cpuver == CPC_PENTIUM_PRO_MMX) { From patchwork Tue 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ybuw7M3eKU_EBT7RU-pWzC26cOgkKQGx X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org From: Vladimir Mezentsev ChangeLog 2024-05-20 Vladimir Mezentsev * src/collctrl.cc: Use StringBuilder to create messages. Remove unused variables and arrays. * src/collctrl.h: Remove unused variables. --- gprofng/src/collctrl.cc | 460 ++++++++++++++++------------------------ gprofng/src/collctrl.h | 2 - 2 files changed, 179 insertions(+), 283 deletions(-) diff --git a/gprofng/src/collctrl.cc b/gprofng/src/collctrl.cc index 28fdb0b577e..7c0219b13f0 100644 --- a/gprofng/src/collctrl.cc +++ b/gprofng/src/collctrl.cc @@ -42,7 +42,6 @@ #include "StringBuilder.h" #define SP_GROUP_HEADER "#analyzer experiment group" -#define DD_MAXPATHLEN (MAXPATHLEN * 4) /* large, to build up data descriptor */ /* If the system doesn't provide strsignal, we get it defined in libiberty but no declaration is supplied. */ @@ -50,11 +49,6 @@ extern const char *strsignal (int); #endif -// _SC_CPUID_MAX is not available on 2.6/2.7 -#ifndef _SC_CPUID_MAX -#define _SC_CPUID_MAX 517 -#endif - static const char *get_fstype (char *); static cpu_info_t cpu_info; @@ -70,7 +64,7 @@ read_str (char *from, char **to) { if (s[i] != '\n' && s[i] != ' ' && s[i] != '\t') { - *to = strndup(s, i + 1); + *to = strndup (s, i + 1); return; } } @@ -88,7 +82,7 @@ read_int (char *from) } cpu_info_t * -read_cpuinfo() +read_cpuinfo () { static int inited = 0; if (inited) @@ -141,7 +135,6 @@ read_cpuinfo() Coll_Ctrl::Coll_Ctrl (int _interactive, bool _defHWC, bool _kernelHWC) { char hostname[MAXPATHLEN]; - long ncpumax; interactive = _interactive; defHWC = _defHWC; kernelHWC = _kernelHWC; @@ -154,24 +147,12 @@ Coll_Ctrl::Coll_Ctrl (int _interactive, bool _defHWC, bool _kernelHWC) *p = 0; default_stem = strdup ("test"); - /* get CPU count and processor clock rate */ - ncpumax = sysconf (_SC_CPUID_MAX); - if (ncpumax == -1) - { - ncpus = sysconf (_SC_NPROCESSORS_CONF); - /* add 2048 to count, since on some systems CPUID does not start at zero */ - ncpumax = ncpus + 2048; - } - cpu_info_t *cpu_p = read_cpuinfo(); + cpu_info_t *cpu_p = read_cpuinfo (); ncpus = cpu_p->cpu_cnt; cpu_clk_freq = cpu_p->cpu_clk_freq; /* check resolution of system clock */ sys_resolution = sysconf (_SC_CLK_TCK); - if (sys_resolution == 0) - sys_period = 10000; - else - sys_period = MICROSEC / (int) sys_resolution; /* determine memory page size and number of pages */ npages = sysconf (_SC_PHYS_PAGES); @@ -238,7 +219,7 @@ Coll_Ctrl::Coll_Ctrl (int _interactive, bool _defHWC, bool _kernelHWC) setup_hwc (); hwcprof_default = 1; } - else // disable the default, and reset the counters + else // disable the default, and reset the counters hwcprof_enabled_cnt = 0; synctrace_enabled = 0; synctrace_thresh = -1; @@ -358,7 +339,6 @@ Coll_Ctrl::Coll_Ctrl (Coll_Ctrl * cc) opened = 0; nofswarn = cc->nofswarn; sys_resolution = cc->sys_resolution; - sys_period = cc->sys_period; // ensure that the default name is updated (void) preprocess_names (); @@ -457,6 +437,7 @@ Coll_Ctrl::delete_expt () // Check the experiment settings for consistency. Returns NULL if OK, // or an error message if there are invalid combinations of settings + char * Coll_Ctrl::check_consistency () { @@ -491,7 +472,7 @@ Coll_Ctrl::check_expt (char **warn) char *ret; *warn = NULL; ret = check_consistency (); - if (ret != NULL) /* something is wrong, return the error */ + if (ret != NULL) /* something is wrong, return the error */ return ret; /* check for heaptrace and java -- warn that it covers native allocations only */ if (heaptrace_enabled == 1 && java_mode == 1 && java_default == 0) @@ -510,7 +491,7 @@ Coll_Ctrl::check_expt (char **warn) store_dir, strerror (errno)); if (access (store_dir, W_OK) != 0) return dbe_sprintf (GTXT ("Store directory %s is not writeable: %s\n"), - store_dir, strerror (errno)); + store_dir, strerror (errno)); /* if an experiment-group, verify that it can be written */ ret = check_group (); @@ -522,218 +503,172 @@ Coll_Ctrl::check_expt (char **warn) char * Coll_Ctrl::show (int i) { - char UEbuf[4096]; - UEbuf[0] = 0; + StringBuilder sb; if (i == 0) { - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("Collection parameters:\n")); - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT (" experiment enabled\n")); + sb.append (GTXT ("Collection parameters:\n")); + sb.append (GTXT (" experiment enabled\n")); } if (target_name != NULL) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\ttarget = %s\n"), target_name); + sb.appendf (GTXT ("\ttarget = %s\n"), target_name); if (uexpt_name != NULL) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tuser_expt_name = %s\n"), uexpt_name); - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\texpt_name = %s\n"), - ((expt_name != NULL) ? expt_name : NTXT (""))); + sb.appendf (GTXT ("\tuser_expt_name = %s\n"), uexpt_name); + sb.appendf (GTXT ("\texpt_name = %s\n"), + ((expt_name != NULL) ? expt_name : "")); if (udir_name != NULL) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tdir_name = %s\n"), udir_name); + sb.appendf (GTXT ("\tdir_name = %s\n"), udir_name); if (expt_group != NULL) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\texpt_group = %s\n"), expt_group); + sb.appendf (GTXT ("\texpt_group = %s\n"), expt_group); if (debug_mode == 1) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tdebug_mode enabled\n")); + sb.append (GTXT ("\tdebug_mode enabled\n")); if (clkprof_enabled != 0) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tclock profiling enabled, %.3f millisec.\n"), + sb.appendf (GTXT ("\tclock profiling enabled, %.3f millisec.\n"), (double) (clkprof_timer) / 1000.); if (synctrace_enabled != 0) { if (synctrace_thresh < 0) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tsynchronization tracing enabled, threshold: calibrate; ")); + sb.append (GTXT ("\tsynchronization tracing enabled, threshold: calibrate; ")); else if (synctrace_thresh == 0) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tsynchronization tracing enabled, threshold: all; ")); + sb.append (GTXT ("\tsynchronization tracing enabled, threshold: all; ")); else - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tsynchronization tracing enabled, threshold: %d micros.; "), synctrace_thresh); + sb.appendf (GTXT ("\tsynchronization tracing enabled, threshold: %d micros.; "), + synctrace_thresh); switch (synctrace_scope) { case SYNCSCOPE_NATIVE: - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("Native-APIs\n")); + sb.append (GTXT ("Native-APIs\n")); break; case SYNCSCOPE_JAVA: - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("Java-APIs\n")); + sb.append (GTXT ("Java-APIs\n")); break; case SYNCSCOPE_NATIVE | SYNCSCOPE_JAVA: - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("Native- and Java-APIs\n")); + sb.append (GTXT ("Native- and Java-APIs\n")); break; default: - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("ERR -- unexpected synctrace_scope %d\n"), synctrace_scope); + sb.appendf (GTXT ("ERR -- unexpected synctrace_scope %d\n"), + synctrace_scope); break; } } if (hwcprof_enabled_cnt != 0) { char ctrbuf[MAXPATHLEN]; - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\thardware counter profiling%s enabled:\n"), - (hwcprof_default == 1 ? GTXT (" (default)") : "")); + if (hwcprof_default == 1) + sb.append (GTXT ("\thardware counter profiling (default) enabled:\n")); + else + sb.append (GTXT ("\thardware counter profiling enabled:\n")); for (int ii = 0; ii < hwcprof_enabled_cnt; ii++) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\t %u. %s\n"), ii + 1, - hwc_hwcentry_specd_string (ctrbuf, MAXPATHLEN, &hwctr[ii])); + sb.appendf ("\t %u. %s\n", ii + 1, + hwc_hwcentry_specd_string (ctrbuf, sizeof (ctrbuf), &hwctr[ii])); } if (heaptrace_enabled != 0) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\theap tracing enabled, %s\n"), - (heaptrace_checkenabled == 0 ? GTXT ("no checking") : - (heaptrace_checkenabled == 1 ? GTXT ("over/underrun checking") : - GTXT ("over/underrun checking and pattern storing")))); + { + if (heaptrace_checkenabled == 0) + sb.append (GTXT ("\theap tracing enabled, no checking\n")); + else if (heaptrace_checkenabled == 1) + sb.append (GTXT ("\theap tracing enabled, over/underrun checking\n")); + else + sb.append (GTXT ("\theap tracing enabled, over/underrun checking and pattern storing\n")); + } if (iotrace_enabled != 0) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tI/O tracing enabled\n")); + sb.append (GTXT ("\tI/O tracing enabled\n")); switch (count_enabled) { case 0: break; case 1: - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tcount data enabled\n")); + sb.append (GTXT ("\tcount data enabled\n")); break; case -1: - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tstatic count data will be generated (for a.out only)\n")); + sb.append (GTXT ("\tstatic count data will be generated (for a.out only)\n")); break; } switch (follow_mode) { case FOLLOW_ON: - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tdescendant processes will be followed\n")); + sb.append (GTXT ("\tdescendant processes will be followed\n")); break; case FOLLOW_ALL: if (follow_spec_usr && follow_spec_cmp) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\texperiments will be recorded for descendant processes that match pattern '%s'\n"), - follow_spec_usr); + sb.appendf (GTXT ("\texperiments will be recorded for descendant processes that match pattern '%s'\n"), + follow_spec_usr); else - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tdescendant processes will all be followed\n")); + sb.append (GTXT ("\tdescendant processes will all be followed\n")); break; case FOLLOW_NONE: - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tdescendant processes will not be followed\n")); + sb.append (GTXT ("\tdescendant processes will not be followed\n")); break; default: - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tfollowing descendant processes: \n")); + sb.append (GTXT ("\tfollowing descendant processes: \n")); break; } if (java_mode == 0) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tjava profiling disabled\n")); + sb.append (GTXT ("\tjava profiling disabled\n")); if (pauseresume_sig != 0) { const char *buf = strsignal (pauseresume_sig); if (buf != NULL) { if (pauseresume_pause == 1) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tpause-resume (delayed initialization) signal %s (%d) -- paused\n"), buf, pauseresume_sig); + sb.appendf (GTXT ("\tpause-resume (delayed initialization) signal %s (%d) -- paused\n"), + buf, pauseresume_sig); else - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tpause-resume (delayed initialization) signal %s (%d)\n"), buf, pauseresume_sig); + sb.appendf (GTXT ("\tpause-resume (delayed initialization) signal %s (%d)\n"), + buf, pauseresume_sig); } else { if (pauseresume_pause == 1) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tpause-resume (delayed initialization) signal %d -- paused\n"), pauseresume_sig); + sb.appendf (GTXT ("\tpause-resume (delayed initialization) signal %d -- paused\n"), + pauseresume_sig); else - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tpause-resume (delayed initialization) signal %d\n"), pauseresume_sig); + sb.appendf (GTXT ("\tpause-resume (delayed initialization) signal %d\n"), + pauseresume_sig); } } if (sample_sig != 0) { const char *buf = strsignal (sample_sig); if (buf != NULL) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tsample signal %s (%d)\n"), buf, sample_sig); + sb.appendf (GTXT ("\tsample signal %s (%d)\n"), buf, sample_sig); else - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tsample signal %d\n"), sample_sig); + sb.appendf (GTXT ("\tsample signal %d\n"), sample_sig); } if (time_run != 0 || start_delay != 0) { if (start_delay != 0) { if (time_run != 0) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tdata-collection duration, %d-%d secs.\n"), start_delay, time_run); + sb.appendf (GTXT ("\tdata-collection duration, %d-%d secs.\n"), + start_delay, time_run); else - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tdata-collection duration, %d- secs.\n"), start_delay); + sb.appendf (GTXT ("\tdata-collection duration, %d- secs.\n"), + start_delay); } else - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tdata-collection duration, %d secs.\n"), time_run); + sb.appendf (GTXT ("\tdata-collection duration, %d secs.\n"), time_run); } if (sample_period != 0) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tperiodic sampling, %d secs.\n"), sample_period); + sb.appendf (GTXT ("\tperiodic sampling, %d secs.\n"), sample_period); else - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tno periodic sampling\n")); + sb.append (GTXT ("\tno periodic sampling\n")); if (size_limit != 0) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\texperiment size limit %d MB.\n"), size_limit); + sb.appendf (GTXT ("\texperiment size limit %d MB.\n"), size_limit); else - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tno experiment size limit set\n")); - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\texperiment archiving: -a %s\n"), archive_mode); - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\tdata descriptor: \"%s\"\n"), + sb.append (GTXT ("\tno experiment size limit set\n")); + sb.appendf (GTXT ("\texperiment archiving: -a %s\n"), archive_mode); + sb.appendf (GTXT ("\tdata descriptor: \"%s\"\n"), ((data_desc != NULL) ? data_desc : NTXT (""))); -#if 0 - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\t expt_dir: %s\n"), - ((expt_dir != NULL) ? expt_dir : NTXT (""))); - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\t base_name: %s\n"), - ((base_name != NULL) ? base_name : NTXT (""))); - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\t store_dir: %s\n"), - ((store_dir != NULL) ? store_dir : NTXT (""))); - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\t store_ptr: %s\n"), - ((store_ptr != NULL) ? store_ptr : NTXT (""))); -#endif - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\t\thost: `%s', ncpus = %d, clock frequency %d MHz.\n"), + sb.appendf (GTXT ("\t\thost: `%s', ncpus = %d, clock frequency %d MHz.\n"), ((node_name != NULL) ? node_name : NTXT ("")), (int) ncpus, (int) cpu_clk_freq); if (npages > 0) { long long memsize = ((long long) npages * (long long) page_size) / (1024 * 1024); - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("\t\tmemory: %ld pages @ %ld bytes = %lld MB.\n"), + sb.appendf (GTXT ("\t\tmemory: %ld pages @ %ld bytes = %lld MB.\n"), npages, page_size, memsize); } - return strdup (UEbuf); + return sb.toString (); } #define MAX_COLLECT_ARGS 100 @@ -741,10 +676,9 @@ Coll_Ctrl::show (int i) char ** Coll_Ctrl::get_collect_args () { - char buf[DD_MAXPATHLEN]; char **p; char **argv = (char **) calloc (MAX_COLLECT_ARGS, sizeof (char *)); - if (argv == NULL) // poor way of dealing with calloc failure + if (argv == NULL) // poor way of dealing with calloc failure abort (); p = argv; *p++ = strdup ("collect"); @@ -753,25 +687,27 @@ Coll_Ctrl::get_collect_args () if (clkprof_enabled != 0) { *p++ = strdup ("-p"); - snprintf (buf, sizeof (buf), "%du", clkprof_timer); - *p++ = strdup (buf); + *p++ = dbe_sprintf ("%du", clkprof_timer); } if (hwcprof_enabled_cnt > 0) { - *buf = 0; + StringBuilder sb; *p++ = strdup ("-h"); for (int ii = 0; ii < hwcprof_enabled_cnt; ii++) { char*rateString = hwc_rate_string (&hwctr[ii], 1); //"1" is for temporary goldfile compatibility. TBR YXXX!! - snprintf (buf + strlen (buf), sizeof (buf) - strlen (buf), - "%s%s,%s%s", ii ? "," : "", hwctr[ii].name, - rateString ? rateString : "", - (ii + 1 < hwcprof_enabled_cnt) ? "," : ""); - free (rateString); + if (ii > 0) + sb.append (','); + sb.append (hwctr[ii].name); + if (rateString) + { + sb.append (rateString); + free (rateString); + } + if (ii + 1 < hwcprof_enabled_cnt) + sb.append (','); } - if (strlen (buf) + 1 >= sizeof (buf)) - abort (); - *p++ = strdup (buf); + *p++ = sb.toString (); } if (heaptrace_enabled != 0) { @@ -870,28 +806,14 @@ Coll_Ctrl::show_expt () { if (enabled == 0) return NULL; - char UEbuf[4096]; - UEbuf[0] = 0; - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("Creating experiment directory %s (Process ID: %ld) ...\n"), - ((store_ptr != NULL) ? store_ptr : NTXT ("")), (long) getpid ()); + StringBuilder sb; + sb.appendf (GTXT ("Creating experiment directory %s (Process ID: %ld) ...\n"), + store_ptr != NULL ? store_ptr : "", (long) getpid ()); char *caller = getenv ("SP_COLLECTOR_FROM_GUI"); // Collector from GUI - if (caller != NULL) // Print non-localized message - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - NTXT ("\nCreating experiment directory %s (Process ID: %ld) ...\n"), - ((store_ptr != NULL) ? store_ptr : NTXT ("")), (long) getpid ()); -#if 0 - char *fstype = get_fstype (store_dir); - if ((fstype != NULL) && (nofswarn == 0)) - { - // only warn if clock or hwc profiling is turned on - if (clkprof_enabled || hwcprof_enabled_cnt != 0) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("this experiment is being recorded to a file system \nof type \"%s\", which may distort the measured performance."), - fstype); - } -#endif - return strdup (UEbuf); + if (caller != NULL) // Print non-localized message + sb.appendf ("\nCreating experiment directory %s (Process ID: %ld) ...\n", + store_ptr != NULL ? store_ptr : "", (long) getpid ()); + return sb.toString (); } void @@ -913,8 +835,8 @@ Coll_Ctrl::reset_clkprof (int val) { // profiler has had to reset to a different value; warn user char *msg = dbe_sprintf ( - GTXT ("Warning: Clock profiling timer reset from %.3f millisec. to %.3f millisec. as required by profiling driver\n\n"), - (double) (clkprof_timer) / 1000., (double) (val) / 1000.); + GTXT ("Warning: Clock profiling timer reset from %.3f millisec. to %.3f millisec. as required by profiling driver\n\n"), + (double) (clkprof_timer) / 1000., (double) (val) / 1000.); adjust_clkprof_timer (val); return msg; } @@ -954,7 +876,7 @@ Coll_Ctrl::set_clkprof (const char *string, char** warn) double dval = strtod (string, &endchar); if (*endchar == 'm' || *endchar == 0) /* user specified milliseconds */ dval = dval * 1000.; - else if (*endchar == 'u') /* user specified microseconds */ + else if (*endchar == 'u') /* user specified microseconds */ dval = dval; else return dbe_sprintf (GTXT ("Unrecognized clock-profiling interval `%s'\n"), string); @@ -983,8 +905,8 @@ Coll_Ctrl::set_clkprof (const char *string, char** warn) { /* value too small, use minimum value, with warning */ *warn = dbe_sprintf ( - GTXT ("Warning: Clock profiling at %.3f millisec. interval is not supported on this system; minimum %.3f millisec. used\n"), - (double) (nclkprof_timer) / 1000., (double) (clk_params.min) / 1000.); + GTXT ("Warning: Clock profiling at %.3f millisec. interval is not supported on this system; minimum %.3f millisec. used\n"), + (double) (nclkprof_timer) / 1000., (double) (clk_params.min) / 1000.); nclkprof_timer = clk_params.min; } @@ -992,8 +914,8 @@ Coll_Ctrl::set_clkprof (const char *string, char** warn) if (nclkprof_timer > clk_params.max) { *warn = dbe_sprintf ( - GTXT ("Clock profiling at %.3f millisec. interval is not supported on this system; maximum %.3f millisec. used\n"), - (double) (nclkprof_timer) / 1000., (double) (clk_params.max) / 1000.); + GTXT ("Clock profiling at %.3f millisec. interval is not supported on this system; maximum %.3f millisec. used\n"), + (double) (nclkprof_timer) / 1000., (double) (clk_params.max) / 1000.); nclkprof_timer = clk_params.max; } @@ -1005,9 +927,9 @@ Coll_Ctrl::set_clkprof (const char *string, char** warn) { /* no, we need to reset to a multiple */ *warn = dbe_sprintf ( - GTXT ("Clock profile interval rounded from %.3f to %.3f (system resolution = %.3f) millisec."), - (double) (nclkprof_timer) / 1000., (double) (ticks) / 1000., - (double) (clk_params.res) / 1000.); + GTXT ("Clock profile interval rounded from %.3f to %.3f (system resolution = %.3f) millisec."), + (double) (nclkprof_timer) / 1000., (double) (ticks) / 1000., + (double) (clk_params.res) / 1000.); nclkprof_timer = ticks; } } @@ -1068,7 +990,7 @@ Coll_Ctrl::set_synctrace (const char *string) /* clear the comma for the threshold determination */ *comma_p = 0; } - else /* no "," -- default to native and Java */ + else /* no "," -- default to native and Java */ synctrace_scope = SYNCSCOPE_NATIVE | SYNCSCOPE_JAVA; if (!strlen (val) || !strcmp (val, "calibrate") || !strcmp (val, "on")) { @@ -1241,7 +1163,7 @@ Coll_Ctrl::set_time_run (const char *valarg) { if (opened == 1) return strdup (GTXT ("Experiment is active; command ignored.\n")); - if (valarg == NULL) /* invalid setting */ + if (valarg == NULL) /* invalid setting */ return strdup (GTXT ("time parameter can not be NULL\n")); /* the string should be a number >= 0 */ int prev_start_delay = start_delay; @@ -1260,7 +1182,7 @@ Coll_Ctrl::set_time_run (const char *valarg) val = val * 60; /* convert to seconds */ endchar++; } - else if (*endchar == 's') /* no conversion needed */ + else if (*endchar == 's') /* no conversion needed */ endchar++; if (*endchar == 0) { @@ -1285,7 +1207,7 @@ Coll_Ctrl::set_time_run (const char *valarg) val = val * 60; /* convert to seconds */ endchar++; } - else if (*endchar == 's') /* no conversion needed */ + else if (*endchar == 's') /* no conversion needed */ endchar++; if (*endchar != 0) { @@ -1366,6 +1288,7 @@ Coll_Ctrl::hwcentry_dup (Hwcentry *hnew, Hwcentry *_hwc) } // Routine to initialize the HWC tables, set up the default experiment, etc. + void Coll_Ctrl::setup_hwc () { @@ -1451,15 +1374,10 @@ Coll_Ctrl::add_hwcstring (const char *string, char **warnmsg) int rc = 0; int old_cnt = hwcprof_enabled_cnt; int prev_cnt = hwcprof_enabled_cnt; - // int old_hwcprof_default = hwcprof_default; - char UEbuf[MAXPATHLEN * 5]; - int UEsz; Hwcentry tmpctr[MAX_PICS]; Hwcentry * ctrtable[MAX_PICS]; char *emsg; char *wmsg; - UEbuf[0] = 0; - UEsz = sizeof (UEbuf); if (opened == 1) return strdup (GTXT ("Experiment is active; command ignored.\n")); if (hwcprof_default == 0) @@ -1468,7 +1386,7 @@ Coll_Ctrl::add_hwcstring (const char *string, char **warnmsg) for (int ii = 0; ii < prev_cnt; ii++) tmpctr[ii] = hwctr[ii]; } - else /* the previously-defined counters were defaulted; don't copy them */ + else /* the previously-defined counters were defaulted; don't copy them */ prev_cnt = 0; /* look up the CPU version */ @@ -1509,22 +1427,28 @@ Coll_Ctrl::add_hwcstring (const char *string, char **warnmsg) hwcprof_default = 0; hwcprof_enabled_cnt = rc; free (hwc_string); + StringBuilder sb; for (int ii = 0; ii < hwcprof_enabled_cnt; ii++) { /* shallow copy of new counters */ hwctr[ii] = tmpctr[ii]; char *rateString = hwc_rate_string (&hwctr[ii], 0); - snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf), - NTXT (",%s,%s"), hwctr[ii].name, - rateString ? rateString : ""); - free (rateString); + if (ii > 0) + sb.append (','); + sb.append (hwctr[ii].name); + sb.append (','); + if (rateString) + { + sb.append (rateString); + free (rateString); + } } - /* now duplicate that string, skipping the leading comma */ - hwc_string = strdup (&UEbuf[1]); + hwc_string = sb.toString (); return NULL; } /* add default HWC counters to counter set with resolution (on, hi, or lo) */ + /* Note that the resultion will also be used to set the clock-profiling default */ char * /* return an error string */ Coll_Ctrl::add_default_hwcstring (const char *resolution, char **warnmsg, bool add, bool forKernel) @@ -1591,7 +1515,7 @@ Coll_Ctrl::add_default_hwcstring (const char *resolution, char **warnmsg, bool a strncat (retp, stringp, (retsize - strlen (retp) - 1)); strncat (retp, ",", (retsize - strlen (retp) - 1)); strncat (retp, resolution, (retsize - strlen (retp) - 1)); - if (nextc == 0) /* string ended in comma; we're done */ + if (nextc == 0) /* string ended in comma; we're done */ break; } else @@ -1606,7 +1530,7 @@ Coll_Ctrl::add_default_hwcstring (const char *resolution, char **warnmsg, bool a } /* string had ,, between fields; move to next field */ stringp = next + 1; - if (* (stringp + 1) == 0) /* name ended in ,, -- we're done */ + if (* (stringp + 1) == 0) /* name ended in ,, -- we're done */ break; continue; } @@ -1765,10 +1689,10 @@ Coll_Ctrl::build_data_desc () if (ii > 0) sb.append (','); sb.appendf ("%d:%d:%lld:%s:%s:%lld:%d:m%lld:%d:%d:0x%x", - h->use_perf_event_type, h->type, (long long) h->config, - strcmp (h->name, h->int_name) ? h->name : "", - h->int_name, (long long) h->reg_num, h->val, - (long long) min_time, ii, /*tag*/ h->timecvt, h->memop); + h->use_perf_event_type, h->type, (long long) h->config, + strcmp (h->name, h->int_name) ? h->name : "", + h->int_name, (long long) h->reg_num, h->val, + (long long) min_time, ii, /*tag*/ h->timecvt, h->memop); } sb.append (";"); } @@ -1801,7 +1725,7 @@ Coll_Ctrl::check_group () // Is the group an relative path, with a store directory set? if ((expt_group[0] == '/') || ((udir_name == NULL) || (udir_name[0] == '0'))) snprintf (group_file, sizeof (group_file), "%s", expt_group); - else // relative path, store directory; make group_file in that directory + else // relative path, store directory; make group_file in that directory snprintf (group_file, sizeof (group_file), "%s/%s", udir_name, expt_group); // See if we can write the group file int ret = access (group_file, W_OK); @@ -1814,11 +1738,11 @@ Coll_Ctrl::check_group () ret = access (dir, W_OK); if (ret != 0) // group file does not exist; return dbe_sprintf (GTXT ("Directory (%s) for group file %s is not writeable: %s\n"), - dir, group_file, strerror (errno)); + dir, group_file, strerror (errno)); } else return dbe_sprintf (GTXT ("Group file %s is not writeable: %s\n"), - group_file, strerror (errno)); + group_file, strerror (errno)); } return NULL; } @@ -1841,8 +1765,8 @@ Coll_Ctrl::join_group () // Is the group an relative path, with a store directory set? if (expt_group[0] == '/' || udir_name == NULL || udir_name[0] == '0') snprintf (group_file, sizeof (group_file), "%s", expt_group); - else // relative path, store directory; make group_file in that directory - snprintf (group_file, sizeof (group_file), "%s/%s", udir_name, expt_group); + else // relative path, store directory; make group_file in that directory + snprintf (group_file, sizeof (group_file), "%s/%s", udir_name, expt_group); for (;;) { tries++; @@ -1910,7 +1834,7 @@ Coll_Ctrl::join_group () // If the error was not that the file did not exist, report it if (errno != ENOENT) return dbe_sprintf (GTXT ("Can't open group file %s: %s\n"), - group_file, strerror (errno)); + group_file, strerror (errno)); // the file did not exist, try to create it groupfd = open (group_file, O_CREAT | O_EXCL | O_RDWR, 0666); if (groupfd < 0) @@ -1919,7 +1843,7 @@ Coll_Ctrl::join_group () if (errno == EEXIST) continue; return dbe_sprintf (GTXT ("Can't create group file %s: %s\n"), - group_file, strerror (errno)); + group_file, strerror (errno)); } // we created the group file, now lock it, waiting for the lock while (fcntl (groupfd, F_SETLKW, &flockbuf) == -1) @@ -1989,7 +1913,7 @@ Coll_Ctrl::set_directory (char *dir, char **warn) } else (void) update_expt_name (false, false); - return NULL; // All is OK + return NULL; // All is OK } int @@ -2020,7 +1944,7 @@ Coll_Ctrl::set_expt (const char *ename, char **warn, bool overwriteExp) uexpt_name = NULL; return NULL; } - char *exptname = canonical_path(strdup(ename)); + char *exptname = canonical_path (strdup (ename)); size_t i = strlen (exptname); if (i < 4 || strcmp (&exptname[i - 3], ".er") != 0) { @@ -2116,7 +2040,7 @@ Coll_Ctrl::set_java_mode (const char *string) java_default = prev_java_default; return ret; } - free (java_path); + free (java_path); java_path = NULL; return NULL; } @@ -2240,11 +2164,6 @@ Coll_Ctrl::set_follow_mode (const char *string) return NULL; } // syntax error in parsing string -#if 0 - char errbuf[256]; - regerror (ercode, ®ex_desc, errbuf, sizeof (errbuf)); - fprintf (stderr, "Coll_Ctrl::set_follow_mode: regerror()=%s\n", errbuf); -#endif free (str); } return dbe_sprintf (GTXT ("Unrecognized follow-mode parameter `%s'\n"), string); @@ -2397,23 +2316,23 @@ Coll_Ctrl::create_exp_dir () int err = errno; if (err == EACCES) return dbe_sprintf (GTXT ("Store directory %s is not writeable: %s\n"), - store_dir, strerror (err)); + store_dir, strerror (err)); if (i + 1 >= max) // no more attempts return dbe_sprintf (GTXT ("Unable to create directory `%s' -- %s\n%s: %d\n"), - store_ptr, strerror (err), - GTXT ("collect: Internal error: loop count achieved"), - max); + store_ptr, strerror (err), + GTXT ("collect: Internal error: loop count achieved"), + max); char *ermsg = update_expt_name (false, false, true); if (ermsg != NULL) { char *msg = dbe_sprintf (GTXT ("Unable to create directory `%s' -- %s\n"), - store_ptr, ermsg); + store_ptr, ermsg); free (ermsg); return msg; } continue; } - return NULL; // All is OK + return NULL; // All is OK } return dbe_sprintf (GTXT ("Unable to create directory `%s'\n"), store_ptr); } @@ -2428,9 +2347,7 @@ Coll_Ctrl::get_exp_name (const char *stembase) char * Coll_Ctrl::preprocess_names () { - char buf[MAXPATHLEN]; - char msgbuf[MAXPATHLEN]; - char *ret = NULL; + StringBuilder sb; /* convert the experiment name and directory into store name/dir */ /* free the old strings */ @@ -2492,34 +2409,23 @@ Coll_Ctrl::preprocess_names () expt_name = c; free (stem); } - snprintf (buf, sizeof (buf), NTXT ("%s"), expt_name); - if (buf[0] == '/') - { - // it's a full path name - if (udir_name != NULL) - { - snprintf (msgbuf, sizeof (msgbuf), - GTXT ("Warning: Experiment name is an absolute path; directory name %s ignored.\n"), - udir_name); - ret = strdup (msgbuf); - } - } + if (*expt_name == '/' && udir_name != NULL) + sb.appendf (GTXT ("Warning: Experiment name is an absolute path; directory name %s ignored.\n"), + udir_name); // now extract the directory and basename - int lastslash = 0; - for (int i = 0;; i++) + char *s = strrchr (expt_name, '/'); + if (s == NULL) { - if (buf[i] == 0) - break; - if (buf[i] == '/') - lastslash = i; + expt_dir = strdup ("."); + base_name = strdup (expt_name); } - expt_dir = strdup (buf); - if (lastslash != 0) - base_name = strdup (&buf[lastslash + 1]); else - base_name = strdup (buf); - expt_dir[lastslash] = 0; + { + expt_dir = dbe_strndup (expt_name, s - expt_name - 1); + base_name = strdup (s + 1); + } + if (expt_dir[0] == '/') store_dir = strdup (expt_dir); else if ((udir_name == NULL) || (udir_name[0] == 0)) @@ -2535,19 +2441,13 @@ Coll_Ctrl::preprocess_names () if (expt_dir[0] == 0) store_dir = strdup (udir_name); else - { - snprintf (buf, sizeof (buf), "%s/%s", udir_name, expt_dir); - store_dir = strdup (buf); - } + store_dir = dbe_sprintf ("%s/%s", udir_name, expt_dir); } free (store_ptr); if (strcmp (store_dir, ".") == 0) store_ptr = strdup (base_name); else - { - snprintf (buf, sizeof (buf), "%s/%s", store_dir, base_name); - store_ptr = strdup (buf); - } + store_ptr = dbe_sprintf ("%s/%s", store_dir, base_name); // determine the file system type if (strcmp (store_dir, prev_store_dir) != 0) @@ -2556,15 +2456,13 @@ Coll_Ctrl::preprocess_names () prev_store_dir = strdup (store_dir); const char *fstype = get_fstype (store_dir); if (interactive && enabled && (fstype != NULL) && (nofswarn == 0)) - { - snprintf (msgbuf, sizeof (msgbuf), - GTXT ("%sExperiment directory is set to a file system of type \"%s\",\n which may distort the measured performance;\n it is preferable to record to a local disk.\n"), - (ret == NULL ? "" : ret), fstype); - free (ret); - ret = strdup (msgbuf); - } + sb.appendf (GTXT ("Experiment directory is set to a file system of type \"%s\",\n" + " which may distort the measured performance;\n" + " it is preferable to record to a local disk.\n"), fstype); } - return ret; + if (sb.length () == 0) + return NULL; + return sb.toString (); } char * @@ -2600,15 +2498,15 @@ Coll_Ctrl::update_expt_name (bool chgmsg, bool chkonly, bool newname) while (isdigit ((int) (base_name[pcount])) != 0) { pcount--; - if (pcount == 0) // name is of the form 12345.er; don't update it + if (pcount == 0) // name is of the form 12345.er; don't update it return dbe_sprintf (GTXT ("name %s is in use and cannot be updated\n"), - base_name); + base_name); digits++; } - if (digits == 0) // name is of form xyz.er (or xyz..er); don't update it + if (digits == 0) // name is of form xyz.er (or xyz..er); don't update it return dbe_sprintf (GTXT ("name %s is in use and cannot be updated\n"), base_name); - if (base_name[pcount] != '.') // name is of form xyz123.er; don't update it + if (base_name[pcount] != '.') // name is of form xyz123.er; don't update it return dbe_sprintf (GTXT ("name %s is in use and cannot be updated\n"), base_name); if (chkonly) @@ -2619,7 +2517,7 @@ Coll_Ctrl::update_expt_name (bool chgmsg, bool chkonly, bool newname) // the name is of the from prefix.nnn.er; extract the value of nnn int version = atoi (&base_name[pcount + 1]); - if (newname) // do not try to use old name + if (newname) // do not try to use old name version++; int max_version = version - 1; @@ -2664,7 +2562,7 @@ Coll_Ctrl::update_expt_name (bool chgmsg, bool chkonly, bool newname) if ((strcmp (oldbase, newbase) != 0) && chgmsg) { ret = dbe_sprintf (GTXT ("name %s is in use; changed to %s\n"), - oldbase, newbase); + oldbase, newbase); free (oldbase); } else @@ -2730,17 +2628,17 @@ Coll_Ctrl::determine_profile_params () // now reset the timer to turn it off itimer.it_value.tv_sec = 0; itimer.it_value.tv_usec = 0; - if (setitimer (ITIMER_REALPROF, &itimer, &otimer) == -1) // call failed + if (setitimer (ITIMER_REALPROF, &itimer, &otimer) == -1) // call failed nperiod = -1; else nperiod = otimer.it_interval.tv_sec * MICROSEC + otimer.it_interval.tv_usec; // check the returned value: is the what we asked for? - if (period == nperiod) // arbitrary precision is OK + if (period == nperiod) // arbitrary precision is OK set_clk_params (PROFINT_MIN, 1, PROFINT_MAX, PROFINT_HIGH, PROFINT_NORM, PROFINT_LOW); else if (nperiod < 10000) // hi resolution allowed, but not arbitrary precision set_clk_params ((int) nperiod, 1000, PROFINT_MAX, 1000, 10000, 100000); - else // low resolution only allowed + else // low resolution only allowed set_clk_params (10000, 10000, PROFINT_MAX, 1000, 10000, 100000); // If old handler was default, ignore it; otherwise restore it @@ -2791,7 +2689,7 @@ const char *ipc_str_synctrace = "synctrace"; const char *ipc_str_heaptrace = "heaptrace"; const char *ipc_str_iotrace = "iotrace"; const char *ipc_str_count = "count"; -const char *ipc_str_prof_idle = "prof_idle"; // -x option +const char *ipc_str_prof_idle = "prof_idle"; // -x option // Standard answers const char *ipc_str_empty = ""; const char *ipc_str_on = "on"; @@ -2870,7 +2768,7 @@ Coll_Ctrl::get (char * control) } if (!strncmp (control, ipc_str_clkprof, len)) { - if (clkprof_default == 1 && clkprof_enabled == 1) // Default value + if (clkprof_default == 1 && clkprof_enabled == 1) // Default value return strdup (ipc_str_empty); if (clkprof_enabled == 0) return strdup (ipc_str_off); @@ -2894,7 +2792,7 @@ Coll_Ctrl::get (char * control) } if (!strncmp (control, ipc_str_sample, len)) { - if (sample_default == 1 && sample_period == 1) // Default value + if (sample_default == 1 && sample_period == 1) // Default value return strdup (ipc_str_empty); if (sample_period == 0) return strdup (ipc_str_off); diff --git a/gprofng/src/collctrl.h b/gprofng/src/collctrl.h index 5f1ee26d902..a41647440ac 100644 --- a/gprofng/src/collctrl.h +++ b/gprofng/src/collctrl.h @@ -87,7 +87,6 @@ public: void set_clk_params(int min, int res, int max, int hi, int norm, int lo); char *set_clkprof(const char *valptr, char **warn); char *reset_clkprof(int val); /* called if profiler must reset value */ - int get_sys_period() { return clk_params.min; }; int get_clk_min() { return clk_params.min; }; int get_clk_max() { return clk_params.max; }; int get_clk_res() { return clk_params.res; }; @@ -275,7 +274,6 @@ private: int cpu_clk_freq; /* chip clock (MHz.), as reported from processor_info */ int cpc_cpuver; /* chip version, as reported from libcpc */ long sys_resolution; /* system clock resolution */ - int sys_period; /* profiling clock resolution on the system */ int sample_period; /* period for sampling, seconds */ int sample_default; /* if period for sampling set by default */ int size_limit; /* experiment size limit, MB */