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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5733becfb83sm11779679a12.46.2024.05.17.02.56.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 May 2024 02:56:38 -0700 (PDT) Message-ID: <68187afc-efbf-41e5-a840-2ee487f4d5b3@suse.com> Date: Fri, 17 May 2024 11:56:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 1/2] x86: correct VCVT{,U}SI2SD Content-Language: en-US From: Jan Beulich To: Binutils Cc: "H.J. Lu" References: <0875913a-e23f-4482-b5a0-1e6796fe42d4@suse.com> Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <0875913a-e23f-4482-b5a0-1e6796fe42d4@suse.com> X-Spam-Status: No, score=-3024.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Properly reject inappropriate suffixes (No_lSuf / No_qSuf mistakenly omitted by cf665fee1d6c ["x86: re-work AVX512 embedded rounding / SAE"]), to avoid emitting bad or arbitrarily guessed instructions. Interestingly check_{long,qword}_suffix() don't help here, which perhaps is another indication that the way they work right now isn't quite appropriate. Sadly correcting just the templates breaks operand ambiguity detection, since so far that worked from a single template permitting more than one suffix. Here we have ambiguity though which can now be noticed only when taking all (matching) templates together. Therefore we need to determine further matching templates (see code comments for constraints), to then accumulate permitted suffixes across all of them. --- To avoid such mistakes an option would be to derive No_?Suf from GPR operands (where possible and applicable, i.e. while still permitting them to be set explicitly). --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -172,7 +172,7 @@ static void optimize_imm (void); static bool optimize_disp (const insn_template *t); static const insn_template *match_template (char); static int check_string (void); -static int process_suffix (void); +static int process_suffix (const insn_template *); static int check_byte_reg (void); static int check_long_reg (void); static int check_qword_reg (void); @@ -6949,7 +6949,7 @@ md_assemble (char *line) if (use_unaligned_vector_move) encode_with_unaligned_vector_move (); - if (!process_suffix ()) + if (!process_suffix (t)) return; /* Check if IP-relative addressing requirements can be satisfied. */ @@ -8361,12 +8361,16 @@ check_VecOperands (const insn_template * if (operand_type_check (i.types[op], disp) && i.op[op].disps->X_op == O_constant) { + /* Make sure to leave i.types[op].bitfield.disp8 alone upon + secondary invocations of match_template(). */ if (fits_in_disp8 (i.op[op].disps->X_add_number)) { - i.types[op].bitfield.disp8 = 1; + if (!i.tm.mnem_off) + i.types[op].bitfield.disp8 = 1; return 0; } - i.types[op].bitfield.disp8 = 0; + if (!i.tm.mnem_off) + i.types[op].bitfield.disp8 = 0; } } @@ -9184,6 +9188,11 @@ match_template (char mnem_suffix) return NULL; } + /* Don't emit diagnostics or install the template when one was already + installed, i.e. when called from process_suffix(). */ + if (i.tm.mnem_off) + return t; + if (!quiet_warnings) { if (!intel_syntax @@ -9290,7 +9299,7 @@ check_string (void) } static int -process_suffix (void) +process_suffix (const insn_template *t) { bool is_movx = false; @@ -9465,6 +9474,39 @@ process_suffix (void) if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) suffixes |= 1 << 5; + /* Operand size may be ambiguous only across multiple templates. Avoid + the extra effort though if we already know that multiple suffixes / + operand sizes are allowed. Also limit this to non-SIMD operand sizes + (i.e. ones expressable via suffixes) for now. + There's one special case though that needs excluding: Insns taking + Disp operands also match templates permitting BaseIndex. JMP in + particular would thus wrongly trigger the check further down. Cover + JUMP_DWORD insns here as well, just in case. */ + if (i.tm.opcode_modifier.jump != JUMP + && i.tm.opcode_modifier.jump != JUMP_DWORD) + while (!(suffixes & (suffixes - 1))) + { + /* Sadly check_VecOperands(), running ahead of install_template(), + may update i.memshift. Save and restore the value here. */ + unsigned int memshift = i.memshift; + + current_templates.start = t + 1; + t = match_template (0); + i.memshift = memshift; + if (t == NULL) + break; + if (!t->opcode_modifier.no_bsuf) + suffixes |= 1 << 0; + if (!t->opcode_modifier.no_wsuf) + suffixes |= 1 << 1; + if (!t->opcode_modifier.no_lsuf) + suffixes |= 1 << 2; + if (!t->opcode_modifier.no_ssuf) + suffixes |= 1 << 4; + if (flag_code == CODE_64BIT && !t->opcode_modifier.no_qsuf) + suffixes |= 1 << 5; + } + /* For [XYZ]MMWORD operands inspect operand sizes. While generally also suitable for AT&T syntax mode, it was requested that this be restricted to just Intel syntax. */ --- a/gas/testsuite/gas/i386/x86-64-inval-avx512f.l +++ b/gas/testsuite/gas/i386/x86-64-inval-avx512f.l @@ -41,6 +41,8 @@ .*:58: Error: .* .*:61: Error: .*unsupported broadcast for `vdpbf16ps' .*:62: Error: .*unsupported broadcast for `vcvtne2ps2bf16' +.*:64: Error: .* `vcvtusi2sd' +.*:65: Error: .* `vcvtusi2sd' GAS LISTING .* @@ -107,3 +109,7 @@ GAS LISTING .* [ ]*60[ ]+\.att_syntax prefix [ ]*61[ ]+vdpbf16ps 8\(%rax\)\{1to8\}, %zmm2, %zmm2 [ ]*62[ ]+vcvtne2ps2bf16 8\(%rax\)\{1to8\}, %zmm2, %zmm2 +[ ]*63[ ]* +[ ]*64[ ]+vcvtusi2sdq %eax, %xmm0, %xmm0 +[ ]*65[ ]+vcvtusi2sdl %rax, \{rn-sae\}, %xmm0, %xmm0 +#pass --- a/gas/testsuite/gas/i386/x86-64-inval-avx512f.s +++ b/gas/testsuite/gas/i386/x86-64-inval-avx512f.s @@ -60,3 +60,6 @@ _start: .att_syntax prefix vdpbf16ps 8(%rax){1to8}, %zmm2, %zmm2 vcvtne2ps2bf16 8(%rax){1to8}, %zmm2, %zmm2 + + vcvtusi2sdq %eax, %xmm0, %xmm0 + vcvtusi2sdl %rax, {rn-sae}, %xmm0, %xmm0 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2366,14 +2366,14 @@ vcvts2usi, 0x79, X-Patchwork-Id: 90364 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 39BDD3849AE3 for ; Fri, 17 May 2024 09:57:31 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by sourceware.org (Postfix) with ESMTPS id E5D37384CB97 for ; Fri, 17 May 2024 09:56:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E5D37384CB97 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=suse.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E5D37384CB97 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::535 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715939818; cv=none; b=rFpWqzmajFi4tqt64WdkrZqYlPnLUgOJSqHXOwFm/V2mI1fWglB4Mm+39D322bSH8WuRuI69g6+sDtVyxrkvnOcRL/x9jooRkb8VYj7ubi5RZUWk6Sk7TJalFIvud6WlSnDfSa/l4GwVygvkWRDEN+mMWKzkI33r6ZieIFgeS7Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715939818; c=relaxed/simple; bh=M02lNMuJonjm28dTMXCzH6ECeyRaxHC2jrPU36S6avs=; h=DKIM-Signature:Message-ID:Date:MIME-Version:Subject:From:To; b=KZL2s9SL5hDupHocSaexyUU3s9kLmMSfVqspXQFeqoG6VFBnsF/NBDugROnzRlWnvWlitphyepLjhAk1b7SffETZM0FxIR68fM4/s/7GqWLiU4ZPkQoZ+qSOn1LXaD2C6HGm5kmn8ZVvLuPBB+65p4IpWUJ2E97BiGje7Iwpfg8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-572e48f91e9so4962515a12.0 for ; Fri, 17 May 2024 02:56:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1715939815; x=1716544615; darn=sourceware.org; h=content-transfer-encoding:in-reply-to:autocrypt:references:cc:to :from:content-language:subject:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=A8StMbnHOu/VAs2snZ3E08Frb8Jhg++zOVuxkensfpQ=; b=JNRvOyIq8TnfYzlBHQqRoV5p6PBAYSNPH1XrDkc9Ccu/qf+SRyLQaqdb1NzCNYNht6 c0yh6f4gvTLvc6R/HALE3ctabNNAlInoKOOdR+qcrrxxcZK6d2LpkDWBeyi+BPlTq2Px RhqKCaEtp7no1vAHN4BOo6J7h8XNOh+080vEpWpADXUkuESifLX7T8XXYBJXvD774ZFS k1KXtl7HjEw2frUjTv8kUkZynIwYbyPPzWJegl7JqdMN5Xl+WzQpuSz/efeBf8wQ3ad6 ARVr4w7cPiuZH/xNzWQjMcC5vHH+1pqu84H32fisqLhN9C9h0z426Q3wfVlD4gTDvQjp jKMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715939815; x=1716544615; h=content-transfer-encoding:in-reply-to:autocrypt:references:cc:to :from:content-language:subject:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=A8StMbnHOu/VAs2snZ3E08Frb8Jhg++zOVuxkensfpQ=; b=qZerWy6I6VTDbcjx3YTrgM5+s6mz5oBeA/O0PbBXLGC1RHqnwN+oFKoLAVV0Ur0bKy ubDoDr+9X3zLNr+5n5KCieTHUKwMQSl6MIaZM6oOZg0Fd/WQKjDUnzTdAatjgALMMmK4 ShVxFGXukcteRc+lNHaKti8rHNHENu9lnVy6h3/OoNswWUJrasbTK9x7TEDnBt6QS/Tw K6PFkrM/ch2ycFUvZebXxZTYstJIeVXQdrWsf8aRRU4+UF6hUPOiXCNFbOvRAmGI3PtZ JT7JGAvHD7dgZwDQaY9KO4lRDGXuGgqH/4aQWCwXQHwzZavaEatYoCwjxIOYyZ1FvS1s lubw== X-Gm-Message-State: AOJu0YzIbC78NhupMxsymmFvbUEvRuWHm7v4sKnN1LjanQeyt1GiMknd dfyB7dgih9M0mI7gVjnhl5+729jrGJZYPYdrt6W90ikOSXPel4bAb4T0lYVUdRzHqur22qcZedg = X-Google-Smtp-Source: AGHT+IFPIOcHvEINJYHIrRCnQBSmHQsXGuSLvAFs4hCaZebVWjJ70z2ez14Ux/nbPHlMUraJOdDASw== X-Received: by 2002:a50:8d50:0:b0:572:6ae4:a9ac with SMTP id 4fb4d7f45d1cf-5734d5e35d6mr15912656a12.21.1715939815404; Fri, 17 May 2024 02:56:55 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. [37.24.206.209]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5733becfb83sm11779679a12.46.2024.05.17.02.56.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 May 2024 02:56:55 -0700 (PDT) Message-ID: <08b4693f-c588-4e72-bff9-909a808c80ea@suse.com> Date: Fri, 17 May 2024 11:56:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 2/2] x86: simplify / consolidate check_{word, long, qword}_reg() Content-Language: en-US From: Jan Beulich To: Binutils Cc: "H.J. Lu" References: <0875913a-e23f-4482-b5a0-1e6796fe42d4@suse.com> Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <0875913a-e23f-4482-b5a0-1e6796fe42d4@suse.com> X-Spam-Status: No, score=-3024.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org These run after template matching. Therefore operands are already known to match the template in use. With the loop bodies skipping anything not a GPR in the actual operands, there's therefore no need to check the template's operand type for permitting Reg or Accum. At the same time bring the three functions in sync for the "byte" part of the logic, as far as checking the template for other sizes (qword specifically) goes. Plus drop a stale comment from check_qword_reg(), when all three are now behaving the same in this regard. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -9867,10 +9867,9 @@ check_long_reg (void) /* Reject eight bit registers, except where the template requires them. (eg. movzb) */ else if (i.types[op].bitfield.byte - && (i.tm.operand_types[op].bitfield.class == Reg - || i.tm.operand_types[op].bitfield.instance == Accum) && (i.tm.operand_types[op].bitfield.word - || i.tm.operand_types[op].bitfield.dword)) + || i.tm.operand_types[op].bitfield.dword + || i.tm.operand_types[op].bitfield.qword)) { as_bad (_("`%s%s' not allowed with `%s%c'"), register_prefix, @@ -9883,8 +9882,6 @@ check_long_reg (void) prefix on a general reg is present. */ else if ((i.types[op].bitfield.word || i.types[op].bitfield.qword) - && (i.tm.operand_types[op].bitfield.class == Reg - || i.tm.operand_types[op].bitfield.instance == Accum) && i.tm.operand_types[op].bitfield.dword) { as_bad (_("incorrect register `%s%s' used with `%c' suffix"), @@ -9907,8 +9904,6 @@ check_qword_reg (void) /* Reject eight bit registers, except where the template requires them. (eg. movzb) */ else if (i.types[op].bitfield.byte - && (i.tm.operand_types[op].bitfield.class == Reg - || i.tm.operand_types[op].bitfield.instance == Accum) && (i.tm.operand_types[op].bitfield.word || i.tm.operand_types[op].bitfield.dword || i.tm.operand_types[op].bitfield.qword)) @@ -9923,12 +9918,8 @@ check_qword_reg (void) /* Error if the r prefix on a general reg is missing. */ else if ((i.types[op].bitfield.word || i.types[op].bitfield.dword) - && (i.tm.operand_types[op].bitfield.class == Reg - || i.tm.operand_types[op].bitfield.instance == Accum) && i.tm.operand_types[op].bitfield.qword) { - /* Prohibit these changes in the 64bit mode, since the - lowering is more complicated. */ as_bad (_("incorrect register `%s%s' used with `%c' suffix"), register_prefix, i.op[op].regs->reg_name, i.suffix); return 0; @@ -9947,10 +9938,9 @@ check_word_reg (void) /* Reject eight bit registers, except where the template requires them. (eg. movzb) */ else if (i.types[op].bitfield.byte - && (i.tm.operand_types[op].bitfield.class == Reg - || i.tm.operand_types[op].bitfield.instance == Accum) && (i.tm.operand_types[op].bitfield.word - || i.tm.operand_types[op].bitfield.dword)) + || i.tm.operand_types[op].bitfield.dword + || i.tm.operand_types[op].bitfield.qword)) { as_bad (_("`%s%s' not allowed with `%s%c'"), register_prefix, @@ -9962,8 +9952,6 @@ check_word_reg (void) /* Error if the e or r prefix on a general reg is present. */ else if ((i.types[op].bitfield.dword || i.types[op].bitfield.qword) - && (i.tm.operand_types[op].bitfield.class == Reg - || i.tm.operand_types[op].bitfield.instance == Accum) && i.tm.operand_types[op].bitfield.word) { as_bad (_("incorrect register `%s%s' used with `%c' suffix"),