From patchwork Fri May 17 04:07:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Mezentsev X-Patchwork-Id: 90316 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 29765384AB6C for ; Fri, 17 May 2024 04:08:45 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mx0b-00069f02.pphosted.com (mx0b-00069f02.pphosted.com [205.220.177.32]) by sourceware.org (Postfix) with ESMTPS id 775993858D20 for ; Fri, 17 May 2024 04:08:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 775993858D20 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=oracle.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oracle.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 775993858D20 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=205.220.177.32 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1715918894; cv=pass; b=vyXzrnHkGhIbSUFkn5HMf5g1kVupB/OR1r7q6oFkDV0q+R2EPvicYv2t7sqFLWEvx8k6X0m4eSrAGTYcwstvKMdEBhqkuoqknITUD6tEhlhO9Go4u9fszi6wSXiQtRwGR1ztVTm9TqdZRzN9VSHs6zQFzA9suelnj3JRXVaX2sg= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1715918894; c=relaxed/simple; bh=AduyXvBRPB2tHdoStGWTx0uF7tmW/9CKpTtT8c60WMw=; h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-Id: MIME-Version; b=eZHAt98bfFIsnC5mFALCZs4leW4Q7oRWBBmp4xa6Tqi2zIClheMrrsfhAiOoqTRi3gZTKNM/erquN18kRXDCZyK6YFcLeEi65x5yVHj9P1n6m3dM27gCfhOTaFGlBpS9hGsgDhs0UCtqtgc/HK3ZzTxZZ14/39qFilViOJsauHQ= ARC-Authentication-Results: i=2; server2.sourceware.org Received: from pps.filterd (m0246632.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 44GNOVCI026360 for ; Fri, 17 May 2024 04:08:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : content-transfer-encoding : content-type : mime-version; s=corp-2023-11-20; bh=CHSCgTZjhZVN54dAXJa6yd15e/aYdgtIbvlxVk0MfuU=; b=AR6ooOa66pQgPkcwsrEZdgdA6CQ5CE8l8t81uYGi7TTp0NkR1lhG1TAVJLgFnsRaf6T4 tkZirX7MJGP47ZKjhzR80rx38mZIXyGtwvg8D4ECjYZWeGR2HXtqFXep5u26i21l0UAF sptGDYgNDNrr87er2uRtWr4VPyd/77vMAgVTpDjgzKNNoPflfbTHGvQAuye9Y1SlqJvt KAiHPo2tMTSEjP/hmWPC2n4IK0ZpwIsvijarUpADq2vhECBh2eKVlaT/N77+MhS2A6mn Ye3cAQaG0gRQFupWtophSf6tCOoRftiCyT0ldxNtSmHd9WtVBaQOdd86duEn2kQflD33 Cw== Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.appoci.oracle.com [138.1.114.2]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3y3tx38q4k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Fri, 17 May 2024 04:08:07 +0000 Received: from pps.filterd (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (8.17.1.19/8.17.1.19) with ESMTP id 44H1UVpp038379 for ; Fri, 17 May 2024 04:08:06 GMT Received: from nam10-mw2-obe.outbound.protection.outlook.com (mail-mw2nam10lp2101.outbound.protection.outlook.com [104.47.55.101]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTPS id 3y24q0uef0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Fri, 17 May 2024 04:08:06 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=l1ii8BmGerRGdvwy4gIR8tBvGvqZ+5ap44lEQMypB15tj1Qxyqjcau6fSzZdaIlOuphO9OSuvqSuinWChDmUimHCoG/BTAH5N0APH2N8YrkQBJdqJkVf83LCZhN9TVShD1GXReTanrfJp0yVyWBHBDq5TAKtWGwXiwlyBLirz3Gljd5PwvokDpLvMcFUv9D7oNOGu61v/u1usffRRiROPO81BuNNlv9S/0zQ82Ge/gim9fqCZYcv/+1BSE8XnXl2MY08eieLaVpn1rj3JsIiynaFViffy2LA6WlDRGOcG6fkQ52CEltWY22TO8USD7VRk2xU3ow8Rhi4eu5Ugjjl0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=CHSCgTZjhZVN54dAXJa6yd15e/aYdgtIbvlxVk0MfuU=; b=gE26U47EYZ299gQvkRk/ZtcQjG9OBiL7EPl1aGyXrIwOlIw4DkVXMt4TkXL9h+rboI+dGCD6wk6G4klme3gLhvUWtMaojbTWm4AQMt7rXHkHsje9JuYxd3IvLB/685uEEf2WH5GNi3e6r49l3R+Qgxsf4XNM6fp9ZbyNhlXh6O6RHcm+H8fuQrbehVVn7seCwz3PhyEMGhHSm1cUygAoFa99Q1jiAXDC+GxRk9wxzLEb8HOGbpNyRWxuW4FPDmrwwkThk7FAcBJR4h55vsHxRJOyaoCRz9kv3yK+St4Ocaeb6Aw3juALetYOzin3xLP44QQM7ka8YMVpXp5hQmIgtg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oracle.com; dmarc=pass action=none header.from=oracle.com; dkim=pass header.d=oracle.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.onmicrosoft.com; s=selector2-oracle-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CHSCgTZjhZVN54dAXJa6yd15e/aYdgtIbvlxVk0MfuU=; b=i80/165aK9ARfWRBZKZpKPcss+9zOeBMS3fYqQF0KA7dYHBzC8rloNQwhzskxZY5Pbj0BL9i50hbZb6gtVQQTO9zfhygVqGkrwqL9DybKlwhkssvqT5EqASACjy9DZqYN8E0HZ7iZoqobVZ4DsDScWdOFc/PvUzsgaPVdNYUKwg= Received: from SA2PR10MB4636.namprd10.prod.outlook.com (2603:10b6:806:11e::10) by PH7PR10MB6602.namprd10.prod.outlook.com (2603:10b6:510:206::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7587.27; Fri, 17 May 2024 04:08:04 +0000 Received: from SA2PR10MB4636.namprd10.prod.outlook.com ([fe80::1b3d:bd64:9100:c3fb]) by SA2PR10MB4636.namprd10.prod.outlook.com ([fe80::1b3d:bd64:9100:c3fb%7]) with mapi id 15.20.7587.028; Fri, 17 May 2024 04:08:03 +0000 From: vladimir.mezentsev@oracle.com To: binutils@sourceware.org Cc: Vladimir Mezentsev Subject: [PATCH 1/2] gprofng: remove old interface with libcpc Date: Thu, 16 May 2024 21:07:56 -0700 Message-Id: <20240517040756.2663399-1-vladimir.mezentsev@oracle.com> X-Mailer: git-send-email 2.31.1 X-ClientProxiedBy: SJ0PR05CA0077.namprd05.prod.outlook.com (2603:10b6:a03:332::22) To SA2PR10MB4636.namprd10.prod.outlook.com (2603:10b6:806:11e::10) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PR10MB4636:EE_|PH7PR10MB6602:EE_ X-MS-Office365-Filtering-Correlation-Id: 5511df5b-703e-46d4-5452-08dc7626f2d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|1800799015|376005; X-Microsoft-Antispam-Message-Info: TbOkfda23NXVvFswhHOtNjj/ggHccPYPJjxLJkIloaLF2X8jNo3w4Rs6lfpK1IpmGTMANDT3t6ydoxFYlXdXovDCnbAeTjZB4tR+bhc6Q8gxtf57pgKxLQe2OyiHIQAJvFLYgNDZwHfOelX4pzUCUcZUTC5yKey3G0DIDwR2ixTj12la66zhhZxg/ZoE5sUUdCcbPSpyJ0P8X84F66i93JoUY19R0JXSB7mKGE8Lk667TYfkE4vle6JD6GVfUqggSvS/7OkzICREbJQsj2Fcq5wCEdJt8XrVDBCBgytSsLMXBL8RLCx5/If1SYtTSRsEpp4RXBYUDjTsATN6qMt3ebHw4CHFsoHZHWueeZbnXYRdKeQupV2dhxbqUywZ9snOB1iQkirnxvFddds2+oSJ4APELTO7KPDvxxpvILqnanMg9JRvivUR/c8UZ81SGLgKv/dKAce6Ufr3hYdoXwYlkoN6Wm0QbOGPC0JwKrMNu3+ZbbzBvDxyUrEkMNE+JMtZI3DRN30/wiXsriiladO+AOoS0LBBTEtSuxLpUwW9ot4mFwA5mHAsw9KdD1RUrnKBTc1xNf2TmzgzGCLUE4Y7kk4W2VKc6R2JipscmLJon+VHAXAvCxq2a3oLXpBaBTNnLpKqUZrNK1QPCqeb4bMZGmzl1aGda5fb+g/ctNn31lWI8O3DqxlpmfNC+vgWOG5+Ui6M2Azc3Dfn8I8WUGmoymXyIN9ahq4uKg7DPgf01dCkPMcHxZcYY5sd28BtWYSbqGAhmPMUcCNs54wCU7s6xfFj5xyUNUxlbYy2mueofI/DodBMXivD5qfW/W9nmR8q6ww3uH5UjXMcSx3FhPZcRCVFp7qnurPePd+quK5eHjb3bFVdlzk3IZQhOiokdcdWwMMJs5Y8smUCfgRrf+I1ytASEkiGHJJB9hc4fUoAfMdqSGIRcJZTr+ZVOzQhAaBjj/k0QrUd9OkwPWy8ZBrFQL2IWEO1sy1x5JlUCOvMH/OMDpxMgSBXX3hj/k2k33cK4P68GYEo0v1N0kn6xwPTslUmq5ie1ZV/jeHdeMxNuvXR2m5H3iN+pVqrKYYNBw8GE1QJLy33FrUTqkU/4WLj31qn2zPYPCDfHuA4yRTbC12D+uZATpGZvXaKZaTgZKjX2QFeKOp2kYEc3SQ1+5ZhiRcHrLon7iF15zj7e3Cuu69W0cYTdcNdJhulAiWc+hbJVFaYDP+WNXvN4qIj2vUG49BmefCdoj+CiTyYHYp6gpJIWEfkj6Htmhr2zStpQFtbJNItXGG4rihqAFVp4mxNqQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SA2PR10MB4636.namprd10.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366007)(1800799015)(376005); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LR0+uTouhswqQS+gr+XYoouY2saShnc4TWqBUMsgovaj5+5c0zfkZ1DhpIzyyIfvsOJPBtwPF+oiuXXq9w1i0R2NvjUKrLa6wvUE9jqXa+BBf4xP/3q4wGD0nl8YhXmsWw/3VWl92Efy/olF2Y16pmuVYHdyNfNfUw5/NAAZevHtvHzhplWsXIUKTf1ajU25Qnf76s0cBdXNZJWGlJyJCZCn//UgSp6SZ1t6GL9qP5VoRwnczNY52AE5U3pDLZvAF5mbCW66V4BQrF97YtSk8PnjIF/5kvyTmdKKbCx4KfEo4jbh7Epvv75cw2VBZiAUrq1Qb5AWw5koPpPyZMfrII3ns4vF157dB94Z3ZnNyE6MQxWLQJJb5XBtYAA1ia8hftv9z/GguMDOulnRUuhFMiPjh+7xfm5lI/YLmmmntzlKzA+qDvpnwoPtjUjAYflvjn5p/++Qnk0NVTSmiTDVWi5E4iFnbbANoNhge3Fs45DTSjmsTRQk0FvQKJ1/XOeoxkIPbU5sOzd+PB0THVnB8wAsywI/t6hKj6cVq0v0wP7jybRZf4h+m8/Dn0w8ENz2Z2mDW0pZwUvLqN2JyStNofpL7qczhT+3MKDUNxPSdgZM7VYkBSsJ/BnXt8hM1003kQ/KCzEfL2nN+rKGv/Xh92JGWaG4tFsqyH2OdPfP1TATPc/P6u0Jt2PkJm4S6kNnYwnmCImDT0lKO4GwhUz0+6QwJFmYtfEm18ET7IBDZpEK2UywBBi8DOkhzOSUHl0k5SYd2OAfpNm09hsCgdRoMs8tDBBorWT5/sG55aCDLyOrE9ic19W+I1ueIo6JBW/YCgjWovd42mIRYUpfgqEYZ6e8LC1qB4adUIgYK4NXYYjrIAcXxQbV7RLuW9v/Nt7zqpcmH4RJ0hgOWfZ/t6Jw+pkqmfUkl2eF6jaSFkXqYKiXH8UEvMPrsvtNyWLyaw7G7KcZGGa643TfEqSEz5RpDODwehNUxAuvCrH8qUfUUWiHCiCDesCxMB5F2B6/Ft792APX3QeDH+0roqBB3y7wELVFL+iKozIsY0sru08FgjBYE23svvovgFJ8jIDk1bEFTAgFVJD6TMEd1/IyYqtGftgFyYSI8ZBZTiMeDxez93xRo81N6SLMnTaJi/WAKIsXwIjlUI0vvSKUOSnvsBoH0TYdDEOKyw7bUO/YTh71gFr+BX0wCHev4+MzY4SkQK6OpKo3Zs4yeeKz8ivQzcm6bIO614bHZdU4KPWHTqya01U43UQ7unRBIrVct8Ebpjez3gFR4Tfo9lW3EUOBApdKTnqO4vNNaG6VPr0ZkdxhPNpKEwbG5nkBTWQg+xJTET9ZZzVojJHMYIp29po7ItaWZDNMhUOcfu7qTYTzw06rq9DQerIgRq2e3dV47cQmLB1ZU+13uhPU96iTNJxB6WtA+w/8dMrLUT/nbHMIp9DUNYcCXTVNO2pfZ+ydRqgszt84Pn2qNrYJGLxL5pF3j1YLYOQ8N1qfd7U/SSBh2f7e3MZjXTX/HjKWzKOiqUKWf5GXOQUOYA8so/ENT9zobfMyzRDvXfkSOjNKgWsNB+vYadbveg5Q1UDpQJniAbwve3tBvublYJQEk1pH6zw2vDV2q2+ic1K/Duef6vgcI5Wzy9P49hTw6ipaIK38XhR3JNZp X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: AuUPgrkPLx205Q8F/tl9QExTFd4OIQ+Fc9mVYwSHLV5YWqabw3FnkMKrnHMhx87YCY/SlnPcGvzJfcnS+32YoZ/aGbZZF/RPYepVGLKztG6JjwOzXcC+yfUdVPNmw+ahTNSHCHi18BEQMEWB058Gfgsq5qEORqwTG/J7a/2/LDMfPEKRRikTVJvIRqORJNkftiaS1tfMqoT1yWsFTpPI54C7dWaWx5S2Z5kHUtc4QM3Tyg7jkuSF8WZ4gJRS3DR86SYV7K/opUgO9UmwnlE0gbyxb6MQOTHenqYgLzn/A60hCLMvAkSJdypKB02gxhl9s4c1J6mgK+QiHb8HQJk/N+dFUdq60hyO+s/6OzZJEH5aemHlQpwVFo4GO7vh+s7sy0MK/RRHKO04yOIBmWWIqOoMqno2JFvT2UIYfxOlL1rrfdEchDUPsHmMpSumpiv6+rqIHfKZwwMGcy/TffYX+Qn3JhaXCoUbP67Trlzes7y19Wd8au4jzrs2G+7HncbQ8n64pstBGR9ElC9dViE6N22lLeL5rpZ74GAwQYaMV8BuuXmyNKz8fHZD7ccv9y6NcUmTT21ic9EjrQhc4Ajxxss3rucTvvMbDOB3be2odPY= X-OriginatorOrg: oracle.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5511df5b-703e-46d4-5452-08dc7626f2d4 X-MS-Exchange-CrossTenant-AuthSource: SA2PR10MB4636.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2024 04:08:03.8885 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9GqaWeH9pC9ysDtWCjuqlwp2RxMKx5stkKd5uS6paHvoNKItH5JZEdwzcC0ZHZSl+StJgFOyefLo1QNmdDM7B/YWLlx/UNEyHKwtIMi6dt0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR10MB6602 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 adultscore=0 mlxscore=0 spamscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405170031 X-Proofpoint-GUID: Wum_4XCPDveJjuuBqnyH1PeVS3LU6Dw5 X-Proofpoint-ORIG-GUID: Wum_4XCPDveJjuuBqnyH1PeVS3LU6Dw5 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org From: Vladimir Mezentsev interface with libcpc was used on Solaris. gprofng doesn't support profiling on Solaris. I removed this old code and other unused macros and variables. gprofng/ChangeLog 2024-04-29 Vladimir Mezentsev PR gprofng/31123 * common/hwcdrv.c: remove old interface with libcpc. * common/hwcdrv.h: Likewise. * common/hwcentry.h: Likewise. * common/hwcfuncs.c: Likewise. * common/hwcfuncs.h: Likewise. * common/hwctable.c: Likewise. * src/Dbe.cc: Likewise. * src/collctrl.cc: Likewise. --- gprofng/common/hwcdrv.c | 83 +------ gprofng/common/hwcdrv.h | 32 --- gprofng/common/hwcentry.h | 3 - gprofng/common/hwcfuncs.c | 39 +-- gprofng/common/hwcfuncs.h | 25 +- gprofng/common/hwctable.c | 501 ++++---------------------------------- gprofng/src/Dbe.cc | 5 +- gprofng/src/collctrl.cc | 14 -- 8 files changed, 50 insertions(+), 652 deletions(-) diff --git a/gprofng/common/hwcdrv.c b/gprofng/common/hwcdrv.c index 2d549b0d6a5..0ada09d0ca8 100644 --- a/gprofng/common/hwcdrv.c +++ b/gprofng/common/hwcdrv.c @@ -44,83 +44,11 @@ static hdrv_pcbe_api_t *hdrv_pcbe_drivers[] = { #include "opteron_pcbe.c" /* CPU-specific code */ #include "core_pcbe.c" /* CPU-specific code */ -extern hwcdrv_api_t hwcdrv_pcl_api; -IS_GLOBAL hwcdrv_api_t *hwcdrv_drivers[] = { - &hwcdrv_pcl_api, - NULL -}; - /*---------------------------------------------------------------------------*/ - -/* utils for drivers */ -IS_GLOBAL int -hwcdrv_assign_all_regnos (Hwcentry* entries[], unsigned numctrs) -{ - unsigned int pmc_assigned[MAX_PICS]; - unsigned idx; - for (int ii = 0; ii < MAX_PICS; ii++) - pmc_assigned[ii] = 0; - - /* assign the HWCs that we already know about */ - for (idx = 0; idx < numctrs; idx++) - { - regno_t regno = entries[idx]->reg_num; - if (regno == REGNO_ANY) - { - /* check to see if list of possible registers only contains one entry */ - regno = REG_LIST_SINGLE_VALID_ENTRY (entries[idx]->reg_list); - } - if (regno != REGNO_ANY) - { - if (regno < 0 || regno >= MAX_PICS || !regno_is_valid (entries[idx], regno)) - { - logerr (GTXT ("For counter #%d, register %d is out of range\n"), idx + 1, regno); /*!*/ - return HWCFUNCS_ERROR_HWCARGS; - } - TprintfT (DBG_LT2, "hwcfuncs_assign_regnos(): preselected: idx=%d, regno=%d\n", idx, regno); - entries[idx]->reg_num = regno; /* assigning back to entries */ - pmc_assigned[regno] = 1; - } - } - - /* assign HWCs that are currently REGNO_ANY */ - for (idx = 0; idx < numctrs; idx++) - { - if (entries[idx]->reg_num == REGNO_ANY) - { - int assigned = 0; - regno_t *reg_list = entries[idx]->reg_list; - for (; reg_list && *reg_list != REGNO_ANY; reg_list++) - { - regno_t regno = *reg_list; - if (regno < 0 || regno >= MAX_PICS) - { - logerr (GTXT ("For counter #%d, register %d is out of range\n"), idx + 1, regno); /*!*/ - return HWCFUNCS_ERROR_HWCARGS; - } - if (pmc_assigned[regno] == 0) - { - TprintfT (DBG_LT2, "hwcfuncs_assign_regnos(): assigned: idx=%d, regno=%d\n", idx, regno); - entries[idx]->reg_num = regno; /* assigning back to entries */ - pmc_assigned[regno] = 1; - assigned = 1; - break; - } - } - if (!assigned) - { - logerr (GTXT ("Counter '%s' could not be bound to a register\n"), - entries[idx]->name ? entries[idx]->name : ""); - return HWCFUNCS_ERROR_HWCARGS; - } - } - } - return 0; -} - -IS_GLOBAL int +static int hwcdrv_lookup_cpuver (const char * cpcN_cciname) { + /* returns hwc_cpus.h ID for a given string. */ libcpc2_cpu_lookup_t *plookup; static libcpc2_cpu_lookup_t cpu_table[] = { LIBCPC2_CPU_LOOKUP_LIST @@ -307,11 +235,6 @@ hwcfuncs_get_x86_eventsel (unsigned int regno, const char *int_name, return -1; } hwcfuncs_parse_ctr (int_name, NULL, &nameOnly, NULL, NULL, NULL); - if (regno == REGNO_ANY) - { - logerr (GTXT ("reg# could not be determined for `%s'\n"), nameOnly); - goto attr_wrapup; - } /* look up evntsel */ if (myperfctr_get_x86_eventnum (nameOnly, regno, @@ -987,7 +910,7 @@ hwcdrv_get_descriptions (hwcf_hwc_cb_t *hwc_cb, hwcf_attr_cb_t *attr_cb) HWCDRV_API int hwcdrv_assign_regnos (Hwcentry* entries[], unsigned numctrs) { - return hwcdrv_assign_all_regnos (entries, numctrs); + return 0; } static int diff --git a/gprofng/common/hwcdrv.h b/gprofng/common/hwcdrv.h index 1829ec88fac..0a5eb33df00 100644 --- a/gprofng/common/hwcdrv.h +++ b/gprofng/common/hwcdrv.h @@ -41,29 +41,6 @@ #include "libcol_util.h" #define get_hwcdrv __collector_get_hwcdrv -#define hwcdrv_drivers __collector_hwcdrv_drivers -#define hwcdrv_cpc1_api __collector_hwcdrv_cpc1_api -#define hwcdrv_cpc2_api __collector_hwcdrv_cpc2_api -#define hwcdrv_default __collector_hwcdrv_default -#define hwcdrv_driver __collector_hwcdrv_driver -#define hwcdrv_init __collector_hwcdrv_init -#define hwcdrv_get_info __collector_hwcdrv_get_info -#define hwcdrv_enable_mt __collector_hwcdrv_enable_mt -#define hwcdrv_get_descriptions __collector_hwcdrv_get_descriptions -#define hwcdrv_assign_regnos __collector_hwcdrv_assign_regnos -#define hwcdrv_create_counters __collector_hwcdrv_create_counters -#define hwcdrv_start __collector_hwcdrv_start -#define hwcdrv_overflow __collector_hwcdrv_overflow -#define hwcdrv_read_events __collector_hwcdrv_read_events -#define hwcdrv_sighlr_restart __collector_hwcdrv_sighlr_restart -#define hwcdrv_lwp_suspend __collector_hwcdrv_lwp_suspend -#define hwcdrv_lwp_resume __collector_hwcdrv_lwp_resume -#define hwcdrv_free_counters __collector_hwcdrv_free_counters -#define hwcdrv_lwp_init __collector_hwcdrv_lwp_init -#define hwcdrv_lwp_fini __collector_hwcdrv_lwp_fini -#define hwcdrv_assign_all_regnos __collector_hwcdrv_assign_all_regnos -#define hwcdrv_lookup_cpuver __collector_hwcdrv_lookup_cpuver -#define hwcfuncs_int_capture_errmsg __collector_hwcfuncs_int_capture_errmsg #define GTXT(x) x @@ -263,7 +240,6 @@ extern "C" extern hwcdrv_api_t *__collector_get_hwcdrv (); extern int __collector_hwcfuncs_bind_descriptor (const char *defstring); extern Hwcentry **__collector_hwcfuncs_get_ctrs (unsigned *defcnt); - extern hwcdrv_api_t *hwcdrv_drivers[]; // array of available drivers /* prototypes for internal use by hwcdrv drivers */ typedef struct @@ -274,14 +250,6 @@ extern "C" const char *cpcN_cciname; } hwcdrv_about_t; - extern int hwcdrv_assign_all_regnos (Hwcentry* entries[], unsigned numctrs); - /* assign user's counters to specific CPU registers */ - - extern int hwcdrv_lookup_cpuver (const char * cpcN_cciname); - /* returns hwc_cpus.h ID for a given string. */ - - extern void hwcfuncs_int_capture_errmsg (const char *fn, int subcode, - const char *fmt, va_list ap); #define logerr hwcfuncs_int_logerr /*---------------------------------------------------------------------------*/ diff --git a/gprofng/common/hwcentry.h b/gprofng/common/hwcentry.h index a35a363e693..946356eabe5 100644 --- a/gprofng/common/hwcentry.h +++ b/gprofng/common/hwcentry.h @@ -119,9 +119,6 @@ extern "C" unsigned int type : 16; /* Type of perf_event_attr */ long long config; /* perf_event_type -specific configuration */ int sort_order; /* "tag" to associate experiment record with HWC def */ - regno_t *reg_list; /* if not NULL, legal values for field above */ - /* Note: reg_list will be terminated by REGNO_ANY */ - /* Max size of array is MAX_PICS */ hrtime_t min_time; /* target minimum time between overflow events. 0 is off. See HWCTIME_* macros */ hrtime_t min_time_default; /* if min_time==HWCTIME_AUTO, use this value instead. 0 is off. */ int ref_val; /* if min_time==HWCTIME_AUTO, use this time. 0 is off. */ diff --git a/gprofng/common/hwcfuncs.c b/gprofng/common/hwcfuncs.c index 86d6935b321..fce711df6a6 100644 --- a/gprofng/common/hwcfuncs.c +++ b/gprofng/common/hwcfuncs.c @@ -162,10 +162,10 @@ ctrdefprint (int dbg_lvl, const char * hdr, Hwcentry*phwcdef) { TprintfT (dbg_lvl, "%s: name='%s', int_name='%s'," " reg_num=%d, timecvt=%d, memop=%d, " - "interval=%d, tag=%u, reg_list=%p\n", + "interval=%d, tag=%u\n", hdr, phwcdef->name, phwcdef->int_name, phwcdef->reg_num, phwcdef->timecvt, phwcdef->memop, phwcdef->val, - phwcdef->sort_order, phwcdef->reg_list); + phwcdef->sort_order); } /*---------------------------------------------------------------------------*/ @@ -198,7 +198,7 @@ hwcfuncs_errmsg_get (char *buf, size_t bufsize, int enable) } /* used by cpc to log an error */ -IS_GLOBAL void +static void hwcfuncs_int_capture_errmsg (const char *fn, int subcode, const char *fmt, va_list ap) { @@ -639,39 +639,6 @@ hwcfuncs_get_ctrs (unsigned *defcnt) return hwctable; } -/* return 1 if is in Hwcentry's list */ -IS_GLOBAL int -regno_is_valid (const Hwcentry * pctr, regno_t regno) -{ - regno_t *reg_list = pctr->reg_list; - if (REG_LIST_IS_EMPTY (reg_list)) - return 0; - if (regno == REGNO_ANY) /* wildcard */ - return 1; - for (int ii = 0; ii < MAX_PICS; ii++) - { - regno_t tmp = reg_list[ii]; - if (REG_LIST_EOL (tmp)) /* end of list */ - break; - if (tmp == regno) /* is in list */ - return 1; - } - return 0; -} - -/* supplied by hwcdrv_api drivers */ -IS_GLOBAL int -hwcfuncs_assign_regnos (Hwcentry* entries[], - unsigned numctrs) -{ - if (numctrs > cpcN_npics) - { - logerr (GTXT ("More than %d counters were specified\n"), cpcN_npics); /*!*/ - return HWCFUNCS_ERROR_HWCARGS; - } - return hwcdrv_driver->hwcdrv_assign_regnos (entries, numctrs); -} - extern hwcdrv_api_t hwcdrv_pcl_api; static int hwcdrv_driver_inited = 0; diff --git a/gprofng/common/hwcfuncs.h b/gprofng/common/hwcfuncs.h index 7db0f725a13..f44b9a7b4ae 100644 --- a/gprofng/common/hwcfuncs.h +++ b/gprofng/common/hwcfuncs.h @@ -29,8 +29,6 @@ #define hwcfuncs_parse_attrs __collector_hwcfuncs_parse_attrs #define hwcfuncs_bind_descriptor __collector_hwcfuncs_bind_descriptor #define hwcfuncs_bind_hwcentry __collector_hwcfuncs_bind_hwcentry -#define hwcfuncs_assign_regnos __collector_hwcfuncs_assign_regnos -#define regno_is_valid __collector_regno_is_valid #define hwcfuncs_get_ctrs __collector_hwcfuncs_get_ctrs #define hwcfuncs_errmsg_get __collector_hwcfuncs_errmsg_get #endif /* --- LIBCOLLECTOR_SRC --- */ @@ -117,7 +115,6 @@ typedef struct { /* supplementary data fields */ #define HWCFUNCS_ERROR_HWCARGS (-5) #define HWCFUNCS_ERROR_MEMORY (-6) #define HWCFUNCS_ERROR_UNAVAIL (-7) -#define HWCFUNCS_ERROR_ERRNO_ZERO (-8) #define HWCFUNCS_ERROR_UNEXPECTED (-99) /*---------------------------------------------------------------------------*/ @@ -137,6 +134,7 @@ extern void hwcfuncs_int_logerr(const char *format,...); #define HWCFUNCS_SUPPORT_OVERFLOW_PROFILING 0x01llu #define HWCFUNCS_SUPPORT_PEBS_SAMPLING 0x02llu #define HWCFUNCS_SUPPORT_OVERFLOW_CTR_ID 0x04llu // OS identifies which counter overflowed +#define SUPPORT_MEMORYSPACE_PROFILING 0x08 /* get info about session Input: : if not NULL, returns value of CPC cpu version @@ -218,27 +216,6 @@ extern void hwcfuncs_int_logerr(const char *format,...); HWCFUNCS_ERROR_HWCARGS if counters were not specified correctly */ - extern int hwcfuncs_assign_regnos (Hwcentry *entries[], unsigned numctrs); - /* Assign entries[]->reg_num values as needed by platform - Note: modifies by supplying a regno to each counter - Input: - : array of counters - : number of items in - Output: - : array of counters is modified - Return: 0 if successful - HWCFUNCS_ERROR_HWCINIT if resources unavailable - HWCFUNCS_ERROR_HWCARGS if counters were not specified correctly - */ - - extern int regno_is_valid (const Hwcentry *pctr, regno_t regno); - /* return 1 if is in Hwcentry's list - Input: - : counter definition, reg_list[] should be initialized - : register to check - Return: 1 if is in Hwcentry's list, 0 otherwise - */ - extern Hwcentry **hwcfuncs_get_ctrs (unsigned *defcnt); /* Get descriptions of the currently bound counters. Input: diff --git a/gprofng/common/hwctable.c b/gprofng/common/hwctable.c index 567f49f80d5..40b4cd850ba 100644 --- a/gprofng/common/hwctable.c +++ b/gprofng/common/hwctable.c @@ -2659,145 +2659,6 @@ is_hidden_alias (Hwcentry* pctr) return 0; } -static int -is_numeric_alias (Hwcentry* pctr) -{ - int is_numeric_alias = 0; - regno_t regno; - char *nameOnly = NULL; - hwcfuncs_parse_ctr (pctr->int_name, NULL, &nameOnly, NULL, NULL, ®no); - if (is_numeric (nameOnly, NULL)) - is_numeric_alias = 1; - free (nameOnly); - return is_numeric_alias; -} - -/* print list of register to a buffer */ -/* - * style e x a m p l e s - * 0 NONE 2 {0|1|2|3} - * 1 NONE 2 : 0, 1, 2, or 3 - * 2 0 1 2 3 6 - */ -static char * -get_regnolist (char *buf, size_t sz, const regno_t *reg_list, int style) -{ - if (!buf || !sz) - return "INTERNAL ERROR"; - buf[0] = 0; - if (style == 2) - { - int ii; - // width should be consistent with that in format_columns() - // the format will accommodate cpcx_npics regs - if (cpcx_npics < 1) - return "INTERNAL ERROR"; - // clear out the buffer - for (ii = 0; ii < sz; ii++) - buf[ii] = '_'; - if (cpcx_npics <= 9) - { - // one char per reg, plus terminating null char - if (cpcx_npics + 1 > sz) - return "INTERNAL ERROR"; - buf[cpcx_npics] = '\0'; - - // fill buf with regnos - for (ii = 0; ii < MAX_PICS; ii++) - { - regno_t regno = reg_list[ii]; - if (REG_LIST_EOL (regno)) - break; - if (regno < 0 || regno >= cpcx_npics) - return "INTERNAL ERROR"; - buf[regno] = '0' + regno; - } - } - else - { - /* space between regs, which may be 1 or 2 digits each - * 1 char for reg 0 - * 2 chars for regs 1-9 each - * 3 chars for regs 10- each - * 1 char for terminating null char - */ - int nchars = 17 + 3 * (cpcx_npics - 9); - if (nchars > sz) - return "INTERNAL ERROR"; - buf[nchars - 1] = '\0'; - - // fill buf with regnos - for (ii = 0; ii < MAX_PICS; ii++) - { - regno_t regno = reg_list[ii]; - if (REG_LIST_EOL (regno)) - break; - if (regno <= 9) - buf[2 * regno ] = '0' + regno; - else - { - buf[3 * (regno - 9) + 17] = '0' + (regno / 10); - buf[3 * (regno - 9) + 18] = '0' + (regno % 10); - } - } - } - return buf; - } - if (REG_LIST_IS_EMPTY (reg_list)) - { - snprintf (buf, sz, GTXT ("NONE")); - return buf; - } - else if (REG_LIST_EOL (reg_list[1])) - { - /* 1 item in list */ - snprintf (buf, sz, "%d", reg_list[0]); - return buf; - } - else - { - /* 2 more items in list */ - int ii, num_regs; - for (ii = 0; ii < MAX_PICS; ii++) - { - regno_t regno = reg_list[ii]; - if (REG_LIST_EOL (regno)) - break; - } - num_regs = ii; - buf[0] = 0; - for (ii = 0; ii < num_regs; ii++) - { - regno_t regno = reg_list[ii]; - if (style == 0) - snprintf (buf + strlen (buf), sz - strlen (buf), - "%c%d", ii ? '|' : '{', regno); - else - { - if (num_regs == 2) - snprintf (buf + strlen (buf), sz - strlen (buf), - "%d%s", regno, !ii ? " or " : ""); - else - { - /* 3 or more items in list */ - if (ii < num_regs - 2) - snprintf (buf + strlen (buf), sz - strlen (buf), - "%d, ", regno); - else if (ii == num_regs - 2) - snprintf (buf + strlen (buf), sz - strlen (buf), - "%d, or ", regno); - else - snprintf (buf + strlen (buf), sz - strlen (buf), - "%d", regno); - } - } - } - if (style == 0) - snprintf (buf + strlen (buf), sz - strlen (buf), "}"); - } - return buf; -} - #if !HWC_DEBUG #define hwcentry_print(lvl,x1,x2) #else @@ -2806,8 +2667,7 @@ get_regnolist (char *buf, size_t sz, const regno_t *reg_list, int style) static void hwcentry_print (int lvl, const char * header, const Hwcentry *pentry) { - char buf[1024]; - Tprintf (lvl, "%s '%s', '%s', %d, '%s', %d, %d, %d, %d, %d, %d, /", + Tprintf (lvl, "%s '%s', '%s', %d, '%s', %d, %d, %d, %d, %d, %d, /\n", header, pentry->name ? pentry->name : "NULL", pentry->int_name ? pentry->int_name : "NULL", @@ -2819,67 +2679,9 @@ hwcentry_print (int lvl, const char * header, const Hwcentry *pentry) pentry->timecvt, pentry->memop, /* type of instruction that can trigger */ pentry->sort_order); - get_regnolist (buf, sizeof (buf), pentry->reg_list, 0); - Tprintf (lvl, "%s\n", buf); } #endif -/* add to a Hwcentry's list */ -static void -regno_add (Hwcentry * pctr, regno_t regno) -{ - int jj; - regno_t *reg_list; - if (!pctr) - { - Tprintf (0, "hwctable: regno_add(): ERROR: pctr==NULL\n"); - return; - } - reg_list = pctr->reg_list; - if (!reg_list) - { - /* create list */ - reg_list = (regno_t*) malloc (sizeof (regno_t*) * MAX_PICS); - if (!reg_list) - { - hwcentry_print (DBG_LT0, "hwctable: regno_add: ERROR:" - " Out of memory: ", pctr); - return; - } - /* initialize list */ - for (jj = 0; jj < MAX_PICS; jj++) - reg_list[jj] = REGNO_ANY; - pctr->reg_list = reg_list; - } - if (regno == REGNO_ANY) - { - /* add all counters up to cpcx_npics */ - for (jj = 0; jj < MAX_PICS && jj < cpcx_npics; jj++) - reg_list[jj] = jj; - } - else - { - /* add to list of registers */ - for (jj = 0; jj < MAX_PICS; jj++) - { - if (reg_list[jj] == regno) - { - hwcentry_print (DBG_LT0, "hwctable: regno_add: WARNING: " - "Duplicate regno: ", pctr); - break; - } - if (reg_list[jj] == REGNO_ANY) - { - reg_list[jj] = regno; - break; - } - } - } - if (jj == MAX_PICS) - hwcentry_print (DBG_LT0, "hwctable: regno_add: WARNING:" - " regno list is full:", pctr); -} - /*---------------------------------------------------------------------------*/ /* utilities for rawlist (list of raw counters with reglist[] filled in) */ @@ -2931,8 +2733,6 @@ list_add (ptr_list *list, uint_t regno, const char *name) tmpctr.name = (char *) name; praw = list_append_shallow_copy (list, &tmpctr); } - if (praw) - regno_add (praw, regno); return praw; } @@ -2989,28 +2789,7 @@ ptrarray_find (const Hwcentry **array, const char *name, const char *int_name, if (NULL == strstr (int_name, pctr->int_name)) continue; } - if (!check_regno) - return pctr; - else - { - /* duplicates aliases are allowed in table because of 6759307 */ - if (REG_LIST_IS_EMPTY (pctr->reg_list)) - { - /* skip aliases that don't have a valid list of registers */ - hwcentry_print (1, "hwctable: stdlist_find_by_name:" - " WARNING: alias found, but event not supported by HW:", - pctr); - continue; - } - if (!regno_is_valid (pctr, regno)) - { - hwcentry_print (1, "hwctable: stdlist_find_by_name():" - " WARNING: alias found, but regno doesn't match:", - pctr); - continue; - } - return pctr; - } + return pctr; } return NULL; } @@ -3046,49 +2825,15 @@ static_table_find (const Hwcentry *table, const char *name, const char *int_name static void stdlist_print (int dbg_lvl, const Hwcentry* table) { - const Hwcentry *pctr; if (!table) { Tprintf (0, "hwctable: stdlist_print: ERROR: " "table is invalid.\n"); return; } - for (pctr = table; pctr->name; pctr++) + for (const Hwcentry *pctr = table; pctr->name; pctr++) { - int ii; hwcentry_print (dbg_lvl, "hwctable: stdlist: ", pctr); - if (REG_LIST_IS_EMPTY (pctr->reg_list)) - { - if (pctr->int_name || !pctr->metric) - hwcentry_print (DBG_LT1, "hwctable: stdlist_print: WARNING: " - "no hardware event found for table entry", pctr); - continue; - } - /* check if incorrect reg_num used in table */ - if (!regno_is_valid (pctr, pctr->reg_num)) - { - hwcentry_print (DBG_LT0, "hwctable: stdlist_print: ERROR: " - "reg_num is not in table. ", pctr); - continue; - } - for (ii = 0; ii < MAX_PICS; ii++) - { - regno_t regno = pctr->reg_list[ii]; - if (REG_LIST_EOL (regno)) - break; - } - if (ii > 1 && pctr->reg_num != REGNO_ANY) - { - /* several regnos were valid, but only one can be specified */ - if (pctr->metric || !pctr->int_name) - { - /* pctr is standard or a raw definition */ - /* (pctr is not an alias like cycles0) */ - hwcentry_print (DBG_LT0, "hwctable: stdlist_print: ERROR: " - "regno in table should have been REGNO_ANY. ", - pctr); - } - } } } #endif @@ -3173,41 +2918,17 @@ check_tables () if (pentry->metric) Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:" " internal && metric @%d, %s\n", cputag, pentry->name); - if (pentry->reg_num != REGNO_ANY) - Tprintf (DBG_LT1, "hwctable: check_tables: WARNING:" - " internal && reg_num!=REGNO_ANY @%d, %s\n", - cputag, pentry->name); if (pentry->val != PRELOAD_DEF && pentry->memop != ABST_EXACT_PEBS_PLUS1) Tprintf (DBG_LT2, "hwctable: check_tables: INFO:" " internal && custom val=%d @%d, %s\n", pentry->val, cputag, pentry->name); -#if 0 - if (!pentry->timecvt && pentry->memop == ABST_NONE) - Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:" - " internal && not special! @%d, %s\n", - cputag, pentry->name); -#endif } if (pentry->metric) { /* aliased */ if (!pentry->int_name) Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:" " aliased && !int_name @%d, %s\n", cputag, pentry->name); -#if 0 - else if (!strcmp (pentry->name, pentry->int_name)) - Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:" - " name==int_name @%d, %s\n", - cputag, pentry->name); -#endif - if (pentry->reg_num != REGNO_ANY && pentry->reg_num != REGNO_INVALID) - Tprintf (DBG_LT1, "hwctable: check_tables: INFO:" - " aliased && custom reg_num==%d @%d, %s\n", - pentry->reg_num, cputag, pentry->name); - if (pentry->reg_num == REGNO_INVALID) - Tprintf (DBG_LT2, "hwctable: check_tables: INFO:" - " aliased && reg_num==REGNO_INVALID @%d, %s\n", - cputag, pentry->name); } if (pentry->int_name && !pentry->metric) { /* convenience */ @@ -3215,10 +2936,6 @@ check_tables () Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:" " convenience && name==int_name @%d, %s\n", cputag, pentry->name); - if (pentry->reg_num == REGNO_ANY) - Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:" - " convenience && reg_num==REGNO_ANY @%d, %s\n", - cputag, pentry->name); } } } @@ -3417,17 +3134,13 @@ try_a_counter (int forKernel) return 0; /* consider this an automatic PASS */ } /* look for a valid table entry, only try valid_cpu_tables[0] */ - { - testevent = cpcx_std[forKernel][0]; - if (!testevent || !testevent->name) - { - Tprintf (0, "hwctable: WARNING: no test metric" - " available to verify counters\n"); - return 0; /* consider this an automatic PASS */ - } - if (REG_LIST_IS_EMPTY (testevent->reg_list)) - return 0; // weird - } + testevent = cpcx_std[forKernel][0]; + if (!testevent || !testevent->name) + { + Tprintf (0, "hwctable: WARNING: no test metric" + " available to verify counters\n"); + return 0; /* consider this an automatic PASS */ + } Hwcentry tmp_testevent; tmp_testevent = *testevent; /* shallow copy */ if (tmp_testevent.int_name == NULL) @@ -3436,9 +3149,6 @@ try_a_counter (int forKernel) tmp_testevent.int_name = strdup (tmp_testevent.name); } Hwcentry * test_array[1] = {&tmp_testevent}; - rc = hwcfuncs_assign_regnos (test_array, 1); /* may modify test_array */ - if (rc) - return rc; rc = test_hwcs ((const Hwcentry**) test_array, 1); if (rc == HWCFUNCS_ERROR_UNAVAIL) { @@ -3677,7 +3387,6 @@ process_ctr_def (int forKernel, hrtime_t global_min_time_nsec, if (tmp) { tmp->name = strdup (nameOnly); - regno_add (tmp, REGNO_ANY); pfound = tmp; } } @@ -3780,27 +3489,6 @@ process_ctr_def (int forKernel, hrtime_t global_min_time_nsec, GTXT ("Warning: HW counter `%s' is not program-related -- callstacks will be not be recorded for this counter\n"), uname); - /* update reg_num */ - if (!regno_is_valid (pfound, regno)) - { - char buf[1024]; - snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf), - GTXT ("For counter `%s', %s is not a valid register; valid registers: %s\n"), - nameOnly, regstr ? regstr + 1 : "?", - get_regnolist (buf, sizeof (buf), pfound->reg_list, 1)); - goto process_ctr_def_wrapup; - } - if (pret_ctr->reg_num == REGNO_ANY) - { /* table's regno is a wildcard */ - if (REG_LIST_EOL (pfound->reg_list[1])) - { - /* valid list only contains one regno, so use it */ - pret_ctr->reg_num = pfound->reg_list[0]; - } - else - pret_ctr->reg_num = regno; /* use user's selection */ - } - /* update name and int_name */ { // validate attributes @@ -4073,43 +3761,9 @@ hwc_validate_ctrs (int forKernel, Hwcentry *entries[], unsigned numctrs) char UEbuf[1024 * 5]; UEbuf[0] = 0; - /* search for obvious duplicates*/ - unsigned ii; - for (ii = 0; ii < numctrs; ii++) - { - regno_t reg_a = entries[ii]->reg_num; - if (reg_a != REGNO_ANY) - { - unsigned jj; - for (jj = ii + 1; jj < numctrs; jj++) - { - int reg_b = entries[jj]->reg_num; - if (reg_a == reg_b) - { - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT ("Only one HW counter is allowed per register. The following counters use register %d: \n"), - reg_a); - for (jj = 0; jj < numctrs; jj++) - { - char buf[256]; - int reg_b = entries[jj]->reg_num; - if (reg_a == reg_b) - snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf), - GTXT (" %d. %s\n"), jj + 1, - hwc_hwcentry_specd_string (buf, sizeof (buf), - entries[jj])); - } - return strdup (UEbuf); - } - } - } - } - /* test counters */ hwcfuncs_errmsg_get (NULL, 0, 1); /* enable errmsg capture */ - int hwc_rc = hwcfuncs_assign_regnos (entries, numctrs); - if (!hwc_rc) - hwc_rc = test_hwcs ((const Hwcentry**) entries, numctrs); + int hwc_rc = test_hwcs ((const Hwcentry**) entries, numctrs); if (hwc_rc) { if (cpcx_cpuver == CPC_PENTIUM_4_HT || cpcx_cpuver == CPC_PENTIUM_4) @@ -4172,15 +3826,12 @@ hwc_post_lookup (Hwcentry * pret_ctr, char *counter, char * int_name, int cpuver } else pret_ctr->int_name = strdup (counter); - if (pret_ctr->reg_num == REGNO_ANY) - pret_ctr->reg_num = regno; /* table's regno is a wildcard */ } else { /* not a standard counter */ *pret_ctr = empty_ctr; pret_ctr->int_name = strdup (counter); - pret_ctr->reg_num = regno; } /* update the name */ @@ -4456,7 +4107,7 @@ int show_regs = 0; // The register setting is available on Solaris only */ static void format_columns (char *buf, int bufsiz, char *s1, char *s2, const char *s3, - const char *s4, char *s5, const char *s6) + const char *s4, const char *s6) { // NULL strings are blanks char *blank = NTXT (""); @@ -4470,7 +4121,7 @@ format_columns (char *buf, int bufsiz, char *s1, char *s2, const char *s3, // get the lengths and target widths // (s6 can be as wide as it likes) int l1 = strlen (s1), n1 = 10, l2 = strlen (s2), n2 = 13; - int l3 = strlen (s3), n3 = 20, l4 = strlen (s4), n4 = 10, n5; + int l3 = strlen (s3), n3 = 20, l4 = strlen (s4), n4 = 10; char divide = ' '; // adjust widths, stealing from one column to help a neighbor @@ -4518,26 +4169,8 @@ format_columns (char *buf, int bufsiz, char *s1, char *s2, const char *s3, n2 = 0; } - if (show_regs) - { - // fifth column should be wide enough for regnolist - // see function get_regnolist() - if (cpcx_npics < 10) - n5 = cpcx_npics; // one char per regno - else - n5 = 16 + 3 * (cpcx_npics - 9); // spaces between regnos and some regnos are 2-char wide - // ... and be wide enough for header "regs" - if (n5 < 4) - n5 = 4; - - // print to buffer - // (don't need a space before s4 since historical precedent to have a trailing space in s3) - snprintf (buf, bufsiz, "%-*s %-*s%c%*s%*s %-*s %s", - n1, s1, n2, s2, divide, n3, s3, n4, s4, n5, s5, s6); - } - else - snprintf (buf, bufsiz, "%-*s %-*s%c%*s%*s %s", - n1, s1, n2, s2, divide, n3, s3, n4, s4, s6); + snprintf (buf, bufsiz, "%-*s %-*s%c%*s%*s %s", + n1, s1, n2, s2, divide, n3, s3, n4, s4, s6); for (int i = strlen (buf); i > 0; i--) if (buf[i] == ' ' || buf[i] == '\t') buf[i] = 0; @@ -4550,7 +4183,6 @@ static char * hwc_hwcentry_string_internal (char *buf, size_t buflen, const Hwcentry *ctr, int show_short_desc) { - char regnolist[256]; if (!buf || !buflen) return buf; if (ctr == NULL) @@ -4565,7 +4197,6 @@ hwc_hwcentry_string_internal (char *buf, size_t buflen, const Hwcentry *ctr, desc = ctr->metric ? hwc_i18n_metric (ctr) : NULL; format_columns (buf, buflen, ctr->name, ctr->int_name, hwc_memop_string (ctr->memop), timecvt_string (ctr->timecvt), - get_regnolist (regnolist, sizeof (regnolist), ctr->reg_list, 2), desc); return buf; } @@ -5157,7 +4788,7 @@ hwc_usage_internal (int forKernel, FILE *f_usage, const char *cmd, const char *d if (has_std_ctrs) { fprintf (f_usage, GTXT ("\nAliases for most useful HW counters:\n\n")); - format_columns (tmp, 1024, "alias", "raw name", "type ", "units", "regs", "description"); + format_columns (tmp, 1024, "alias", "raw name", "type ", "units", "description"); fprintf (f_usage, NTXT (" %s\n\n"), tmp); for (Hwcentry **pctr = std_ctrs; *pctr; pctr++) { @@ -5170,7 +4801,7 @@ hwc_usage_internal (int forKernel, FILE *f_usage, const char *cmd, const char *d { fprintf (f_usage, GTXT ("\nRaw HW counters:\n\n")); hwc_usage_raw_overview_sparc (f_usage, cpuver); - format_columns (tmp, 1024, "name", NULL, "type ", "units", "regs", "description"); + format_columns (tmp, 1024, "name", NULL, "type ", "units", "description"); fprintf (f_usage, NTXT (" %s\n\n"), tmp); for (Hwcentry **pctr = raw_ctrs; *pctr; pctr++) { @@ -5210,8 +4841,6 @@ static char* supported_pebs_counters[] = { }; /* callback, (see setup_cpc()) called for each valid regno/name combo */ - -/* builds rawlist,, creates and updates reg_list[] arrays in stdlist table */ static void hwc_cb (uint_t cpc_regno, const char *name) { @@ -5219,6 +4848,20 @@ hwc_cb (uint_t cpc_regno, const char *name) list_add (&unfiltered_raw, regno, name); } +static int +supported_hwc (Hwcentry *pctr) +{ + if (ABST_PLUS_BY_DEFAULT (pctr->memop) && + (cpcx_support_bitmask & SUPPORT_MEMORYSPACE_PROFILING) == 0) + return 0; + // remove specific PEBs counters when back end doesn't support sampling + if ((cpcx_support_bitmask & HWCFUNCS_SUPPORT_PEBS_SAMPLING) == 0) + for (int ii = 0; supported_pebs_counters[ii]; ii++) + if (strcmp (supported_pebs_counters[ii], pctr->name) == 0) + return 0; + return 1; +} + /* input: * forKernel: 1 - generate lists for er_kernel, 0 - generate lists for collect * @@ -5248,57 +4891,29 @@ hwc_process_raw_ctrs (int forKernel, Hwcentry ***pstd_out, // copy records from std [0] and generic [1] static input tables into table_copy[0],[1],or[2] for (int tt = 0; tt < 2; tt++) for (Hwcentry *pctr = static_tables[tt]; pctr && pctr->name; pctr++) - if (is_hidden_alias (pctr)) - list_append_shallow_copy (&table_copy[2], pctr); // hidden list - else - list_append_shallow_copy (&table_copy[tt], pctr); + { + if (!supported_hwc (pctr)) + continue; + if (is_hidden_alias (pctr)) + list_append_shallow_copy (&table_copy[2], pctr); // hidden list + else + list_append_shallow_copy (&table_copy[tt], pctr); + } // copy raw_unfiltered_in to raw_out for (int ii = 0; raw_unfiltered_in && raw_unfiltered_in[ii]; ii++) { Hwcentry *pctr = raw_unfiltered_in[ii]; - // filter out raw counters that don't work correctly - -#ifdef WORKAROUND_6231196_NIAGARA1_NO_CTR_0 - if (cpcx_cpuver == CPC_ULTRA_T1) - if (!regno_is_valid (pctr, 1)) - continue; /* Niagara can not profile on register zero; skip this */ -#endif - // remove specific PEBs counters when back end doesn't support sampling - const char *name = pctr->name; - if ((cpcx_support_bitmask & HWCFUNCS_SUPPORT_PEBS_SAMPLING) == 0 || forKernel) - { - int skip = 0; - for (int ii = 0; supported_pebs_counters[ii]; ii++) - if (strcmp (supported_pebs_counters[ii], name) == 0) - { - skip = 1; - break; - } - if (skip) - continue; - } - - Hwcentry *pnew = list_append_shallow_copy (raw_out, pctr); -#ifdef WORKAROUND_6231196_NIAGARA1_NO_CTR_0 - if (cpcx_cpuver == CPC_ULTRA_T1) - { - free (pnew->reg_list); - pnew->reg_list = NULL; - regno_add (pnew, 1); // only allow register 1 - } -#endif - } // raw_unfiltered_in + if (supported_hwc (pctr)) + list_append_shallow_copy (raw_out, pctr); + } // Scan raw counters to populate Hwcentry fields from matching static_tables entries - // Also populate reg_list for aliases found in table_copy[] for (int uu = 0; uu < raw_out->sz; uu++) { Hwcentry *praw = (Hwcentry*) raw_out->array[uu]; Hwcentry *pstd = NULL; // set if non-alias entry from std table matches char *name = praw->name; - /* in the standard counter and generic lists, - update reg_list for all matching items */ for (int tt = 0; tt < NUM_TABLES; tt++) { // std, generic, and hidden if (table_copy[tt].sz == 0) @@ -5315,24 +4930,6 @@ hwc_process_raw_ctrs (int forKernel, Hwcentry ***pstd_out, if (!is_same (name, pname, '~')) continue; - /* truncated pname matches ... */ - // check to see if table entry applies only to specific register - int specific_reg_num_only = 0; - if (pctr->reg_num != REGNO_ANY) - { - // table entry applies only to specific register - if (!regno_is_valid (praw, pctr->reg_num)) - continue; - specific_reg_num_only = 1; - } - - // Match! - // Update cpu_table_copy's supported registers - if (specific_reg_num_only) - regno_add (pctr, pctr->reg_num); - else - pctr->reg_list = praw->reg_list; - if (!is_visible_alias (pctr) && !is_hidden_alias (pctr)) { // Note: we could expand criteria to also allow aliases to set default rates for raw HWCs @@ -5366,20 +4963,6 @@ hwc_process_raw_ctrs (int forKernel, Hwcentry ***pstd_out, // prune unsupported rows from std table if (!is_visible_alias (pctr) && !is_hidden_alias (pctr)) continue; // only aliases - if (REG_LIST_IS_EMPTY (pctr->reg_list)) - { - if (is_numeric_alias (pctr)) - { -#if 1 //22844570 DTrace cpc provider does not accept numeric counter names - if (forKernel) - continue; -#endif - regno_add (pctr, REGNO_ANY); // hwcs specified by number allowed on any register - } - else - continue; - } - ptr_list *dest = (tt == 0) ? std_out : hidden_out; Hwcentry *isInList; if (pctr->short_desc == NULL) diff --git a/gprofng/src/Dbe.cc b/gprofng/src/Dbe.cc index 91a5aa5ef05..95daa727186 100644 --- a/gprofng/src/Dbe.cc +++ b/gprofng/src/Dbe.cc @@ -7121,10 +7121,7 @@ dbeGetHwcs (Hwcentry **hwcs) { Hwcentry *ctr = hwcs[i]; Vector *registers = new Vector(MAX_PICS); - regno_t *reglist = ctr->reg_list; - for (int k = 0; !REG_LIST_EOL (reglist[k]) && k < MAX_PICS; k++) - registers->store (k, reglist[k]); - + registers->store (0, REGNO_ANY); i18n->store (i, dbe_strdup (hwc_i18n_metric (ctr))); name->store (i, dbe_strdup (ctr->name)); int_name->store (i, dbe_strdup (ctr->int_name)); diff --git a/gprofng/src/collctrl.cc b/gprofng/src/collctrl.cc index ebf888c5a20..7d2b23c12ac 100644 --- a/gprofng/src/collctrl.cc +++ b/gprofng/src/collctrl.cc @@ -1361,20 +1361,6 @@ Coll_Ctrl::hwcentry_dup (Hwcentry *hnew, Hwcentry *_hwc) hnew->short_desc = strdup (_hwc->short_desc); else hnew->short_desc = NULL; - if (_hwc->reg_list != NULL) - { - hnew->reg_list = (regno_t*) malloc (sizeof (regno_t*) * MAX_PICS); - // poor way of dealing with malloc failure - if (hnew->reg_list) - { - for (int i = 0; i < MAX_PICS; i++) - { - hnew->reg_list[i] = _hwc->reg_list[i]; - if (hnew->reg_list[i] == REGNO_ANY) - break; - } - } - } } // Routine to initialize the HWC tables, set up the default experiment, etc. From patchwork Fri May 17 04:08:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Mezentsev X-Patchwork-Id: 90317 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D8DA63849AC1 for ; Fri, 17 May 2024 04:09:19 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mx0a-00069f02.pphosted.com (mx0a-00069f02.pphosted.com [205.220.165.32]) by sourceware.org (Postfix) with ESMTPS id 3396F384A880 for ; Fri, 17 May 2024 04:08:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3396F384A880 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=oracle.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oracle.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3396F384A880 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=205.220.165.32 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1715918919; cv=pass; b=RdcwuVsW45ozcpJMHluovjCXjxLXgN2owyAUPB+mJdHd/Sk5zNRzdxuEgWCI0SfDj1Sf3ibH/zhXDlU9Ybpul/lDIVy8vBvHEeRTtHTVydRv+WFg+Durd425XnNBdMq6vq830eIac2Yq0WbSg0ECrM6KuDGAaq8+6PZIzVC1HjI= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1715918919; c=relaxed/simple; bh=G62rxlBVRl+ou6utR8PvWapqs/bqrA7EZzJms2WMl2o=; h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-Id: MIME-Version; b=RnYSK9K99i3dHUagXDYRSdrnCeAr6jo/wFdlivPhQ0PL2cEpk6/sH3oq4mYMTFri4EfPu9PrqatW0ytbWxO2Ys8BbL+KM+f96pXUS7tRZHotAu+ouoDxFfhkVqkNC5oGl6NYMPQqDwNypbbkiOck3DF6o7np7lOIjchs42jcnHE= ARC-Authentication-Results: i=2; server2.sourceware.org Received: from pps.filterd (m0246629.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 44H3P9Gq028281 for ; Fri, 17 May 2024 04:08:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : content-transfer-encoding : content-type : mime-version; s=corp-2023-11-20; bh=q7jd9oOJBjwGhZ70sKHmh/QoTm9YFpUcPtkiwfsiHq8=; b=E3CI24rbENzivDZXsWr1fdDUV8IY49+J8aLn3UesY3jYsFslU5IVcDcNusMwMZ1JBJQS I0KxabBUcIi/HHBJdz5/bFHr4kEN0WwzFxx8rKdMudDbcSMLVBKZi8HVHlgQIwliFj5n ijZBxAznoL4JozO9DVJyiXMlvbRdrCW2Ttms4EtRiC6GD5aJ6r2krsgBdedigxmXcS3U IYS/2pt+Wii1ynXyiXs8aUpiaJaWcN+MIia0ee2yEwuBjCXKbSg3My+V0T2LWgQbMZqy F9R+dpY8dffzVYzZygc1NMOcvroKuwJ6lpsqQNX6OwFz/UL7KyZzuLdatA0kvJyenw2q 5Q== Received: from iadpaimrmta02.imrmtpd1.prodappiadaev1.oraclevcn.com (iadpaimrmta02.appoci.oracle.com [147.154.18.20]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3y3tx8prhh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Fri, 17 May 2024 04:08:30 +0000 Received: from pps.filterd (iadpaimrmta02.imrmtpd1.prodappiadaev1.oraclevcn.com [127.0.0.1]) by iadpaimrmta02.imrmtpd1.prodappiadaev1.oraclevcn.com (8.17.1.19/8.17.1.19) with ESMTP id 44H30J2C005717 for ; Fri, 17 May 2024 04:08:29 GMT Received: from nam10-mw2-obe.outbound.protection.outlook.com (mail-mw2nam10lp2101.outbound.protection.outlook.com [104.47.55.101]) by iadpaimrmta02.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTPS id 3y1y4b36wp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Fri, 17 May 2024 04:08:28 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=EpTxfahwDGpNpzstAgKyV+rPRv2KIhPCZf5fWcUuk5OO5H3LT3irgKvAsIgdrHawr+kwjC+z2yEdtm+i4O7rn62rutygdy98V/tqjbrMM4U7QgPOEoVjfUfC7Q4p1pAnn09UVhda80+nDtQ0WZJUQ2CCCux9ejhhyRZHAQU9KPMtkVLubnkiFTsyLNAt+4ogZBLjBOJMIQ9uq7lyVN/SzORybbbiPW5it8DZVUJL5wHTCMskiGjfIcW6lc7fDgONEEVB11kX0SkY35+6ZLRclwzNlcQQqbHTSnOLYxemGb7T23ci2jRHwqQnPFKteKFivg9dGR9M35iTTw2JOLFyTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=q7jd9oOJBjwGhZ70sKHmh/QoTm9YFpUcPtkiwfsiHq8=; b=dqs1pioRIGXcoc2KwXL6i8IR6WJq56ux8nloaK922TecQNRolp/LzVzgN/ibH9KOvVl1btTIvGCRDVhJtMuOEMLwpWzUZsWzVYtrNrv1BmmM+S1KXO0VdNW88uV539GmLEJqitiOPacYC70unxdVggfdj7PGgDoKoVAP86YtycuoOc2BEYCEzt/S0rupdcHRxS4pN4oGNP8yis28wZZYNT4auvpyxUb1z4RWpGxs+bwsx/GqCewWUTS0cwS9wsKGpbCxERWcvnmljEzf2W3kde6enLO7s79nJodFkFYtdSPVZWVzJnFVtx3EhwYwasuKgH9j3y64YSRoIHnBl5JtNQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oracle.com; dmarc=pass action=none header.from=oracle.com; dkim=pass header.d=oracle.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.onmicrosoft.com; s=selector2-oracle-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=q7jd9oOJBjwGhZ70sKHmh/QoTm9YFpUcPtkiwfsiHq8=; b=ii8BKL5Q7mdjf306L9AaWEoFQm1b+Mg09IBWKM0rYXofJf+ZHQANbQTMzEQgbHU7UOLwZktHzhZh8Sn4HYQSnXq73Ii+om+6zdjxRY4JE2ziQLLoV6nAYGPMzSI5yIwIaGXivCU7zCEerq9SCsZ0bqa5JhZhOemkvwzdMJVfWgs= Received: from SA2PR10MB4636.namprd10.prod.outlook.com (2603:10b6:806:11e::10) by PH7PR10MB6602.namprd10.prod.outlook.com (2603:10b6:510:206::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7587.27; Fri, 17 May 2024 04:08:25 +0000 Received: from SA2PR10MB4636.namprd10.prod.outlook.com ([fe80::1b3d:bd64:9100:c3fb]) by SA2PR10MB4636.namprd10.prod.outlook.com ([fe80::1b3d:bd64:9100:c3fb%7]) with mapi id 15.20.7587.028; Fri, 17 May 2024 04:08:25 +0000 From: vladimir.mezentsev@oracle.com To: binutils@sourceware.org Cc: Vladimir Mezentsev Subject: [PATCH 2/2] gprofng: add hardware counters for AMD Zen3 Date: Thu, 16 May 2024 21:08:18 -0700 Message-Id: <20240517040818.2663535-1-vladimir.mezentsev@oracle.com> X-Mailer: git-send-email 2.31.1 X-ClientProxiedBy: BY3PR05CA0060.namprd05.prod.outlook.com (2603:10b6:a03:39b::35) To SA2PR10MB4636.namprd10.prod.outlook.com (2603:10b6:806:11e::10) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PR10MB4636:EE_|PH7PR10MB6602:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f1741a0-2171-4fb2-9a8f-08dc7626ffa7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|1800799015|376005; X-Microsoft-Antispam-Message-Info: EDCZudQwOlE8XvuPMvN451isy9i73V3BxFz+ldFAjtMZw1ufY/BiIatW3NCyKtg3P3nt60sSEVdYyNENBdQKUwrqqb9ygTBt1fw+zHdn5Z0bty+7WsNeuVrCw8SdWvuFr2mPHZo4m0xpkqsJiQvsgVozv/kOTJ7yDwf91/qkxdKlbS5D8cS+C39iadU2+NJAcoeqkL410RhiVQOW3oizSJf56OKCtxDRg6HATE1vcVPGZNwVZRD2+IEVQX8khm4PMjU6o6nxqgG0xbz/3Hezcrede96RPFHbMGxFoMLSdTPPjYxyluxqZ/7r4Vrpl81hAlfOLhton+CX6INSCkCjyR/GNfVQLwzKprZQjvQYA2zltGhXQa5NS0k0qrM1p7vrxpfzDJyr6CNDkZcCfVlGs38PYwZnzhgeBVZYOk2pBnpDgJgRXPXeqgGG7BN3Z2dI94YmQNsznhBdZJmFD+rhOhYyGeCelONptebjOMYmtMD20CXkIt/qRXPhO2u1J9L6nwmujyuW/7qeg3YkVTjt0AL3Mm0qD+F4XQ1Ve9NOUHdGbpNaKB5W9jzqEARU8SCwF5Y/mUR1U4JPjIkCIOljYfafqc2MZcGzPsDPTUNb+Ek93vp1rrL6FR8BbSZmcQWhwyUNAsSpYh6ElHl2pyIA+nZpU0LeijgxmB93IwsZobPg3OcOADpymvPHX03U+GVeSFlTxpKeAaHuULECJZwecUYnqyW/CuAigmsJDYfgEuBj0v35oIjqa2knRqoQ+vqSiLOEs8WpVOHRey+kSvvTip+rxxSPQDrgHiGAMssCb6eOjSqtc1DIAeynMjcK+RWUZlaCYa+YkxH/9S2qurXVg0BQmfkLvV39qhzASRCZL6d6Y5CxXAgYeUdEkybW0gq3e342G3koPy+AZ3R5MvXo5Etailjn6qfxnwoT5AJQE9I4Yn55KzDtJI4ITUj/h3dhwmJcrnO4qsVR4a94mDZUpo4CHRzk5j4Zk8jFTHwTyjAwHY7rsr92a3kg0JWsdg2VJLLLdkA5PTk5miRcyPUGZRoPIDVVVg7tPkjzI/F+jccP9rl95HzAaayy0wrxRKntJbyvdCxeQbH8B+IBM41jnb6jOIq00VIzdafXDiteyEmFmF++T72FcI3izMNs/L/SAo+tn3xKOgc/KAaBEhyJbAP/C/L4UeSV3xjXdKkdaLVYe4wXV3291QWtcrKLkLJcFqI/xCK6yh1L42qZ6q3yLjGalAJPvSqaeDxdqC4IQcg= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SA2PR10MB4636.namprd10.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366007)(1800799015)(376005); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Wyvnrg4zl9xvWcb6qzsmVErBXq0KBEqAG8vpYCMg9nHZsnLjJRJil1m6UF7Uts7l462R/fIRL+A8jQ+NfRIltmwZ+zwCy1ASPjmm86UEdNQeSU4dSkGi+boVW4EOEGH1z96BO81UVhtB/r07c0Fo425+cWCsr1RqqD5UVV5+S8rOM/PldHZvm7UaP5DwAaEtt5dsr1T1MieKfkygb7O/To7KYM58iJTbF/ob6vOyumEL7Fw+VA2UbOY9+DjSBF5CToWwbp+qhHGN8af8uIeGXLFuzko0nw+Qw1yvtQniJL8RBm+KhrYmxCUYL//KqGBGotlXdK7+PVyS1SoPuRwhwvMwWRFZQgNxQyki+Aq0sW9CZnSWaPQ/1OrIsmvKGrhEZNIP/eKgAcgB5TlDARG2pwJpT5pA5ucJCigmO43iUhVnpVyphsTujKaHFeTwhoqao6uYNjJ6G48vWn4+aGTqCJ/uFznG8W7nL7ft2quWMv6Uu3z9NP4kBXIb0QDNN5ikAjikXAVIxOmJXy4iVwwdlJ7ZT7O4jyLRD0/VQDd2xPdMrqGSf0MHS7RUBh6iYRHpRdYcSlswjkJzYLbZD9WHjouDqVvTHGNVPcbAvgDWHjnzzbS0ldw16SfHqixtNObid6EQsC28gv08H1OasgI6mejmFwAwFUGS9bqEaqC3XRv+Kj0iOK4vEVRcT/7TVc98lJ0bp8XGw5sAk4sr4GRYlyIB2lBNU+4RJGKeB8F9gzRIXBUI9e145ERGA+3WSzFOXQYYLfuPhrAQj5lysaufhLlcD5sivUjoEPkpHsLrboHbx+ujuMHj4P6PI2N+Cz/3RaNZN7YSbhLouHkWAurkD3qDIOmtPmyzQNfVeUb7hbvWNHvfaMljxVZ3nKkqwrD64lgnkj8Y+55MnNKkRdPtnpIvMTJ1GbfLcc/k0BZ/RbbsGdGkywLWfOBsMOlnuwvXIGZ0bJxL8wlc2yY3xac0J9Oyd4yHacALKwmYZHcOLzOema9zw6USr6nF2tR+tmfj2wX+g+GOPsOq7KzHXHkVEpZ4HA8NF6Uy8uZPLZFBWqRUeuFpdyaqPGQlGsFSS8oQuu0M6KW2ZzxufkqS3lOjPfvHfB8ZDIahbS4+xOfF2PFGDPgdR01c/oe4+faNCI9nyn3eQ9COuYrod6Fe4pvugXVTJzYJg3Ad1LZohHvRHIP46vjyvkMZZeAc4X0ZQX2CaWbpz+9BuJk/SFP+7DWacUWmOk8tPwPMOzSIBis4UVQeV2v46p2JpObzSRv1UwyIIDarAuoDOKzRZm+GdcwsYZJMcoIb/Ltm0GycVyRcnDSKTuRVzqtSmCFcmkL3+rxiA2vIL88urbtuHAh+6gu3U770bq3+eFm3WlkOK0zKSSao8tX+WDcAp+sVnFnL591jsSC3AAR+BSZAn4a1OxZEbD+7ktSXNhTkHKsKzn0sldMWUsXo7xDnwAnb1amjnD+8HfzlR1aGesm6vbalcmrBUc6EnkzTr/rkfGE2BXiDvX0ULi1EkaUP2tfDBaqPAQTJ1Oi5RuY5MG6h/PVkeFaxsj7S6nonPoMrO2jy/YZJnixUHc6mifdyAcA8VZjndkam/Arp3M5NdDukYGfW99W2xYIFWhy0LHfikp7GeZXolT5GUho/i9J3AYvyV2z0pcUC X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: d29lDicA60QD7xCJZhj/dtYQc+slXtLqaqZzYolB/Q9g0Pq8/W3PdY4MVMhjHNTrQwq8mhRtJ0mFulpsOzgxhW/4D1yNZuqXO4G7lwnPVD/k7Fh9IJOvhXNcpZZ5P95renyWnBrSud4ZTrt0brJ/95nOPgIz1W4YKxaODTohEGtPTxkKQM7ctFRQztUs+SxWyTFdWHzEZsmhzufhBIOa/cCdFO827ofAcDonzOb73A26pfo0LtBpDnN5vodz/P/K2L+tIl7i+2wZBIWJE7bUzltjkRu0l+FaumDioBIotytr5cNBAiNrbuaT94k6r/Z0cbnWmMHnVC3BJkNJk+S27lSPxLVJQq09A9ZrEcqDVtMcRwcUboumqc8jSuXax/xtCnBoxVBoeoA6xQ1dZGq99hbhTFwv9pwdGn+vfkACvzwv8uI/Xt2izTH7G98BLj65o/8PkRIotIsQERXy/AVnDGMc7xs6aEUv8sb82bdlEnWYkS/oC5h/mFEn7ek2pzsFY5UgTRURNTW6T6PRAIX61XO1LyjYaBRwBPRpZ+dPqlPAiTvgHn9cqOuBDXYw0YfjaCAeKsS953G64YxUUYdUWkCLr1nD91Y0nSvmw+v2uvU= X-OriginatorOrg: oracle.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8f1741a0-2171-4fb2-9a8f-08dc7626ffa7 X-MS-Exchange-CrossTenant-AuthSource: SA2PR10MB4636.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2024 04:08:25.5084 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: F153FJr1DRpxpGh01rCnVGKXXOoOXAwLk4Y7T0nRw7MMofsFVT7DfvwvnwinFslxnnTtx4I2ZdaumzHegrrQBXOGyJItYNuEpXUErvkfxds= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR10MB6602 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 adultscore=0 mlxlogscore=999 phishscore=0 malwarescore=0 suspectscore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405170031 X-Proofpoint-GUID: 61E-efnEn-FfsRJyl9hGHcV1Z3nU0nrE X-Proofpoint-ORIG-GUID: 61E-efnEn-FfsRJyl9hGHcV1Z3nU0nrE X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org From: Vladimir Mezentsev Historically, we have used several APIs (perfctr, libcpc, perf_event_open) for profiling. For each hardware we have several tables of hardware counters. Some information is duplicated in these tables. Some of the information is no longer used. I did not touch the existing hwc tables. I added a new hwc table for an AMD Zen3 machine. ChangeLog 2024-05-16 Vladimir Mezentsev PR gprofng/31123 * common/core_pcbe.c (core_pcbe_get_events): Add new argument. * common/hwc_cpus.h: New constants for AMD hardware. * common/hwcdrv.c: Add new argument to hwcdrv_get_descriptions. Clean up the code. * common/hwcdrv.h: Likewise. * common/hwcfuncs.c (hwcdrv_get_descriptions): Add new argument. * common/hwctable.c: Add the hwc table for AMD Zen3. * src/hwc_amd_zen3.h: New file. * common/opteron_pcbe.c: Add new argument to opt_pcbe_get_events. * src/collctrl.cc: Remove unused variable. * src/collctrl.h: Likewise. --- gprofng/common/core_pcbe.c | 17 +- gprofng/common/hwc_cpus.h | 39 ++- gprofng/common/hwcdrv.c | 22 +- gprofng/common/hwcdrv.h | 17 +- gprofng/common/hwcfuncs.c | 2 +- gprofng/common/hwctable.c | 149 ++++---- gprofng/common/opteron_pcbe.c | 60 +++- gprofng/src/collctrl.cc | 7 +- gprofng/src/collctrl.h | 1 - gprofng/src/hwc_amd_zen3.h | 632 ++++++++++++++++++++++++++++++++++ 10 files changed, 820 insertions(+), 126 deletions(-) create mode 100644 gprofng/src/hwc_amd_zen3.h diff --git a/gprofng/common/core_pcbe.c b/gprofng/common/core_pcbe.c index 30977f0ebb2..805bd14465b 100644 --- a/gprofng/common/core_pcbe.c +++ b/gprofng/common/core_pcbe.c @@ -2734,13 +2734,6 @@ core_pcbe_init (void) { switch (cpuid_getvendor ()) { - case X86_VENDOR_AMD: - snprintf (core_impl_name, sizeof (core_impl_name), "%s", X86_VENDORSTR_AMD); - events_table = events_generic; - num_gpc = 4; - num_ffc = 0; - total_pmc = num_gpc + num_ffc; - return 0; case ARM_CPU_IMP_ARM: case ARM_CPU_IMP_BRCM: case ARM_CPU_IMP_CAVIUM: @@ -2948,7 +2941,7 @@ core_pcbe_cpuref (void) } static int -core_pcbe_get_events (hwcf_hwc_cb_t *hwc_cb) +core_pcbe_get_events (hwcf_hwc_cb_t *hwc_cb, Hwcentry *raw_hwc_tbl) { int count = 0; const struct events_table_t *pevent; @@ -2966,6 +2959,14 @@ core_pcbe_get_events (hwcf_hwc_cb_t *hwc_cb) count++; } /* add generic events here */ + if (raw_hwc_tbl) + for (Hwcentry *h = raw_hwc_tbl; h->name; h++) + if (h->use_perf_event_type) + for (int jj = 0; jj < num_gpc; jj++) + { + hwc_cb (jj, h->name); + count++; + } return count; } diff --git a/gprofng/common/hwc_cpus.h b/gprofng/common/hwc_cpus.h index 4b770832b15..59052a0912c 100644 --- a/gprofng/common/hwc_cpus.h +++ b/gprofng/common/hwc_cpus.h @@ -34,8 +34,16 @@ typedef struct char *cpu_modelstr; } cpu_info_t; +#ifdef __cplusplus +extern "C" +{ +#endif extern cpu_info_t *read_cpuinfo(); +#ifdef __cplusplus +} +#endif + #define MAX_PICS 20 /* Max # of HW ctrs that can be enabled simultaneously */ /* type for specifying CPU register number */ @@ -105,6 +113,8 @@ extern cpu_info_t *read_cpuinfo(); #define CPC_AMD_FAM_11H 2502 /* Griffin... */ #define CPC_AMD_FAM_15H 2503 #define CPC_AMD_Authentic 2504 +#define CPC_AMD_FAM_19H_ZEN3 2505 +#define CPC_AMD_FAM_19H_ZEN4 2506 #define CPC_KPROF 3003 // OBSOLETE (To support 12.3 and earlier) #define CPC_FOX 3004 /* pseudo-chip */ @@ -117,7 +127,32 @@ extern cpu_info_t *read_cpuinfo(); #define CPC_SPARC64_X 4006 /* Athena */ #define CPC_SPARC64_XII 4010 /* Athena++ */ -// aarch64. Constants from tools/arch/arm64/include/asm/cputype.h +#define AMD_FAM_19H_ZEN3_NAME "AMD Family 19h (Zen3)" +#define AMD_FAM_19H_ZEN4_NAME "AMD Family 19h (Zen4)" + +enum Amd_famaly +{ + AMD_ZEN_FAMILY = 0x17, + AMD_ZEN3_FAMILY = 0x19 +}; + +enum Amd_model +{ + AMD_ZEN_RYZEN = 0x1, + AMD_ZENPLUS_RYZEN = 0x8, + AMD_ZENPLUS_RYZEN2 = 0x18, + AMD_ZEN2_RYZEN = 0x31, + AMD_ZEN2_RYZEN2 = 0x71, + AMD_ZEN2_RYZEN3 = 0x60, + AMD_ZEN3_RYZEN = 0x1, + AMD_ZEN3_RYZEN2 = 0x21, + AMD_ZEN3_RYZEN3 = 0x50, + AMD_ZEN3_EPYC_TRENTO = 0x30, + AMD_ZEN4_RYZEN = 0x61, + AMD_ZEN4_EPYC = 0x11 +}; + + // aarch64. Constants from tools/arch/arm64/include/asm/cputype.h // in https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git enum { ARM_CPU_IMP_ARM = 0x41, @@ -147,6 +182,8 @@ enum { {CPC_AMD_FAM_15H , "AMD Family 15h Model 01h"}, \ {CPC_AMD_FAM_15H , "AMD Family 15h Model 02h"},/*future*/ \ {CPC_AMD_FAM_15H , "AMD Family 15h Model 03h"},/*future*/ \ + {CPC_AMD_FAM_19H_ZEN3 , AMD_FAM_19H_ZEN3_NAME}, \ + {CPC_AMD_FAM_19H_ZEN4 , AMD_FAM_19H_ZEN4_NAME}, \ {CPC_PENTIUM_4_HT , "Pentium 4 with HyperThreading"}, \ {CPC_PENTIUM_4 , "Pentium 4"}, \ {CPC_PENTIUM_PRO_MMX , "Pentium Pro with MMX, Pentium II"}, \ diff --git a/gprofng/common/hwcdrv.c b/gprofng/common/hwcdrv.c index 0ada09d0ca8..0b4cfc306b7 100644 --- a/gprofng/common/hwcdrv.c +++ b/gprofng/common/hwcdrv.c @@ -34,6 +34,7 @@ #include "cpuid.c" /* ftns for identifying a chip */ +static hdrv_pcbe_api_t *pcbe_driver = NULL; static hdrv_pcbe_api_t hdrv_pcbe_core_api; static hdrv_pcbe_api_t hdrv_pcbe_opteron_api; static hdrv_pcbe_api_t *hdrv_pcbe_drivers[] = { @@ -94,8 +95,6 @@ hwcdrv_lookup_cpuver (const char * cpcN_cciname) * For M8, a 4-bit mask of supported PICs is stored in bits [23:20]. */ -IS_GLOBAL hwcdrv_get_eventnum_fn_t *hwcdrv_get_x86_eventnum = 0; - static const attr_info_t perfctr_sparc_attrs[] = { {NTXT ("user"), 0, 0x01, 16}, //usr {NTXT ("system"), 0, 0x01, 17}, //os @@ -132,8 +131,9 @@ myperfctr_get_x86_eventnum (const char *eventname, uint_t pmc, eventsel_t *eventsel, eventsel_t *valid_umask, uint_t *pmc_sel) { - if (hwcdrv_get_x86_eventnum && - !hwcdrv_get_x86_eventnum (eventname, pmc, eventsel, valid_umask, pmc_sel)) + if (pcbe_driver && pcbe_driver->hdrv_pcbe_get_eventnum && + !pcbe_driver->hdrv_pcbe_get_eventnum (eventname, pmc, eventsel, + valid_umask, pmc_sel)) return 0; /* check for numerically-specified counters */ @@ -214,7 +214,7 @@ set_x86_attr_bits (eventsel_t *result_mask, eventsel_t evnt_valid_umask, return 0; } -IS_GLOBAL int +static int hwcfuncs_get_x86_eventsel (unsigned int regno, const char *int_name, eventsel_t *return_event, uint_t *return_pmc_sel) { @@ -287,6 +287,7 @@ perf_event_open (struct perf_event_attr *hw_event_uptr, pid_t pid, rc = syscall (__NR_perf_event_open, hw_event_uptr, pid, cpu, group_fd, flags); if (rc != -1) return rc; + TprintfT (0, "perf_event_open %d: errno=%d %s\n", retry, errno, strerror(errno)); } return rc; } @@ -375,7 +376,6 @@ static struct int internal_open_called; hwcfuncs_tsd_get_fn_t find_vpc_ctx; unsigned hwcdef_cnt; /* number of *active* hardware counters */ - hwcdrv_get_events_fn_t *get_events; } hdrv_pcl_state; static hwcdrv_about_t hdrv_pcl_about = {.cpcN_cpuver = CPUVER_UNDEFINED}; @@ -813,14 +813,13 @@ hdrv_pcl_internal_open () hdrv_pcbe_api_t *ppcbe = hdrv_pcbe_drivers[ii]; if (!ppcbe->hdrv_pcbe_init ()) { + pcbe_driver = ppcbe; hdrv_pcl_about.cpcN_cciname = ppcbe->hdrv_pcbe_impl_name (); hdrv_pcl_about.cpcN_cpuver = hwcdrv_lookup_cpuver (hdrv_pcl_about.cpcN_cciname); if (hdrv_pcl_about.cpcN_cpuver == CPUVER_UNDEFINED) goto internal_open_error; hdrv_pcl_about.cpcN_npics = ppcbe->hdrv_pcbe_ncounters (); hdrv_pcl_about.cpcN_docref = ppcbe->hdrv_pcbe_cpuref (); - hdrv_pcl_state.get_events = ppcbe->hdrv_pcbe_get_events; - hwcdrv_get_x86_eventnum = ppcbe->hdrv_pcbe_get_eventnum; break; } } @@ -894,11 +893,12 @@ hwcdrv_enable_mt (hwcfuncs_tsd_get_fn_t tsd_ftn) } HWCDRV_API int -hwcdrv_get_descriptions (hwcf_hwc_cb_t *hwc_cb, hwcf_attr_cb_t *attr_cb) +hwcdrv_get_descriptions (hwcf_hwc_cb_t *hwc_cb, hwcf_attr_cb_t *attr_cb, + Hwcentry *raw_hwc_tbl) { int count = 0; - if (hwc_cb && hdrv_pcl_state.get_events) - count = hdrv_pcl_state.get_events (hwc_cb); + if (hwc_cb && pcbe_driver && pcbe_driver->hdrv_pcbe_get_events) + count = pcbe_driver->hdrv_pcbe_get_events (hwc_cb, raw_hwc_tbl); if (attr_cb) for (int ii = 0; perfctr_attrs_table && perfctr_attrs_table[ii].attrname; ii++) attr_cb (perfctr_attrs_table[ii].attrname); diff --git a/gprofng/common/hwcdrv.h b/gprofng/common/hwcdrv.h index 0a5eb33df00..fb97c8abe04 100644 --- a/gprofng/common/hwcdrv.h +++ b/gprofng/common/hwcdrv.h @@ -126,11 +126,13 @@ extern "C" */ int (*hwcdrv_get_descriptions)(hwcf_hwc_cb_t *hwc_find_action, - hwcf_attr_cb_t *attr_find_action); - /* Initiate callbacks with all available HWC names and and HWC attributes. + hwcf_attr_cb_t *attr_find_action, + Hwcentry *raw_hwc_tbl); + /* Initiate callbacks with all available HWC names and HWC attributes. Input: : if not NULL, will be called once for each HWC : if not NULL, will be called once for each attribute + : counter definitions. Return: 0 if successful or a cpc return code upon error */ @@ -260,15 +262,6 @@ extern "C" ( (((eventsel_t)(evnum) & 0x0f00ULL) << 24) | ((eventsel_t)(evnum) & ~0x0f00ULL) ) typedef uint64_t eventsel_t; - extern int hwcfuncs_get_x86_eventsel (unsigned int regno, const char *int_name, - eventsel_t *return_event, uint_t *return_pmc_sel); - - typedef int (hwcdrv_get_events_fn_t) (hwcf_hwc_cb_t *hwc_cb); - typedef int (hwcdrv_get_eventnum_fn_t) (const char *eventname, uint_t pmc, - eventsel_t *eventnum, - eventsel_t *valid_umask, uint_t *pmc_sel); - extern hwcdrv_get_eventnum_fn_t *hwcdrv_get_x86_eventnum; - typedef struct { const char * attrname; // user-visible name of attribute @@ -285,7 +278,7 @@ extern "C" uint_t (*hdrv_pcbe_ncounters)(void); const char *(*hdrv_pcbe_impl_name)(void); const char *(*hdrv_pcbe_cpuref)(void); - int (*hdrv_pcbe_get_events)(hwcf_hwc_cb_t *hwc_cb); + int (*hdrv_pcbe_get_events)(hwcf_hwc_cb_t *hwc_cb, Hwcentry *raw_hwc_tbl); int (*hdrv_pcbe_get_eventnum)(const char * eventname, uint_t pmc, eventsel_t *eventnum, eventsel_t *valid_umask, uint_t *pmc_sel); diff --git a/gprofng/common/hwcfuncs.c b/gprofng/common/hwcfuncs.c index fce711df6a6..e6448a9e062 100644 --- a/gprofng/common/hwcfuncs.c +++ b/gprofng/common/hwcfuncs.c @@ -63,7 +63,7 @@ hwcdrv_enable_mt (hwcfuncs_tsd_get_fn_t tsd_ftn) HWCDRV_API int hwcdrv_get_descriptions (hwcf_hwc_cb_t *hwc_find_action, - hwcf_attr_cb_t *attr_find_action) + hwcf_attr_cb_t *attr_find_action, Hwcentry *hwcdef) { return 0; } diff --git a/gprofng/common/hwctable.c b/gprofng/common/hwctable.c index 40b4cd850ba..5dc8dde7d97 100644 --- a/gprofng/common/hwctable.c +++ b/gprofng/common/hwctable.c @@ -2369,82 +2369,86 @@ static Hwcentry amd_15h[] = { #define HWCE(nm, mtr, id, op, res) \ INIT_HWC(nm, mtr, (id) | ((op) << 8) | ((res) << 16), PERF_TYPE_HW_CACHE) -static Hwcentry generic_list[] = { -// Hardware event: - { HWE("usr_time", STXT("User CPU"), PERF_COUNT_HW_CPU_CYCLES), .timecvt = 1, - .int_name = "cycles" }, - { HWE("sys_time", STXT("System CPU"), PERF_COUNT_HW_CPU_CYCLES), .timecvt = 1, - .int_name = "cycles~system=1~user=0" }, - { HWE("branch-instructions", STXT("Branch-instructions"), - PERF_COUNT_HW_BRANCH_INSTRUCTIONS) }, - { HWE("branch-misses", STXT("Branch-misses"), PERF_COUNT_HW_BRANCH_MISSES) }, - { HWE("bus-cycles", STXT("Bus Cycles"), PERF_COUNT_HW_BUS_CYCLES), - .timecvt = 1 }, - { HWE("cache-misses", STXT("Cache-misses"), PERF_COUNT_HW_CACHE_MISSES) }, - { HWE("cache-references", STXT("Cache-references"), - PERF_COUNT_HW_CACHE_REFERENCES) }, - { HWE("cycles", STXT("CPU Cycles"), PERF_COUNT_HW_CPU_CYCLES), .timecvt = 1 }, - { HWE("insts", STXT("Instructions Executed"), PERF_COUNT_HW_INSTRUCTIONS), - .int_name = "instructions" }, - { HWE("ref-cycles", STXT("Total Cycles"), PERF_COUNT_HW_REF_CPU_CYCLES), - .timecvt = 1 }, - { HWE("stalled-cycles-backend", STXT("Stalled Cycles during issue."), - PERF_COUNT_HW_STALLED_CYCLES_BACKEND), .timecvt = 1 }, - { HWE("stalled-cycles-frontend", STXT("Stalled Cycles during retirement."), - PERF_COUNT_HW_STALLED_CYCLES_FRONTEND), .timecvt = 1 }, -// Software event: - { SWE("alignment-faults", STXT("Alignment Faults"), - PERF_COUNT_SW_ALIGNMENT_FAULTS) }, - { SWE("context-switches", STXT("Context Switches"), - PERF_COUNT_SW_CONTEXT_SWITCHES) }, - { SWE("cpu-clock", STXT("CPU Clock"), PERF_COUNT_SW_CPU_CLOCK), - .timecvt = 1 }, - { SWE("cpu-migrations", STXT("CPU Migrations"), - PERF_COUNT_SW_CPU_MIGRATIONS) }, - { SWE("emulation-faults", STXT("Emulation Faults"), - PERF_COUNT_SW_EMULATION_FAULTS) }, - { SWE("major-faults", STXT("Major Page Faults"), - PERF_COUNT_SW_PAGE_FAULTS_MAJ) }, - { SWE("minor-faults", STXT("Minor Page Faults"), - PERF_COUNT_SW_PAGE_FAULTS_MIN) }, - { SWE("page-faults", STXT("Page Faults"), PERF_COUNT_SW_PAGE_FAULTS) }, - { SWE("task-clock", STXT("Clock Count Specific"), PERF_COUNT_SW_TASK_CLOCK), - .timecvt = 1 }, -// Hardware cache event - { HWCE("L1-dcache-load-misses", STXT("L1 D-cache Load Misses"), - PERF_COUNT_HW_CACHE_L1D, - PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_MISS) }, - { HWCE("L1-dcache-loads", STXT("L1 D-cache Loads"), - PERF_COUNT_HW_CACHE_L1D, - PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_ACCESS) }, - { HWCE("L1-dcache-store-misses", STXT("L1 D-cache Store Misses"), - PERF_COUNT_HW_CACHE_L1D, - PERF_COUNT_HW_CACHE_RESULT_MISS, PERF_COUNT_HW_CACHE_RESULT_ACCESS) }, - { HWCE("L1-dcache-stores", STXT("L1 D-cache Store Stores"), - PERF_COUNT_HW_CACHE_L1D, - PERF_COUNT_HW_CACHE_OP_WRITE, PERF_COUNT_HW_CACHE_RESULT_ACCESS) }, - { HWCE("L1-icache-load-misses", STXT("L1 Instructions Load Misses"), - PERF_COUNT_HW_CACHE_L1I, - PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_MISS) }, - { HWCE("L1-icache-load-misses", STXT("L1 Instructions Loads"), - PERF_COUNT_HW_CACHE_L1I, - PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_ACCESS) }, - { HWCE("dTLB-load-misses", STXT("D-TLB Load Misses"), - PERF_COUNT_HW_CACHE_DTLB, - PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_MISS) }, - { HWCE("dTLB-loads", STXT("D-TLB Loads"), - PERF_COUNT_HW_CACHE_DTLB, - PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_ACCESS) }, - { HWCE("iTLB-load-misses", STXT("The Instruction TLB Load Misses"), - PERF_COUNT_HW_CACHE_ITLB, - PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_MISS) }, - { HWCE("iTLB-loads", STXT("The Instruction TLB Loads"), - PERF_COUNT_HW_CACHE_ITLB, +#define HWC_GENERIC \ + /* Hardware event: */\ + { HWE("usr_time", STXT("User CPU"), PERF_COUNT_HW_CPU_CYCLES), .timecvt = 1,\ + .int_name = "cycles" },\ + { HWE("sys_time", STXT("System CPU"), PERF_COUNT_HW_CPU_CYCLES), .timecvt = 1,\ + .int_name = "cycles~system=1~user=0" },\ + { HWE("branch-instructions", STXT("Branch-instructions"),\ + PERF_COUNT_HW_BRANCH_INSTRUCTIONS) },\ + { HWE("branch-misses", STXT("Branch-misses"), PERF_COUNT_HW_BRANCH_MISSES) },\ + { HWE("bus-cycles", STXT("Bus Cycles"), PERF_COUNT_HW_BUS_CYCLES),\ + .timecvt = 1 },\ + { HWE("cache-misses", STXT("Cache-misses"), PERF_COUNT_HW_CACHE_MISSES) },\ + { HWE("cache-references", STXT("Cache-references"),\ + PERF_COUNT_HW_CACHE_REFERENCES) },\ + { HWE("cycles", STXT("CPU Cycles"), PERF_COUNT_HW_CPU_CYCLES), .timecvt = 1 },\ + { HWE("insts", STXT("Instructions Executed"), PERF_COUNT_HW_INSTRUCTIONS),\ + .int_name = "instructions" },\ + { HWE("ref-cycles", STXT("Total Cycles"), PERF_COUNT_HW_REF_CPU_CYCLES),\ + .timecvt = 1 },\ + { HWE("stalled-cycles-backend", STXT("Stalled Cycles during issue."),\ + PERF_COUNT_HW_STALLED_CYCLES_BACKEND), .timecvt = 1 },\ + { HWE("stalled-cycles-frontend", STXT("Stalled Cycles during retirement."),\ + PERF_COUNT_HW_STALLED_CYCLES_FRONTEND), .timecvt = 1 },\ + /* Software event: */\ + { SWE("alignment-faults", STXT("Alignment Faults"),\ + PERF_COUNT_SW_ALIGNMENT_FAULTS) },\ + { SWE("context-switches", STXT("Context Switches"),\ + PERF_COUNT_SW_CONTEXT_SWITCHES) },\ + { SWE("cpu-clock", STXT("CPU Clock"), PERF_COUNT_SW_CPU_CLOCK),\ + .timecvt = 1 },\ + { SWE("cpu-migrations", STXT("CPU Migrations"),\ + PERF_COUNT_SW_CPU_MIGRATIONS) },\ + { SWE("emulation-faults", STXT("Emulation Faults"),\ + PERF_COUNT_SW_EMULATION_FAULTS) },\ + { SWE("major-faults", STXT("Major Page Faults"),\ + PERF_COUNT_SW_PAGE_FAULTS_MAJ) },\ + { SWE("minor-faults", STXT("Minor Page Faults"),\ + PERF_COUNT_SW_PAGE_FAULTS_MIN) },\ + { SWE("page-faults", STXT("Page Faults"), PERF_COUNT_SW_PAGE_FAULTS) },\ + { SWE("task-clock", STXT("Clock Count Specific"), PERF_COUNT_SW_TASK_CLOCK),\ + .timecvt = 1 },\ + /* Hardware cache event: */\ + { HWCE("L1-dcache-load-misses", STXT("L1 D-cache Load Misses"),\ + PERF_COUNT_HW_CACHE_L1D,\ + PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_MISS) },\ + { HWCE("L1-dcache-loads", STXT("L1 D-cache Loads"),\ + PERF_COUNT_HW_CACHE_L1D,\ + PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_ACCESS) },\ + { HWCE("L1-dcache-store-misses", STXT("L1 D-cache Store Misses"),\ + PERF_COUNT_HW_CACHE_L1D,\ + PERF_COUNT_HW_CACHE_RESULT_MISS, PERF_COUNT_HW_CACHE_RESULT_ACCESS) },\ + { HWCE("L1-dcache-stores", STXT("L1 D-cache Store Stores"),\ + PERF_COUNT_HW_CACHE_L1D,\ + PERF_COUNT_HW_CACHE_OP_WRITE, PERF_COUNT_HW_CACHE_RESULT_ACCESS) },\ + { HWCE("L1-icache-load-misses", STXT("L1 Instructions Load Misses"),\ + PERF_COUNT_HW_CACHE_L1I,\ + PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_MISS) },\ + { HWCE("L1-icache-load-misses", STXT("L1 Instructions Loads"),\ + PERF_COUNT_HW_CACHE_L1I,\ + PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_ACCESS) },\ + { HWCE("dTLB-load-misses", STXT("D-TLB Load Misses"),\ + PERF_COUNT_HW_CACHE_DTLB,\ + PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_MISS) },\ + { HWCE("dTLB-loads", STXT("D-TLB Loads"),\ + PERF_COUNT_HW_CACHE_DTLB,\ + PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_ACCESS) },\ + { HWCE("iTLB-load-misses", STXT("The Instruction TLB Load Misses"),\ + PERF_COUNT_HW_CACHE_ITLB,\ + PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_MISS) },\ + { HWCE("iTLB-loads", STXT("The Instruction TLB Loads"),\ + PERF_COUNT_HW_CACHE_ITLB,\ PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_ACCESS) }, +static Hwcentry generic_list[] = { + HWC_GENERIC {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE} }; +#include "hwc_amd_zen3.h" + /* structure defining the counters for a CPU type */ typedef struct { @@ -2516,6 +2520,7 @@ static cpu_list_t cputabs[] = { {CPC_KPROF, kproflist, {NULL}}, // OBSOLETE (To support 12.3 and earlier, TBR) {ARM_CPU_IMP_APM, generic_list, {"insts,,cycles", 0}}, {CPC_AMD_Authentic, generic_list, {"insts,,cycles", 0}}, + {CPC_AMD_FAM_19H_ZEN3, amd_zen3_list, {"insts,,cycles", 0}}, {0, generic_list, {"insts,,cycles", 0}}, }; @@ -3033,7 +3038,7 @@ setup_cpc_general (int skip_hwc_test) valid_cpu_tables[1] = papi_generic_list; Tprintf (DBG_LT2, "hwctable: setup_cpc(): getting descriptions \n"); // populate cpcx_raw and cpcx_attr - hwcdrv->hwcdrv_get_descriptions (hwc_cb, attrs_cb); + hwcdrv->hwcdrv_get_descriptions (hwc_cb, attrs_cb, cputabs_entry->stdlist_table); for (int kk = 0; kk < 2; kk++) { // collect and er_kernel hwc_process_raw_ctrs (kk, &cpcx_std[kk], &cpcx_raw[kk], &cpcx_hidden[kk], diff --git a/gprofng/common/opteron_pcbe.c b/gprofng/common/opteron_pcbe.c index 0f1815d42e8..a8d7e76731e 100644 --- a/gprofng/common/opteron_pcbe.c +++ b/gprofng/common/opteron_pcbe.c @@ -304,6 +304,8 @@ static amd_generic_event_t family_10h_generic_events[] = { }; static amd_event_t *amd_events = NULL; +static const char *amd_impl_name = ""; +static const char *amd_cpuref = ""; static uint_t amd_family; static amd_generic_event_t *amd_generic_events = NULL; @@ -318,19 +320,39 @@ opt_pcbe_init (void) if (cpuid_getvendor () != X86_VENDOR_AMD) return -1; - /* - * Figure out processor revision here and assign appropriate - * event configuration. - */ + amd_impl_name = GTXT ("Unknown AMD processor"); switch (amd_family) { case OPTERON_FAMILY: amd_events = opt_events_rev_E; amd_generic_events = opt_generic_events; + amd_impl_name = "AMD Opteron & Athlon64"; + amd_cpuref = GTXT ("See Chapter 10 of the \"BIOS and Kernel Developer's" + " Guide for the AMD Athlon 64 and AMD Opteron Processors,\"\n" + "AMD publication #26094"); break; case AMD_FAMILY_10H: amd_events = family_10h_events; amd_generic_events = family_10h_generic_events; + amd_impl_name = "AMD Family 10h"; + amd_cpuref = GTXT ("See section 3.15 of the \"BIOS and Kernel Developer's" + " Guide (BKDG) For AMD Family 10h Processors,\"\n" + "AMD publication #31116"); + break; + case AMD_ZEN3_FAMILY: + switch (cpuid_getmodel ()) + { + case AMD_ZEN3_RYZEN: + case AMD_ZEN3_RYZEN2: + case AMD_ZEN3_RYZEN3: + case AMD_ZEN3_EPYC_TRENTO: + amd_impl_name = AMD_FAM_19H_ZEN3_NAME; + break; + case AMD_ZEN4_RYZEN: + case AMD_ZEN4_EPYC: + amd_impl_name = AMD_FAM_19H_ZEN4_NAME; + break; + } break; } return 0; @@ -345,27 +367,17 @@ opt_pcbe_ncounters (void) static const char * opt_pcbe_impl_name (void) { - if (amd_family == OPTERON_FAMILY) - return ("AMD Opteron & Athlon64"); - else if (amd_family == AMD_FAMILY_10H) - return ("AMD Family 10h"); - else - return ("Unknown AMD processor"); + return amd_impl_name; } static const char * opt_pcbe_cpuref (void) { - if (amd_family == OPTERON_FAMILY) - return GTXT ("See Chapter 10 of the \"BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD Opteron Processors,\"\nAMD publication #26094"); - else if (amd_family == AMD_FAMILY_10H) - return GTXT ("See section 3.15 of the \"BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors,\"\nAMD publication #31116"); - else - return GTXT ("Unknown AMD processor"); + return amd_cpuref; } static int -opt_pcbe_get_events (hwcf_hwc_cb_t *hwc_cb) +opt_pcbe_get_events (hwcf_hwc_cb_t *hwc_cb, Hwcentry *raw_hwc_tbl) { int count = 0; for (uint_t kk = 0; amd_events && amd_events[kk].name; kk++) @@ -380,6 +392,14 @@ opt_pcbe_get_events (hwcf_hwc_cb_t *hwc_cb) hwc_cb (jj, amd_generic_events[kk].name); count++; } + if (raw_hwc_tbl) + for (Hwcentry *h = raw_hwc_tbl; h->name; h++) + if (h->use_perf_event_type) + for (uint_t jj = 0; jj < opt_pcbe_ncounters (); jj++) + { + hwc_cb (jj, h->name); + count++; + } return count; } @@ -392,6 +412,12 @@ opt_pcbe_get_eventnum (const char *eventname, uint_t pmc, eventsel_t *eventsel, *eventsel = (eventsel_t) - 1; *event_valid_umask = 0x0; + if (amd_events == NULL && amd_generic_events == NULL) + { // These tables are created only for old hardware. + *eventsel = 0; + return 0; + } + /* search table */ for (kk = 0; amd_events && amd_events[kk].name; kk++) { diff --git a/gprofng/src/collctrl.cc b/gprofng/src/collctrl.cc index 7d2b23c12ac..28fdb0b577e 100644 --- a/gprofng/src/collctrl.cc +++ b/gprofng/src/collctrl.cc @@ -131,6 +131,10 @@ read_cpuinfo() } fclose (procf); } + if (cpu_info.cpu_vendorstr == NULL) + cpu_info.cpu_vendorstr = GTXT ("Unknown processor"); + if (cpu_info.cpu_modelstr == NULL) + cpu_info.cpu_modelstr = GTXT ("Unknown cpu model"); return &cpu_info; } @@ -176,7 +180,6 @@ Coll_Ctrl::Coll_Ctrl (int _interactive, bool _defHWC, bool _kernelHWC) /* set default clock parameters */ hwcprof_enabled_cnt = 0; // must be set before calling determine_profile_params(); determine_profile_params (); // inits clk_params which is used by clock profiling AND HWCs - cpc_cpuver = CPUVER_UNDEFINED; /* set default control values */ debug_mode = 0; @@ -271,7 +274,6 @@ Coll_Ctrl::Coll_Ctrl (Coll_Ctrl * cc) cpu_clk_freq = cc->cpu_clk_freq; npages = cc->npages; page_size = cc->page_size; - cpc_cpuver = cc->cpc_cpuver; debug_mode = cc->debug_mode; java_mode = cc->java_mode; java_default = cc->java_default; @@ -1470,7 +1472,6 @@ Coll_Ctrl::add_hwcstring (const char *string, char **warnmsg) prev_cnt = 0; /* look up the CPU version */ - cpc_cpuver = hwc_get_cpc_cpuver (); if (string && *string) { /* lookup counters */ diff --git a/gprofng/src/collctrl.h b/gprofng/src/collctrl.h index c32b4303f68..5f1ee26d902 100644 --- a/gprofng/src/collctrl.h +++ b/gprofng/src/collctrl.h @@ -251,7 +251,6 @@ public: char *get_node_name () { return node_name; }; long get_ncpus () { return ncpus; }; int get_cpu_clk_freq () { return cpu_clk_freq; }; - int get_cpc_cpuver () { return cpc_cpuver; }; /* disable warning about non-local filesystems */ void set_nofswarn () { nofswarn = 1; }; diff --git a/gprofng/src/hwc_amd_zen3.h b/gprofng/src/hwc_amd_zen3.h new file mode 100644 index 00000000000..a6400f51ca4 --- /dev/null +++ b/gprofng/src/hwc_amd_zen3.h @@ -0,0 +1,632 @@ +/* Copyright (C) 2024 Free Software Foundation, Inc. + Contributed by Oracle. + + This file is part of GNU Binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define I(nm, event, umask, mtr) INIT_HWC(nm, mtr, (event) | ((umask) << 8), PERF_TYPE_RAW) + +static Hwcentry amd_zen3_list[] = { + HWC_GENERIC +/* branch: */ + { I("bp_de_redirect", 0x91, 0, STXT("Decode Redirects")) }, + { I("bp_dyn_ind_pred", 0x8e, 0, STXT("Dynamic Indirect Predictions")) }, + { I("bp_l1_btb_correct", 0x8a, 0, + STXT("L1 Branch Prediction Overrides Existing Prediction (speculative)")) }, + { I("bp_l1_tlb_fetch_hit", 0x94, 0xff, + STXT("The number of instruction fetches that hit in the L1 ITLB")) }, + { I("bp_l1_tlb_fetch_hit.if1g", 0x94, 0x4, + STXT("The number of instruction fetches that hit in the L1 ITLB. L1" + "Instruction TLB hit (1G page size)")) }, + { I("bp_l1_tlb_fetch_hit.if2m", 0x94, 0x2, + STXT("The number of instruction fetches that hit in the L1 ITLB. L1" + "Instruction TLB hit (2M page size)")) }, + { I("bp_l1_tlb_fetch_hit.if4k", 0x94, 0x1, + STXT("The number of instruction fetches that hit in the L1 ITLB. L1" + "Instrcution TLB hit (4K or 16K page size)")) }, + { I("bp_l2_btb_correct", 0x8b, 0, + STXT("L2 Branch Prediction Overrides Existing Prediction (speculative)")) }, + { I("bp_tlb_rel", 0x99, 0, STXT("The number of ITLB reload requests")) }, +/* cache: */ + { I("bp_l1_tlb_miss_l2_tlb_hit", 0x84, 0, + STXT("L1 ITLB Miss, L2 ITLB Hit. The number of instruction fetches that miss" + "in the L1 ITLB but hit in the L2 ITLB")) }, + { I("bp_l1_tlb_miss_l2_tlb_miss", 0x85, 0xff, + STXT("The number of instruction fetches that miss in both the L1 and L2 TLBs")) }, + { I("bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k", 0x85, 0x8, + STXT("The number of valid fills into the ITLB originating from the LS" + "Page-Table Walker. Tablewalk requests are issued for L1-ITLB and" + "L2-ITLB misses. Walk for >4K Coalesced page")) }, + { I("bp_l1_tlb_miss_l2_tlb_miss.if1g", 0x85, 0x4, + STXT("The number of valid fills into the ITLB originating from the LS" + "Page-Table Walker. Tablewalk requests are issued for L1-ITLB and" + "L2-ITLB misses. Walk for 1G page")) }, + { I("bp_l1_tlb_miss_l2_tlb_miss.if2m", 0x85, 0x2, + STXT("The number of valid fills into the ITLB originating from the LS" + "Page-Table Walker. Tablewalk requests are issued for L1-ITLB and" + "L2-ITLB misses. Walk for 2M page")) }, + { I("bp_l1_tlb_miss_l2_tlb_miss.if4k", 0x85, 0x1, + STXT("The number of valid fills into the ITLB originating from the LS" + "Page-Table Walker. Tablewalk requests are issued for L1-ITLB and" + "L2-ITLB misses. Walk to 4K page")) }, + { I("bp_snp_re_sync", 0x86, 0, + STXT("The number of pipeline restarts caused by invalidating probes that hit" + "on the instruction stream currently being executed. This would happen" + "if the active instruction stream was being modified by another" + "processor in an MP system - typically a highly unlikely event")) }, + { I("ic_cache_fill_l2", 0x82, 0, + STXT("Instruction Cache Refills from L2. The number of 64 byte instruction" + "cache line was fulfilled from the L2 cache")) }, + { I("ic_cache_fill_sys", 0x83, 0, + STXT("Instruction Cache Refills from System. The number of 64 byte" + "instruction cache line fulfilled from system memory or another cache")) }, + { I("ic_cache_inval.fill_invalidated", 0x8c, 0x1, + STXT("IC line invalidated due to overwriting fill response. The number of" + "instruction cache lines invalidated. A non-SMC event is CMC (cross" + "modifying code), either from the other thread of the core or another" + "core")) }, + { I("ic_cache_inval.l2_invalidating_probe", 0x8c, 0x2, + STXT("IC line invalidated due to L2 invalidating probe (external or LS). The" + "number of instruction cache lines invalidated. A non-SMC event is CMC" + "(cross modifying code), either from the other thread of the core or" + "another core")) }, + { I("ic_fetch_stall.ic_stall_any", 0x87, 0x4, + STXT("Instruction Pipe Stall. IC pipe was stalled during this clock cycle" + "for any reason (nothing valid in pipe ICM1)")) }, + { I("ic_fetch_stall.ic_stall_back_pressure", 0x87, 0x1, + STXT("Instruction Pipe Stall. IC pipe was stalled during this clock cycle" + "(including IC to OC fetches) due to back-pressure")) }, + { I("ic_fetch_stall.ic_stall_dq_empty", 0x87, 0x2, + STXT("Instruction Pipe Stall. IC pipe was stalled during this clock cycle" + "(including IC to OC fetches) due to DQ empty")) }, + { I("ic_fw32", 0x80, 0, + STXT("The number of 32B fetch windows transferred from IC pipe to DE" + "instruction decoder (includes non-cacheable and cacheable fill" + "responses)")) }, + { I("ic_fw32_miss", 0x81, 0, + STXT("The number of 32B fetch windows tried to read the L1 IC and missed in" + "the full tag")) }, + { I("ic_oc_mode_switch.ic_oc_mode_switch", 0x28a, 0x1, + STXT("OC Mode Switch. IC to OC mode switch")) }, + { I("ic_oc_mode_switch.oc_ic_mode_switch", 0x28a, 0x2, + STXT("OC Mode Switch. OC to IC mode switch")) }, + { I("ic_tag_hit_miss.all_instruction_cache_accesses", 0x18e, 0x1f, + STXT("All Instruction Cache Accesses. Counts various IC tag related hit and" + "miss events")) }, + { I("ic_tag_hit_miss.instruction_cache_hit", 0x18e, 0x7, + STXT("Instruction Cache Hit. Counts various IC tag related hit and miss" + "events")) }, + { I("ic_tag_hit_miss.instruction_cache_miss", 0x18e, 0x18, + STXT("Instruction Cache Miss. Counts various IC tag related hit and miss" + "events")) }, + { I("l2_cache_req_stat.ic_access_in_l2", 0x64, 0x7, + STXT("Core to L2 cacheable request access status (not including L2" + "Prefetch). Instruction cache requests in L2")) }, + { I("l2_cache_req_stat.ic_dc_hit_in_l2", 0x64, 0xf6, + STXT("Core to L2 cacheable request access status (not including L2" + "Prefetch). Instruction cache request hit in L2 and Data cache request" + "hit in L2 (all types)")) }, + { I("l2_cache_req_stat.ic_dc_miss_in_l2", 0x64, 0x9, + STXT("Core to L2 cacheable request access status (not including L2" + "Prefetch). Instruction cache request miss in L2 and Data cache request" + "miss in L2 (all types)")) }, + { I("l2_cache_req_stat.ic_fill_hit_s", 0x64, 0x2, + STXT("Core to L2 cacheable request access status (not including L2" + "Prefetch). Instruction cache hit non-modifiable line in L2")) }, + { I("l2_cache_req_stat.ic_fill_hit_x", 0x64, 0x4, + STXT("Core to L2 cacheable request access status (not including L2" + "Prefetch). Instruction cache hit modifiable line in L2")) }, + { I("l2_cache_req_stat.ic_fill_miss", 0x64, 0x1, + STXT("Core to L2 cacheable request access status (not including L2" + "Prefetch). Instruction cache request miss in L2. Use" + "l2_cache_misses_from_ic_miss instead")) }, + { I("l2_cache_req_stat.ls_rd_blk_c", 0x64, 0x8, + STXT("Core to L2 cacheable request access status (not including L2" + "Prefetch). Data cache request miss in L2 (all types). Use" + "l2_cache_misses_from_dc_misses instead")) }, + { I("l2_cache_req_stat.ls_rd_blk_cs", 0x64, 0x80, + STXT("Core to L2 cacheable request access status (not including L2" + "Prefetch). Data cache shared read hit in L2")) }, + { I("l2_cache_req_stat.ls_rd_blk_l_hit_s", 0x64, 0x20, + STXT("Core to L2 cacheable request access status (not including L2" + "Prefetch). Data cache read hit non-modifiable line in L2")) }, + { I("l2_cache_req_stat.ls_rd_blk_l_hit_x", 0x64, 0x40, + STXT("Core to L2 cacheable request access status (not including L2" + "Prefetch). Data cache read hit in L2. Modifiable")) }, + { I("l2_cache_req_stat.ls_rd_blk_x", 0x64, 0x10, + STXT("Core to L2 cacheable request access status (not including L2" + "Prefetch). Data cache store or state change hit in L2")) }, + { I("l2_fill_pending.l2_fill_busy", 0x6d, 0x1, + STXT("Cycles with fill pending from L2. Total cycles spent with one or more" + "fill requests in flight from L2")) }, + { I("l2_latency.l2_cycles_waiting_on_fills", 0x62, 0x1, + STXT("Total cycles spent waiting for L2 fills to complete from L3 or memory," + "divided by four. Event counts are for both threads. To calculate" + "average latency, the number of fills from both threads must be used")) }, + { I("l2_pf_hit_l2", 0x70, 0xff, + STXT("L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead")) }, + { I("l2_pf_miss_l2_hit_l3", 0x71, 0xff, + STXT("L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2" + "pipeline which miss the L2 cache and hit the L3")) }, + { I("l2_pf_miss_l2_l3", 0x72, 0xff, + STXT("L2 prefetcher misses in L3. Counts all L2 prefetches accepted by the" + "L2 pipeline which miss the L2 and the L3 caches")) }, + { I("l2_request_g1.all_no_prefetch", 0x60, 0xf9, STXT("(null)")) }, + { I("l2_request_g1.cacheable_ic_read", 0x60, 0x10, + STXT("All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads")) }, + { I("l2_request_g1.change_to_x", 0x60, 0x8, + STXT("All L2 Cache Requests (Breakdown 1 - Common). Data cache state change" + "requests. Request change to writable, check L2 for current state")) }, + { I("l2_request_g1.group2", 0x60, 0x1, + STXT("Miscellaneous events covered in more detail by l2_request_g2 (PMCx061)")) }, + { I("l2_request_g1.l2_hw_pf", 0x60, 0x2, + STXT("All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All" + "prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2" + "hit/miss broken out in a separate perfmon event")) }, + { I("l2_request_g1.ls_rd_blk_c_s", 0x60, 0x20, + STXT("All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads")) }, + { I("l2_request_g1.prefetch_l2_cmd", 0x60, 0x4, + STXT("All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd")) }, + { I("l2_request_g1.rd_blk_l", 0x60, 0x80, + STXT("All L2 Cache Requests (Breakdown 1 - Common). Data cache reads" + "(including hardware and software prefetch)")) }, + { I("l2_request_g1.rd_blk_x", 0x60, 0x40, + STXT("All L2 Cache Requests (Breakdown 1 - Common). Data cache stores")) }, + { I("l2_request_g2.bus_locks_originator", 0x61, 0x2, + STXT("All L2 Cache Requests (Breakdown 2 - Rare). Bus locks")) }, + { I("l2_request_g2.bus_locks_responses", 0x61, 0x1, + STXT("All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response")) }, + { I("l2_request_g2.group1", 0x61, 0x80, + STXT("Miscellaneous events covered in more detail by l2_request_g1 (PMCx060)")) }, + { I("l2_request_g2.ic_rd_sized", 0x61, 0x10, + STXT("All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read" + "sized")) }, + { I("l2_request_g2.ic_rd_sized_nc", 0x61, 0x8, + STXT("All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read" + "sized non-cacheable")) }, + { I("l2_request_g2.ls_rd_sized", 0x61, 0x40, + STXT("All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized")) }, + { I("l2_request_g2.ls_rd_sized_nc", 0x61, 0x20, + STXT("All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized" + "non-cacheable")) }, + { I("l2_request_g2.smc_inval", 0x61, 0x4, + STXT("All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code" + "invalidates")) }, + { I("l2_wcb_req.cl_zero", 0x63, 0x1, + STXT("LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2" + "WCB (Write Combining Buffer) cache line zeroing requests")) }, + { I("l2_wcb_req.wcb_close", 0x63, 0x20, + STXT("LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write" + "Combining Buffer) close requests")) }, + { I("l2_wcb_req.wcb_write", 0x63, 0x40, + STXT("LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write" + "Combining Buffer) write requests")) }, + { I("l2_wcb_req.zero_byte_store", 0x63, 0x4, + STXT("LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB" + "(Write Combining Buffer) zero byte store requests")) }, + { I("op_cache_hit_miss.all_op_cache_accesses", 0x28f, 0x7, + STXT("All Op Cache accesses. Counts Op Cache micro-tag hit/miss events")) }, + { I("op_cache_hit_miss.op_cache_hit", 0x28f, 0x3, + STXT("Op Cache Hit. Counts Op Cache micro-tag hit/miss events")) }, + { I("op_cache_hit_miss.op_cache_miss", 0x28f, 0x4, + STXT("Op Cache Miss. Counts Op Cache micro-tag hit/miss events")) }, +/* core: */ + { I("ex_div_busy", 0xd3, 0, STXT("Div Cycles Busy count")) }, + { I("ex_div_count", 0xd4, 0, STXT("Div Op Count")) }, + { I("ex_ret_brn", 0xc2, 0, STXT("Retired Branch Instructions")) }, + { I("ex_ret_brn_far", 0xc6, 0, STXT("Retired Far Control Transfers")) }, + { I("ex_ret_brn_ind_misp", 0xca, 0, + STXT("Retired Indirect Branch Instructions Mispredicted")) }, + { I("ex_ret_brn_misp", 0xc3, 0, + STXT("Retired Branch Instructions Mispredicted")) }, + { I("ex_ret_brn_resync", 0xc7, 0, STXT("Retired Branch Resyncs")) }, + { I("ex_ret_brn_tkn", 0xc4, 0, STXT("Retired Taken Branch Instructions")) }, + { I("ex_ret_brn_tkn_misp", 0xc5, 0, + STXT("Retired Taken Branch Instructions Mispredicted")) }, + { I("ex_ret_cond", 0xd1, 0, + STXT("Retired Conditional Branch Instructions")) }, + { I("ex_ret_fused_instr", 0x1d0, 0, + STXT("Counts retired Fused Instructions")) }, + { I("ex_ret_ind_brch_instr", 0xcc, 0, + STXT("Retired Indirect Branch Instructions. The number of indirect branches" + "retired")) }, + { I("ex_ret_instr", 0xc0, 0, STXT("Retired Instructions")) }, + { I("ex_ret_mmx_fp_instr.mmx_instr", 0xcb, 0x2, STXT("MMX instructions")) }, + { I("ex_ret_mmx_fp_instr.sse_instr", 0xcb, 0x4, + STXT("SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX)")) }, + { I("ex_ret_mmx_fp_instr.x87_instr", 0xcb, 0x1, STXT("x87 instructions")) }, + { I("ex_ret_msprd_brnch_instr_dir_msmtch", 0x1c7, 0, + STXT("Retired Mispredicted Branch Instructions due to Direction Mismatch")) }, + { I("ex_ret_near_ret", 0xc8, 0, STXT("Retired Near Returns")) }, + { I("ex_ret_near_ret_mispred", 0xc9, 0, + STXT("Retired Near Returns Mispredicted")) }, + { I("ex_ret_ops", 0xc1, 0, + STXT("Retired Ops. Use macro_ops_retired instead")) }, + { I("ex_tagged_ibs_ops.ibs_count_rollover", 0x1cf, 0x4, + STXT("Tagged IBS Ops. Number of times an op could not be tagged by IBS" + "because of a previous tagged op that has not retired")) }, + { I("ex_tagged_ibs_ops.ibs_tagged_ops", 0x1cf, 0x1, + STXT("Tagged IBS Ops. Number of Ops tagged by IBS")) }, + { I("ex_tagged_ibs_ops.ibs_tagged_ops_ret", 0x1cf, 0x2, + STXT("Tagged IBS Ops. Number of Ops tagged by IBS that retired")) }, +/* floating point: */ + { I("fp_disp_faults.x87_fill_fault", 0xe, 0x1, + STXT("Floating Point Dispatch Faults. x87 fill fault")) }, + { I("fp_disp_faults.xmm_fill_fault", 0xe, 0x2, + STXT("Floating Point Dispatch Faults. XMM fill fault")) }, + { I("fp_disp_faults.ymm_fill_fault", 0xe, 0x4, + STXT("Floating Point Dispatch Faults. YMM fill fault")) }, + { I("fp_disp_faults.ymm_spill_fault", 0xe, 0x8, + STXT("Floating Point Dispatch Faults. YMM spill fault")) }, + { I("fp_num_mov_elim_scal_op.opt_potential", 0x4, 0x4, + STXT("Number of Ops that are candidates for optimization (have Z-bit either" + "set or pass). This is a dispatch based speculative event, and is" + "useful for measuring the effectiveness of the Move elimination and" + "Scalar code optimization schemes")) }, + { I("fp_num_mov_elim_scal_op.optimized", 0x4, 0x8, + STXT("Number of Scalar Ops optimized. This is a dispatch based speculative" + "event, and is useful for measuring the effectiveness of the Move" + "elimination and Scalar code optimization schemes")) }, + { I("fp_num_mov_elim_scal_op.sse_mov_ops", 0x4, 0x1, + STXT("Number of SSE Move Ops. This is a dispatch based speculative event," + "and is useful for measuring the effectiveness of the Move elimination" + "and Scalar code optimization schemes")) }, + { I("fp_num_mov_elim_scal_op.sse_mov_ops_elim", 0x4, 0x2, + STXT("Number of SSE Move Ops eliminated. This is a dispatch based" + "speculative event, and is useful for measuring the effectiveness of" + "the Move elimination and Scalar code optimization schemes")) }, + { I("fp_ret_sse_avx_ops.add_sub_flops", 0x3, 0x1, + STXT("Add/subtract FLOPs. This is a retire-based event. The number of" + "retired SSE/AVX FLOPs. The number of events logged per cycle can vary" + "from 0 to 64. This event requires the use of the MergeEvent since it" + "can count above 15 events per cycle. See 2.1.17.3 [Large Increment per" + "Cycle Events]. It does not provide a useful count without the use of" + "the MergeEvent")) }, + { I("fp_ret_sse_avx_ops.all", 0x3, 0xff, + STXT("All FLOPS. This is a retire-based event. The number of retired SSE/AVX" + "FLOPS. The number of events logged per cycle can vary from 0 to 64." + "This event can count above 15")) }, + { I("fp_ret_sse_avx_ops.div_flops", 0x3, 0x4, + STXT("Divide/square root FLOPs. This is a retire-based event. The number of" + "retired SSE/AVX FLOPs. The number of events logged per cycle can vary" + "from 0 to 64. This event requires the use of the MergeEvent since it" + "can count above 15 events per cycle. See 2.1.17.3 [Large Increment per" + "Cycle Events]. It does not provide a useful count without the use of" + "the MergeEvent")) }, + { I("fp_ret_sse_avx_ops.mac_flops", 0x3, 0x8, + STXT("Multiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS." + "This is a retire-based event. The number of retired SSE/AVX FLOPs. The" + "number of events logged per cycle can vary from 0 to 64. This event" + "requires the use of the MergeEvent since it can count above 15 events" + "per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does" + "not provide a useful count without the use of the MergeEvent")) }, + { I("fp_ret_sse_avx_ops.mult_flops", 0x3, 0x2, + STXT("Multiply FLOPs. This is a retire-based event. The number of retired" + "SSE/AVX FLOPs. The number of events logged per cycle can vary from 0" + "to 64. This event requires the use of the MergeEvent since it can" + "count above 15 events per cycle. See 2.1.17.3 [Large Increment per" + "Cycle Events]. It does not provide a useful count without the use of" + "the MergeEvent")) }, + { I("fp_retired_ser_ops.sse_bot_ret", 0x5, 0x8, + STXT("SSE/AVX bottom-executing ops retired. The number of serializing Ops" + "retired")) }, + { I("fp_retired_ser_ops.sse_ctrl_ret", 0x5, 0x4, + STXT("SSE/AVX control word mispredict traps. The number of serializing Ops" + "retired")) }, + { I("fp_retired_ser_ops.x87_bot_ret", 0x5, 0x2, + STXT("x87 bottom-executing ops retired. The number of serializing Ops" + "retired")) }, + { I("fp_retired_ser_ops.x87_ctrl_ret", 0x5, 0x1, + STXT("x87 control word mispredict traps due to mispredictions in RC or PC," + "or changes in mask bits. The number of serializing Ops retired")) }, + { I("fpu_pipe_assignment.total", 0, 0xf, STXT("Total number of fp uOps")) }, + { I("fpu_pipe_assignment.total0", 0, 0x1, + STXT("Total number of fp uOps on pipe 0")) }, + { I("fpu_pipe_assignment.total1", 0, 0x2, + STXT("Total number uOps assigned to pipe 1")) }, + { I("fpu_pipe_assignment.total2", 0, 0x4, + STXT("Total number uOps assigned to pipe 2")) }, + { I("fpu_pipe_assignment.total3", 0, 0x8, + STXT("Total number uOps assigned to pipe 3")) }, +/* memory: */ + { I("ls_alloc_mab_count", 0x5f, 0, STXT("Count of Allocated Mabs")) }, + { I("ls_any_fills_from_sys.ext_cache_local", 0x44, 0x4, + STXT("Any Data Cache Fills by Data Source. From cache of different CCX in" + "same node")) }, + { I("ls_any_fills_from_sys.ext_cache_remote", 0x44, 0x10, + STXT("Any Data Cache Fills by Data Source. From CCX Cache in different Node")) }, + { I("ls_any_fills_from_sys.int_cache", 0x44, 0x2, + STXT("Any Data Cache Fills by Data Source. From L3 or different L2 in same" + "CCX")) }, + { I("ls_any_fills_from_sys.lcl_l2", 0x44, 0x1, + STXT("Any Data Cache Fills by Data Source. From Local L2 to the core")) }, + { I("ls_any_fills_from_sys.mem_io_local", 0x44, 0x8, + STXT("Any Data Cache Fills by Data Source. From DRAM or IO connected in same" + "node")) }, + { I("ls_any_fills_from_sys.mem_io_remote", 0x44, 0x40, + STXT("Any Data Cache Fills by Data Source. From DRAM or IO connected in" + "different Node")) }, + { I("ls_bad_status2.stli_other", 0x24, 0x2, + STXT("Non-forwardable conflict; used to reduce STLI's via software. All" + "reasons. Store To Load Interlock (STLI) are loads that were unable to" + "complete because of a possible match with an older store, and the" + "older store could not do STLF for some reason")) }, + { I("ls_dc_accesses", 0x40, 0, + STXT("Number of accesses to the dcache for load/store references")) }, + { I("ls_dispatch.ld_dispatch", 0x29, 0x1, + STXT("Dispatch of a single op that performs a memory load. Counts the number" + "of operations dispatched to the LS unit. Unit Masks ADDed")) }, + { I("ls_dispatch.ld_st_dispatch", 0x29, 0x4, + STXT("Load-op-Store Dispatch. Dispatch of a single op that performs a load" + "from and store to the same memory address. Counts the number of" + "operations dispatched to the LS unit. Unit Masks ADDed")) }, + { I("ls_dispatch.store_dispatch", 0x29, 0x2, + STXT("Dispatch of a single op that performs a memory store. Counts the" + "number of operations dispatched to the LS unit. Unit Masks ADDed")) }, + { I("ls_dmnd_fills_from_sys.ext_cache_local", 0x43, 0x4, + STXT("Demand Data Cache Fills by Data Source. From cache of different CCX in" + "same node")) }, + { I("ls_dmnd_fills_from_sys.ext_cache_remote", 0x43, 0x10, + STXT("Demand Data Cache Fills by Data Source. From CCX Cache in different" + "Node")) }, + { I("ls_dmnd_fills_from_sys.int_cache", 0x43, 0x2, + STXT("Demand Data Cache Fills by Data Source. From L3 or different L2 in" + "same CCX")) }, + { I("ls_dmnd_fills_from_sys.lcl_l2", 0x43, 0x1, + STXT("Demand Data Cache Fills by Data Source. From Local L2 to the core")) }, + { I("ls_dmnd_fills_from_sys.mem_io_local", 0x43, 0x8, + STXT("Demand Data Cache Fills by Data Source. From DRAM or IO connected in" + "same node")) }, + { I("ls_dmnd_fills_from_sys.mem_io_remote", 0x43, 0x40, + STXT("Demand Data Cache Fills by Data Source. From DRAM or IO connected in" + "different Node")) }, + { I("ls_hw_pf_dc_fills.ext_cache_local", 0x5a, 0x4, + STXT("Hardware Prefetch Data Cache Fills by Data Source. From cache of" + "different CCX in same node")) }, + { I("ls_hw_pf_dc_fills.ext_cache_remote", 0x5a, 0x10, + STXT("Hardware Prefetch Data Cache Fills by Data Source. From CCX Cache in" + "different Node")) }, + { I("ls_hw_pf_dc_fills.int_cache", 0x5a, 0x2, + STXT("Hardware Prefetch Data Cache Fills by Data Source. From L3 or" + "different L2 in same CCX")) }, + { I("ls_hw_pf_dc_fills.lcl_l2", 0x5a, 0x1, + STXT("Hardware Prefetch Data Cache Fills by Data Source. From Local L2 to" + "the core")) }, + { I("ls_hw_pf_dc_fills.mem_io_local", 0x5a, 0x8, + STXT("Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO" + "connected in same node")) }, + { I("ls_hw_pf_dc_fills.mem_io_remote", 0x5a, 0x40, + STXT("Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO" + "connected in different Node")) }, + { I("ls_inef_sw_pref.data_pipe_sw_pf_dc_hit", 0x52, 0x1, + STXT("The number of software prefetches that did not fetch data outside of" + "the processor core. Software PREFETCH instruction saw a DC hit")) }, + { I("ls_inef_sw_pref.mab_mch_cnt", 0x52, 0x2, + STXT("The number of software prefetches that did not fetch data outside of" + "the processor core. Software PREFETCH instruction saw a match on an" + "already-allocated miss request buffer")) }, + { I("ls_int_taken", 0x2c, 0, + STXT("Counts the number of interrupts taken")) }, + { I("ls_l1_d_tlb_miss.all", 0x45, 0xff, + STXT("All L1 DTLB Misses or Reloads. Use l1_dtlb_misses instead")) }, + { I("ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit", 0x45, 0x8, + STXT("L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB")) }, + { I("ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss", 0x45, 0x80, + STXT("L1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLB")) }, + { I("ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit", 0x45, 0x4, + STXT("L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB")) }, + { I("ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss", 0x45, 0x40, + STXT("L1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLB")) }, + { I("ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit", 0x45, 0x1, + STXT("L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB")) }, + { I("ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss", 0x45, 0x10, + STXT("L1 DTLB Miss. DTLB reload to a 4K page that missed the L2 TLB")) }, + { I("ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit", 0x45, 0x2, + STXT("L1 DTLB Miss. DTLB reload to a coalesced page that hit in the L2 TLB")) }, + { I("ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss", 0x45, 0x20, + STXT("L1 DTLB Miss. DTLB reload coalesced page that also missed in the L2" + "TLB")) }, + { I("ls_locks.bus_lock", 0x25, 0x1, + STXT("Retired lock instructions. Comparable to legacy bus lock")) }, + { I("ls_locks.non_spec_lock", 0x25, 0x2, + STXT("Retired lock instructions. Non-speculative lock succeeded")) }, + { I("ls_locks.spec_lock_hi_spec", 0x25, 0x8, + STXT("Retired lock instructions. High speculative cacheable lock speculation" + "succeeded")) }, + { I("ls_locks.spec_lock_lo_spec", 0x25, 0x4, + STXT("Retired lock instructions. Low speculative cacheable lock speculation" + "succeeded")) }, + { I("ls_mab_alloc.all_allocations", 0x41, 0x7f, + STXT("All Allocations. Counts when a LS pipe allocates a MAB entry")) }, + { I("ls_mab_alloc.dc_prefetcher", 0x41, 0x8, + STXT("LS MAB Allocates by Type. DC prefetcher")) }, + { I("ls_mab_alloc.hardware_prefetcher_allocations", 0x41, 0x40, + STXT("Hardware Prefetcher Allocations. Counts when a LS pipe allocates a MAB" + "entry")) }, + { I("ls_mab_alloc.load_store_allocations", 0x41, 0x3f, + STXT("Load Store Allocations. Counts when a LS pipe allocates a MAB entry")) }, + { I("ls_mab_alloc.loads", 0x41, 0x1, + STXT("LS MAB Allocates by Type. Loads")) }, + { I("ls_mab_alloc.stores", 0x41, 0x2, + STXT("LS MAB Allocates by Type. Stores")) }, + { I("ls_misal_loads.ma4k", 0x47, 0x2, + STXT("The number of 4KB misaligned (i.e., page crossing) loads")) }, + { I("ls_misal_loads.ma64", 0x47, 0x1, + STXT("The number of 64B misaligned (i.e., cacheline crossing) loads")) }, + { I("ls_not_halted_cyc", 0x76, 0, STXT("Cycles not in Halt")) }, + { I("ls_pref_instr_disp", 0x4b, 0xff, + STXT("Software Prefetch Instructions Dispatched (Speculative)")) }, + { I("ls_pref_instr_disp.prefetch", 0x4b, 0x1, + STXT("Software Prefetch Instructions Dispatched (Speculative). PrefetchT0," + "T1 and T2 instructions. See docAPM3 PREFETCHlevel")) }, + { I("ls_pref_instr_disp.prefetch_nta", 0x4b, 0x4, + STXT("Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA" + "instruction. See docAPM3 PREFETCHlevel")) }, + { I("ls_pref_instr_disp.prefetch_w", 0x4b, 0x2, + STXT("Software Prefetch Instructions Dispatched (Speculative). PrefetchW" + "instruction. See docAPM3 PREFETCHW")) }, + { I("ls_rdtsc", 0x2d, 0, + STXT("Number of reads of the TSC (RDTSC instructions). The count is" + "speculative")) }, + { I("ls_ret_cl_flush", 0x26, 0, + STXT("The number of retired CLFLUSH instructions. This is a non-speculative" + "event")) }, + { I("ls_ret_cpuid", 0x27, 0, + STXT("The number of CPUID instructions retired")) }, + { I("ls_smi_rx", 0x2b, 0, STXT("Counts the number of SMIs received")) }, + { I("ls_st_commit_cancel2.st_commit_cancel_wcb_full", 0x37, 0x1, + STXT("A non-cacheable store and the non-cacheable commit buffer is full")) }, + { I("ls_stlf", 0x35, 0, STXT("Number of STLF hits")) }, + { I("ls_sw_pf_dc_fills.ext_cache_local", 0x59, 0x4, + STXT("Software Prefetch Data Cache Fills by Data Source. From cache of" + "different CCX in same node")) }, + { I("ls_sw_pf_dc_fills.ext_cache_remote", 0x59, 0x10, + STXT("Software Prefetch Data Cache Fills by Data Source. From CCX Cache in" + "different Node")) }, + { I("ls_sw_pf_dc_fills.int_cache", 0x59, 0x2, + STXT("Software Prefetch Data Cache Fills by Data Source. From L3 or" + "different L2 in same CCX")) }, + { I("ls_sw_pf_dc_fills.lcl_l2", 0x59, 0x1, + STXT("Software Prefetch Data Cache Fills by Data Source. From Local L2 to" + "the core")) }, + { I("ls_sw_pf_dc_fills.mem_io_local", 0x59, 0x8, + STXT("Software Prefetch Data Cache Fills by Data Source. From DRAM or IO" + "connected in same node")) }, + { I("ls_sw_pf_dc_fills.mem_io_remote", 0x59, 0x40, + STXT("Software Prefetch Data Cache Fills by Data Source. From DRAM or IO" + "connected in different Node")) }, + { I("ls_tablewalker.dc_type0", 0x46, 0x1, + STXT("Total Page Table Walks DC Type 0")) }, + { I("ls_tablewalker.dc_type1", 0x46, 0x2, + STXT("Total Page Table Walks DC Type 1")) }, + { I("ls_tablewalker.dside", 0x46, 0x3, + STXT("Total Page Table Walks on D-side")) }, + { I("ls_tablewalker.ic_type0", 0x46, 0x4, + STXT("Total Page Table Walks IC Type 0")) }, + { I("ls_tablewalker.ic_type1", 0x46, 0x8, + STXT("Total Page Table Walks IC Type 1")) }, + { I("ls_tablewalker.iside", 0x46, 0xc, + STXT("Total Page Table Walks on I-side")) }, + { I("ls_tlb_flush.all_tlb_flushes", 0x78, 0xff, + STXT("All TLB Flushes. Requires unit mask 0xFF to engage event for counting." + "Use all_tlbs_flushed instead")) }, +/* other: */ + { I("de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch", 0xab, 0x4, + STXT("Any FP dispatch. Types of Oops Dispatched from Decoder")) }, + { I("de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch", 0xab, 0x8, + STXT("Any Integer dispatch. Types of Oops Dispatched from Decoder")) }, + { I("de_dis_dispatch_token_stalls1.fp_flush_recovery_stall", 0xae, 0x80, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a Token Stall. Also counts cycles when the thread is not selected" + "to dispatch but would have been stalled due to a Token Stall. FP Flush" + "recovery stall")) }, + { I("de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall", 0xae, 0x20, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a Token Stall. Also counts cycles when the thread is not selected" + "to dispatch but would have been stalled due to a Token Stall. Floating" + "point register file resource stall. Applies to all FP ops that have a" + "destination register")) }, + { I("de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall", 0xae, 0x40, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a Token Stall. Also counts cycles when the thread is not selected" + "to dispatch but would have been stalled due to a Token Stall. FP" + "scheduler resource stall. Applies to ops that use the FP scheduler")) }, + { I("de_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stall", 0xae, 0x1, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a Token Stall. Also counts cycles when the thread is not selected" + "to dispatch but would have been stalled due to a Token Stall. Integer" + "Physical Register File resource stall. Integer Physical Register File," + "applies to all ops that have an integer destination register")) }, + { I("de_dis_dispatch_token_stalls1.int_sched_misc_token_stall", 0xae, 0x8, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a token stall. Integer Scheduler miscellaneous resource stall")) }, + { I("de_dis_dispatch_token_stalls1.load_queue_rsrc_stall", 0xae, 0x2, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a Token Stall. Also counts cycles when the thread is not selected" + "to dispatch but would have been stalled due to a Token Stall. Load" + "Queue resource stall. Applies to all ops with load semantics")) }, + { I("de_dis_dispatch_token_stalls1.store_queue_rsrc_stall", 0xae, 0x4, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a Token Stall. Also counts cycles when the thread is not selected" + "to dispatch but would have been stalled due to a Token Stall. Store" + "Queue resource stall. Applies to all ops with store semantics")) }, + { I("de_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrc", 0xae, 0x10, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a Token Stall. Also counts cycles when the thread is not selected" + "to dispatch but would have been stalled due to a Token Stall. Taken" + "branch buffer resource stall")) }, + { I("de_dis_dispatch_token_stalls2.agsq_token_stall", 0xaf, 0x10, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a token stall. AGSQ Tokens unavailable")) }, + { I("de_dis_dispatch_token_stalls2.int_sch0_token_stall", 0xaf, 0x1, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a token stall. No tokens for Integer Scheduler Queue 0 available")) }, + { I("de_dis_dispatch_token_stalls2.int_sch1_token_stall", 0xaf, 0x2, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a token stall. No tokens for Integer Scheduler Queue 1 available")) }, + { I("de_dis_dispatch_token_stalls2.int_sch2_token_stall", 0xaf, 0x4, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a token stall. No tokens for Integer Scheduler Queue 2 available")) }, + { I("de_dis_dispatch_token_stalls2.int_sch3_token_stall", 0xaf, 0x8, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a token stall. No tokens for Integer Scheduler Queue 3 available")) }, + { I("de_dis_dispatch_token_stalls2.retire_token_stall", 0xaf, 0x20, + STXT("Cycles where a dispatch group is valid but does not get dispatched due" + "to a token stall. Insufficient Retire Queue tokens available")) }, + { I("de_dis_uop_queue_empty_di0", 0xa9, 0, + STXT("Cycles where the Micro-Op Queue is empty")) }, +/* recommended: */ + { I("all_data_cache_accesses", 0x29, 0x7, + STXT("All L1 Data Cache Accesses")) }, + { I("all_tlbs_flushed", 0x78, 0xff, STXT("All TLBs Flushed")) }, + { I("l1_data_cache_fills_all", 0x44, 0xff, + STXT("L1 Data Cache Fills: All")) }, + { I("l1_data_cache_fills_from_external_ccx_cache", 0x44, 0x14, + STXT("L1 Data Cache Fills: From External CCX Cache")) }, + { I("l1_data_cache_fills_from_memory", 0x44, 0x48, + STXT("L1 Data Cache Fills: From Memory")) }, + { I("l1_data_cache_fills_from_remote_node", 0x44, 0x50, + STXT("L1 Data Cache Fills: From Remote Node")) }, + { I("l1_data_cache_fills_from_within_same_ccx", 0x44, 0x3, + STXT("L1 Data Cache Fills: From within same CCX")) }, + { I("l1_dtlb_misses", 0x45, 0xff, STXT("L1 DTLB Misses")) }, + { I("l2_cache_accesses_from_dc_misses", 0x60, 0xe8, + STXT("L2 Cache Accesses from L1 Data Cache Misses (including prefetch)")) }, + { I("l2_cache_accesses_from_ic_misses", 0x60, 0x10, + STXT("L2 Cache Accesses from L1 Instruction Cache Misses (including" + "prefetch)")) }, + { I("l2_cache_hits_from_dc_misses", 0x64, 0xf0, + STXT("L2 Cache Hits from L1 Data Cache Misses")) }, + { I("l2_cache_hits_from_ic_misses", 0x64, 0x6, + STXT("L2 Cache Hits from L1 Instruction Cache Misses")) }, + { I("l2_cache_hits_from_l2_hwpf", 0x70, 0xff, + STXT("L2 Cache Hits from L2 Cache HWPF")) }, + { I("l2_cache_misses_from_dc_misses", 0x64, 0x8, + STXT("L2 Cache Misses from L1 Data Cache Misses")) }, + { I("l2_cache_misses_from_ic_miss", 0x64, 0x1, + STXT("L2 Cache Misses from L1 Instruction Cache Misses")) }, + { I("l2_dtlb_misses", 0x45, 0xf0, + STXT("L2 DTLB Misses & Data page walks")) }, + { I("l2_itlb_misses", 0x85, 0x7, + STXT("L2 ITLB Misses & Instruction page walks")) }, + { I("macro_ops_retired", 0xc1, 0, STXT("Macro-ops Retired")) }, + { I("sse_avx_stalls", 0xe, 0xe, STXT("Mixed SSE/AVX Stalls")) }, + { NULL, NULL, 0, NULL } +}; + +#undef I +