From patchwork Fri Apr 26 13:52:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 89036 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6F9A1384AB64 for ; Fri, 26 Apr 2024 13:53:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id C92FF384AB52 for ; Fri, 26 Apr 2024 13:53:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C92FF384AB52 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C92FF384AB52 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714139585; cv=none; b=nVlkmNECYDKkehUoVEbiNGKtrOKA46UBdv7QpdKQxQnz/bgp2/eDZl24fzbnPOsu3ZT70FCp/F1KoGtzu24Dqhqn18l8NU9Y39tuV/sQSgnHql4eqdM8QiC/A7Altce7VXXdZqsvyw1vcWEcropUST4H+jqDWAIQIn6OysKgSjQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714139585; c=relaxed/simple; bh=mr24SDvSUeMr7J8Bzx1JoesUZy6IJvTcENydr+dU+34=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=B/cauoGZmXMfcgP0KSXaGL362WtEEfE1UO+LxGw3N+N2+qUrusILYHVUZEpPiiftcndUOp7wAB8rf6JAo6jXTqz9fDA/c8k06lufdnz62O0w+6o8HM/hOWJDb8kvzEqaWvibjdy0wHPpfRm+hNb6yPQ6Nkzcr0/Cdjtq4f20XIM= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1714139579; bh=mr24SDvSUeMr7J8Bzx1JoesUZy6IJvTcENydr+dU+34=; h=From:To:Cc:Subject:Date:From; b=j1OFy18TwQ8k+JTLCsuchpBKQxv4Lx81DJ2Q/IufqkjSsZKG2iCqstm3UbeZ9Qhit kmQNmChTw228EcZVoTGcGdDIBOOojp9IiO0QvToNeJj/8R5oWS2/pw5mZ6eh7kJp+a GWMySUEjhhOzEML94nRe/gT+oJsQEJLPMK+qR0h0= Received: from stargazer.. (unknown [IPv6:240e:358:1105:4a00:dc73:854d:832e:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 8FBB9675D3; Fri, 26 Apr 2024 09:52:53 -0400 (EDT) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH] LoongArch: Add constraints for bit string operation define_insn_and_split's [PR114861] Date: Fri, 26 Apr 2024 21:52:38 +0800 Message-ID: <20240426135241.893321-1-xry111@xry111.site> X-Mailer: git-send-email 2.44.0 MIME-Version: 1.0 X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Without the constrants, the compiler attempts to use a stack slot as the target, causing an ICE building the kernel with -Os: drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c:3144:1: error: could not split insn (insn:TI 1764 67 1745 (set (mem/c:DI (reg/f:DI 3 $r3) [707 %sfp+-80 S8 A64]) (and:DI (reg/v:DI 28 $r28 [orig:422 raster_config ] [422]) (const_int -50331649 [0xfffffffffcffffff]))) "drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c":1386:21 111 {*bstrins_di_for_mask} (nil)) Add these constrants to fix the issue. gcc/ChangeLog: PR target/114861 * config/loongarch/loongarch.md (bstrins__for_mask): Add constraints for operands. (bstrins__for_ior_mask): Likewise. gcc/testsuite/ChangeLog: PR target/114861 * gcc.target/loongarch/pr114861.c: New test. --- gcc/config/loongarch/loongarch.md | 16 ++++---- gcc/testsuite/gcc.target/loongarch/pr114861.c | 39 +++++++++++++++++++ 2 files changed, 47 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/pr114861.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index a316c8fb820..5c80c169cbf 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -1543,9 +1543,9 @@ (define_insn "and3_extended" (set_attr "mode" "")]) (define_insn_and_split "*bstrins__for_mask" - [(set (match_operand:GPR 0 "register_operand") - (and:GPR (match_operand:GPR 1 "register_operand") - (match_operand:GPR 2 "ins_zero_bitmask_operand")))] + [(set (match_operand:GPR 0 "register_operand" "=r") + (and:GPR (match_operand:GPR 1 "register_operand" "r") + (match_operand:GPR 2 "ins_zero_bitmask_operand" "i")))] "" "#" "" @@ -1563,11 +1563,11 @@ (define_insn_and_split "*bstrins__for_mask" }) (define_insn_and_split "*bstrins__for_ior_mask" - [(set (match_operand:GPR 0 "register_operand") - (ior:GPR (and:GPR (match_operand:GPR 1 "register_operand") - (match_operand:GPR 2 "const_int_operand")) - (and:GPR (match_operand:GPR 3 "register_operand") - (match_operand:GPR 4 "const_int_operand"))))] + [(set (match_operand:GPR 0 "register_operand" "=r") + (ior:GPR (and:GPR (match_operand:GPR 1 "register_operand" "r") + (match_operand:GPR 2 "const_int_operand" "i")) + (and:GPR (match_operand:GPR 3 "register_operand" "r") + (match_operand:GPR 4 "const_int_operand" "i"))))] "loongarch_pre_reload_split () && loongarch_use_bstrins_for_ior_with_mask (mode, operands)" "#" diff --git a/gcc/testsuite/gcc.target/loongarch/pr114861.c b/gcc/testsuite/gcc.target/loongarch/pr114861.c new file mode 100644 index 00000000000..e6507c406b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr114861.c @@ -0,0 +1,39 @@ +/* PR114861: ICE building the kernel with -Os + Reduced from linux/fs/ntfs3/attrib.c at revision c942a0cd3603. */ +/* { dg-do compile } */ +/* { dg-options "-Os -march=loongarch64 -msoft-float -mabi=lp64s" } */ + +long evcn, attr_collapse_range_vbo, attr_collapse_range_bytes; +unsigned short flags; +int attr_collapse_range_ni_0_0; +int *attr_collapse_range_mi; +unsigned attr_collapse_range_svcn, attr_collapse_range_vcn1; +void ni_insert_nonresident (unsigned, unsigned short, int **); +int mi_pack_runs (int); +int +attr_collapse_range (void) +{ + _Bool __trans_tmp_1; + int run = attr_collapse_range_ni_0_0; + unsigned evcn1, vcn, end; + short a_flags = flags; + __trans_tmp_1 = flags & (32768 | 1); + if (__trans_tmp_1) + return 2; + vcn = attr_collapse_range_vbo; + end = attr_collapse_range_bytes; + evcn1 = evcn; + for (;;) + if (attr_collapse_range_svcn >= end) + { + unsigned eat, next_svcn = mi_pack_runs (42); + attr_collapse_range_vcn1 = (vcn ? vcn : attr_collapse_range_svcn); + eat = (0 < end) - attr_collapse_range_vcn1; + mi_pack_runs (run - eat); + if (next_svcn + eat) + ni_insert_nonresident (evcn1 - eat - next_svcn, a_flags, + &attr_collapse_range_mi); + } + else + return 42; +}