From patchwork Mon Apr 22 03:19:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 88825 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 127C4384AB60 for ; Mon, 22 Apr 2024 03:20:10 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by sourceware.org (Postfix) with ESMTPS id 1367D3858D38 for ; Mon, 22 Apr 2024 03:19:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1367D3858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1367D3858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1713755985; cv=none; b=m2U2XlHxqIKBAJXIbeKz1HT/+60V2i8uJ0ahMUijGTGt11Cr0iIgkP0xtfKNumB3MzqACMF4P64UxaMFV71/jG/dqVgtSm37XykQWF0ew6CEKApf8R1pITWlHc3qXJH0qMD5UC+krGhQKFRvX8RuXdjrm8IS8+f/asiubxAHxoo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1713755985; c=relaxed/simple; bh=bjTtIhNxWnUz7TStzxpa+7ZYHw0ZvV1Iv8GTRwqfRjI=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=uHJkB+9r2VPwrdNPERWuP3U17Nfy1lY/fqsFW+grAZkRjosD32V7u7CAeJuzybjgGoxuBqz171VTXvu6l3CmpvHLYev5U+JBHCrVz0KqpWX0eeN2HBgfZJ4RzOWj3C/581raA1ZBysC8tRtQfUj4rjNsMHU2+lh5qj3g6shTZKQ= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713755984; x=1745291984; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=bjTtIhNxWnUz7TStzxpa+7ZYHw0ZvV1Iv8GTRwqfRjI=; b=bnHjk5wP8VhVi3udwE8rjZTCmvPTnvRfWaWhahXJWhpS1gV6VHOr0eCD cGVnvPO3FmZ/mCl6071TtGDfDthqcri1BoGKhbPaJxRePix9DUmYc16gX KzViXxRNYOkhfTbU91KVAAgmPZi9ZEhhC+B1pd8QvCn2D1e5Fd7SECzxG euVbJWw0usNrKZ6YrVhjr55tbZKMauflsJiHWgV+beKQWQbmP5lNt5VT/ uBkIqvLt7zd3946JUFDP5aGYpfN/6f290BLPgAUrp1P9R7h2LtT+BHm1F LRsKV5oGXh0IxOwMvXzNT2Ly06IEFTqNUOGmkvzHxtccR8a96/3hsGbdn g==; X-CSE-ConnectionGUID: 8ZPE4k34RL6OGfgGE5DH6w== X-CSE-MsgGUID: mOJsEqhKRRKqk00RT2YFFw== X-IronPort-AV: E=McAfee;i="6600,9927,11051"; a="9432789" X-IronPort-AV: E=Sophos;i="6.07,219,1708416000"; d="scan'208";a="9432789" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2024 20:19:42 -0700 X-CSE-ConnectionGUID: pqTLbFQuRtGfaSw/+Szf8A== X-CSE-MsgGUID: Fb65CEnAQdihAHqTolOrEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,219,1708416000"; d="scan'208";a="23934595" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmviesa006.fm.intel.com with ESMTP; 21 Apr 2024 20:19:39 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 7E48C10080FE; Mon, 22 Apr 2024 11:19:38 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1] RISC-V: Add xfail test case for widening register overlap of vf4/vf8 Date: Mon, 22 Apr 2024 11:19:37 +0800 Message-Id: <20240422031937.569341-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org From: Pan Li We reverted below patch for register group overlap, add the related insn test and mark it as xfail. And we will remove the xfail after we support the register overlap in GCC-15. 303195e2a6b RISC-V: Support widening register overlap for vf4/vf8 The below test suites are passed. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-16.c: New test. * gcc.target/riscv/rvv/base/pr112431-17.c: New test. * gcc.target/riscv/rvv/base/pr112431-18.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/base/pr112431-16.c | 68 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/pr112431-17.c | 51 ++++++++++++++ .../gcc.target/riscv/rvv/base/pr112431-18.c | 51 ++++++++++++++ 3 files changed, 170 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-18.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c new file mode 100644 index 00000000000..42d11611d98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c @@ -0,0 +1,68 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +size_t __attribute__ ((noinline)) +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, + size_t sum5, size_t sum6, size_t sum7) +{ + return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7; +} + +size_t +foo (char const *buf, size_t len) +{ + size_t sum = 0; + size_t vl = __riscv_vsetvlmax_e8m8 (); + size_t step = vl * 4; + const char *it = buf, *end = buf + len; + for (; it + step <= end;) + { + vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + + asm volatile("nop" ::: "memory"); + vint32m4_t vw0 = __riscv_vsext_vf4_i32m4 (v0, vl); + vint32m4_t vw1 = __riscv_vsext_vf4_i32m4 (v1, vl); + vint32m4_t vw2 = __riscv_vsext_vf4_i32m4 (v2, vl); + vint32m4_t vw3 = __riscv_vsext_vf4_i32m4 (v3, vl); + vint32m4_t vw4 = __riscv_vsext_vf4_i32m4 (v4, vl); + vint32m4_t vw5 = __riscv_vsext_vf4_i32m4 (v5, vl); + vint32m4_t vw6 = __riscv_vsext_vf4_i32m4 (v6, vl); + vint32m4_t vw7 = __riscv_vsext_vf4_i32m4 (v7, vl); + + asm volatile("nop" ::: "memory"); + size_t sum0 = __riscv_vmv_x_s_i32m4_i32 (vw0); + size_t sum1 = __riscv_vmv_x_s_i32m4_i32 (vw1); + size_t sum2 = __riscv_vmv_x_s_i32m4_i32 (vw2); + size_t sum3 = __riscv_vmv_x_s_i32m4_i32 (vw3); + size_t sum4 = __riscv_vmv_x_s_i32m4_i32 (vw4); + size_t sum5 = __riscv_vmv_x_s_i32m4_i32 (vw5); + size_t sum6 = __riscv_vmv_x_s_i32m4_i32 (vw6); + size_t sum7 = __riscv_vmv_x_s_i32m4_i32 (vw7); + + sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7); + } + return sum; +} + +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c new file mode 100644 index 00000000000..9ecc62e234b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +size_t __attribute__ ((noinline)) +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3) +{ + return sum0 + sum1 + sum2 + sum3; +} + +size_t +foo (char const *buf, size_t len) +{ + size_t sum = 0; + size_t vl = __riscv_vsetvlmax_e8m8 (); + size_t step = vl * 4; + const char *it = buf, *end = buf + len; + for (; it + step <= end;) + { + vint8m2_t v0 = __riscv_vle8_v_i8m2 ((void *) it, vl); + it += vl; + vint8m2_t v1 = __riscv_vle8_v_i8m2 ((void *) it, vl); + it += vl; + vint8m2_t v2 = __riscv_vle8_v_i8m2 ((void *) it, vl); + it += vl; + vint8m2_t v3 = __riscv_vle8_v_i8m2 ((void *) it, vl); + it += vl; + + asm volatile("nop" ::: "memory"); + vint32m8_t vw0 = __riscv_vsext_vf4_i32m8 (v0, vl); + vint32m8_t vw1 = __riscv_vsext_vf4_i32m8 (v1, vl); + vint32m8_t vw2 = __riscv_vsext_vf4_i32m8 (v2, vl); + vint32m8_t vw3 = __riscv_vsext_vf4_i32m8 (v3, vl); + + asm volatile("nop" ::: "memory"); + size_t sum0 = __riscv_vmv_x_s_i32m8_i32 (vw0); + size_t sum1 = __riscv_vmv_x_s_i32m8_i32 (vw1); + size_t sum2 = __riscv_vmv_x_s_i32m8_i32 (vw2); + size_t sum3 = __riscv_vmv_x_s_i32m8_i32 (vw3); + + sum += sumation (sum0, sum1, sum2, sum3); + } + return sum; +} + +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-18.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-18.c new file mode 100644 index 00000000000..4365fe0af54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-18.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +size_t __attribute__ ((noinline)) +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3) +{ + return sum0 + sum1 + sum2 + sum3; +} + +size_t +foo (char const *buf, size_t len) +{ + size_t sum = 0; + size_t vl = __riscv_vsetvlmax_e8m8 (); + size_t step = vl * 4; + const char *it = buf, *end = buf + len; + for (; it + step <= end;) + { + vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl); + it += vl; + + asm volatile("nop" ::: "memory"); + vint64m8_t vw0 = __riscv_vsext_vf8_i64m8 (v0, vl); + vint64m8_t vw1 = __riscv_vsext_vf8_i64m8 (v1, vl); + vint64m8_t vw2 = __riscv_vsext_vf8_i64m8 (v2, vl); + vint64m8_t vw3 = __riscv_vsext_vf8_i64m8 (v3, vl); + + asm volatile("nop" ::: "memory"); + size_t sum0 = __riscv_vmv_x_s_i64m8_i64 (vw0); + size_t sum1 = __riscv_vmv_x_s_i64m8_i64 (vw1); + size_t sum2 = __riscv_vmv_x_s_i64m8_i64 (vw2); + size_t sum3 = __riscv_vmv_x_s_i64m8_i64 (vw3); + + sum += sumation (sum0, sum1, sum2, sum3); + } + return sum; +} + +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */