From patchwork Thu Apr 11 03:51:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 88325 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DFABC384AB51 for ; Thu, 11 Apr 2024 03:52:07 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by sourceware.org (Postfix) with ESMTPS id DC14E385840B for ; Thu, 11 Apr 2024 03:51:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC14E385840B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DC14E385840B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712807499; cv=none; b=D9NkJvjN4EM/STVUn1XE+THUZn4hxCkcVDW0msl9iq0vi0RXclqDcj5CvNxyleQykVUR9rxj0YHLZRY7gGew0a1S0l+EUH0oqdeW6LIgoZok52bfk2z4/zM8fjIxdmqq/eQAZ2hu0W26Jjqw1b6PHl88HS6RCzE2snluy6ZvWS8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712807499; c=relaxed/simple; bh=zLEBjw5L63jvpmYdoOD31UvPOwV2Ei4V9GRQi7DvPh0=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=ljH16Fu0GMSsJ6XnruVRt6va2kNKV+9PhGc/v89ELSxHYBRP86apTAk7fLwRQXpsKFjQj9MW/MbJCNgZW5MR9q0v8QAjuSXtVgqzaxbv4zKKFz4euI46ejb1Um3oRckUpa6/blbtaPr/rjOXvHZIf7xi4dKq4E2SaLVM7tR4pEU= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712807494; x=1744343494; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=zLEBjw5L63jvpmYdoOD31UvPOwV2Ei4V9GRQi7DvPh0=; b=bUROBsz77GBB7kHFqryZQmqbURDAESmr0hICaLGP/Z+7U9qXEVQ4HGrO 3ewqnQRwbHJzGBgflC2NpBuLMJTN84BHx+fNsmR6+R1YWPT+B2RD5Cfx9 I2q/YCiOhPPK690YkN5knyfMAvaEiePOX/XqRMxhjdbsuKx2Qb/GZDX4d a8wKxc0Kka7qv2yTQ66DbfusRImWv5ualbLO1JY4V70i7mZKt3FV2Wojj S8dhQu24HKiAyKvpznJzDFD2wczG78nveQijvG6bzoIp/RRBden3FbPd2 NcebCz0KgJV9GJgXdSdpcN1HT23226YEBWlXgsc3qY23JHoyZF1kuLHq8 A==; X-CSE-ConnectionGUID: HZ3m24XvQ7mJT3GxZPbMiw== X-CSE-MsgGUID: 5IQtz9XoRISIXaDB9GCyXg== X-IronPort-AV: E=McAfee;i="6600,9927,11039"; a="8116633" X-IronPort-AV: E=Sophos;i="6.07,192,1708416000"; d="scan'208";a="8116633" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2024 20:51:33 -0700 X-CSE-ConnectionGUID: X/ss9vUKQ3a/fmyz5gtwEg== X-CSE-MsgGUID: MPdrzW5lQV6aWUMWqTaNCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,192,1708416000"; d="scan'208";a="20746122" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmviesa010.fm.intel.com with ESMTP; 10 Apr 2024 20:51:30 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 1BBC51005533; Thu, 11 Apr 2024 11:51:30 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, Pan Li Subject: [PATCH v1] RISC-V: Remove -Wno-psabi for test build option [NFC] Date: Thu, 11 Apr 2024 11:51:26 +0800 Message-Id: <20240411035126.3780666-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org From: Pan Li Just notice there are some test case still have -Wno-psabi option, which is deprecated now. Remove them all for riscv test cases. The below test are passed for this patch. * The riscv rvv regression test. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr109244.C: Remove deprecated -Wno-psabi option. * g++.target/riscv/rvv/base/pr109535.C: Ditto. * gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: Ditto. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C | 2 +- gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c | 2 +- 62 files changed, 62 insertions(+), 62 deletions(-) diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C index b0ce04f4921..eebfc239d3a 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ typedef int a; using c = float; template < typename > using e = int; diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C index aec613f3f97..7013cfcf4ee 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ typedef long size_t; typedef signed char int8_t; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c index ee5f18c9f8b..d8112ae4851 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c index 216ecb40bf8..bdd17774225 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c index 481f409c4a4..f783433672e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c index d30a0d4ef80..9d76ef3a94e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c index 1b0a1913bf5..77b2b15ef02 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c index 1ea57b8f210..07d47093e62 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c index 39b7e8125fb..dada929d80d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c index b3d859d2cba..79c52b6ae8a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include #include "compress-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c index 5aa7b3f8112..187c6fea183 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include #include "compress-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c index cf3477d389d..4a102fe0903 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include #include "compress-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c index d5480ed93a7..ce819de1ade 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include #include "compress-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c index 5c0ce6b7d56..75520eed144 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include #include "compress-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c index a1d2696bb27..43d83c9274a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include #include "compress-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c index cb9423440f9..ccc17d7add7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c index ce96aa504c7..d6e49e29a14 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c index ea41ae3a3f4..035fe95bfff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include #include "consecutive-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c index 8a7a67971c8..bafdcb97175 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include #include "consecutive-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c index 2b39e0b5ed9..fc3c528acfa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c index 4b2d077100d..ee6ad76a65e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c index 3b6895e9509..03441a86a8d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c index 5ef7036c833..3095a6df189 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c index ec8f198534a..9e83320c2be 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c index 986b85cd425..4c7ebe1497c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c index b5ebce07e36..dcb1d7744ba 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c index b960d99f06a..ad1c961e3a6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include "merge-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c index e907320c075..2f0845adca2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include "merge-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c index db16077a0a9..f3a172a505f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include "merge-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c index dda8b3beecf..d2321c7ba48 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include "merge-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c index 8d429b80765..cc02aa7eb46 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include "merge-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c index 7945baab39c..e49f1cca91b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include "merge-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c index 8401f1da5ba..988b21e5dd8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ #include "merge-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c index b361a04836e..58c2cd8ce23 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */ #include "perm.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c index 9e9123a6cef..d88b6461da5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */ #include "perm.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c index 0cefb241647..110df490c6e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */ #include "perm.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c index 7ab31043547..0ba3affb008 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */ #include "perm.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c index e03f8e1ad51..7117a492dc7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */ #include "perm.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c index c74ad03935e..67b2e6f680e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */ #include "perm.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c index 46c4a71256d..0ac98287254 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */ #include "perm.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c index 2172d7794ef..1f9740ccd16 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "perm-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c index 8874c0521fc..7168068def8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "perm-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c index 139ff087985..40a20918a98 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "perm-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c index 08f03dec708..3cbe609a8d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "perm-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c index 6b7db30b259..af203691933 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "perm-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c index 240acf2b1e3..50848b5e637 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "perm-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c index dce65f91ec8..2d2c1a9ecaa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-mrvv-vector-bits=zvl -O0 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O0" } */ #include "perm-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c index 34a82128042..725f56b21d2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c index 98f6c7dc17e..14334ba1a94 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c index 4288a6d2411..d9959a38ecb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c index 9223bc56f91..b9865948087 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c index 0102848656a..c8bca3c29dc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c index c4047b6eba5..552c48ecc49 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c index d8deb7dc3ed..e872c94e492 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c index a276700cd94..36d4926e4f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c index 5df7e08c42f..86351d481ea 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-std=c99 -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c index 7c77ae87f08..5b609a9fb8f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-std=c99 -Wno-pedantic" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c index e97f6f5f8ee..ecb160933d6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c index 6d077d649b3..194abff77cc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c index 5f6cb321ac9..9495d5163d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c index c6f696409f4..9992bc24c34 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c index 5dc095cce51..e0c8ff8b935 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */ +/* { dg-additional-options "-std=c99 -Wno-pedantic" } */ #include