From patchwork Tue Mar 5 17:36:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 86835 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F3BAE385829F for ; Tue, 5 Mar 2024 17:37:42 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 538363858404 for ; Tue, 5 Mar 2024 17:37:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 538363858404 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 538363858404 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709660237; cv=none; b=sPoAih5IfoHIGHVVvCCao7lJjiNkNO3sBIbUWf+IwwOEtoXBhyhYKY9ToOXbbRGdopJpmJEAgketokaOLtYVxMM+eZ5YNF6hsDA4bH2ucIYmG8osqyhGxndxWSUkLw5Jr69jUlnFyhORtYvgkWP94tv8ChRRwxAZcbV/NZSxwWo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709660237; c=relaxed/simple; bh=ZsJAspwK5OGOk5v2Vf19S7Q0Ia9CApj9gg+saS/UHbc=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=D+AKMNjptT7o0+orLVkPNkR4mu0Zm7zc/gTNnaX4BMqFoKYIu/Sb2TKHaFohRYvJqVyzqBJ/tfie2FXh57/VsWcWXPwGcC6vBoLkYQiW0I+uGnsqHSQHsO1POMeUn12kJDhnfW4eeYeeaH5tRWxpidlSUyzLOj5wYvNIXc3W7ME= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9D8741FB; Tue, 5 Mar 2024 09:37:52 -0800 (PST) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.78.54]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 60E9C3F738; Tue, 5 Mar 2024 09:37:15 -0800 (PST) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH] arm: check for low register before applying peephole [PR113510] Date: Tue, 5 Mar 2024 17:36:44 +0000 Message-Id: <20240305173644.3892514-1-rearnsha@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-13.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org For thumb1, when using a peephole to fuse mov reg, #const add reg, reg, SP into add reg, SP, #const we must first check that reg is a low register, otherwise we will ICE when trying to recognize the resulting insn. gcc/ChangeLog: PR target/113510 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use low_register_operand. --- This appears to have gone latent again, but checked against the known failing version. gcc/config/arm/thumb1.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index 14d6df580af..d7074b43f60 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -113,7 +113,7 @@ (define_insn_and_split "*thumb1_addsi3" ;; Reloading and elimination of the frame pointer can ;; sometimes cause this optimization to be missed. (define_peephole2 - [(set (match_operand:SI 0 "arm_general_register_operand" "") + [(set (match_operand:SI 0 "low_register_operand" "") (match_operand:SI 1 "const_int_operand" "")) (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI SP_REGNUM)))]