From patchwork Fri Mar 1 06:27:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "demin.han" X-Patchwork-Id: 86627 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DF3073858410 for ; Fri, 1 Mar 2024 06:28:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2102.outbound.protection.partner.outlook.cn [139.219.146.102]) by sourceware.org (Postfix) with ESMTPS id AE1363858C74 for ; Fri, 1 Mar 2024 06:27:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AE1363858C74 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AE1363858C74 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=139.219.146.102 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1709274481; cv=pass; b=mREn51i785DXxVjARbuWg8PHeq19m+KhrygRUW2o2TX8pELwdJUmEJuu/XRs0S4NEYvE8f19+iTec1GjKJAzyeOeViVXEMERsr06cL/gLncsmzC9DrInQ9Ru9G25WGIGtxlgQXTcqDXcD3GHoWEvPNS3QkChJVcLOdCb/baw7i0= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1709274481; c=relaxed/simple; bh=6xY2YZxfc+vzzMhWCEnkGKMjtnQ6PbOR+dtU2v+x2To=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=Td6yZ6Y30FJ1bOogELYUukcRL/0h8AjmQWcYYuDbIqPBAUS2OaGfd7WKTlcjVSmc8wIRV5TGuRIwz/VAJ8xsL9QFPWe2EEgbF1A+FXrIbtREzJfQkxL3qGHZgBDdeRfg1dNAxmyYcD5+4aSRVWVz5JTRLRdsULseMfTEjoG/BtE= ARC-Authentication-Results: i=2; server2.sourceware.org ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iUfjIqqMi02QvO7MX5sA/DS9I2BZrmdilPuO3pvdSkK1+WHgcRhCM4jEX3bEWWepaUJag+wlL4plNY0WOnXOUX7YVMddKSldz5MGyd0d3AE0hT6iVeVVYUGxl3DvT5mysrd3c8qu1f+hWQg4fd0zHREnmoA0xVcEgu6o6oh9LnBey7/uYcAuqoxwHB6EOTTRMaBpRYsTaKLa1i0wBEjkKZU2c7F14y2sKRvSNzeQ1aRrUaVf9fqnzZAiGrKHO+xsGYaPicEuhtRV7gkuqXgZdUEhIwneW5NilOym95L+m92EKGLj0D0306uhL6N1j/WyDVRcEqVBy1M6CG1tw8LZEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=thuhOZ3bRCGJXqmgDxUFvm+8lpFcNF0SbLPw+E0cFYU=; b=GJac8z1jJLLjSNv9fANLmM+tkZhra2HdznG0jhthndBfsI9yQi39Rtd//ZXeJAT/s83GnkUQ2R9oueV38PQDtd389Z2oId6nXvM2VJdlew6FIs/tGrvQBcUpVqfri+AhtGv8Ws+5MvaQXW/fwiY3HtkT/ogzAwAC9cce0nC3PCUpy1VBhGSf0K2UxpPZHNyh5kO4LIN6TvQYrj6wKcdQSl/h9LNlwSah77yKZdpUKKExLYHCMAcvmXNV2JpB6DQdTKvsjto4Vnkmz5yq2SSU2V8WPp5WSKj+PubZ9SGEjaI5HUnvXCiN0DYkxueTc2Vtork2yKQPEvXWcJZf4Je7AQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) by ZQ0PR01MB1080.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.47; Fri, 1 Mar 2024 06:27:49 +0000 Received: from ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn ([fe80::21d1:48e1:7ca0:1d76]) by ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn ([fe80::21d1:48e1:7ca0:1d76%4]) with mapi id 15.20.7270.047; Fri, 1 Mar 2024 06:27:49 +0000 From: "demin.han" To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, pan2.li@intel.com, jeffreyalaw@gmail.com Subject: [PATCH 1/5] RISC-V: Remove float vector eqne pattern Date: Fri, 1 Mar 2024 14:27:07 +0800 Message-ID: <20240301062711.207137-2-demin.han@starfivetech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240301062711.207137-1-demin.han@starfivetech.com> References: <20240301062711.207137-1-demin.han@starfivetech.com> X-ClientProxiedBy: BJSPR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::35) To ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1063:EE_|ZQ0PR01MB1080:EE_ X-MS-Office365-Filtering-Correlation-Id: ef1e59d8-8f3c-41a7-4630-08dc39b8b760 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2vRWhm0YrajNbd7yUT3bi8y01l4NWbqqVGEMxmA/rJSLhHZi0KJSPc6cy1khCMWWybGSYpc0SCUsg2Gvesw0Ff778x3//Olr45vjhaiMJ+W0t2U0wvmfvJ7TbHPx1REBOjxAt8R2iOS3QpxVv+DJdFyVgXo3xZuRHNMHy+fjW/PherK1tBTqDXHskT4l5A5L790ngRYwz2hYa6efppImiLAF5w6cCpgvPxmfxFsnoIUdI3yELrlsFnCHGAi3dYuraeetMtECbrdsLI6KGMUJ0D7U6f8J4uQkQmStRq2DZqXprfa1839/NLw7pW8a1bAbfSSjQUO1cLMqGy6kKM3HouOtdXvCQU/JEjLuhrNuWml4VsAR4IroJGOzUZR9oSaZnTvIqiDSOyZB8FiC3BbTB5DS4S6FB5iTd8Dq+8sjSDiHOToph5sxusMN6cNL2HVfu14/D53NOpciwHMhIS+dLeF9Yj9yCTFVjA/N2aUlEEszqirdtn0zycKtmgP5RbtJwsbvYJ3uQUXytQL+TU8+ipIzfKFJdl4Gwx+Ahvx+/UOQRtep6rJYjnDjYQ7PgqrMXXX58wupaO22Psq68qKJoFRLCu5F8zZRYJOSkmKc10/V81bgNvI3sxrsLXNbid2q X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn; PTR:; CAT:NONE; SFS:(13230031)(41320700004)(38350700005); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: NCfP7ghBVABO2pGibrLzS89F+tsy5hFzURyvrzkHEu9tqnlOM5jWLMjRwO2DHrWtoex6L2jSyNVrHBxnnk6HDtwsEzWYB37my4b9uNeMFwWIuvSAOD3XnvpQKtEa8575LBmsjCE0K6ACzOy9416rId01ekq8eybVG8ldU+lLZVd8JVBOLClpG076WCwI+ZdxOkTKp12oNqxPBp2kJmYGv6CwlanOQAcytsHoGr2QNBY3MyE6lHX+nHZTAgiduCG47sbAT8J6mbarNC4VB8oT9R8whZQywlEK16sHjwkjUllrosPM6mIO0Ngi4zjp9lPmrvg5BZs19yrGAsnQEaXRIh/1JPbnbPmF7k+QP/pMnWAxQPByYq2QHjlrdoFcQMNzUsvC/9L2fGAdrz813tZZhUaLTo+o2LPBF9qvRO4j7GM0nRoh/7VQoG7JkcfwKQYij7XOQmwz/jn1znImYY6XTWZmiZ7LEiUOE0zGsVLxJUG6a9S2BySKOr7xIqkMHPmt2iut6gpRnJfNYTUUfA+QJJv/8iVNErLCQC4tbtRKTDUnhLP+g/gNXWMGPQpPWeXmOPN8v8/Doz1XBdjK836sbp7Bc1e2k91voDO/2RAgi4ePxrZij2QdTdvZF3wR9nGTe2hw7T4NaVdziZVxnfvajvMH6h5tosJTzILGYl6whnR5ZLXCY1wp/bzqaKchE/uP4vxGlg0t73hteEH4ovMvISPwpi/qjuaPuuJvG0bvB3Pq2SA4jyy2CohOG21Xv6oDhoQAzkp1sbUGOxGvw+/L5Us2jPUsMuzlDnrD3B3J6eNj6RTCmhac4nR8LJFF00F1gxD0mUrIwXuKDY+1ZOy90haLhxILNO3srH+UO2rSUvoK+sJpehTd88R9OICjcP+s1knAwlIBChUVVmQvEWEptcXBC/FC1byDd/uhwizz42WGHBeT9gpVYzro07fPxB1YOWnjBI8RKm1q8YPV6UgytKPLbNIMH2BVfeBrVI36vXZy9u0AiMUF73o1+fYVCagoYvsfVFKmABVmZ0ECEe23U4AjcWGR7IAz09bE4PJrfrqdb3LGtIxBprJVwWG5HTSVLwwSXpa5EZRKbQ+zW+4CFxVrxbA+KzCaeDGBygkvZkzdDtF/WdWZT3YhH6p63I24KfaUq9ixkFmQTzz+1c0CskepCB4vyTSUCsbqLU/ZDLukz0M6fluoJZn/ut6Wy5vuZyPkp12C50lbLMk29ziKZJriO1NDBjK+yMnMWcPtZH2bXlkZn63NsaYLqNVFbfof3K2PlCTMm2IbR6TDbUGdGoJYgj6nYRWHs6DIHqOSr3hB3Iz6KZvtqY+tRs83jfRIAp7yngO5NCzEacZ0XB3jlThS9Tc7uFbocOFACBXRAHvmMJPUBAQIkHBzXTkOG0zwKyB2gP/B1Zi10lLMBgIbQ9ASOUK8oeBOfFmaTNR1lFZLCZAxPC0REcNrw4m5FxO/8Gw3lmiGWhll+DCnlJSjT66lfsCWgDiXs1JfarFPWGZvLB12C0hqXuS7WIUqxy+fW0nC3sXhOqpqZD7TiL8eOnG2EplbOKWNKNGyIoaW0BIkjyQ2Sj6UDgYol740i9kQVkV5eogOFacrwHbR1zHa5g== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: ef1e59d8-8f3c-41a7-4630-08dc39b8b760 X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2024 06:27:49.5863 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +plvSy1JbwPLxH6u6VjOIOvIaK87moKOA9qWMh5JWw/gv0bTeqtfJBYnIOvzgg8pFDCVYlM39sEPqIO9esz8OBsUIob5YDzFpBpPmHvjEbo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1080 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org We can unify eqne and other comparison operations. Tested on RV32 and RV64 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond * config/riscv/vector.md (@pred_eqne_scalar): Remove patterns (*pred_eqne_scalar_merge_tie_mask): Ditto (*pred_eqne_scalar): Ditto (*pred_eqne_scalar_narrow): Ditto Signed-off-by: demin.han Signed-off-by: demin.han > --- .../riscv/riscv-vector-builtins-bases.cc | 4 - gcc/config/riscv/vector.md | 86 ------------------- 2 files changed, 90 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index b6f6e4ff37e..d414721ede8 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1420,10 +1420,6 @@ public: switch (e.op_info->op) { case OP_TYPE_vf: { - if (CODE == EQ || CODE == NE) - return e.use_compare_insn (CODE, code_for_pred_eqne_scalar ( - e.vector_mode ())); - else return e.use_compare_insn (CODE, code_for_pred_cmp_scalar ( e.vector_mode ())); } diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index ab6e099852d..9210d7c28ad 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7520,92 +7520,6 @@ (define_insn "*pred_cmp_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -(define_expand "@pred_eqne_scalar" - [(set (match_operand: 0 "register_operand") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 6 "vector_length_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSF - (match_operand: 5 "register_operand")) - (match_operand:V_VLSF 4 "register_operand")]) - (match_operand: 2 "vector_merge_operand")))] - "TARGET_VECTOR" - {}) - -(define_insn "*pred_eqne_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSF - (match_operand: 4 "register_operand" " f")) - (match_operand:V_VLSF 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR" - "vmf%B2.vf\t%0,%3,%4,v0.t" - [(set_attr "type" "vfcmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSF - (match_operand: 5 "register_operand" " f, f, f, f")) - (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" - "vmf%B3.vf\t%0,%4,%5%p1" - [(set_attr "type" "vfcmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -;; We use early-clobber for source LMUL > dest LMUL. -(define_insn "*pred_eqne_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSF - (match_operand: 5 "register_operand" " f, f, f, f, f")) - (match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" - "vmf%B3.vf\t%0,%4,%5%p1" - [(set_attr "type" "vfcmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point merge ;; ------------------------------------------------------------------------------- From patchwork Fri Mar 1 06:27:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "demin.han" X-Patchwork-Id: 86629 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 502083858426 for ; Fri, 1 Mar 2024 06:30:06 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2102.outbound.protection.partner.outlook.cn [139.219.146.102]) by sourceware.org (Postfix) with ESMTPS id B910A385840C for ; Fri, 1 Mar 2024 06:28:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B910A385840C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B910A385840C Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=139.219.146.102 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1709274486; cv=pass; b=EqAPFJEj2jF7qJ/Z5EwtdeKcNTC5X/q2jR7qZbfrmrHp5mX1uc1Zkdi+KbZtcmeo3T8y75myuO4sR1fNsspDZpHqLbvKJS2UNK36szWDE2CY2aRFF424ja72NgGifp24U+RK0rmrsnlv+XQt5+njMuz0f07RWYzlLktpze+Ffds= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1709274486; c=relaxed/simple; bh=qxaj1lLwahI5LikBJIrZzq7bmpp96DnkQOW6sB6fmxI=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=DGHBsvXWogsJb9M6CcN1CO4lKtA6yMPN1ZCzRv6lCaTngO4eaJKMmJIGgV0pEFrLy5GnStIiHa8+NjgWdQg1rr/UcYO2MKerUqyljNAjTLtX4fMPN+4110ZMd7U/PP9P7Xzhg589Y+UsmGwT8CULYpA75i0qxHXL1Hg3eO1UzCo= ARC-Authentication-Results: i=2; server2.sourceware.org ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=g7VuDB1QWOozbE3goARVjRebS5wBAB50ZBB3mSeH6r7nP3YlFzdBELLTmTUi0Mh32rnt3gGR/D2GBO5DQIVYOhCVNzlVrCXMdlduS/81TgrG+CxO9fNDtawHs561PK/0VZhPplPkKuJ95I7qdnEZhMkJXHhJcmbYr5607ECxRJHOeA81yqsjm9ep81r8k9rMw05yBG/fnM5DE0UJU2C9v+LsV/SOeGqXrpgKLc0HndgUcYrR7DBkRIS2osznxZcmlnzgaP+/KM6+axgTi98PywOsHcQHANXS9konrTH6IepUQkTMR03zXNw+H7hXyYopiUzgMe7p8f15Bax05TztKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=th1viYMbCnQBE8GPd5qn+4LaB3S/BD3bztfHp05jgp8=; b=VHH2NJ4oUeXrOLm9oqYh8zonsOJvtWT6cDVb9NOqWLV+kL/F4t5oCS3XJlozrpI8b6Eu93cPMH+qSncTJkfGz6zH3mcSHa8gtoqmdTYRrNusUnmMulG2FZqEnfocy6rbrqYedzRuen0OBtoNtHgQpJbxf3yfzWcyQUjVxLk/lsJ8vm+3+x1oBaA2lXkZweFRXMCMtEvf1xbjh6pU4tYVdoxP5PhJzVt2RyCy/rnV02TQVhulx1f3+aT8Onc4XxUOmeytS0G7BpeA0g6B0E0+YbZ2CioJ1mA8gCsB3obhhMvMEaHh6l9LZUmnLl8A9ARWHTSLY5KmPYP0ZRe5Sw26MA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) by ZQ0PR01MB1080.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.47; Fri, 1 Mar 2024 06:27:50 +0000 Received: from ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn ([fe80::21d1:48e1:7ca0:1d76]) by ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn ([fe80::21d1:48e1:7ca0:1d76%4]) with mapi id 15.20.7270.047; Fri, 1 Mar 2024 06:27:50 +0000 From: "demin.han" To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, pan2.li@intel.com, jeffreyalaw@gmail.com Subject: [PATCH 2/5] RISC-V: Refactor expand_vec_cmp Date: Fri, 1 Mar 2024 14:27:08 +0800 Message-ID: <20240301062711.207137-3-demin.han@starfivetech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240301062711.207137-1-demin.han@starfivetech.com> References: <20240301062711.207137-1-demin.han@starfivetech.com> X-ClientProxiedBy: BJSPR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::35) To ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1063:EE_|ZQ0PR01MB1080:EE_ X-MS-Office365-Filtering-Correlation-Id: c469d51e-8ad4-423b-15e4-08dc39b8b7d5 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6Yrl66OAo/3gVBHIaptAy5F0meNkZH3Yv69rsNfkXIqHWmIJS4s3S+oqivOlvCrZkPYliGuylfo71Czs25AjkcW6jJA5SkbviyLKP7boVwuU0MNTgPiWJ2qiXG2d1KMjIBznWEQgdNL87ylhwlQUcfScMO6vefpeSp1YnhFlijbl6/rEApW0JzGveJqMk6XvirPZfC0SI6TdXXnpMCbH3kvg+XORj8HGl662nR7YavoGbuugT3yexdKaUKasUalbyiRaPNUX44AIPnmnSikjY+4ZLU8i/1BuanLnG6hn6BDvmeyQL2ULNHewbFIWSSBrxuQn02xutdDz+JwE2zcnfZgogowT5U+/ai53528bAVP44Jh8MOPStlrpwd236Avo94Gay8tEwEVLcNkwaFSuPf2F2hFwzYWJ00RMgklg4yU5fxRjV0hmiWeXXqXNM6g3lWzuIx2+fBtAUeubOm+VXbydJmKJ7ANs3l27MNOZfxIppI5SrtzRSUIRQVGxzct3Ho9KdJiXcmaC7P/cK40HwlbOrVV0j4Im3adfvzehIfTDJDKB0ajYcT89x5UWCeGEYVG9OM0dsshvi9irQ/6yvfKCqND972Z/1WmI/0K2rSuXuwgUUR/igXk1fi45mLAi X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn; PTR:; CAT:NONE; SFS:(13230031)(41320700004)(38350700005); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3Slv3CSMP+31ZIo70KLgiDStNyCE39V4v7XFyTAwSyHAW1ja5TK/nrvV7DgIzCnLKX+2oBMm3Ds4UBKYxA460yREkM+bcpyXAhHWjLPTQth7pErin0kQDFd8yrfQpvP8i1qiS7KJlyeGoZ8L8Bv1wTpR1c/21ZcjnJ5OXx3TGffuYTMrjHOdWlGS0CUOL2/iaCCRuG0NHPFOg6WoRB5yZzwiYQWWgJ8U3mewoJ7gb0cval8xZD+1WpJogISiwQEqJsqHRyz0qrdugCwqMep+xtEAEB+7XkImErcB6kXhSz4fuOhbBGBXhv1TVQtVUVDUTfyo/Xaq7MkAPsZn4+DeoFqy4kY40+0t+Va3Q0NoVaKuW0yVCQTQiO+Pq0ikLzCsiXcV/AI1p2HxhKilrdmtu+NoTMpFDGmLC4R3mycxUGXa7b6d+vTmy4gbza6gAOSQHqKrYFlEZ111yBE9eKImVage4ouXhRAOhR1+kyaQ9I4AYmGA9OnmE/7f2iAhBGez6s7wSif5jDgrCPqkMmjxL6b+jK4ESELmuMobYMT0A+VpZkwjuUkWq6g4qDBseZ5JRdC9qJCxBR+GM4saffgJHtGZbqDqBs8LVvPVs00SEODygmJbfv/gU13MPWqZNiaqsWCtluM4R5G1v6pFUOzs27gGUAgP5LR7GCnnW46fmfgKsSRkX9M+aZmZ/Fh3vTovmg2NzfqELIsMUzyKjyHgNdn67cRgI9tOHUkTwlHhbdPjRIhGquUToJJ9D+dk7TxSlkphB4ArMPXU9fVIlYwnvqwia3+K+cRwFVvyNxp9pF9GQnzOSG2U1/gyqZYQrf6+/dV6O5v6D8n63xU0L+zJ7hKUqzJuSyPt34ZRKufzYxxlU4mQ/MBhT1dg4OvaTQVeRBgzvP8HbAmvkUx9BPcPOz+t95Yl2Ei7ml60Qux2HmDmnZ0aiLS7Q90QKSoDzzeImjwNEWPKdmCBuXWGIjJjaY4x5Q4JKBoAg4IkZIZPBIR/SAcizo8VaatXPHyLYNikWZLBgv7GkPnXUX+z4Og/+HSQc68khFmlubCS4RU13rls3N19EAn43oM51w89xXTZIHiEFNuxVXuS87x9YKdLXZzRKcE89BKfuLa7a0IOhkEmrjJB0Wl4dLxFWNey6w+O5Ho+9VBYdaanM6iMgdf35E5oKD33QH5apR8JCrUwPPzc6nYNP+Lx/OqOCCiJUattRFP8xlek+3p9D0MOUhDMXQj5CoS4pdRxM1yigwzUe5zcftxyhHlfdQhC1DpXLYQfh7VGIF3SKuaa+MhpOEwFU0lnFCUcePiC86Uxl1E6lychUcaSpqCywaePJ0A/8/LtWUyRV3HKCa2oWeRAb0YhtqisY+0BLaSekjMs6s0mc59y/XCfvAenHIOemtNupjo5KSC3V/uLqMYCSOkAzIN6zmq7ZnttGNEXFc/uDUk4t9ys92bSHxFpyarF6EbYVtb4EFfto8PldQ53AU8ExaS9rV9ZsYMV+eHnvdQPk6GtSW1oOZFIRBYr/ndI/rtB8DWDK8Fe+BF6NcwiAG4Y+ACL22wtyCoM9+7b4RGj6jmrVn+ItauNHddJjigZfHpc+h8hpjgU7CGh0sKnELMlin927w== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: c469d51e-8ad4-423b-15e4-08dc39b8b7d5 X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2024 06:27:50.1714 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6d33HsaziteJHqBc9JlObruton5E/xFIETuUnhfg4sNtctLenwPMAjPF3Clj8xoCNpw+h80pnJ4aqWX/UJ/+GL7mkLAtFajFz9ke66KrzYQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1080 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org There are two expand_vec_cmp functions. They have same structure and similar code. We can use default arguments instead of overloading. Tested on RV32 and RV64. gcc/ChangeLog: * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments (expand_vec_cmp_float): Adapt arguments Signed-off-by: demin.han Signed-off-by: demin.han X-Patchwork-Id: 86630 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 780D23858417 for ; Fri, 1 Mar 2024 06:30:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2102.outbound.protection.partner.outlook.cn [139.219.146.102]) by sourceware.org (Postfix) with ESMTPS id B6D153858C35 for ; Fri, 1 Mar 2024 06:28:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B6D153858C35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B6D153858C35 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=139.219.146.102 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1709274490; cv=pass; b=sZ/tvoSf0gAE3Jw/FePuVccQVfs/4m9ruj+jNBR5J2TgeWQCiCMXaxVAy1Z0NpMWNAduDGDtn66rJusq4FRMrJQYdHmqKF5ZAijSSdAoL4b1i2LtvSgY97G0mTkiiDdMqJlntQIAweUuizTSvCOEFrXrbg+ZE0YlEfd3pqPmkCs= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1709274490; c=relaxed/simple; bh=HZXcJ6H8E4qUtrI0o6kvTH8aJwAMKtQxMJB1WrJ4KiA=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=fXjlHyi7EneInXGC0ykLEuMQnr4qkN1HUOKrOW68G9AZTag5Tp9m/+sthDolLOQDwJlj6XNtB6WtHTcsp29Wn22YcM51VvG+K/k4yPtzCtodoSEP55o1ueFVbXtXwXTNAFdZPtRU65fpKwlYaK6sAZFLO5hDYp5nzsUKhz1sfO4= ARC-Authentication-Results: i=2; server2.sourceware.org ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=f3h+7/UF5tgnVrirWZv6yI15Owv8RV4uTYnGeYMNWnFajTo6mj/GKEzGV7hnSSACkk8dIoZet9O1pM70K8jxBCWZcpr7P+VaM/Badirl9ONDEV6UznTxDdSjtzcIqA/ECYKEJEaHIL+aukgLla1/SXqUR8DWSJlgEzG6JWWoP99p4A4+qD9EhzzY7FVJWIDZQ6bxoxBf1X++qn1iA8kyV/pNMN/70f6pahPGRCgtG0M3tZE/bvn2Dq3+EuV1FpVFpKtruQcPA2+srQtLGrYs8ZFJ/K8rhvQJvavhTszwO7+39dDwR6DuEsJabrCXnO9rXooTTrkN6GSbj6h/CMH4lQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qDfpiMMRi6G5N3ORQCaus80aTZuKiMj/Qy6iROf7ZOQ=; b=GIhZwnaMfDl1wqZ+CJ5hMH4D45zhTKw9KRjcSXcrUUFfC5hMRhnEXb+7+/GJi0wnDtVfua98Sf8Y/2Cl3O8lMpD4QtjCodFCnDQJEySkg259+fU17NPzmulqFIYkiri7x+ph5FMonP4VjM7uLtitylXypWzlyEdNPH87peoSgggsS/pG4PPNUYQJLUSxFHNpBVp7sdthjV74LYYqrvq0MsC+IH7QCQFJwgYlhbraDhUUy1/qQCUTRxpK8cqW+tIDyxAH+2l2Jc326spc6JF0zojFj4C5gOPZvSFHX5fCiUuv9tjRfXOl7LXV9t6DDBK39aR02H6JiMWmWNEMKsK4DQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) by ZQ0PR01MB1080.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.47; Fri, 1 Mar 2024 06:27:50 +0000 Received: from ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn ([fe80::21d1:48e1:7ca0:1d76]) by ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn ([fe80::21d1:48e1:7ca0:1d76%4]) with mapi id 15.20.7270.047; Fri, 1 Mar 2024 06:27:50 +0000 From: "demin.han" To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, pan2.li@intel.com, jeffreyalaw@gmail.com Subject: [PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm Date: Fri, 1 Mar 2024 14:27:09 +0800 Message-ID: <20240301062711.207137-4-demin.han@starfivetech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240301062711.207137-1-demin.han@starfivetech.com> References: <20240301062711.207137-1-demin.han@starfivetech.com> X-ClientProxiedBy: BJSPR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::35) To ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1063:EE_|ZQ0PR01MB1080:EE_ X-MS-Office365-Filtering-Correlation-Id: c8bd0f30-bacc-4399-abcd-08dc39b8b82f X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eg40foBzzvUXq7367SrSTk4vTRZsx2M6NAlyhLiOscr3S9E0+Wqeav3xwUnyT0odzA0Rh6AztWusvtDwMv05sItVMUgvxzka3pIL8FxnX7/CPcbbUZepDWBiiXUnwhPFTpbO+VZNLuc17EN7OZ0aJAk2cVg7MqbFa9uz6C5xMvzzeXJoim8ffF9sfLNtlQUFzYNg0q7WSj3fUzEEXekEqCM485yiU8JwLPKXIs62FtkmsGy+OGDBVMYtvVr/xFxcVw839g7j1Nd8Ili3NZinwuWkwMhJut3ABn7XuPUVNp/aJG7MnvGjVPZ8PYs5G+r2/Il3TdY69u26BIJTecydhVqCmO3qlg4mN27dgUDcHMNIHdP5NUite/wJIOcwK9SvRkeSpX7tfRr3smDINwryDbedZRy5fEegFLHAgquvVd4AqGaNePapvruhTGLvW35UkiKQCPtLIltUdBNmh/49RXveVGzKhaNM6wsow5iYGpKGqREvGswwWQz2TscPCbf7GCf3AuT89nP2pgUmO8Kur4rtVsTYUcDHOVT1qjX4wlp79LfWAN8sYuZVTDPQIvaAQLNiney4NezZUnq+c25ERo4oUp68pNlUTo8sDCqA+yf7bfD8oZiyo+fJgGIJ6uci X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn; PTR:; CAT:NONE; SFS:(13230031)(41320700004)(38350700005); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DAd7qNPU2QsAy+SQLF3yTDYwG3D4mV0AsrlG7AUy5dGNRjW9NpqC8yYehW/L+2mhlQoyZ3eb2do3gD669OJ3hMbkcdAfopZdDPgxR1gaND0aF8CGMJjp1GFTV+vS+p8/9evu8PGATLIr90igDlKq5S54Y48pRjE11x3U0/61pMZzKzu3twu7Kp3AAlXAsxEueGrQ27bXtnJuZ4ojgW6v+g0aVA2HvVKZN3qkg0SCb++nR188rZQ9l9N76XyL1bBp7jWtVC/bfzsl/vaFfLuONyx6H76NceDQwI2QQtgBFN/N1rYWTcYlSQNCXyayU43X2fw+73X282fZK6Rw58AWjBcOCtu+zWKArX+F7qZGBm7kgzVe3QcG9bwEqXTHxSojKcrhb8eXADCruc2QMhUWwwDz2jm27ZSAidu29wQSEXS5n5w8smUfJRdhq/w/DRTIZSug2smNF3Xgks1MwFtOKuHuNk8VTPq5S6NTeRspJwo48QQyfJiVa8pNsolUgc+lzlYjqAGxgh/HKq62ApFwPllgtZXT5TShxDIkkFX5lhfAwKb/tgx0VU0K7k2zSNkbxN0/dvZGnT6DWbKzT3KP6gig1HT9Pik1jbunCESsruxk51ZHd/o25PzxP2dwvvIf57M0WIKh4OGjvzeTkoFjhOVs848TMG/RwArq1MY9vY4rmYlvnfLr6FvI4ph044kQsdKKXNDkONYt9NMsQZwt5l6chQRjh+i7lcOIFHCR7BMkoiTbP0jFp9okk5L8ts3+GCaNnYfNTXUYTQnR31pQnZFyNgdB+SJvD+h7ni0kQR5ov61OcvoNk53n5D3t4abcCR2oAuMHgXxcDx3Qn+hLJtpsdaRuUNKMrKTny00qzxmtwj0BYIGvIE+FXvduHvyzcTRivYIUEIebGgybghjr/rGxbzfuPbmTk0d3RSl8AUkzqvF6MFFmtunoOc/Q15W7c8NuT159Hn69rpy+Csv0oVW75Bb1RjruWavczw2iV+L/yLWa3/QeAwBrgvh4smMEc1agg5+3+zwu5edFt4QoL8RIq9Dq6vGB6o4LxHoRnkVbGe/prkiW/jQLGevgE5I5ahPVyEynDOmzpJ7OSvqEm3H+88iqgKzkhk+10LqzeIo/4cgcHE68YHFSPyblUs9KKOYMrxmwv+ikkaUwWpsQq9MuRAFW3xhHOELjN2AQip8DUR3/Fhl/bYTkjKlq0a+kuLO9d+uCZb4StthDKUMxeUhAZcZN9AMycbfHSVCbDYLcyzsFgnxSmofLDHD6n1Mr05vE9EshVd7HIOltW2p7pZK8Q99Fz+uX56nppPoF6+APgIfWjgg+0hHES0eGGCS5EFBhQveUpKAJ2qaCq2mwjDonDP380g1WORrEfMGfr+Fetl5WjLWOiklfRA59544icncJAEJ/8CdNDB+AuQrzW5mkpmOtwviQUe9UmLE+kFi0PNO5utlVeil3u0wlX6oZeKciwXphV15gatgA/fVZjCjz8HtjcNpG+0MT/QxqDfNdp11y9iMXpb6KmfQyoEERxeko59Dhw8wqOQxKYBU61qzZGt6LlUjt2ud+Lo2+hzu+CWNLhs4mLf+z6oYHKHwmwc14h12lThHFHcrL0vqW5A== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: c8bd0f30-bacc-4399-abcd-08dc39b8b82f X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2024 06:27:50.8260 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: v3PaFreIZs9Gu1cW4S+6gCApjhNzZbiBjeBn/VH85a4PXFNNe1kk6b+dNL4BnNEZn7wke5SOLF7DDr+334uTyTggMfMjIsGNGp9knwrpxnA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1080 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Currently, following instructions generated in autovector: flw vsetvli vfmv.v.f ... vmfxx.vv Two issues: 1. Additional vsetvl and vfmv instructions 2. Occupy one vector register and may results in smaller lmul We expect: flw ... vmfxx.vf Tested on RV32 and RV64 gcc/ChangeLog: * config/riscv/autovec.md: Accept imm * config/riscv/riscv-v.cc (get_cmp_insn_code): Select scalar pattern (expand_vec_cmp): Ditto * config/riscv/riscv.cc (riscv_const_insns): Exclude float mode gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Add new tests Signed-off-by: demin.han Signed-off-by: demin.han > --- gcc/config/riscv/autovec.md | 2 +- gcc/config/riscv/riscv-v.cc | 23 +++++++++---- gcc/config/riscv/riscv.cc | 2 +- .../riscv/rvv/autovec/cmp/vcond-1.c | 34 +++++++++++++++++++ 4 files changed, 52 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 3b32369f68c..6cfb0800c45 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -690,7 +690,7 @@ (define_expand "vec_cmp" [(set (match_operand: 0 "register_operand") (match_operator: 1 "comparison_operator" [(match_operand:V_VLSF 2 "register_operand") - (match_operand:V_VLSF 3 "register_operand")]))] + (match_operand:V_VLSF 3 "nonmemory_operand")]))] "TARGET_VECTOR" { riscv_vector::expand_vec_cmp_float (operands[0], GET_CODE (operands[1]), diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 14e75b9a117..2a188ac78e0 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2610,9 +2610,15 @@ expand_vec_init (rtx target, rtx vals) /* Get insn code for corresponding comparison. */ static insn_code -get_cmp_insn_code (rtx_code code, machine_mode mode) +get_cmp_insn_code (rtx_code code, machine_mode mode, bool scalar_p) { insn_code icode; + if (FLOAT_MODE_P (mode)) + { + icode = !scalar_p ? code_for_pred_cmp (mode) + : code_for_pred_cmp_scalar (mode); + return icode; + } switch (code) { case EQ: @@ -2628,10 +2634,7 @@ get_cmp_insn_code (rtx_code code, machine_mode mode) case LTU: case GE: case GEU: - if (FLOAT_MODE_P (mode)) - icode = code_for_pred_cmp (mode); - else - icode = code_for_pred_ltge (mode); + icode = code_for_pred_ltge (mode); break; default: gcc_unreachable (); @@ -2757,7 +2760,6 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask, { machine_mode mask_mode = GET_MODE (target); machine_mode data_mode = GET_MODE (op0); - insn_code icode = get_cmp_insn_code (code, data_mode); if (code == LTGT) { @@ -2765,12 +2767,19 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask, rtx gt = gen_reg_rtx (mask_mode); expand_vec_cmp (lt, LT, op0, op1, mask, maskoff); expand_vec_cmp (gt, GT, op0, op1, mask, maskoff); - icode = code_for_pred (IOR, mask_mode); + insn_code icode = code_for_pred (IOR, mask_mode); rtx ops[] = {target, lt, gt}; emit_vlmax_insn (icode, BINARY_MASK_OP, ops); return; } + rtx elt; + machine_mode scalar_mode = GET_MODE_INNER (GET_MODE (op1)); + bool scalar_p = const_vec_duplicate_p (op1, &elt) && FLOAT_MODE_P (data_mode); + if (scalar_p) + op1 = force_reg (scalar_mode, elt); + insn_code icode = get_cmp_insn_code (code, data_mode, scalar_p); + rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1); if (!mask && !maskoff) { diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 4100abc9dd1..1ffe4865c19 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1760,7 +1760,7 @@ riscv_const_insns (rtx x) register vec_duplicate into vmv.v.x. */ scalar_mode smode = GET_MODE_INNER (GET_MODE (x)); if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD) - && !immediate_operand (elt, Pmode)) + && !FLOAT_MODE_P (smode) && !immediate_operand (elt, Pmode)) return 0; /* Constants from -16 to 15 can be loaded with vmv.v.i. The Wc0, Wc1 constraints are already covered by the diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c index 99a230d1c8a..7f6738518ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c @@ -141,6 +141,34 @@ TEST_VAR_ALL (DEF_VCOND_VAR) TEST_IMM_ALL (DEF_VCOND_IMM) +#define TEST_COND_IMM_FLOAT(T, COND, IMM, SUFFIX) \ + T (float, float, COND, IMM, SUFFIX##_float_float) \ + T (double, double, COND, IMM, SUFFIX##_double_double) + +#define TEST_IMM_FLOAT_ALL(T) \ + TEST_COND_IMM_FLOAT (T, >, 0.0, _gt) \ + TEST_COND_IMM_FLOAT (T, <, 0.0, _lt) \ + TEST_COND_IMM_FLOAT (T, >=, 0.0, _ge) \ + TEST_COND_IMM_FLOAT (T, <=, 0.0, _le) \ + TEST_COND_IMM_FLOAT (T, ==, 0.0, _eq) \ + TEST_COND_IMM_FLOAT (T, !=, 0.0, _ne) \ + \ + TEST_COND_IMM_FLOAT (T, >, 1.0, _gt1) \ + TEST_COND_IMM_FLOAT (T, <, 1.0, _lt1) \ + TEST_COND_IMM_FLOAT (T, >=, 1.0, _ge1) \ + TEST_COND_IMM_FLOAT (T, <=, 1.0, _le1) \ + TEST_COND_IMM_FLOAT (T, ==, 1.0, _eq1) \ + TEST_COND_IMM_FLOAT (T, !=, 1.0, _ne1) \ + \ + TEST_COND_IMM_FLOAT (T, >, -1.0, _gt2) \ + TEST_COND_IMM_FLOAT (T, <, -1.0, _lt2) \ + TEST_COND_IMM_FLOAT (T, >=, -1.0, _ge2) \ + TEST_COND_IMM_FLOAT (T, <=, -1.0, _le2) \ + TEST_COND_IMM_FLOAT (T, ==, -1.0, _eq2) \ + TEST_COND_IMM_FLOAT (T, !=, -1.0, _ne2) + +TEST_IMM_FLOAT_ALL (DEF_VCOND_IMM) + /* { dg-final { scan-assembler-times {\tvmseq\.vi} 42 } } */ /* { dg-final { scan-assembler-times {\tvmsne\.vi} 42 } } */ /* { dg-final { scan-assembler-times {\tvmsgt\.vi} 30 } } */ @@ -155,3 +183,9 @@ TEST_IMM_ALL (DEF_VCOND_IMM) /* { dg-final { scan-assembler-times {\tvmslt} 38 } } */ /* { dg-final { scan-assembler-times {\tvmsge} 38 } } */ /* { dg-final { scan-assembler-times {\tvmsle} 82 } } */ +/* { dg-final { scan-assembler-times {\tvmfgt.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmflt.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmfge.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmfle.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmfeq.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmfne.vf} 6 } } */ From patchwork Fri Mar 1 06:27:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "demin.han" X-Patchwork-Id: 86631 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BA1463858430 for ; Fri, 1 Mar 2024 06:30:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2102.outbound.protection.partner.outlook.cn [139.219.146.102]) by sourceware.org (Postfix) with ESMTPS id 30E033858402 for ; Fri, 1 Mar 2024 06:28:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 30E033858402 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 30E033858402 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=139.219.146.102 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1709274494; cv=pass; b=TQ2kPHgmm4voVG5WXeNXT2+lvdSZcp2HITO62DB/TFsLcFqU+R3Y7y5z23E2NBmeCeDDHSMg5oPDH5Icm9+LvRvzVy+3NxnVgocoOmh9lB5BBAXbgRKK37NnOGQFgeC8wxNX/VZWFn/rjK9Se+A+HlqPGK3Clj4v6TZUbwnPCVk= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1709274494; c=relaxed/simple; bh=HMYzqyH8mldUhSmhqFUQVCfNJvEXhewk4Y6H153ddRU=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=UkVnN3cCtwxRsBaaulZPBlRXT/AKOR7oS4mnbOzckVFHtdcVHIsbWS18Y/2zy87dF7BMnyt7XqFwCs7ZT+2zoHSBEOvnquKEzKKrKu0lns8T4e4iTQA64a1YZ9vNdW8AFrFmd2x448Jr9GZ1U5Wi4WLzXWCG8Za+Q6ZTu5FvF5I= ARC-Authentication-Results: i=2; server2.sourceware.org ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=md6jw7hTchEQKdfyr2yVEM1y6e+b731HBlGkw8z02PYRno3/Q3NMFBH7PGjTosmaK7wXA9po9Sct/bPtlP80rDZRpZQ5YxH7ZX+ukImum3S3DIXOyiBWmXEANu4GxSQkeUxLeEWwSdswCmcJZPmCDXzIekRCD4mNgr/llOBGhqOAmgfnzNva5FK8gXypSEYhUkWlTxyvQvVrNuNxtrDJGiZMvaZ+ODnpW1R/OlHjaeEz6jP8+1ggUvmvDwzc8X9lqGtIISnNmwB2CFYieQnZk+9//mdvFAkHO7xSpjxm1W6KkQ9A0154jkVinrtByVG3rjw3OD5Izhl5JQw5nxTWZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hQKBptBU6q+q5mYulUrIBZkGcHB8giwXf8ZrNNfC8sA=; b=cJuJ6dJFfnAP/6E4Xp1uES0Io3c8OZ9o4quJIDNEpnED9yN+qD7FonMPvJxbPmWfxnc0ppyH6gARszOarmJ9WGNr9SAKckrtxdi4XQ5bYFln0pyvCMDixNlwKvSqQaIoIlMaAJrvWWfQK8/3rVBTkEO7Br4eVdJMZhUEdIsfvjAhaBRPhbrmyNNH7w8pUlHjiOPO6C4vX5osHHG6vqocmeDWx0syQ2vrUzWOo0h1CFX1Qs1tinAFxAJZ72uMe+5KbOUH4ZA182aokO394Lg3M2Z6Aehec3a4RsKRAnh89s3vQhtew9KhNfhDoDUGcR/7v+vkIaAUOrs0PQZfl4n+Hw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) by ZQ0PR01MB1080.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.47; Fri, 1 Mar 2024 06:27:51 +0000 Received: from ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn ([fe80::21d1:48e1:7ca0:1d76]) by ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn ([fe80::21d1:48e1:7ca0:1d76%4]) with mapi id 15.20.7270.047; Fri, 1 Mar 2024 06:27:51 +0000 From: "demin.han" To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, pan2.li@intel.com, jeffreyalaw@gmail.com Subject: [PATCH 4/5] RISC-V: Remove integer vector eqne pattern Date: Fri, 1 Mar 2024 14:27:10 +0800 Message-ID: <20240301062711.207137-5-demin.han@starfivetech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240301062711.207137-1-demin.han@starfivetech.com> References: <20240301062711.207137-1-demin.han@starfivetech.com> X-ClientProxiedBy: BJSPR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::35) To ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1063:EE_|ZQ0PR01MB1080:EE_ X-MS-Office365-Filtering-Correlation-Id: fc18a36c-5375-48c9-c6da-08dc39b8b893 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dPSQuXrm2cqgkQJVTR7S5cbCapCzvMPbNwtejQrg/5kUcA+ErLVahB92JaOAu5VeAehXAkixfrfWdl0z+IWADiBCQ4LheIvnUew8ouU9dYPvUl2GjUPeO7awsE8qbqdjaJCQ1d61/W8AW9lSN1Z+BBTrUM4sxjd9YEFDlv6gb0Wo82RF/CWlCBhWbegirvf5AukAXVp4/25jTB7MNtfisNTQ1KMN5+CNyVQZy/DINlCAR6MMCUUl9jQqofK61IJoCkT1RGKEmFBu9QlHSiRi7QUoy+UQFYcclHdNjXZvZx4YjTqAaHHShJ/uo2SPx/gpzhUzGmWGPA7mzQo8HGDAs1iuk9PVnYgov6IcLMmgnIIKQzoYI1NbYMgwToZwxDViemJPHcB3nlgxEBkNJg3MWdnXQgiDBLz53y6Wp5kOMLinpf8+GjdL9mIZHHk7Yt/hZTFoce8y4zbUPlMaLTn54q3svoEFxmD3SCEBDnnFFUh/3VTmO49dlnAb1PmgEUjK7Py/l2VSlnZmNLYY784v/B6vKdZBzGhDL/8/TVp4RpH/h3Q2qxh2SSwZlAVNUCkFRV3pRm0+GUs4Izu9yDkVJ9nxkaHTCI0DCpANW8jpNJGbJP8O4XZUALhHCWufspob X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn; PTR:; CAT:NONE; SFS:(13230031)(41320700004)(38350700005); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BJGonB5IG3dl7ChgwQs8z5+Shr69QfKk1NpkzlAJDxgGTGY9T3oKXhCgCR26AX/j2ZTFc/bNUc+tpr/WM+ou+j3fVbBVvM9oVokLGVeVmQvnyTpY8AWKbjKEUr8a1aS1B0vASOmGtUKI0t1HvihGsJ5F+fED6KB06CH1sA5RTY7C5lakO7xS2bpoQj2MpHLXbRmFrhAsYGyBoCB7jrusazFM3XoGxhopFbmHrldtoMExle/DPEBJHN+UFdWyWWzLUbs71VD5to8a3fRXqmvdiPtQKctnmRvYb210PM8iLNQHezoXrLrSThFWvcsIx7mfPi0y77p9L21/wUbG4fx5Ae3zj3E2ERwS36eQVCL6+mkPEWBfmlurUGvlwmNNlM6lBhe6c4BXR5cFaKDLetOTYhyO/U2MWPiOVu9YJaU+SFi4Vfh3+9/tbUpAIaAp0hSz+Lkt0epiMCKo9XuVAxgldkuuvDUFkDJO4Tsx6z7WybAd9EuWXCu9OfldUwHi9pHqtbtGCSuCTJzvHKr8wWYDUKHgbFPdmBNSFquuf20TEuQp/lryIGn29kf3c7UuSai3tXjnEP5KAs/GziKgOEMBUVESU6p3hGQhBV1bGq4mN1485JzFV83jcGxl2gEbtUZ/42buYg8QlszXn0vA6N3jWhQWLhBJBDjKZMjQ17L9N9d7IvA1JfVDkiZmpQoVd08wgDoBXx7+bbitdVAVP5adYKwQPUs1RzorTyuxCx/FbN1qIHCJwThvFWdxuiXrWTTg3FwTJYy57O5fcBVVutk7qCQpiF06P/8+EBmmCpO+mHL8aRnueqJofwbFNjV7cFSGTQrJRcVNRRu0aOcwEQ0Tgo13cr+6SkyCbaVgtXMldEaHF4m8GSXDB6DLV57Vop/7Nd1LNUSoVQp1UHmwdTpAtZzyW3j+cQSS3bo0xpoJHzghnc/T9W8YqIbvFDL8bHsY1xXv8toKIuvdZZMZcaRzx2jEv7r3AiwYCXxY6hBWsxulNc3vVJiExXembcqKGm5CHniI/sKFLpIs+NyP+UOgnuaPaWoitCSdA9rHk8gCUXBXSrYpaT7QGsTznGSdo+FfHZ+c3Wpm69rkScWAdOaLzrTS1gsqXs5UB/9kO8evv3QVdrs/7/PZyjM+t+XcliDzWWCxr/GFv4Qqa3gF5GhpWj8iSF+ac/V7Tq31qAlUhdkjWr13AHIfJf4DKGTYyuLJUhpcNi/gZA/pGKYCbxpmUlIpUeMUpneb9aDU6xLvU0P4YU7Bk2UDCen2h896etVni57j3yg79ULw7+U+pBl6w0z2/1JgcIKS5+2JjvWvegzOpUXTRqKPX1CSP+BKeEIm66SXQKdBqnBIyh+kf8TozviHxsSp86avcLvAyU8UvuqbRmR/eKP9A+EHC8Tq7Av+kv8deY1AIRp9Qo5lb7o+hbNOtfiSLStn9zGPHm2JPHoc9lsT7Tggrv4Q9e5icPAEoq52EpOnrb2nMC7Rn9N3TgKTYjevLhP12roD+Kp3qMjxYT0Ki1uDbN7/ibbOyqn99YdvwW55fTuhWFhYOu5WmvViJ131Wv/J7DvqzHOV3cM/wVJCrkLVF7diQsgdZXKB3HZVnxrrzmHIGEkGTvJJTw== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: fc18a36c-5375-48c9-c6da-08dc39b8b893 X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2024 06:27:51.4636 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: U5BcmMfvYmSm5OGUvwz+0QgiKMrZLunOKFQs2pvIwhm6sa98iwla1GVHbYbw43E4BGzHMdNlFFjNovIsLZnk/zzPdVkEkJsHmwC+Me4ZlyA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1080 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org We can unify eqne and other comparison operations. Tested on RV32 and RV64. gcc/ChangeLog: * config/riscv/predicates.md (comparison_except_eqge_operator): Only exclue ge (comparison_except_ge_operator): Ditto * config/riscv/riscv-string.cc (expand_rawmemchr): Use cmp pattern (expand_strcmp): Ditto * config/riscv/riscv-vector-builtins-bases.cc: Remvoe eqne cond * config/riscv/vector.md (@pred_eqne_scalar): Remove eqne patterns (*pred_eqne_scalar_merge_tie_mask): Ditto (*pred_eqne_scalar): Ditto (*pred_eqne_scalar_narrow): Ditto (*pred_eqne_extended_scalar_merge_tie_mask): Ditto (*pred_eqne_extended_scalar): Ditto (*pred_eqne_extended_scalar_narrow): Ditto Signed-off-by: demin.han Signed-off-by: demin.han _scalar" (match_operand 8 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 4 "register_operand") (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand"))]) @@ -4689,7 +4689,7 @@ (define_insn "*pred_cmp_scalar_merge_tie_mask" (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "comparison_except_eqge_operator" + (match_operator: 2 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 3 "register_operand" " vr") (vec_duplicate:V_VLSI_QHS (match_operand: 4 "register_operand" " r"))]) @@ -4714,7 +4714,7 @@ (define_insn "*pred_cmp_scalar" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand" " r, r, r, r"))]) @@ -4736,7 +4736,7 @@ (define_insn "*pred_cmp_scalar_narrow" (match_operand 8 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr") (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand" " r, r, r, r, r"))]) @@ -4747,92 +4747,6 @@ (define_insn "*pred_cmp_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -(define_expand "@pred_eqne_scalar" - [(set (match_operand: 0 "register_operand") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 6 "vector_length_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand")) - (match_operand:V_VLSI_QHS 4 "register_operand")]) - (match_operand: 2 "vector_merge_operand")))] - "TARGET_VECTOR" - {}) - -(define_insn "*pred_eqne_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 4 "register_operand" " r")) - (match_operand:V_VLSI_QHS 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR" - "vms%B2.vx\t%0,%3,%4,v0.t" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand" " r, r, r, r")) - (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -;; We use early-clobber for source LMUL > dest LMUL. -(define_insn "*pred_eqne_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand" " r, r, r, r, r")) - (match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since ;; we need to deal with SEW = 64 in RV32 system. (define_expand "@pred_cmp_scalar" @@ -4845,7 +4759,7 @@ (define_expand "@pred_cmp_scalar" (match_operand 8 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand") (vec_duplicate:V_VLSI_D (match_operand: 5 "reg_or_int_operand"))]) @@ -4875,39 +4789,6 @@ (define_expand "@pred_cmp_scalar" DONE; }) -(define_expand "@pred_eqne_scalar" - [(set (match_operand: 0 "register_operand") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 6 "vector_length_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 5 "reg_or_int_operand")) - (match_operand:V_VLSI_D 4 "register_operand")]) - (match_operand: 2 "vector_merge_operand")))] - "TARGET_VECTOR" -{ - enum rtx_code code = GET_CODE (operands[3]); - if (riscv_vector::sew64_scalar_helper ( - operands, - /* scalar op */&operands[5], - /* vl */operands[6], - mode, - riscv_vector::has_vi_variant_p (code, operands[5]), - [] (rtx *operands, rtx boardcast_scalar) { - emit_insn (gen_pred_cmp (operands[0], operands[1], - operands[2], operands[3], operands[4], boardcast_scalar, - operands[6], operands[7], operands[8])); - }, - (riscv_vector::avl_type) INTVAL (operands[8]))) - DONE; -}) - (define_insn "*pred_cmp_scalar_merge_tie_mask" [(set (match_operand: 0 "register_operand" "=vm") (if_then_else: @@ -4918,7 +4799,7 @@ (define_insn "*pred_cmp_scalar_merge_tie_mask" (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "comparison_except_eqge_operator" + (match_operator: 2 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 3 "register_operand" " vr") (vec_duplicate:V_VLSI_D (match_operand: 4 "register_operand" " r"))]) @@ -4932,30 +4813,6 @@ (define_insn "*pred_cmp_scalar_merge_tie_mask" (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) (set (attr "avl_type_idx") (const_int 7))]) -(define_insn "*pred_eqne_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 4 "register_operand" " r")) - (match_operand:V_VLSI_D 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR" - "vms%B2.vx\t%0,%3,%4,v0.t" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_cmp_scalar" [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") @@ -4967,7 +4824,7 @@ (define_insn "*pred_cmp_scalar" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_D (match_operand: 5 "register_operand" " r, r, r, r"))]) @@ -4989,7 +4846,7 @@ (define_insn "*pred_cmp_scalar_narrow" (match_operand 8 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr") (vec_duplicate:V_VLSI_D (match_operand: 5 "register_operand" " r, r, r, r, r"))]) @@ -5000,50 +4857,6 @@ (define_insn "*pred_cmp_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 5 "register_operand" " r, r, r, r")) - (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -;; We use early-clobber for source LMUL > dest LMUL. -(define_insn "*pred_eqne_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 5 "register_operand" " r, r, r, r, r")) - (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - (define_insn "*pred_cmp_extended_scalar_merge_tie_mask" [(set (match_operand: 0 "register_operand" "=vm") (if_then_else: @@ -5054,7 +4867,7 @@ (define_insn "*pred_cmp_extended_scalar_merge_tie_mask" (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "comparison_except_eqge_operator" + (match_operator: 2 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 3 "register_operand" " vr") (vec_duplicate:V_VLSI_D (sign_extend: @@ -5080,7 +4893,7 @@ (define_insn "*pred_cmp_extended_scalar" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_D (sign_extend: @@ -5102,7 +4915,7 @@ (define_insn "*pred_cmp_extended_scalar_narrow" (match_operand 8 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr") (vec_duplicate:V_VLSI_D (sign_extend: @@ -5114,76 +4927,6 @@ (define_insn "*pred_cmp_extended_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -(define_insn "*pred_eqne_extended_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSI_D - (sign_extend: - (match_operand: 4 "register_operand" " r"))) - (match_operand:V_VLSI_D 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR && !TARGET_64BIT" - "vms%B2.vx\t%0,%3,%4,v0.t" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_extended_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (sign_extend: - (match_operand: 5 "register_operand" " r, r, r, r"))) - (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode) && !TARGET_64BIT" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -(define_insn "*pred_eqne_extended_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (sign_extend: - (match_operand: 5 "register_operand" " r, r, r, r, r"))) - (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode) && !TARGET_64BIT" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - ;; GE, vmsge.vx/vmsgeu.vx ;; ;; unmasked va >= x From patchwork Fri Mar 1 06:27:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "demin.han" X-Patchwork-Id: 86628 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F28E13858281 for ; Fri, 1 Mar 2024 06:28:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2132.outbound.protection.partner.outlook.cn [139.219.17.132]) by sourceware.org (Postfix) with ESMTPS id 06E3F3858C31 for ; Fri, 1 Mar 2024 06:27:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 06E3F3858C31 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 06E3F3858C31 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=139.219.17.132 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1709274481; cv=pass; b=wJ7/V96Uju+VEm3Jr2vZ/wny4b8Qdotm1CSEWaJ5l6yhUYfzdfJFzrwTCqPl7cWmS5QEy5Im20l93jO4Jc/zgtWnsNkcaDslXR9mgVykdQ572/ITM+Nq97KetfvCkY5tgvV+/kFirpBjwUJypz9jW0c2VXEAEtRbOTJEgXGkfN4= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1709274481; c=relaxed/simple; bh=OUtwS3dflL//IZiZ6YsHOSZCDKKoJgI3ziDZnouAhi0=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=ApcvE5TUrvLV54YBn/HWPkx64u6IFAiK1ZEPmBqNolycRo88H6dM0WHzf9esyhk33xgoLX+c2ahMGrW778Ukt+i41ji+PV1/EMckVqSgZ3rFre3VJMI4q71L2StHRntTw88C4kkjr8Vb7eNuQj68yYxjsiy+IcladYbPFBfLd84= ARC-Authentication-Results: i=2; server2.sourceware.org ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=KDWU+uS2W1JKmf7qKi39VuWCiEQnpzUKn8fqnFynNCzL9u+LJG3xK75Ymm57gmOb2EAdt6t+uEFn/cAdC/5mYoll+qaYffctLgFKdO+n82nJwxtsmSGnqFh4SWnF7sMUnHNbXBsSoetX2OFASuWFjoYvoCcrIrFnixbkQI3EL27e9OTxLRehH3CHG4zbHflF9amIWmI14id1IyUoW8+JiMxtNBctSYB9ly08gyev7rAfaMKgRnLvaPPgm/ZlHfKTIIOXOj0r32LNGjVfNBo6Ko1l7tbfvpAcJ1kxQuQk/p3rwNU7GEUvOoU978FsEs2sFRdS+nl5m32LHnjATZr/2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=010M9Q8rYQFasQOALYGfjFnNlL6qAybv2H3rBvWfA8k=; b=GOAspOjvdkMY2Qq0WiFSi8XTEh7BnwtzeWVcnHhlrSusLuwJ6/CIggZpGmm3QMZwFZyY4Vn0Y6R6ReeCWpS4GV20aZAc2iB2zABlK/Lhs00smrS5Esur0Q30E4Pr4MSF/FwNqfwJP7hcInWUiKrB2Rp/bxdqkwqm29LbNPdytdLvWQCUC4OGhpWrQMN/87tt6DnFqE/ZiyMoCXj+9pAoZfu9za1VpVJF6973A/30CcIKV0LU+ROh57edv+WJG4JwugICCWhQtCcJuXgP1xI7egvnQNCrQZzFksCKqM3Lmo9MefyFJCMoghtJeGwgZ2GZa2sJW9tT616XSRpP4YynNw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) by ZQ0PR01MB1000.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:c::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.39; Fri, 1 Mar 2024 06:27:52 +0000 Received: from ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn ([fe80::21d1:48e1:7ca0:1d76]) by ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn ([fe80::21d1:48e1:7ca0:1d76%4]) with mapi id 15.20.7270.047; Fri, 1 Mar 2024 06:27:52 +0000 From: "demin.han" To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, pan2.li@intel.com, jeffreyalaw@gmail.com Subject: [PATCH 5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm Date: Fri, 1 Mar 2024 14:27:11 +0800 Message-ID: <20240301062711.207137-6-demin.han@starfivetech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240301062711.207137-1-demin.han@starfivetech.com> References: <20240301062711.207137-1-demin.han@starfivetech.com> X-ClientProxiedBy: BJSPR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::35) To ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1063:EE_|ZQ0PR01MB1000:EE_ X-MS-Office365-Filtering-Correlation-Id: fa16049a-53ed-4700-82a1-08dc39b8b8f5 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wgw9O8bmXH57vLjdO+qd4UuJSVOGMfH3ujAgrJvF2lOodIbyhIwh3uh58nolN7EvOUQmhQi5/hmF7zUi3GE5vViVdhAwnlhhBU2gUy7eM+A/qC3OoAIclqh3nikXIEinDWt//sC3iTG0cbkKkxjn8kKPIPIJn2H/4/BjxrScmZ1BEBW5uOJhwSEKifsjeD6+tj+qgO4Fv+3gbzstQ6MuBr3byiU1ECmp6bWNSZAE6pfsnoazW97p0AAn5dMF4byhF+TdzZKfs7HXz/+6fPmkx5TsO1qnnZF8vsH0JALtWKphxWCZMfHgMC5A0YNKLLBRjNo5vD5LdAIvW8cI1sEZjolGNHBtI+q272GrRJHj9xjTU7pheMIg85otU3wJUiRixLs2EmqPFu7RnyNjB+Ftxe3RptafyugAf+iXWTYB8eF1+f4mDti0RUUuic0rBJDoDIMhxUgzbu3KmhWNRU7uAMcAWMYMAT/UERyFDsNtM9xp/5KoxPmUBGD9ZpsMp+go4Y/udcypqs9/k6J2pN5mqvjh4EstrBqsms/ilMYF1Jns+IVQ2NUzhroWPzQBTCS73xqixHuTlzvOxqto0ItqL/YbLYLmmibmppG2GKHYseZNFso0fNA12FeKjHxheFZL X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn; PTR:; CAT:NONE; SFS:(13230031)(41320700004)(38350700005); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: kSvjLhgqrCbZDvJEn5c3/7c4TNsa7Z+Vb87d2Ny0Av9D3//oOzP2jSiyVxkDAJvfV/vPcT2SWOrntZ2Btaetyytg2ysOV0bcFIRmA0jSv4YR06p4zKn9fH/o6V+NyR27q8LmUWAOb2x7YN566jrF2kpHDyksyTKA8TUf0ILScObW/V/xH+ugrfJRH/93KC4D5KgE+hKDpjYlakx+bwTVCpnv/YjY3Y2mao2HwXeFovrykBWthMEvD2+JFE72wx+mUhNLNWvQe0+EGFogB6prlN1GGmbbVs+9QhsOgxl+lIRFkvop6pmSsSFDKuoqo1qCR4y1tJ/afi8veH7EQLrL4zOmKmHYh35cnV0jT0XjF5X+WIFB+CvRh8PdUaSHYUvWuIoY7SX0WMitpCc5Y15sauz7f+3vIMxXjDgoKtdZZlHabuOJU7LSp2X2qAWYefIwoZw18cHC71yDXvfekSW1QXZUVVFLLDJnRO5XqdS+bGvc6kNJKoU7n4XTYYAdCA1RZ99WTFBGqSMpeH5rUX/lvqo9X6rhbGdZX4vsBGUgndWTU5Hr/yzsyXW0WtE6xDUVFIVW8wkVUMFelS13eLQmkLkGNoq3GRJpVcCu98g61rTlurQ1mWuFByB6R4fEr5QHYyOwYV7rH20dqBNMzCXgZL6k9c9bmmzylIX0uScXex/m5Ki3riyGvpY+TRdhviVJlDQWiLCz4GeMrjtdoOYCpBbmYeaN/hr3ndWTnFmtj1LT19kYz8NUQraPb9QOFlcNinZJnvhykkfe7HqJxtPFMj5V49tg7GgAVgZMJ3WuAWmldI13XUiqhh6k6Nd8IwSuIWW0L36NPmAJjpbj0K8CRNAT39+Sx4hRhPywjJfRW95GUUyT0/8Xtsh16maPv0u4Iz5mNbudIH7y1CJ8iBR26IMdiMegM6ssgRSYnt4e3zK7iyMk3SNFeTr0TTj+V/jTtgLpbtmLTaJuEgnBTfHDc5Fr8BR1fwgwWCh4CPduQZmkhiiBnwPP1Rjc6ZxERdo7yut811iISMqW3ppTXotojzdfRzvyCVvnQBgHqY5QLQ4HzuWk/XktMilCTSOKjukX8bOi+cA/RX6c7v6LWxHi0k6T4u7JyDUYtpDIYvVeyBh+a1WqB81rs6T/TCRraGgmf0SbAxJsKLMM9bNWJ0ra9xAYki8sui16+g22oy8nMATZkJubgqL6xaZal/7Z8Hm/BnZhw9wHpO3cItZkf6+OdtYdXgPd3faSXbLyaecdEz7LvHWxCQ1hiC5NkgJ3X01OugkhYEAII3gU8iZCd4oiIK8rRRhravNXti6zaMp38G4LsjhCRn2azVgxT0lxdLeuwKPBA3OSYxmhHnYzViHIMVJDVumltQp5QLr2tY94BwWQc9xMJN3Ea1H6ukE3iGekAiiAXwxYPPArNeYUeNRmKLRiX+wn9WltbDwGa6MfUQR8GvKAwXvmmC8SUlpfcCo55uR/i9NBYIssbathb8tULs+ov9NLTR/KF83n5zdKxAKVpds3l3G0EzUFNEFP1VacPFTczcOKgARnFfAUO7x1g/kfeO4RbW5wdfA9xK1Hkl3c0eYf8y9N6+2vYwOMZlsFoeeUtsB4u5CFjslVsfi8HA== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: fa16049a-53ed-4700-82a1-08dc39b8b8f5 X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2024 06:27:52.0434 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 1e/HIYQpR5tKR+dfXdgixr/hHxZ9ot9QZgxRYqpHv8XBUOiyrE61pCIFYUMn1zG3BwoDThXtwbag9a1I0/QftIAx4V3jCp88qXgFSW7kZgs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1000 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Similar to previous float change, vmsxx.vx is needed. 1. Only those which can't match vi should use vx. 2. DImode is processed by sew64_scalar_helper. Tested on RV32 and RV64. gcc/ChangeLog: * config/riscv/riscv-v.cc (get_cmp_insn_code): Select scalar pattern (expand_vec_cmp): Ditto gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Update expect Signed-off-by: demin.han Signed-off-by: demin.han