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Mon, 26 Feb 2024 05:43:23 +0000 Received: from smtpav06.dal12v.mail.ibm.com (smtpav06.dal12v.mail.ibm.com [10.241.53.105]) by smtprelay04.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 41Q5hKGx18416340 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 26 Feb 2024 05:43:22 GMT Received: from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CDDDE5805D; Mon, 26 Feb 2024 05:43:20 +0000 (GMT) Received: from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3149158060; Mon, 26 Feb 2024 05:43:19 +0000 (GMT) Received: from [9.109.208.145] (unknown [9.109.208.145]) by smtpav06.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 26 Feb 2024 05:43:18 +0000 (GMT) Message-ID: <1a62a215-98e2-4e3b-9059-681189157d0a@linux.vnet.ibm.com> Date: Mon, 26 Feb 2024 11:13:17 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH] rs6000: load high and low part of 128bit vector independently [PR110040] Content-Language: en-US References: From: jeevitha To: GCC Patches , "Kewen.Lin" , Segher Boessenkool Cc: Peter Bergner In-Reply-To: X-Forwarded-Message-Id: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: sOYRX03CHEW3FRj3PlR-bVzjRd8mc3uo X-Proofpoint-GUID: sOYRX03CHEW3FRj3PlR-bVzjRd8mc3uo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-26_02,2024-02-23_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 suspectscore=0 impostorscore=0 mlxscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 adultscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402260041 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Hi All, The following patch has been bootstrapped and regtested on powerpc64le-linux. PR110040 exposes an issue concerning moves from vector registers to GPRs. There are two moves, one for upper 64 bits and the other for the lower 64 bits. In the problematic test case, we are only interested in storing the lower 64 bits. However, the instruction for copying the upper 64 bits is still emitted and is dead code. This patch adds a splitter that splits apart the two move instructions so that DCE can remove the dead code after splitting. 2024-02-26 Jeevitha Palanisamy gcc/ PR target/110040 * config/rs6000/vsx.md (split pattern for V1TI to DI move): Defined. gcc/testsuite/ PR target/110040 * gcc.target/powerpc/pr110040-1.c: New testcase. * gcc.target/powerpc/pr110040-2.c: New testcase. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 6111cc90eb7..78457f8fb14 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -6706,3 +6706,19 @@ "vmsumcud %0,%1,%2,%3" [(set_attr "type" "veccomplex")] ) + +(define_split + [(set (match_operand:V1TI 0 "int_reg_operand") + (match_operand:V1TI 1 "vsx_register_operand"))] + "reload_completed + && TARGET_DIRECT_MOVE_64BIT" + [(pc)] +{ + rtx op0 = gen_rtx_REG (DImode, REGNO (operands[0])); + rtx op1 = gen_rtx_REG (V2DImode, REGNO (operands[1])); + rtx op2 = gen_rtx_REG (DImode, REGNO (operands[0]) + 1); + rtx op3 = gen_rtx_REG (V2DImode, REGNO (operands[1])); + emit_insn (gen_vsx_extract_v2di (op0, op1, GEN_INT (0))); + emit_insn (gen_vsx_extract_v2di (op2, op3, GEN_INT (1))); + DONE; +}) diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-1.c b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c new file mode 100644 index 00000000000..fb3bd254636 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c @@ -0,0 +1,14 @@ +/* PR target/110040 */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */ + +#include + +void +foo (signed long *dst, vector signed __int128 src) +{ + *dst = (signed long) src[0]; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-2.c b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c new file mode 100644 index 00000000000..f3aa22be4e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c @@ -0,0 +1,13 @@ +/* PR target/110040 */ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */ + +#include + +void +foo (signed int *dst, vector signed __int128 src) +{ + __builtin_vec_xst_trunc (src, 0, dst); +}