From patchwork Fri Feb 23 11:41:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 86277 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1E9833858434 for ; Fri, 23 Feb 2024 11:42:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 7A87D3858425 for ; Fri, 23 Feb 2024 11:42:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7A87D3858425 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7A87D3858425 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708688538; cv=none; b=BH16nzpBITBCxPbZ+RxWmVa56ePprTP43rCJ/WVAtK6kDumSu6WbJELRwvLMeXt25wYszBvEZsofS4a8/LFODI6TZx/C/C3eJHtwRROBrWSQENR8ipqI4OouBfo5wJjsjBtLCTHBVhEiZdxXbaDTkEEcV/RCLe426aNWZyEROwA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708688538; c=relaxed/simple; bh=x/5XwcJsZmmI+Rk8E1powL672S0tGTsqKHA5avoQJj8=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=X7folcEzP4UW55WTCX1MfVuzOxsQnQS+In+py8vLd3KB4dqXi2cjE2qwCP6nikzgeEBpTRRpzw0GvSfMfiVGvknk+n5v3Sjh/C5DsGpin4NBH/1atzZpaLVe/LxX7GlVfQSrAh0+LSuwQko8sESMIutIKkXyMUedqzAc9Sx4hBg= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B520611FB; Fri, 23 Feb 2024 03:42:53 -0800 (PST) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.78.54]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B31F33F762; Fri, 23 Feb 2024 03:42:14 -0800 (PST) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [committed] arm: fix ICE with vectorized reciprocal division [PR108120] Date: Fri, 23 Feb 2024 11:41:55 +0000 Message-Id: <20240223114155.1748856-1-rearnsha@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-13.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org The expand pattern for reciprocal division was enabled for all math optimization modes, but the patterns it was generating were not enabled unless -funsafe-math-optimizations were enabled, this leads to an ICE when the pattern we generate cannot be recognized. Fixed by only enabling vector division when doing unsafe math. gcc: PR target/108120 * config/arm/neon.md (div3): Rename from div3. Gate with ARM_HAVE_NEON__ARITH. gcc/testsuite: PR target/108120 * gcc.target/arm/neon-recip-div-1.c: New file. --- gcc/config/arm/neon.md | 4 ++-- gcc/testsuite/gcc.target/arm/neon-recip-div-1.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/neon-recip-div-1.c diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 17c90f436c6..fa4a7aeda35 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -553,11 +553,11 @@ (define_insn "*mul3_neon" Enabled with -funsafe-math-optimizations -freciprocal-math and disabled for -Os since it increases code size . */ -(define_expand "div3" +(define_expand "div3" [(set (match_operand:VCVTF 0 "s_register_operand") (div:VCVTF (match_operand:VCVTF 1 "s_register_operand") (match_operand:VCVTF 2 "s_register_operand")))] - "TARGET_NEON && !optimize_size + "ARM_HAVE_NEON__ARITH && !optimize_size && flag_reciprocal_math" { rtx rec = gen_reg_rtx (mode); diff --git a/gcc/testsuite/gcc.target/arm/neon-recip-div-1.c b/gcc/testsuite/gcc.target/arm/neon-recip-div-1.c new file mode 100644 index 00000000000..e15c3ca5fe9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-recip-div-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O3 -freciprocal-math -fno-unsafe-math-optimizations -save-temps" } */ +/* { dg-add-options arm_neon } */ + +int *a; +int n; +void b() { + int c; + for (c = 0; c < 100000; c++) + a[c] = (float)c / n; +} +/* We should not ICE, or get a vectorized reciprocal instruction when unsafe + math optimizations are disabled. */ +/* { dg-final { scan-assembler-not "vrecpe\\.f32\\t\[qd\].*" } } */ +/* { dg-final { scan-assembler-not "vrecps\\.f32\\t\[qd\].*" } } */