From patchwork Wed Feb 21 11:14:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 86151 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8C3B53858422 for ; Wed, 21 Feb 2024 11:15:36 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id DD85E3858C42 for ; Wed, 21 Feb 2024 11:14:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DD85E3858C42 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DD85E3858C42 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708514092; cv=none; b=ShZL0ZiU76R6EMPSwGa70ns2LpHY2pnc5gdGMsFvVD0x4vhvVReRzeMxgFisP13H38Vr7iAzTF+HXp9Zo0EyefVqMqjYst7fQDEQE5iv4GftyiWjjGJnKAReH6AqYstlvg6GHsNUhfrRbJnxplA8D7ZEiItef5kMC9S3GuXQvmc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708514092; c=relaxed/simple; bh=b6DPvlit8Z1DuWlduaUQhCBzWJJSmoWaE3K6LqPbU94=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=IZ28t5PhMXz7aJ2ckyo51TWNRvZj5vOGGmgx3BAnnzFyNp3ZBBswk+nUxrblZNKkFz6sl+2lipxlWq/yiQvZ9+mnpLPdJWGVfbV47yfsYa55BvQ1JqkF2xkaAoVh7ZhG3MsKrDe0iBSxuHuevIA3eXzp8XBm1KHyTFfaLYJOwu0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 22BA7FEC for ; Wed, 21 Feb 2024 03:15:29 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3E24D3F73F for ; Wed, 21 Feb 2024 03:14:50 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [PATCH] aarch64: Ensure ZT0 is zeroed in a new-ZT0 function Date: Wed, 21 Feb 2024 11:14:48 +0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-20.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org ACLE guarantees that a function like: __arm_new("zt0") foo() { ... } will start with ZT0 equal to zero. I'd forgotten to enforce that after commiting a lazy save. After such a save, we should zero ZA iff the function has ZA state and zero ZT0 iff the function has ZT0 state. Tested on aarch64-linux-gnu & pushed. Richard gcc/ * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state): In the code that commits a lazy save, only zero ZA if the function has ZA state. Similarly zero ZT0 if the function has ZT0 state. gcc/testsuite/ * gcc.target/aarch64/sme/zt0_state_5.c (test3): Expect ZT0 rather than ZA to be zeroed. (test5): Remove zeroing of ZA. --- gcc/config/aarch64/aarch64.cc | 8 +++++++- gcc/testsuite/gcc.target/aarch64/sme/zt0_state_5.c | 3 +-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index ed7fbca512b..de746e28ca5 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -29338,6 +29338,7 @@ aarch64_mode_emit_local_sme_state (aarch64_local_sme_state mode, bl __arm_tpidr2_save msr tpidr2_el0, xzr zero { za } // Only if ZA is live + zero { zt0 } // Only if ZT0 is live no_save: */ auto tmp_reg = gen_reg_rtx (DImode); emit_insn (gen_aarch64_read_tpidr2 (tmp_reg)); @@ -29348,7 +29349,12 @@ aarch64_mode_emit_local_sme_state (aarch64_local_sme_state mode, emit_insn (gen_aarch64_clear_tpidr2 ()); if (mode == aarch64_local_sme_state::ACTIVE_LIVE || mode == aarch64_local_sme_state::ACTIVE_DEAD) - emit_insn (gen_aarch64_initial_zero_za ()); + { + if (aarch64_cfun_has_state ("za")) + emit_insn (gen_aarch64_initial_zero_za ()); + if (aarch64_cfun_has_state ("zt0")) + emit_insn (gen_aarch64_sme_zero_zt0 ()); + } emit_label (label); } diff --git a/gcc/testsuite/gcc.target/aarch64/sme/zt0_state_5.c b/gcc/testsuite/gcc.target/aarch64/sme/zt0_state_5.c index 0fba21868ed..2e008463aec 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/zt0_state_5.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/zt0_state_5.c @@ -54,7 +54,7 @@ __arm_new("zt0") int test3() ** cbz x0, [^\n]+ ** bl __arm_tpidr2_save ** msr tpidr2_el0, xzr -** zero { za } +** zero { zt0 } ** smstart za ** bl in_zt0 ** smstop za @@ -102,7 +102,6 @@ __arm_new("zt0") void test5() ** cbz x0, [^\n]+ ** bl __arm_tpidr2_save ** msr tpidr2_el0, xzr -** zero { za } ** smstart za ** bl out_zt0 ** ...