From patchwork Mon Jan 29 08:21:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 84854 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E83A038582BF for ; Mon, 29 Jan 2024 08:28:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id E2F5B3858419 for ; Mon, 29 Jan 2024 08:22:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E2F5B3858419 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E2F5B3858419 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706516557; cv=none; b=NWK2OENcI2cmKk0/EkUznZlx4Nf1gqrcpFhvymKUQzlrNsIzL0bpBjMtLdUiswA/Lz+lwyAlkJG/S2T6oC953QOyDM9uiGQmBkET4rcqy2YoqYrvRX1Fwjdx8mMaN7VblwQ1e0tHcTrLTB9nWqyzmXclJUVLJhvddkvu0l0pwpE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706516557; c=relaxed/simple; bh=lEIToE3HYbOnuueXca+V74jpuAv28A1+HUfV6bY81Eo=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=kdz77p1z/8Lo+xrtSfvey0uAeB23zJoHPkiYgbm3eVilej7GujfsE/801lakVcbjlOwblmGDp5/pkD/xwSMcCHUcyDJTN/xod6JanrekducWIVfSoASV1dnP5Hn+GcGH/aRnJzT8MWlwEpb25VeQCfhiSugBy2PlFW0xponC5IA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUMuS-00014n-MQ for gcc-patches@gcc.gnu.org; Mon, 29 Jan 2024 03:22:30 -0500 Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8DxJ+g7YLdljbEHAA--.4524S3; Mon, 29 Jan 2024 16:22:19 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxnhMrYLdlKxklAA--.26775S3; Mon, 29 Jan 2024 16:22:12 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, Lulu Cheng Subject: [PATCH v5 1/5] LoongArch: Merge template got_load_tls_{ld/gd/le/ie}. Date: Mon, 29 Jan 2024 16:21:57 +0800 Message-Id: <20240129082201.26087-2-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240129082201.26087-1-chenglulu@loongson.cn> References: <20240129082201.26087-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxnhMrYLdlKxklAA--.26775S3 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW3Jw4kur15ZFWxWF4UCrW3urX_yoWxXFy3pr Z7Cw13Kw4rJrn8C3yUG345Wr4DGa17Wr4aqF4ftrWrCF17Xr45ZrWIkF9Iqayjg34rXr40 gayrAa4YqF45AwcCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE 14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU8r9N3UUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenglulu@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_STOCKGEN, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_load_tls): Load all types of tls symbols through one function. (loongarch_got_load_tls_gd): Delete. (loongarch_got_load_tls_ld): Delete. (loongarch_got_load_tls_ie): Delete. (loongarch_got_load_tls_le): Delete. (loongarch_call_tls_get_addr): Modify the called function name. (loongarch_legitimize_tls_address): Likewise. * config/loongarch/loongarch.md (@got_load_tls_gd): Delete. (@load_tls): New template. (@got_load_tls_ld): Delete. (@got_load_tls_le): Delete. (@got_load_tls_ie): Delete. --- gcc/config/loongarch/loongarch.cc | 47 +++++------------------- gcc/config/loongarch/loongarch.md | 59 ++++++++++++------------------- 2 files changed, 30 insertions(+), 76 deletions(-) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index b494040d165..7b4edf1c1fd 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -2736,36 +2736,12 @@ loongarch_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) /* The __tls_get_attr symbol. */ static GTY (()) rtx loongarch_tls_symbol; -/* Load an entry from the GOT for a TLS GD access. */ +/* Load an entry for a TLS access. */ static rtx -loongarch_got_load_tls_gd (rtx dest, rtx sym) +loongarch_load_tls (rtx dest, rtx sym) { - return gen_got_load_tls_gd (Pmode, dest, sym); -} - -/* Load an entry from the GOT for a TLS LD access. */ - -static rtx -loongarch_got_load_tls_ld (rtx dest, rtx sym) -{ - return gen_got_load_tls_ld (Pmode, dest, sym); -} - -/* Load an entry from the GOT for a TLS IE access. */ - -static rtx -loongarch_got_load_tls_ie (rtx dest, rtx sym) -{ - return gen_got_load_tls_ie (Pmode, dest, sym); -} - -/* Add in the thread pointer for a TLS LE access. */ - -static rtx -loongarch_got_load_tls_le (rtx dest, rtx sym) -{ - return gen_got_load_tls_le (Pmode, dest, sym); + return gen_load_tls (Pmode, dest, sym); } /* Return an instruction sequence that calls __tls_get_addr. SYM is @@ -2809,14 +2785,7 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0) emit_insn (gen_tls_low (Pmode, a0, high, loc)); } else - { - if (type == SYMBOL_TLSLDM) - emit_insn (loongarch_got_load_tls_ld (a0, loc)); - else if (type == SYMBOL_TLSGD) - emit_insn (loongarch_got_load_tls_gd (a0, loc)); - else - gcc_unreachable (); - } + emit_insn (loongarch_load_tls (a0, loc)); if (flag_plt) { @@ -2953,10 +2922,10 @@ loongarch_legitimize_tls_address (rtx loc) /* la.tls.ie; tp-relative add. */ tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); tmp1 = gen_reg_rtx (Pmode); + tmp2 = loongarch_unspec_address (loc, SYMBOL_TLS_IE); dest = gen_reg_rtx (Pmode); if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE) { - tmp2 = loongarch_unspec_address (loc, SYMBOL_TLS_IE); tmp3 = gen_reg_rtx (Pmode); rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2)); high = loongarch_force_temporary (tmp3, high); @@ -2979,7 +2948,7 @@ loongarch_legitimize_tls_address (rtx loc) emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2)); } else - emit_insn (loongarch_got_load_tls_ie (tmp1, loc)); + emit_insn (loongarch_load_tls (tmp1, tmp2)); emit_insn (gen_add3_insn (dest, tmp1, tp)); } break; @@ -3011,11 +2980,11 @@ loongarch_legitimize_tls_address (rtx loc) tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); tmp1 = gen_reg_rtx (Pmode); + tmp2 = loongarch_unspec_address (loc, SYMBOL_TLS_LE); dest = gen_reg_rtx (Pmode); if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE) { - tmp2 = loongarch_unspec_address (loc, SYMBOL_TLS_LE); tmp3 = gen_reg_rtx (Pmode); rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2)); high = loongarch_force_temporary (tmp3, high); @@ -3043,7 +3012,7 @@ loongarch_legitimize_tls_address (rtx loc) } } else - emit_insn (loongarch_got_load_tls_le (tmp1, loc)); + emit_insn (loongarch_load_tls (tmp1, tmp2)); emit_insn (gen_add3_insn (dest, tmp1, tp)); } break; diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index dda3cdf8be5..231c6568c85 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -51,10 +51,7 @@ (define_c_enum "unspec" [ UNSPEC_BITREV_8B ;; TLS - UNSPEC_TLS_GD - UNSPEC_TLS_LD - UNSPEC_TLS_LE - UNSPEC_TLS_IE + UNSPEC_TLS ;; Stack tie UNSPEC_TIE @@ -2701,45 +2698,33 @@ (define_insn "store_word" ;; Thread-Local Storage -(define_insn "@got_load_tls_gd" +(define_insn "@load_tls" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(match_operand:P 1 "symbolic_operand" "")] - UNSPEC_TLS_GD))] + UNSPEC_TLS))] "" - "la.tls.gd\t%0,%1" - [(set_attr "got" "load") - (set_attr "mode" "")]) - -(define_insn "@got_load_tls_ld" - [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P - [(match_operand:P 1 "symbolic_operand" "")] - UNSPEC_TLS_LD))] - "" - "la.tls.ld\t%0,%1" - [(set_attr "got" "load") - (set_attr "mode" "")]) +{ + enum loongarch_symbol_type symbol_type; + gcc_assert (loongarch_symbolic_constant_p (operands[1], &symbol_type)); -(define_insn "@got_load_tls_le" - [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P - [(match_operand:P 1 "symbolic_operand" "")] - UNSPEC_TLS_LE))] - "" - "la.tls.le\t%0,%1" - [(set_attr "got" "load") - (set_attr "mode" "")]) + switch (symbol_type) + { + case SYMBOL_TLS_LE: + return "la.tls.le\t%0,%1"; + case SYMBOL_TLS_IE: + return "la.tls.ie\t%0,%1"; + case SYMBOL_TLSLDM: + return "la.tls.ld\t%0,%1"; + case SYMBOL_TLSGD: + return "la.tls.gd\t%0,%1"; -(define_insn "@got_load_tls_ie" - [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P - [(match_operand:P 1 "symbolic_operand" "")] - UNSPEC_TLS_IE))] - "" - "la.tls.ie\t%0,%1" - [(set_attr "got" "load") - (set_attr "mode" "")]) + default: + gcc_unreachable (); + } +} + [(set_attr "mode" "") + (set_attr "insn_count" "2")]) ;; Move operand 1 to the high word of operand 0 using movgr2frh.w, preserving the ;; value in the low word. From patchwork Mon Jan 29 08:21:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 84850 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5DCC2385843E for ; Mon, 29 Jan 2024 08:23:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id D1F3B3858413 for ; Mon, 29 Jan 2024 08:22:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D1F3B3858413 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D1F3B3858413 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706516557; cv=none; b=t3W2X3N6pZ5eT/FrGoJXVaGi1yU/AdYaQYfLv6BwzYI2CT5L1b9mpU0WeT/aqp4dQB2WFMvlOSKWEtVzMCHvJQNmtUY8HlTORGUqz0AvW66mfNQT4GSIDJTn0dIPFEkrbyOTulOBCYLpnAGuN1A/HR06e3mT/1DBZ40MMFVttXg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706516557; c=relaxed/simple; bh=sA4j8Q05UipV/7Utl6Jtv9eotn5FZGoxkg0fw344Fyc=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=muCwVS848Ncajk1jcO5rhHiIeexN182/ey4YQeks9ciz8jidt3dmXbFBZtIcuok8tqbzG2FE54G9UKEs05oavuMxG7c+OBgJOnEaAZS/iLRcWiJrtj45+2hAc4RoupoWMk+7IuohwyUfh4wsXcB5SMr5CfcblzZ73mEs+rrEM5I= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUMuO-00014D-Rx for gcc-patches@gcc.gnu.org; Mon, 29 Jan 2024 03:22:27 -0500 Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8DxJ+g8YLdlkLEHAA--.4525S3; Mon, 29 Jan 2024 16:22:20 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxnhMrYLdlKxklAA--.26775S4; Mon, 29 Jan 2024 16:22:19 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, Lulu Cheng Subject: [PATCH v5 2/5] LoongArch: Add the macro implementation of mcmodel=extreme. Date: Mon, 29 Jan 2024 16:21:58 +0800 Message-Id: <20240129082201.26087-3-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240129082201.26087-1-chenglulu@loongson.cn> References: <20240129082201.26087-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxnhMrYLdlKxklAA--.26775S4 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj9fXoW3Kw48Kr45Cr1kZr4DZFW3XFc_yoW8WFy5Wo WrAFWUJw48Gr12krs8KrsxXry0yF1vyrWxAa9Fvw1rCan7Ar15Ary3Gw45Z3sxXr9rXry5 u347WFnrJ3y7Xrs8l-sFpf9Il3svdjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUYb7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26r1I6r4UM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r1j6r4UM28EF7xvwVC2z280aVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv 67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07jOb18UUUUU= Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenglulu@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, KAM_STOCKGEN, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog: * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p): Add function declaration. * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p): For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend" is not allowed (loongarch_load_tls): Added macro support in extreme mode. (loongarch_call_tls_get_addr): Likewise. (loongarch_legitimize_tls_address): Likewise. (loongarch_force_address): Likewise. (loongarch_legitimize_move): Likewise. (loongarch_output_mi_thunk): Likewise. (loongarch_option_override_internal): Remove the code that detects explicit relocs status. (loongarch_handle_model_attribute): Likewise. * config/loongarch/loongarch.md (movdi_symbolic_off64): New template. * config/loongarch/predicates.md (symbolic_off64_operand): New predicate. (symbolic_off64_or_reg_operand): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/attr-model-5.c: New test. * gcc.target/loongarch/func-call-extreme-5.c: New test. * gcc.target/loongarch/func-call-extreme-6.c: New test. * gcc.target/loongarch/tls-extreme-macro.c: New test. --- gcc/config/loongarch/loongarch-protos.h | 1 + gcc/config/loongarch/loongarch.cc | 110 +++++++++++------- gcc/config/loongarch/loongarch.md | 48 +++++++- gcc/config/loongarch/predicates.md | 12 ++ .../gcc.target/loongarch/attr-model-5.c | 8 ++ .../loongarch/func-call-extreme-5.c | 7 ++ .../loongarch/func-call-extreme-6.c | 7 ++ .../gcc.target/loongarch/tls-extreme-macro.c | 35 ++++++ 8 files changed, 184 insertions(+), 44 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/attr-model-5.c create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-extreme-5.c create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-extreme-6.c create mode 100644 gcc/testsuite/gcc.target/loongarch/tls-extreme-macro.c diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h index 9ffc92afead..1fdfda9af01 100644 --- a/gcc/config/loongarch/loongarch-protos.h +++ b/gcc/config/loongarch/loongarch-protos.h @@ -222,4 +222,5 @@ extern rtx loongarch_build_signbit_mask (machine_mode, bool, bool); extern void loongarch_emit_swrsqrtsf (rtx, rtx, machine_mode, bool); extern void loongarch_emit_swdivsf (rtx, rtx, rtx, machine_mode); extern bool loongarch_explicit_relocs_p (enum loongarch_symbol_type); +extern bool loongarch_symbol_extreme_p (enum loongarch_symbol_type); #endif /* ! GCC_LOONGARCH_PROTOS_H */ diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 7b4edf1c1fd..a0c14f908a8 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -1935,8 +1935,13 @@ loongarch_symbolic_constant_p (rtx x, enum loongarch_symbol_type *symbol_type) relocations. */ switch (*symbol_type) { - case SYMBOL_PCREL: case SYMBOL_PCREL64: + /* When the code model is extreme, the non-zero offset situation + has not been handled well, so it is disabled here now. */ + if (!loongarch_explicit_relocs_p (SYMBOL_PCREL64)) + return false; + /* fall through */ + case SYMBOL_PCREL: /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */ return sext_hwi (INTVAL (offset), 32) == INTVAL (offset); @@ -2739,9 +2744,15 @@ static GTY (()) rtx loongarch_tls_symbol; /* Load an entry for a TLS access. */ static rtx -loongarch_load_tls (rtx dest, rtx sym) +loongarch_load_tls (rtx dest, rtx sym, enum loongarch_symbol_type type) { - return gen_load_tls (Pmode, dest, sym); + /* TLS LE gets a 32 or 64 bit offset here, so one register can do it. */ + if (type == SYMBOL_TLS_LE) + return gen_load_tls (Pmode, dest, sym); + + return loongarch_symbol_extreme_p (type) + ? gen_movdi_symbolic_off64 (dest, sym, gen_reg_rtx (DImode)) + : gen_load_tls (Pmode, dest, sym); } /* Return an instruction sequence that calls __tls_get_addr. SYM is @@ -2773,8 +2784,6 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0) if (TARGET_CMODEL_EXTREME) { - gcc_assert (TARGET_EXPLICIT_RELOCS); - rtx tmp1 = gen_reg_rtx (Pmode); emit_insn (gen_tls_low (Pmode, tmp1, gen_rtx_REG (Pmode, 0), loc)); emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loc)); @@ -2785,7 +2794,7 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0) emit_insn (gen_tls_low (Pmode, a0, high, loc)); } else - emit_insn (loongarch_load_tls (a0, loc)); + emit_insn (loongarch_load_tls (a0, loc, type)); if (flag_plt) { @@ -2852,22 +2861,28 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0) case CMODEL_EXTREME: { - gcc_assert (TARGET_EXPLICIT_RELOCS); - - rtx tmp1 = gen_reg_rtx (Pmode); - rtx high = gen_reg_rtx (Pmode); - - loongarch_emit_move (high, - gen_rtx_HIGH (Pmode, loongarch_tls_symbol)); - loongarch_emit_move (tmp1, gen_rtx_LO_SUM (Pmode, - gen_rtx_REG (Pmode, 0), - loongarch_tls_symbol)); - emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loongarch_tls_symbol)); - emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loongarch_tls_symbol)); - loongarch_emit_move (dest, - gen_rtx_MEM (Pmode, - gen_rtx_PLUS (Pmode, - high, tmp1))); + if (loongarch_explicit_relocs_p (SYMBOL_GOT_DISP)) + { + rtx tmp1 = gen_reg_rtx (Pmode); + rtx high = gen_reg_rtx (Pmode); + + loongarch_emit_move (high, + gen_rtx_HIGH (Pmode, + loongarch_tls_symbol)); + loongarch_emit_move (tmp1, + gen_rtx_LO_SUM (Pmode, + gen_rtx_REG (Pmode, 0), + loongarch_tls_symbol)); + emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loongarch_tls_symbol)); + emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loongarch_tls_symbol)); + loongarch_emit_move (dest, + gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, + high, tmp1))); + } + else + emit_insn (gen_movdi_symbolic_off64 (dest, loongarch_tls_symbol, + gen_reg_rtx (DImode))); } break; @@ -2932,8 +2947,6 @@ loongarch_legitimize_tls_address (rtx loc) if (TARGET_CMODEL_EXTREME) { - gcc_assert (TARGET_EXPLICIT_RELOCS); - rtx tmp3 = gen_reg_rtx (Pmode); emit_insn (gen_tls_low (Pmode, tmp3, gen_rtx_REG (Pmode, 0), tmp2)); @@ -2948,7 +2961,7 @@ loongarch_legitimize_tls_address (rtx loc) emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2)); } else - emit_insn (loongarch_load_tls (tmp1, tmp2)); + emit_insn (loongarch_load_tls (tmp1, tmp2, SYMBOL_TLS_IE)); emit_insn (gen_add3_insn (dest, tmp1, tp)); } break; @@ -3005,14 +3018,12 @@ loongarch_legitimize_tls_address (rtx loc) if (TARGET_CMODEL_EXTREME) { - gcc_assert (TARGET_EXPLICIT_RELOCS); - emit_insn (gen_lui_h_lo20 (tmp1, tmp1, tmp2)); emit_insn (gen_lui_h_hi12 (tmp1, tmp1, tmp2)); } } else - emit_insn (loongarch_load_tls (tmp1, tmp2)); + emit_insn (loongarch_load_tls (tmp1, tmp2, SYMBOL_TLS_LE)); emit_insn (gen_add3_insn (dest, tmp1, tp)); } break; @@ -3085,7 +3096,7 @@ loongarch_force_address (rtx x, machine_mode mode) return x; } -static bool +bool loongarch_symbol_extreme_p (enum loongarch_symbol_type type) { switch (type) @@ -3363,6 +3374,21 @@ loongarch_legitimize_move (machine_mode mode, rtx dest, rtx src) return true; } + /* Obtain the address of the symbol through the macro instruction + of two registers. */ + enum loongarch_symbol_type symbol_type; + if (TARGET_64BIT && register_operand (dest, mode) + && loongarch_symbolic_constant_p (src, &symbol_type) + && loongarch_symbol_extreme_p (symbol_type)) + { + gcc_assert (can_create_pseudo_p ()); + rtx tmp_reg = gen_reg_rtx (DImode); + emit_insn (gen_movdi_symbolic_off64 (dest, src, tmp_reg)); + set_unique_reg_note (get_last_insn (), REG_UNUSED, tmp_reg); + set_unique_reg_note (get_last_insn (), REG_EQUAL, src); + return true; + } + return false; } @@ -7419,12 +7445,22 @@ loongarch_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, allowed, otherwise load the address into a register first. */ if (use_sibcall_p) { - insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx)); + if (TARGET_CMODEL_EXTREME) + { + emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2)); + insn = emit_call_insn (gen_sibcall_internal (temp1, const0_rtx)); + } + else + insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx)); SIBLING_CALL_P (insn) = 1; } else { - loongarch_emit_move (temp1, fnaddr); + if (TARGET_CMODEL_EXTREME) + emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2)); + else + loongarch_emit_move (temp1, fnaddr); + emit_jump_insn (gen_indirect_jump (temp1)); } @@ -7529,10 +7565,6 @@ loongarch_option_override_internal (struct gcc_options *opts, switch (la_target.cmodel) { case CMODEL_EXTREME: - if (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE) - error ("code model %qs is not compatible with %s", - "extreme", "-mexplicit-relocs=none"); - if (opts->x_flag_plt) { if (global_options_set.x_flag_plt) @@ -7950,14 +7982,6 @@ loongarch_handle_model_attribute (tree *node, tree name, tree arg, int, *no_add_attrs = true; return NULL_TREE; } - if (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE) - { - error_at (DECL_SOURCE_LOCATION (decl), - "%qE attribute is not compatible with %s", name, - "-mexplicit-relocs=none"); - *no_add_attrs = true; - return NULL_TREE; - } arg = TREE_VALUE (arg); if (TREE_CODE (arg) != STRING_CST) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 231c6568c85..5ec1d5a46d5 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -82,6 +82,8 @@ (define_c_enum "unspec" [ UNSPEC_SIBCALL_VALUE_MULTIPLE_INTERNAL_1 UNSPEC_CALL_VALUE_MULTIPLE_INTERNAL_1 + + UNSPEC_LOAD_SYMBOL_OFFSET64 ]) (define_c_enum "unspecv" [ @@ -2182,6 +2184,46 @@ (define_insn_and_split "*movdi_64bit" [(set_attr "move_type" "move,const,load,store,mgtf,fpload,mftg,fpstore") (set_attr "mode" "DI")]) +;; Use two registers to get the global symbol address from the got table. +;; la.global rd, rt, sym + +(define_insn_and_split "movdi_symbolic_off64" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (match_operand:DI 1 "symbolic_off64_or_reg_operand" "Yd,r")) + (unspec:DI [(const_int 0)] + UNSPEC_LOAD_SYMBOL_OFFSET64) + (clobber (match_operand:DI 2 "register_operand" "=&r,r"))] + "TARGET_64BIT && TARGET_CMODEL_EXTREME" +{ + if (which_alternative == 1) + return "#"; + + enum loongarch_symbol_type symbol_type; + gcc_assert (loongarch_symbolic_constant_p (operands[1], &symbol_type)); + + switch (symbol_type) + { + case SYMBOL_PCREL64: + return "la.local\t%0,%2,%1"; + case SYMBOL_GOT_DISP: + return "la.global\t%0,%2,%1"; + case SYMBOL_TLS_IE: + return "la.tls.ie\t%0,%2,%1"; + case SYMBOL_TLSGD: + return "la.tls.gd\t%0,%2,%1"; + case SYMBOL_TLSLDM: + return "la.tls.ld\t%0,%2,%1"; + + default: + gcc_unreachable (); + } +} + "&& REG_P (operands[1]) && find_reg_note (insn, REG_UNUSED, operands[2]) != 0" + [(set (match_dup 0) (match_dup 1))] + "" + [(set_attr "mode" "DI") + (set_attr "insn_count" "5")]) + ;; 32-bit Integer moves (define_expand "movsi" @@ -2724,7 +2766,11 @@ (define_insn "@load_tls" } } [(set_attr "mode" "") - (set_attr "insn_count" "2")]) + (set (attr "insn_count") + (if_then_else + (match_test "TARGET_CMODEL_EXTREME") + (const_int 4) + (const_int 2)))]) ;; Move operand 1 to the high word of operand 0 using movgr2frh.w, preserving the ;; value in the low word. diff --git a/gcc/config/loongarch/predicates.md b/gcc/config/loongarch/predicates.md index 01aad8dc631..eba7f246c84 100644 --- a/gcc/config/loongarch/predicates.md +++ b/gcc/config/loongarch/predicates.md @@ -576,6 +576,18 @@ (define_predicate "mem_simple_ldst_operand" || symbolic_pcrel_offset_operand (op, Pmode)); }) +(define_predicate "symbolic_off64_operand" + (match_code "const,symbol_ref,label_ref") +{ + enum loongarch_symbol_type type; + return loongarch_symbolic_constant_p (op, &type) + && loongarch_symbol_extreme_p (type); +}) + +(define_predicate "symbolic_off64_or_reg_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "symbolic_off64_operand"))) + (define_predicate "equality_operator" (match_code "eq,ne")) diff --git a/gcc/testsuite/gcc.target/loongarch/attr-model-5.c b/gcc/testsuite/gcc.target/loongarch/attr-model-5.c new file mode 100644 index 00000000000..5f2c3ec9e44 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/attr-model-5.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-mexplicit-relocs=none -mcmodel=extreme -O2 -fno-pic" } */ +/* { dg-final { scan-assembler "la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,x" } } */ +/* { dg-final { scan-assembler "la.local\t\\\$r\[0-9\]+,y" } } */ +/* { dg-final { scan-assembler "la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,counter" } } */ + +#define ATTR_MODEL_TEST +#include "attr-model-test.c" diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-5.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-5.c new file mode 100644 index 00000000000..b1bd9d236ea --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-5.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs=none -mcmodel=extreme" } */ +/* { dg-final { scan-assembler "test:.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,g" } } */ +/* { dg-final { scan-assembler "test1:.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,f" } } */ +/* { dg-final { scan-assembler "test2:.*la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,l" } } */ + +#include "func-call-extreme-1.c" diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-6.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-6.c new file mode 100644 index 00000000000..6e6ad5c9f5c --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-6.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs=none -mcmodel=extreme" } */ +/* { dg-final { scan-assembler "test:.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,g" } } */ +/* { dg-final { scan-assembler "test1:.*la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,f" } } */ +/* { dg-final { scan-assembler "test2:.*la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,l" } } */ + +#include "func-call-extreme-1.c" diff --git a/gcc/testsuite/gcc.target/loongarch/tls-extreme-macro.c b/gcc/testsuite/gcc.target/loongarch/tls-extreme-macro.c new file mode 100644 index 00000000000..4341f82129c --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/tls-extreme-macro.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=none" } */ +/* { dg-final { scan-assembler "test_le:.*la.tls.le\t\\\$r\[0-9\]+,\\\.L" { target tls_native } } } */ +/* { dg-final { scan-assembler "test_ie:.*la.tls.ie\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,\\\.L" { target tls_native } } } */ +/* { dg-final { scan-assembler "test_ld:.*la.tls.ld\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,\\\.L.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,__tls_get_addr" { target tls_native } } } */ +/* { dg-final { scan-assembler "test_le:.*la.tls.gd\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,\\\.L.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,__tls_get_addr" { target tls_native } } } */ + +__thread int c __attribute__ ((tls_model ("local-exec"))); +__thread int d __attribute__ ((tls_model ("initial-exec"))); +__thread int e __attribute__ ((tls_model ("local-dynamic"))); +__thread int f __attribute__ ((tls_model ("global-dynamic"))); + +int +test_le (void) +{ + return c; +} + +int +test_ie (void) +{ + return d; +} + +int +test_ld (void) +{ + return e; +} + +int +test_gd (void) +{ + return f; +} From patchwork Mon Jan 29 08:21:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 84851 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C5BD7385829D for ; Mon, 29 Jan 2024 08:25:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 114783858402 for ; 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server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8Cxbes_YLdllbEHAA--.24262S3; Mon, 29 Jan 2024 16:22:23 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxnhMrYLdlKxklAA--.26775S5; Mon, 29 Jan 2024 16:22:20 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, Lulu Cheng Subject: [PATCH v5 3/5] LoongArch: Enable explicit reloc for extreme TLS GD/LD with -mexplicit-relocs=auto. Date: Mon, 29 Jan 2024 16:21:59 +0800 Message-Id: <20240129082201.26087-4-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240129082201.26087-1-chenglulu@loongson.cn> References: <20240129082201.26087-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxnhMrYLdlKxklAA--.26775S5 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW3Gw1kCrW5uFWxWrWfZrWkAFc_yoW7Wr1kpa y7Zw17Kr48X397K3WDX3WfXF1kXFsFgFW2gasIqryfuF47J34SqF18tF1YqFy7J3W5K3y7 WF1Fka4rX3W5X3cCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUk2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r126r13M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5McIj6I8E87Iv 67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxUco7KUUUUU X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, KAM_STOCKGEN, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Binutils does not support relaxation using four instructions to obtain symbol addresses gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p): When the code model of the symbol is extreme and -mexplicit-relocs=auto, the macro instruction loading symbol address is not applicable. (loongarch_call_tls_get_addr): Adjust code. (loongarch_legitimize_tls_address): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c: New test. * gcc.target/loongarch/explicit-relocs-medium-auto-tls-ld-gd.c: New test. --- gcc/config/loongarch/loongarch.cc | 19 +++++++++---------- .../explicit-relocs-extreme-auto-tls-ld-gd.c | 5 +++++ .../explicit-relocs-medium-auto-tls-ld-gd.c | 5 +++++ 3 files changed, 19 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-auto-tls-ld-gd.c diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index a0c14f908a8..684ae81870c 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -1971,6 +1971,10 @@ loongarch_explicit_relocs_p (enum loongarch_symbol_type type) if (la_opt_explicit_relocs != EXPLICIT_RELOCS_AUTO) return la_opt_explicit_relocs == EXPLICIT_RELOCS_ALWAYS; + /* The linker don't know how to relax accesses in extreme code model. */ + if (loongarch_symbol_extreme_p (type)) + return true; + switch (type) { case SYMBOL_TLS_IE: @@ -1982,11 +1986,6 @@ loongarch_explicit_relocs_p (enum loongarch_symbol_type type) does not relax 64-bit pc-relative accesses as at now. */ return true; case SYMBOL_GOT_DISP: - /* The linker don't know how to relax GOT accesses in extreme - code model. */ - if (TARGET_CMODEL_EXTREME) - return true; - /* If we are performing LTO for a final link, and we have the linker plugin so we know the resolution of the symbols, then all GOT references are binding to external symbols or @@ -2776,7 +2775,7 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0) start_sequence (); - if (la_opt_explicit_relocs == EXPLICIT_RELOCS_ALWAYS) + if (loongarch_explicit_relocs_p (type)) { /* Split tls symbol to high and low. */ rtx high = gen_rtx_HIGH (Pmode, copy_rtx (loc)); @@ -2809,7 +2808,7 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0) case CMODEL_MEDIUM: { rtx reg = gen_reg_rtx (Pmode); - if (TARGET_EXPLICIT_RELOCS) + if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE) { emit_insn (gen_pcalau12i (Pmode, reg, loongarch_tls_symbol)); rtx call = gen_call_value_internal_1 (Pmode, v0, reg, @@ -2845,7 +2844,7 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0) case CMODEL_NORMAL: case CMODEL_MEDIUM: { - if (TARGET_EXPLICIT_RELOCS) + if (loongarch_explicit_relocs_p (SYMBOL_GOT_DISP)) { rtx high = gen_reg_rtx (Pmode); loongarch_emit_move (high, @@ -2939,7 +2938,7 @@ loongarch_legitimize_tls_address (rtx loc) tmp1 = gen_reg_rtx (Pmode); tmp2 = loongarch_unspec_address (loc, SYMBOL_TLS_IE); dest = gen_reg_rtx (Pmode); - if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE) + if (loongarch_explicit_relocs_p (SYMBOL_TLS_IE)) { tmp3 = gen_reg_rtx (Pmode); rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2)); @@ -2996,7 +2995,7 @@ loongarch_legitimize_tls_address (rtx loc) tmp2 = loongarch_unspec_address (loc, SYMBOL_TLS_LE); dest = gen_reg_rtx (Pmode); - if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE) + if (loongarch_explicit_relocs_p (SYMBOL_TLS_LE)) { tmp3 = gen_reg_rtx (Pmode); rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2)); diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c new file mode 100644 index 00000000000..35bd4570a9e --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fPIC -mexplicit-relocs=auto -mcmodel=extreme -fno-plt" } */ +/* { dg-final { scan-assembler-not "la.tls.\[lg\]d" { target tls_native } } } */ + +#include "./explicit-relocs-auto-tls-ld-gd.c" diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-auto-tls-ld-gd.c b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-auto-tls-ld-gd.c new file mode 100644 index 00000000000..47bffae8af7 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-auto-tls-ld-gd.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fPIC -mexplicit-relocs=auto -mcmodel=medium -fplt" } */ +/* { dg-final { scan-assembler-not "la.global" { target tls_native } } } */ + +#include "./explicit-relocs-auto-tls-ld-gd.c" From patchwork Mon Jan 29 08:22:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 84849 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 69AF23858437 for ; Mon, 29 Jan 2024 08:23:43 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 5298D3858D32 for ; Mon, 29 Jan 2024 08:22:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5298D3858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5298D3858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; 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Date: Mon, 29 Jan 2024 16:22:00 +0800 Message-Id: <20240129082201.26087-5-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240129082201.26087-1-chenglulu@loongson.cn> References: <20240129082201.26087-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxnhMrYLdlKxklAA--.26775S6 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW7WFWxCFyxZFy7WF4kXF4DZFc_yoW5JryDp3 yxuw13Kr48ZrZF9wn7Ja4fKr4kGr42gFW29ayavryfCr47JryfXF1kKF1fXF1UGw4UtrWa qr4rC3WYqF1UX3cCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUk2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r126r13M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5McIj6I8E87Iv 67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxUco7KUUUUU X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr): Add support for call36. gcc/testsuite/ChangeLog: * gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c: New test. --- gcc/config/loongarch/loongarch.cc | 22 ++++++++++++++----- ...icit-relocs-medium-call36-auto-tls-ld-gd.c | 5 +++++ 2 files changed, 21 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 684ae81870c..564de9c2642 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -2807,17 +2807,27 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0) case CMODEL_MEDIUM: { - rtx reg = gen_reg_rtx (Pmode); if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE) { - emit_insn (gen_pcalau12i (Pmode, reg, loongarch_tls_symbol)); - rtx call = gen_call_value_internal_1 (Pmode, v0, reg, - loongarch_tls_symbol, - const0_rtx); - insn = emit_call_insn (call); + rtx call; + + if (HAVE_AS_SUPPORT_CALL36) + call = gen_call_value_internal (v0, loongarch_tls_symbol, + const0_rtx); + else + { + rtx reg = gen_reg_rtx (Pmode); + emit_insn (gen_pcalau12i (Pmode, reg, + loongarch_tls_symbol)); + call = gen_call_value_internal_1 (Pmode, v0, reg, + loongarch_tls_symbol, + const0_rtx); + } + insn = emit_call_insn (call); } else { + rtx reg = gen_reg_rtx (Pmode); emit_move_insn (reg, loongarch_tls_symbol); insn = emit_call_insn (gen_call_value_internal (v0, reg, diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c new file mode 100644 index 00000000000..d1a4820834c --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fPIC -mexplicit-relocs=auto -mcmodel=medium -fplt" } */ +/* { dg-final { scan-assembler "pcaddu18i\t\\\$r1,%call36\\\(__tls_get_addr\\\)" { target { tls_native && loongarch_call36_support } } } } */ + +#include "./explicit-relocs-auto-tls-ld-gd.c" From patchwork Mon Jan 29 08:22:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 84852 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C4D84385829A for ; Mon, 29 Jan 2024 08:25:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id A7A94385840B for ; Mon, 29 Jan 2024 08:22:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A7A94385840B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A7A94385840B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706516557; cv=none; b=cG49bo45IB3LwG5JNl+eJgMKkI4ETprgeTl8np1nbGjE8GdVh0lpwSPxd3Hxr8TD4dnaB+i4L/Os7KCc1WPya5ihNplabYpK5As4cpt6y8kR3mZTeA1HH7lArDIfNgVU4r4PgpDFNumgIsIER89FpEg1zSJlPD742AIcN0rrgLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706516557; c=relaxed/simple; bh=rmMLezwVy5Wb8TrCKKSnen/dZIcMNQ2E7nQm4Ppm4Bs=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Z/r4cGokm2Aeb6P9zLxr6/WwqYcfTcQc5K/fvC2C3XhFwf3fXgKKiUw9Dg0m/Gn+ukFLo49CqGJFZTUB59xqtVULhvg0uqYZeCoiPipVPnvQjT+D0If1fzy99UxhTY7BZwnFzc1NFHjGifTiPwjBQGWmGQyC4KXca7TjJdQXX9U= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8AxPOlBYLdlm7EHAA--.14009S3; Mon, 29 Jan 2024 16:22:25 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxnhMrYLdlKxklAA--.26775S7; Mon, 29 Jan 2024 16:22:23 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn Subject: [PATCH v5 5/5] LoongArch: Don't split the instructions containing relocs for extreme code model. Date: Mon, 29 Jan 2024 16:22:01 +0800 Message-Id: <20240129082201.26087-6-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240129082201.26087-1-chenglulu@loongson.cn> References: <20240129082201.26087-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxnhMrYLdlKxklAA--.26775S7 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj9fXoWftr4xGw1ktrW3Zw1xGF17Jwc_yoW8uryrAo Z3CF4UJw48Wr1SkwsrKrnxJr10yFyIyw4rZa9Fvr1rGF40yryYv3s3KanYv34fZrsrJry5 uFW7WF9rC3y7Xr98l-sFpf9Il3svdjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUY87kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI 0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUtVWrXwAv7VC2z280 aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r4j6ryUMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aV CY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8l38UUUUUU== X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, KAM_STOCKGEN, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org From: Xi Ruoyao The ABI mandates the pcalau12i/addi.d/lu32i.d/lu52i.d instructions for addressing a symbol to be adjacent. So model them as "one large instruction", i.e. define_insn, with two output registers. The real address is the sum of these two registers. The advantage of this approach is the RTL passes can still use ldx/stx instructions to skip an addi.d instruction. gcc/ChangeLog: * config/loongarch/loongarch.md (unspec): Add UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2. (la_pcrel64_two_parts): New define_insn. * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a typo in the comment. (loongarch_call_tls_get_addr): If -mcmodel=extreme -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL note to allow CSE addressing __tls_get_addr. (loongarch_legitimize_tls_address): If -mcmodel=extreme -mexplicit-relocs={always,auto}, address TLS IE symbols with la_pcrel64_two_parts. (loongarch_split_symbol): If -mcmodel=extreme -mexplicit-relocs={always,auto}, address symbols with la_pcrel64_two_parts. (loongarch_output_mi_thunk): Clean up unreachable code. If -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI thunks with la_pcrel64_two_parts. gcc/testsuite/ChangeLog: * gcc.target/loongarch/func-call-extreme-1.c (dg-options): Use -O2 instead of -O0 to ensure the pcalau12i/addi/lu32i/lu52i instruction sequences are not reordered by the compiler. (NOIPA): Disallow interprocedural optimizations. * gcc.target/loongarch/func-call-extreme-2.c: Remove the content duplicated from func-call-extreme-1.c, include it instead. (dg-options): Likewise. * gcc.target/loongarch/func-call-extreme-3.c (dg-options): Likewise. * gcc.target/loongarch/func-call-extreme-4.c (dg-options): Likewise. * gcc.target/loongarch/cmodel-extreme-1.c: New test. * gcc.target/loongarch/cmodel-extreme-2.c: New test. * g++.target/loongarch/cmodel-extreme-mi-thunk-1.C: New test. * g++.target/loongarch/cmodel-extreme-mi-thunk-2.C: New test. * g++.target/loongarch/cmodel-extreme-mi-thunk-3.C: New test. --- gcc/config/loongarch/loongarch.cc | 131 ++++++++++-------- gcc/config/loongarch/loongarch.md | 20 +++ .../loongarch/cmodel-extreme-mi-thunk-1.C | 11 ++ .../loongarch/cmodel-extreme-mi-thunk-2.C | 6 + .../loongarch/cmodel-extreme-mi-thunk-3.C | 6 + .../gcc.target/loongarch/cmodel-extreme-1.c | 18 +++ .../gcc.target/loongarch/cmodel-extreme-2.c | 7 + .../loongarch/func-call-extreme-1.c | 14 +- .../loongarch/func-call-extreme-2.c | 29 +--- .../loongarch/func-call-extreme-3.c | 2 +- .../loongarch/func-call-extreme-4.c | 2 +- 11 files changed, 154 insertions(+), 92 deletions(-) create mode 100644 gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-1.C create mode 100644 gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-2.C create mode 100644 gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-3.C create mode 100644 gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 564de9c2642..89dd33553da 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -2737,7 +2737,7 @@ loongarch_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) return plus_constant (Pmode, reg, offset); } -/* The __tls_get_attr symbol. */ +/* The __tls_get_addr symbol. */ static GTY (()) rtx loongarch_tls_symbol; /* Load an entry for a TLS access. */ @@ -2777,20 +2777,22 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0) if (loongarch_explicit_relocs_p (type)) { - /* Split tls symbol to high and low. */ - rtx high = gen_rtx_HIGH (Pmode, copy_rtx (loc)); - high = loongarch_force_temporary (tmp, high); - if (TARGET_CMODEL_EXTREME) { - rtx tmp1 = gen_reg_rtx (Pmode); - emit_insn (gen_tls_low (Pmode, tmp1, gen_rtx_REG (Pmode, 0), loc)); - emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loc)); - emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loc)); - emit_move_insn (a0, gen_rtx_PLUS (Pmode, high, tmp1)); + rtx part1 = gen_reg_rtx (Pmode); + rtx part2 = gen_reg_rtx (Pmode); + + emit_insn (gen_la_pcrel64_two_parts (part1, part2, loc)); + emit_move_insn (a0, gen_rtx_PLUS (Pmode, part1, part2)); } else - emit_insn (gen_tls_low (Pmode, a0, high, loc)); + { + /* Split tls symbol to high and low. */ + rtx high = gen_rtx_HIGH (Pmode, copy_rtx (loc)); + + high = loongarch_force_temporary (tmp, high); + emit_insn (gen_tls_low (Pmode, a0, high, loc)); + } } else emit_insn (loongarch_load_tls (a0, loc, type)); @@ -2872,22 +2874,28 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0) { if (loongarch_explicit_relocs_p (SYMBOL_GOT_DISP)) { - rtx tmp1 = gen_reg_rtx (Pmode); - rtx high = gen_reg_rtx (Pmode); + gcc_assert (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE); - loongarch_emit_move (high, - gen_rtx_HIGH (Pmode, - loongarch_tls_symbol)); - loongarch_emit_move (tmp1, - gen_rtx_LO_SUM (Pmode, - gen_rtx_REG (Pmode, 0), + rtx part1 = gen_reg_rtx (Pmode); + rtx part2 = gen_reg_rtx (Pmode); + + emit_insn (gen_la_pcrel64_two_parts (part1, part2, loongarch_tls_symbol)); - emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loongarch_tls_symbol)); - emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loongarch_tls_symbol)); - loongarch_emit_move (dest, - gen_rtx_MEM (Pmode, - gen_rtx_PLUS (Pmode, - high, tmp1))); + loongarch_emit_move ( + dest, + gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, + part1, + part2))); + + /* Put an REG_EQUAL note here to allow CSE (storing + part1 + part2, i.e. the address of tls_get_addr into + a saved register and use it for multiple TLS + accesses). */ + rtx sum = gen_rtx_UNSPEC ( + Pmode, gen_rtvec (1, loongarch_tls_symbol), + UNSPEC_ADDRESS_FIRST + + loongarch_classify_symbol (loongarch_tls_symbol)); + set_unique_reg_note (get_last_insn (), REG_EQUAL, sum); } else emit_insn (gen_movdi_symbolic_off64 (dest, loongarch_tls_symbol, @@ -2950,24 +2958,30 @@ loongarch_legitimize_tls_address (rtx loc) dest = gen_reg_rtx (Pmode); if (loongarch_explicit_relocs_p (SYMBOL_TLS_IE)) { - tmp3 = gen_reg_rtx (Pmode); - rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2)); - high = loongarch_force_temporary (tmp3, high); - if (TARGET_CMODEL_EXTREME) { - rtx tmp3 = gen_reg_rtx (Pmode); - emit_insn (gen_tls_low (Pmode, tmp3, - gen_rtx_REG (Pmode, 0), tmp2)); - emit_insn (gen_lui_h_lo20 (tmp3, tmp3, tmp2)); - emit_insn (gen_lui_h_hi12 (tmp3, tmp3, tmp2)); + gcc_assert (la_opt_explicit_relocs + != EXPLICIT_RELOCS_NONE); + + rtx part1 = gen_reg_rtx (Pmode); + rtx part2 = gen_reg_rtx (Pmode); + + emit_insn (gen_la_pcrel64_two_parts (part1, part2, + tmp2)); emit_move_insn (tmp1, gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, - high, tmp3))); + part1, + part2))); } else - emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2)); + { + tmp3 = gen_reg_rtx (Pmode); + rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2)); + + high = loongarch_force_temporary (tmp3, high); + emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2)); + } } else emit_insn (loongarch_load_tls (tmp1, tmp2, SYMBOL_TLS_IE)); @@ -3146,24 +3160,23 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out) || !loongarch_split_symbol_type (symbol_type)) return false; - rtx high, temp1 = NULL; + rtx high; if (temp == NULL) temp = gen_reg_rtx (Pmode); - /* Get the 12-31 bits of the address. */ - high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); - high = loongarch_force_temporary (temp, high); - if (loongarch_symbol_extreme_p (symbol_type) && can_create_pseudo_p ()) { gcc_assert (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE); - temp1 = gen_reg_rtx (Pmode); - emit_move_insn (temp1, gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 0), - addr)); - emit_insn (gen_lui_h_lo20 (temp1, temp1, addr)); - emit_insn (gen_lui_h_hi12 (temp1, temp1, addr)); + high = gen_reg_rtx (Pmode); + emit_insn (gen_la_pcrel64_two_parts (high, temp, addr)); + } + else + { + /* Get the 12-31 bits of the address. */ + high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); + high = loongarch_force_temporary (temp, high); } if (low_out) @@ -3172,7 +3185,7 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out) case SYMBOL_PCREL64: if (can_create_pseudo_p ()) { - *low_out = gen_rtx_PLUS (Pmode, high, temp1); + *low_out = gen_rtx_PLUS (Pmode, high, temp); break; } /* fall through */ @@ -3184,7 +3197,8 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out) /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */ { if (TARGET_CMODEL_EXTREME && can_create_pseudo_p ()) - *low_out = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, high, temp1)); + *low_out = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, high, + temp)); else { rtx low = gen_rtx_LO_SUM (Pmode, high, addr); @@ -7454,21 +7468,24 @@ loongarch_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, allowed, otherwise load the address into a register first. */ if (use_sibcall_p) { - if (TARGET_CMODEL_EXTREME) - { - emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2)); - insn = emit_call_insn (gen_sibcall_internal (temp1, const0_rtx)); - } - else - insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx)); + /* If TARGET_CMODEL_EXTREME, we cannot do a direct jump at all + and const_call_insn_operand should have returned false. */ + gcc_assert (!TARGET_CMODEL_EXTREME); + + insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx)); SIBLING_CALL_P (insn) = 1; } else { - if (TARGET_CMODEL_EXTREME) + if (!TARGET_CMODEL_EXTREME) + loongarch_emit_move (temp1, fnaddr); + else if (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE) emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2)); else - loongarch_emit_move (temp1, fnaddr); + { + emit_insn (gen_la_pcrel64_two_parts (temp1, temp2, fnaddr)); + emit_move_insn (temp1, gen_rtx_PLUS (Pmode, temp1, temp2)); + } emit_jump_insn (gen_indirect_jump (temp1)); } diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 5ec1d5a46d5..dffa41b0bf5 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -84,6 +84,8 @@ (define_c_enum "unspec" [ UNSPEC_CALL_VALUE_MULTIPLE_INTERNAL_1 UNSPEC_LOAD_SYMBOL_OFFSET64 + UNSPEC_LA_PCREL_64_PART1 + UNSPEC_LA_PCREL_64_PART2 ]) (define_c_enum "unspecv" [ @@ -2224,6 +2226,24 @@ (define_insn_and_split "movdi_symbolic_off64" [(set_attr "mode" "DI") (set_attr "insn_count" "5")]) +;; The 64-bit PC-relative part of address loading. +;; Note that the psABI does not allow splitting it. +(define_insn "la_pcrel64_two_parts" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 2 "") (pc)] UNSPEC_LA_PCREL_64_PART1)) + (set (match_operand:DI 1 "register_operand" "=r") + (unspec:DI [(match_dup 2) (pc)] UNSPEC_LA_PCREL_64_PART2))] + "TARGET_ABI_LP64 && la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE" + { + return "pcalau12i\t%0,%r2\n\t" + "addi.d\t%1,$r0,%L2\n\t" + "lu32i.d\t%1,%R2\n\t" + "lu52i.d\t%1,%1,%H2"; + } + [(set_attr "move_type" "move") + (set_attr "mode" "DI") + (set_attr "length" "16")]) + ;; 32-bit Integer moves (define_expand "movsi" diff --git a/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-1.C b/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-1.C new file mode 100644 index 00000000000..ff1f7c165e2 --- /dev/null +++ b/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-1.C @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-inline -march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=always -mdirect-extern-access" } */ + +struct A { + virtual ~A(); +}; + +struct B : virtual A {}; +void var() { B(); } + +/* { dg-final { scan-assembler "pcalau12i\t\[^\n\]*%pc_hi20\\(\\.LTHUNK0\\)\n\taddi\\.d\t\[^\n\]*%pc_lo12\\(\\\.LTHUNK0\\)\n\tlu32i\\.d\t\[^\n\]*%pc64_lo20\\(\\.LTHUNK0\\)\n\tlu52i\\.d\t\[^\n\]*%pc64_hi12\\(\\.LTHUNK0\\)" } } */ diff --git a/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-2.C b/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-2.C new file mode 100644 index 00000000000..c9aa16b410d --- /dev/null +++ b/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-2.C @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-inline -march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=auto -mdirect-extern-access" } */ + +#include "cmodel-extreme-mi-thunk-1.C" + +/* { dg-final { scan-assembler "pcalau12i\t\[^\n\]*%pc_hi20\\(\\.LTHUNK0\\)\n\taddi\\.d\t\[^\n\]*%pc_lo12\\(\\\.LTHUNK0\\)\n\tlu32i\\.d\t\[^\n\]*%pc64_lo20\\(\\.LTHUNK0\\)\n\tlu52i\\.d\t\[^\n\]*%pc64_hi12\\(\\.LTHUNK0\\)" } } */ diff --git a/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-3.C b/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-3.C new file mode 100644 index 00000000000..afb86c8bdee --- /dev/null +++ b/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-3.C @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-inline -march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=none -mdirect-extern-access" } */ + +#include "cmodel-extreme-mi-thunk-1.C" + +/* { dg-final { scan-assembler "la.local\t\[^\n\]*\\.LTHUNK0" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c b/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c new file mode 100644 index 00000000000..564ee4017f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=always -fdump-rtl-final" } */ + +int a; +extern int b; +__thread int c __attribute__ ((tls_model ("local-exec"))); +__thread int d __attribute__ ((tls_model ("initial-exec"))); +__thread int e __attribute__ ((tls_model ("local-dynamic"))); +__thread int f __attribute__ ((tls_model ("global-dynamic"))); + +void +test (void) +{ + a = b + c + d + e + f; +} + +/* a, b, d, e, f, and __tls_get_addr. */ +/* { dg-final { scan-rtl-dump-times "la_pcrel64_two_parts" 6 "final" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c b/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c new file mode 100644 index 00000000000..ce834805f38 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=auto -fdump-rtl-final" } */ + +#include "cmodel-extreme-1.c" + +/* a, b, d, e, f, and __tls_get_addr. */ +/* { dg-final { scan-rtl-dump-times "la_pcrel64_two_parts" 6 "final" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c index db1e0f85396..fdb4cf1ff7f 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c @@ -1,31 +1,33 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */ +/* { dg-options "-mabi=lp64d -O2 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */ /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */ /* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */ /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */ +#define NOIPA __attribute__ ((noipa)) + extern void g (void); -void +NOIPA void f (void) {} -static void +NOIPA static void l (void) {} -void +NOIPA void test (void) { g (); } -void +NOIPA void test1 (void) { f (); } -void +NOIPA void test2 (void) { l (); diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c index 21bf81ae837..dfba3882b97 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c @@ -1,32 +1,7 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */ +/* { dg-options "-mabi=lp64d -O2 -fpic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */ /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */ /* { dg-final { scan-assembler "test1:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */ /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */ -extern void g (void); -void -f (void) -{} - -static void -l (void) -{} - -void -test (void) -{ - g (); -} - -void -test1 (void) -{ - f (); -} - -void -test2 (void) -{ - l (); -} +#include "func-call-extreme-1.c" diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-3.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-3.c index a4da44b4a3d..1f5234f83d1 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-3.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */ +/* { dg-options "-mabi=lp64d -O2 -fno-pic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */ /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */ /* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */ /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-4.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-4.c index 16b00f4c5f2..c4228500635 100644 --- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-4.c +++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */ +/* { dg-options "-mabi=lp64d -O2 -fpic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */ /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */ /* { dg-final { scan-assembler "test1:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */ /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */