From patchwork Wed Jan 10 06:02:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: joshua X-Patchwork-Id: 83720 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8C55C385800E for ; Wed, 10 Jan 2024 06:03:09 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-132.freemail.mail.aliyun.com (out30-132.freemail.mail.aliyun.com [115.124.30.132]) by sourceware.org (Postfix) with ESMTPS id B02CE38582B3 for ; Wed, 10 Jan 2024 06:02:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B02CE38582B3 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B02CE38582B3 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.132 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704866555; cv=none; b=NhRln3mSBQF82R3jwz7DzKKfbpYt8MwgG/xh/WNI/3HF5lSupJzJC8JBzNSHlbLGiSFnzAsPX9KlRLZ0sQ3m1c+NEtbJ53W/spf9wo3DYATbRU7HfS7+gkxmZZoiJUXa41FCZ2ygWrZIbiNR9FbEzHN4hCcyf5QQnvH4utMOFrw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704866555; c=relaxed/simple; bh=+sGMmLFw0f5HvJww64s8jn/Xdplv6bUUL1M0R42N/LQ=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=mmdg5zdKGe2BLqNNkbAG18MS3pQ3t2OnIXXxAEDZKHo9CyLZiwj418p2rKJMJfaElKG+uDCl3tLkoia5vbPPSJ8joGSNWxm/21QUbjaNdFa5IsT3MT/aSpTCrd4KaGAzcaxm++lzNztsBAZeRKOt8cLuyANMLE9SERV/HeUcrZY= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R141e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046049; MF=cooper.joshua@linux.alibaba.com; NM=1; PH=DS; RN=11; SR=0; TI=SMTPD_---0W-L-ZS6_1704866542; Received: from localhost.localdomain(mailfrom:cooper.joshua@linux.alibaba.com fp:SMTPD_---0W-L-ZS6_1704866542) by smtp.aliyun-inc.com; Wed, 10 Jan 2024 14:02:24 +0800 From: "Jun Sha (Joshua)" To: gcc-patches@gcc.gnu.org Cc: jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, juzhe.zhong@rivai.ai, "Jun Sha (Joshua)" , Jin Ma , Xianmiao Qu Subject: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions Date: Wed, 10 Jan 2024 14:02:12 +0800 Message-Id: <20240110060212.1132-1-cooper.joshua@linux.alibaba.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20240103075409.1790-1-cooper.joshua@linux.alibaba.com> References: <20240103075409.1790-1-cooper.joshua@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.1 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps a source vector register group. To handle this issue, we use "group_overlap" and "enabled" attribute to disable some alternatives for xtheadvector. gcc/ChangeLog: * config/riscv/riscv.md (none,W21,W42,W84,W43,W86,W87,W0): (none,W21,W42,W84,W43,W86,W87,W0,th): Add group-overlap constraint for xtheadvector. * config/riscv/vector.md: Disable alternatives that destination register overlaps source register group for xtheadvector. Co-authored-by: Jin Ma Co-authored-by: Xianmiao Qu Co-authored-by: Christoph Müllner --- gcc/config/riscv/riscv.md | 12 +- gcc/config/riscv/vector.md | 314 +++++++++++++++++++++---------------- 2 files changed, 190 insertions(+), 136 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 84212430dc0..2fe15fd7340 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -537,7 +537,7 @@ ;; Widening instructions have group-overlap constraints. Those are only ;; valid for certain register-group sizes. This attribute marks the ;; alternatives not matching the required register-group size as disabled. -(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87,W0" +(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87,W0,th,rvv" (const_string "none")) (define_attr "group_overlap_valid" "no,yes" @@ -576,7 +576,15 @@ (and (eq_attr "group_overlap" "W0") (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) > 1")) (const_string "no") - ] + + (and (eq_attr "group_overlap" "th") + (match_test "TARGET_XTHEADVECTOR")) + (const_string "no") + + (and (eq_attr "group_overlap" "rvv") + (match_test "TARGET_VECTOR && !TARGET_XTHEADVECTOR")) + (const_string "no") + ] (const_string "yes"))) ;; Attribute to control enable or disable instructions. diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 3eb6daafbc2..cd83c1f3321 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -3260,7 +3260,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "4") - (set (attr "avl_type_idx") (const_int 5))]) + (set (attr "avl_type_idx") (const_int 5)) + (set_attr "group_overlap" "th,none,none")]) (define_insn "@pred_msbc" [(set (match_operand: 0 "register_operand" "=vr, vr, &vr") @@ -3279,7 +3280,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "4") - (set (attr "avl_type_idx") (const_int 5))]) + (set (attr "avl_type_idx") (const_int 5)) + (set_attr "group_overlap" "th,th,none")]) (define_insn "@pred_madc_scalar" [(set (match_operand: 0 "register_operand" "=vr, &vr") @@ -3299,7 +3301,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "4") - (set (attr "avl_type_idx") (const_int 5))]) + (set (attr "avl_type_idx") (const_int 5)) + (set_attr "group_overlap" "th,none")]) (define_insn "@pred_msbc_scalar" [(set (match_operand: 0 "register_operand" "=vr, &vr") @@ -3319,7 +3322,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "4") - (set (attr "avl_type_idx") (const_int 5))]) + (set (attr "avl_type_idx") (const_int 5)) + (set_attr "group_overlap" "th,none")]) (define_expand "@pred_madc_scalar" [(set (match_operand: 0 "register_operand") @@ -3368,7 +3372,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "4") - (set (attr "avl_type_idx") (const_int 5))]) + (set (attr "avl_type_idx") (const_int 5)) + (set_attr "group_overlap" "th,none")]) (define_insn "*pred_madc_extended_scalar" [(set (match_operand: 0 "register_operand" "=vr, &vr") @@ -3389,7 +3394,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "4") - (set (attr "avl_type_idx") (const_int 5))]) + (set (attr "avl_type_idx") (const_int 5)) + (set_attr "group_overlap" "th,none")]) (define_expand "@pred_msbc_scalar" [(set (match_operand: 0 "register_operand") @@ -3438,7 +3444,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "4") - (set (attr "avl_type_idx") (const_int 5))]) + (set (attr "avl_type_idx") (const_int 5)) + (set_attr "group_overlap" "th,none")]) (define_insn "*pred_msbc_extended_scalar" [(set (match_operand: 0 "register_operand" "=vr, &vr") @@ -3459,7 +3466,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "4") - (set (attr "avl_type_idx") (const_int 5))]) + (set (attr "avl_type_idx") (const_int 5)) + (set_attr "group_overlap" "th,none")]) (define_insn "@pred_madc_overflow" [(set (match_operand: 0 "register_operand" "=vr, &vr, &vr") @@ -3477,7 +3485,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "3") - (set (attr "avl_type_idx") (const_int 4))]) + (set (attr "avl_type_idx") (const_int 4)) + (set_attr "group_overlap" "th,none,none")]) (define_insn "@pred_msbc_overflow" [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") @@ -3495,7 +3504,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "3") - (set (attr "avl_type_idx") (const_int 4))]) + (set (attr "avl_type_idx") (const_int 4)) + (set_attr "group_overlap" "th,th,none,none")]) (define_insn "@pred_madc_overflow_scalar" [(set (match_operand: 0 "register_operand" "=vr, &vr") @@ -3514,7 +3524,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "3") - (set (attr "avl_type_idx") (const_int 4))]) + (set (attr "avl_type_idx") (const_int 4)) + (set_attr "group_overlap" "th,none")]) (define_insn "@pred_msbc_overflow_scalar" [(set (match_operand: 0 "register_operand" "=vr, &vr") @@ -3533,7 +3544,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "3") - (set (attr "avl_type_idx") (const_int 4))]) + (set (attr "avl_type_idx") (const_int 4)) + (set_attr "group_overlap" "th,none")]) (define_expand "@pred_madc_overflow_scalar" [(set (match_operand: 0 "register_operand") @@ -3580,7 +3592,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "3") - (set (attr "avl_type_idx") (const_int 4))]) + (set (attr "avl_type_idx") (const_int 4)) + (set_attr "group_overlap" "th,none")]) (define_insn "*pred_madc_overflow_extended_scalar" [(set (match_operand: 0 "register_operand" "=vr, &vr") @@ -3600,7 +3613,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "3") - (set (attr "avl_type_idx") (const_int 4))]) + (set (attr "avl_type_idx") (const_int 4)) + (set_attr "group_overlap" "th,none")]) (define_expand "@pred_msbc_overflow_scalar" [(set (match_operand: 0 "register_operand") @@ -3647,7 +3661,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "3") - (set (attr "avl_type_idx") (const_int 4))]) + (set (attr "avl_type_idx") (const_int 4)) + (set_attr "group_overlap" "th,none")]) (define_insn "*pred_msbc_overflow_extended_scalar" [(set (match_operand: 0 "register_operand" "=vr, &vr") @@ -3667,7 +3682,8 @@ [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "3") - (set (attr "avl_type_idx") (const_int 4))]) + (set (attr "avl_type_idx") (const_int 4)) + (set_attr "group_overlap" "th,none")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated integer unary operations @@ -3987,7 +4003,8 @@ "TARGET_VECTOR" "vn.w%o4\t%0,%3,%v4%p1" [(set_attr "type" "vnshift") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "none,none,th,th,none,th,none,none,none,th,none,none")]) (define_insn "@pred_narrow__scalar" [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") @@ -4008,7 +4025,8 @@ "TARGET_VECTOR" "vn.w%o4\t%0,%3,%4%p1" [(set_attr "type" "vnshift") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "none,none,th,th,none,none")]) ;; vncvt.x.x.w (define_insn "@pred_trunc" @@ -4032,7 +4050,8 @@ (set_attr "vl_op_idx" "4") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) + (set (attr "avl_type_idx") (const_int 7)) + (set_attr "group_overlap" "none,none,th,th,none,none")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated fixed-point operations @@ -4438,7 +4457,8 @@ "TARGET_VECTOR" "vnclip.w%o4\t%0,%3,%v4%p1" [(set_attr "type" "vnclip") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,th,th,th,th,none,none,th,th,none,none")]) (define_insn "@pred_narrow_clip_scalar" [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") @@ -4460,7 +4480,8 @@ "TARGET_VECTOR" "vnclip.w%o4\t%0,%3,%4%p1" [(set_attr "type" "vnclip") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,th,th,none,none")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated integer comparison operations @@ -4511,23 +4532,24 @@ ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_cmp" - [(set (match_operand: 0 "register_operand" "=vr, vr, vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr, vr, vr, &vr, &vr, &vr, &vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_ltge_operator" - [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr") - (match_operand:V_VLSI 5 "vector_arith_operand" " vr, vr, vi, vi")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] + [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr") + (match_operand:V_VLSI 5 "vector_arith_operand" " vr, vr, vi, vi, vr, vr, vi, vi")]) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.v%o5\t%0,%4,%v5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,th,th,rvv,rvv,rvv,rvv")]) ;; We use early-clobber for source LMUL > dest LMUL. (define_insn "*pred_cmp_narrow" @@ -4547,7 +4569,8 @@ "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.v%o5\t%0,%4,%v5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "none,th,th,th,th,th,th,none,none")]) (define_expand "@pred_ltge" [(set (match_operand: 0 "register_operand") @@ -4591,23 +4614,24 @@ ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_ltge" - [(set (match_operand: 0 "register_operand" "=vr, vr, vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr, vr, vr, &vr, &vr, &vr, &vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "ltge_operator" - [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr") - (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vr, vr, vj, vj")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] + [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr") + (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vr, vr, vj, vj, vr, vr, vj, vj")]) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.v%o5\t%0,%4,%v5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,th,th,rvv,rvv,rvv,rvv")]) ;; We use early-clobber for source LMUL > dest LMUL. (define_insn "*pred_ltge_narrow" @@ -4627,7 +4651,8 @@ "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.v%o5\t%0,%4,%v5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "none,th,th,th,th,th,th,none,none")]) (define_expand "@pred_cmp_scalar" [(set (match_operand: 0 "register_operand") @@ -4673,24 +4698,25 @@ ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_cmp_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_eqge_operator" - [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr") + [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand" " r, r"))]) - (match_operand: 2 "vector_merge_operand" " vu, 0")))] + (match_operand: 5 "register_operand" " r, r, r, r"))]) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,rvv,rvv")]) ;; We use early-clobber for source LMUL > dest LMUL. (define_insn "*pred_cmp_scalar_narrow" @@ -4711,7 +4737,8 @@ "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "none,th,th,none,none")]) (define_expand "@pred_eqne_scalar" [(set (match_operand: 0 "register_operand") @@ -4757,24 +4784,25 @@ ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "equality_operator" [(vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand" " r, r")) - (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0")))] + (match_operand: 5 "register_operand" " r, r, r, r")) + (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")]) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,rvv,rvv")]) ;; We use early-clobber for source LMUL > dest LMUL. (define_insn "*pred_eqne_scalar_narrow" @@ -4795,7 +4823,8 @@ "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "none,th,th,none,none")]) ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since ;; we need to deal with SEW = 64 in RV32 system. @@ -4922,24 +4951,25 @@ ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_cmp_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_eqge_operator" - [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr") + [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_D - (match_operand: 5 "register_operand" " r, r"))]) - (match_operand: 2 "vector_merge_operand" " vu, 0")))] + (match_operand: 5 "register_operand" " r, r, r, r"))]) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,rvv,rvv")]) ;; We use early-clobber for source LMUL > dest LMUL. (define_insn "*pred_cmp_scalar_narrow" @@ -4960,28 +4990,30 @@ "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "none,th,th,none,none")]) ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "equality_operator" [(vec_duplicate:V_VLSI_D - (match_operand: 5 "register_operand" " r, r")) - (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0")))] + (match_operand: 5 "register_operand" " r, r, r, r")) + (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")]) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,rvv,rvv")]) ;; We use early-clobber for source LMUL > dest LMUL. (define_insn "*pred_eqne_scalar_narrow" @@ -5002,7 +5034,8 @@ "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "none,th,th,none,none")]) (define_insn "*pred_cmp_extended_scalar_merge_tie_mask" [(set (match_operand: 0 "register_operand" "=vm") @@ -5031,25 +5064,26 @@ ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_cmp_extended_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "comparison_except_eqge_operator" - [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr") + [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_D (sign_extend: - (match_operand: 5 "register_operand" " r, r")))]) - (match_operand: 2 "vector_merge_operand" " vu, 0")))] + (match_operand: 5 "register_operand" " r, r, r, r")))]) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode) && !TARGET_64BIT" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,rvv,rvv")]) (define_insn "*pred_cmp_extended_scalar_narrow" [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") @@ -5070,7 +5104,8 @@ "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode) && !TARGET_64BIT" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "none,th,th,none,none")]) (define_insn "*pred_eqne_extended_scalar_merge_tie_mask" [(set (match_operand: 0 "register_operand" "=vm") @@ -5099,25 +5134,26 @@ ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_eqne_extended_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "equality_operator" [(vec_duplicate:V_VLSI_D (sign_extend: - (match_operand: 5 "register_operand" " r, r"))) - (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0")))] + (match_operand: 5 "register_operand" " r, r, r, r"))) + (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")]) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode) && !TARGET_64BIT" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,rvv,rvv")]) (define_insn "*pred_eqne_extended_scalar_narrow" [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") @@ -5138,7 +5174,8 @@ "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode) && !TARGET_64BIT" "vms%B3.vx\t%0,%4,%5%p1" [(set_attr "type" "vicmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "none,th,th,none,none")]) ;; GE, vmsge.vx/vmsgeu.vx ;; @@ -7327,23 +7364,24 @@ ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_cmp" - [(set (match_operand: 0 "register_operand" "=vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "signed_order_operator" - [(match_operand:V_VLSF 4 "register_operand" " vr, vr") - (match_operand:V_VLSF 5 "register_operand" " vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0")))] + [(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSF 5 "register_operand" " vr, vr, vr, vr")]) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vmf%B3.vv\t%0,%4,%5%p1" [(set_attr "type" "vfcmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,rvv,rvv")]) (define_insn "*pred_cmp_narrow_merge_tie_mask" [(set (match_operand: 0 "register_operand" "=vm") @@ -7386,7 +7424,8 @@ "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vmf%B3.vv\t%0,%4,%5%p1" [(set_attr "type" "vfcmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "none,th,th,th,th,th,th,none,none")]) (define_expand "@pred_cmp_scalar" [(set (match_operand: 0 "register_operand") @@ -7432,24 +7471,25 @@ ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_cmp_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "signed_order_operator" - [(match_operand:V_VLSF 4 "register_operand" " vr, vr") + [(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSF - (match_operand: 5 "register_operand" " f, f"))]) - (match_operand: 2 "vector_merge_operand" " vu, 0")))] + (match_operand: 5 "register_operand" " f, f, f, f"))]) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vmf%B3.vf\t%0,%4,%5%p1" [(set_attr "type" "vfcmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,rvv,rvv")]) ;; We use early-clobber for source LMUL > dest LMUL. (define_insn "*pred_cmp_scalar_narrow" @@ -7470,7 +7510,8 @@ "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vmf%B3.vf\t%0,%4,%5%p1" [(set_attr "type" "vfcmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "none,th,th,none,none")]) (define_expand "@pred_eqne_scalar" [(set (match_operand: 0 "register_operand") @@ -7516,24 +7557,25 @@ ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operator: 3 "equality_operator" [(vec_duplicate:V_VLSF - (match_operand: 5 "register_operand" " f, f")) - (match_operand:V_VLSF 4 "register_operand" " vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0")))] + (match_operand: 5 "register_operand" " f, f, f, f")) + (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")]) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" "vmf%B3.vf\t%0,%4,%5%p1" [(set_attr "type" "vfcmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "th,th,rvv,rvv")]) ;; We use early-clobber for source LMUL > dest LMUL. (define_insn "*pred_eqne_scalar_narrow" @@ -7554,7 +7596,8 @@ "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" "vmf%B3.vf\t%0,%4,%5%p1" [(set_attr "type" "vfcmp") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set_attr "group_overlap" "none,th,th,none,none")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point merge @@ -7774,7 +7817,8 @@ [(set_attr "type" "vfncvtftoi") (set_attr "mode" "") (set (attr "frm_mode") - (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) + (symbol_ref "riscv_vector::get_frm_mode (operands[8])")) + (set_attr "group_overlap" "none,none,th,th,none,none")]) (define_insn "@pred_narrow_" [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") @@ -7816,7 +7860,8 @@ [(set_attr "type" "vfncvtitof") (set_attr "mode" "") (set (attr "frm_mode") - (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) + (symbol_ref "riscv_vector::get_frm_mode (operands[8])")) + (set_attr "group_overlap" "none,none,th,th,none,none")]) (define_insn "@pred_trunc" [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") @@ -7839,7 +7884,8 @@ [(set_attr "type" "vfncvtftof") (set_attr "mode" "") (set (attr "frm_mode") - (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) + (symbol_ref "riscv_vector::get_frm_mode (operands[8])")) + (set_attr "group_overlap" "none,none,th,th,none,none")]) (define_insn "@pred_rod_trunc" [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")