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Wed, 3 Jan 2024 01:17:42 +0000 From: Victor Do Nascimento To: CC: , , Victor Do Nascimento Subject: [PATCH 01/12] aarch64: Add +d128 architectural feature support Date: Wed, 3 Jan 2024 01:17:15 +0000 Message-ID: <20240103011739.2444792-2-victor.donascimento@arm.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240103011739.2444792-1-victor.donascimento@arm.com> References: <20240103011739.2444792-1-victor.donascimento@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM4PEPF00025F99:EE_|GV2PR08MB8170:EE_|DB1PEPF00039230:EE_|AM9PR08MB6721:EE_ X-MS-Office365-Filtering-Correlation-Id: 29778507-7b7a-47ea-a87f-08dc0bf9d1ba X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: s4B9x3+/9zzonT9UPLmluQzR9PcOuryXKuWTGvTxalUxHxgumxQE/SSGJiUWar601Yw8Hfs73Bk68nD3MEcYG0hoJs307873ag3Bu7bMvEOHG248/JoNs1fBi2GIdsLaMEKgwq7XMHUMqWsuNgcG14zxbliT3aqde5yqMJi7Eegjp4jKGNV3/vH7UPEE3Ogochq1iAViaRc30uiWpS9AIyJbeQoD8eEcgfll03qT/aCm64DaY3A3Qp6sK3ebGydmaJKdEwxo0Rd7sHAeXK6ApfgvYeYL/PYqnluu+lx4chOlROj//AZ6Z4Lro0txvLkyLN2huOHP7qOWY6EnCc+1f57R4YPsd6ggRG4/NBI0XT72hBBBl86ldXH95sy/HsUohn5f1Z9Mo/WL7g8vvBELWO+9yMhvpXUdIzz3qdwFusKS3I1PTfnZMrMokzi/dU4gOJ5H38/sCjKEnUCdITeJl/iPn26wSS6JGf22DC8PecDAxLR5VDniXnzgvbASyRP2/7tluXfL8EAMBNLJrAFTvnsGJQFm3b1gSYsg6ZtFeM31ShyX75uuocIO0RLWspxoFgiQaK440Qi4HoWwKuyr4prrkxsu+IRQMncMYcTQRaBfsUg57F/W2AofUVI72QXBuzlb+bRTDIKtRwIxLF5dj9ECshRSIGMChzNuUh0BYWyj1ihFriKjRRzHLKvPi16FGRgvZLhHwV9DhkAYDJM0F51KYQi77U+epiHm9PqrJcGTSyP2KEJgNOC28v/2amUd1/88GrEYBmFcm634gTbSsg== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF00039230.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6721 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Indicating the presence of the Armv9.4-a features concerning 128-bit Page Table Descriptors, 128-bit System Registers and Instructions, the "+d128" architectural extension flag is added to the list of possible -march options in Binutils, together with the necessary macro for encoding d128 instructions. --- gas/config/tc-aarch64.c | 2 ++ gas/doc/c-aarch64.texi | 2 ++ include/opcode/aarch64.h | 3 +++ opcodes/aarch64-tbl.h | 5 +++++ 4 files changed, 12 insertions(+) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index c10d8201f5e..bfe91c90139 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10297,6 +10297,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"the", AARCH64_FEATURE (THE), AARCH64_NO_FEATURES}, {"rasv2", AARCH64_FEATURE (RASv2), AARCH64_FEATURE (RAS)}, {"ite", AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES}, + {"d128", AARCH64_FEATURE (D128), + AARCH64_FEATURE (LSE128)}, {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}, }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 209d20fa832..7383343d167 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -274,6 +274,8 @@ automatically cause those extensions to be disabled. @tab Enable Prediction instructions. @item @code{ite} @tab N/A @tab no @tab Enable TRCIT instruction. +@item @code{d128} @tab Armv9.4-A @tab No + @tab Enable the 128-bit Page Descriptor Extension. This implies @code{lse128}. @end multitable @node AArch64 Syntax diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 1da337aaa58..9fc7643ffa1 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -201,6 +201,9 @@ enum aarch64_feature_bit { AARCH64_FEATURE_PREDRES2, /* Instrumentation Extension. */ AARCH64_FEATURE_ITE, + /* 128-bit page table descriptor, system registers + and isntructions. */ + AARCH64_FEATURE_D128, AARCH64_NUM_FEATURES }; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 5dd0864c0ab..3be6daeb3b0 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2582,6 +2582,8 @@ static const aarch64_feature_set aarch64_feature_gcs = AARCH64_FEATURE (GCS); static const aarch64_feature_set aarch64_feature_ite = AARCH64_FEATURE (ITE); +static const aarch64_feature_set aarch64_feature_d128 = + AARCH64_FEATURE (D128); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2645,6 +2647,7 @@ static const aarch64_feature_set aarch64_feature_ite = #define CHK &aarch64_feature_chk #define GCS &aarch64_feature_gcs #define ITE &aarch64_feature_ite +#define D128 &aarch64_feature_d128 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2798,6 +2801,8 @@ static const aarch64_feature_set aarch64_feature_ite = { NAME, OPCODE, MASK, ic_system, 0, CHK, OPS, QUALS, FLAGS, 0, 0, NULL } #define GCS_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, gcs, 0, GCS, OPS, QUALS, FLAGS, 0, 0, NULL } +#define D128_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, ic_system, 0, D128, OPS, QUALS, FLAGS, 0, 0, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ From patchwork Wed Jan 3 01:17:16 2024 Content-Type: text/plain; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C70E.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB5315 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Given the introduction of the new Armv9.4-a `sysp' insn using the following syntax: sysp #, , , #{, , } and by extension the need to encode 6 assembly operands, extend Binutils to handle instructions taking 6 operands, up from a previous maximum of 5. --- include/opcode/aarch64.h | 2 +- opcodes/aarch64-tbl.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 9fc7643ffa1..b9ea73c4259 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1075,7 +1075,7 @@ enum err_type }; /* Maximum number of operands an instruction can have. */ -#define AARCH64_MAX_OPND_NUM 6 +#define AARCH64_MAX_OPND_NUM 7 /* Maximum number of qualifier sequences an instruction can have. */ #define AARCH64_MAX_QLF_SEQ_NUM 10 /* Operand qualifier typedef; optimized for the size. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 3be6daeb3b0..605f6f2438f 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -34,6 +34,7 @@ #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)} #define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)} #define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)} +#define OP6(a,b,c,d,e,f) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e), OPND(f)} #define QLF(x) AARCH64_OPND_QLF_##x #define QLF1(a) {QLF(a)} @@ -41,6 +42,7 @@ #define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)} #define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)} #define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)} +#define QLF6(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e), QLF(f)} /* Qualifiers list. */ From patchwork Wed Jan 3 01:17:17 2024 Content-Type: text/plain; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B8F.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB9559 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Analysis of the allowed operand values for `sysp' and `tlbip' reveals a significant departure from the allowed behavior for operand register pairs (hitherto labeled AARCH64_OPND_PAIRREG) observed for other insns in this category. For instructions `casp', `mrrs' and `msrr' the register pair must always start at an even index and the second register in the pair is the index + 1. This precludes the use of xzr as the first register, given it corresponds to register number 31. This is different in the case of `sysp' and `tlbip', however. These allow the use of xzr and, where the first operand in the pair is omitted, this is the default value assigned to it. When this operand is assigned xzr, it is expected that the second operand will likewise take on a value of xzr. These two instructions therefore "break" two rules of register pairs: * The first of the two registers is odd-numbered. * The index of the second register is equal to that of the first, and not n+1. To allow for this departure from hitherto standard behavior, we extend the functionality of the assembler by defining an extension of the AARCH64_OPND_PAIRREG, called AARCH64_OPND_PAIRREG_OR_XZR. It is used in defining `sysp' and `tlbip' and allows `operand_general_constraint_met_p' to allow the pair to both take on the value of xzr. --- gas/config/tc-aarch64.c | 1 + include/opcode/aarch64.h | 1 + opcodes/aarch64-dis.c | 7 +++++-- opcodes/aarch64-opc.c | 19 +++++++++++++++++-- opcodes/aarch64-tbl.h | 2 ++ 5 files changed, 26 insertions(+), 4 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index bfe91c90139..796a6da267b 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6532,6 +6532,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_Rt_LS64: case AARCH64_OPND_Rt_SYS: case AARCH64_OPND_PAIRREG: + case AARCH64_OPND_PAIRREG_OR_XZR: case AARCH64_OPND_SVE_Rm: po_int_fp_reg_or_fail (REG_TYPE_R_ZR); diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index b9ea73c4259..d3db252e5c2 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -455,6 +455,7 @@ enum aarch64_opnd AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */ AARCH64_OPND_PAIRREG, /* Paired register operand. */ + AARCH64_OPND_PAIRREG_OR_XZR, /* Paired register operand, optionally xzr. */ AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 3bf5f50effc..e9f47807654 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -302,8 +302,11 @@ aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_op aarch64_operand_error *errors ATTRIBUTE_UNUSED) { assert (info->idx == 1 - || info->idx ==3); - info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1; + || info->idx == 3); + + unsigned prev_regno = inst->operands[info->idx - 1].reg.regno; + info->reg.regno = (prev_regno == 0x1f) ? 0x1f + : prev_regno + 1; return true; } diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 4d84071ba8c..4530591b329 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1693,8 +1693,22 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, switch (aarch64_operands[type].op_class) { case AARCH64_OPND_CLASS_INT_REG: - /* Check pair reg constraints for cas* instructions. */ - if (type == AARCH64_OPND_PAIRREG) + /* Check for pair of xzr registers. */ + if (type == AARCH64_OPND_PAIRREG_OR_XZR + && opnds[idx - 1].reg.regno == 0x1f) + { + if (opnds[idx].reg.regno != 0x1f) + { + set_syntax_error (mismatch_detail, idx - 1, + _("second reg in pair should be xzr if first is" + " xzr")); + return 0; + } + } + /* Check pair reg constraints for instructions taking a pair of + consecutively-numbered general-purpose registers. */ + else if (type == AARCH64_OPND_PAIRREG + || type == AARCH64_OPND_PAIRREG_OR_XZR) { assert (idx == 1 || idx == 3); if (opnds[idx - 1].reg.regno % 2 != 0) @@ -3771,6 +3785,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_Rt_LS64: case AARCH64_OPND_Rt_SYS: case AARCH64_OPND_PAIRREG: + case AARCH64_OPND_PAIRREG_OR_XZR: case AARCH64_OPND_SVE_Rm: case AARCH64_OPND_LSE128_Rt: case AARCH64_OPND_LSE128_Rt2: diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 605f6f2438f..1dfbee25786 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -6174,6 +6174,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an integer or stack pointer register") \ X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \ "the second reg of a pair") \ + X(INT_REG, 0, ext_regno_pair, "PAIRREG_OR_XZR", 0, F(), \ + "the second reg of a pair") \ Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \ "an integer register with optional extension") \ Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(), \ From patchwork Wed Jan 3 01:17:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Do Nascimento X-Patchwork-Id: 83183 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 99CC2386180B for ; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF0001E9C3.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR08MB10666 X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Two of the instructions added by the `+d128' architectural extension add the flexibility to have two optional operands. Prior to the addition of the `tlbip' and `sysp' instructions, no mnemonic allowed more than one such optional operand. With `tlbip' as an example, some TLBIP instruction names do not allow for any optional operands, while others allow for both to be optional. In the latter case, it is possible that either the second operand alone is omitted or both operands are omitted. Therefore, a considerable degree of flexibility needed to be added to the way operands were parsed. It was, however, possible to achieve this with relatively few changes to existing code. it is noteworthy that opcode flags specifying the optional operand number are non-orthogonal. For example, we have: #define F_OPD1_OPT (2 << 12) : 0b10 << 12 #define F_OPD2_OPT (3 << 12) : 0b11 << 12 such that by virtue of the observation that (F_OPD1_OPT | F_OPD2_OPT) == F_OPD2_OPT it is impossible to mark both operands 1 and 2 as optional for an instruction and it is assumed that a maximum of 1 operand can ever be optional. This is not overly-problematic given that, for optional pairs, the second optional operand is always found immediately after the first. Thus, it suffices for us to flag that there is a second optional operand. With this fact, we can infer its position in the mnemonic from the position of the first (e.g. if the second operand in the mnemonic is optional, we know the third is too). We therefore define the `F_OPD_PAIR_OPT' flag and calculate its position in the mnemonic from the value encoded by the `F_OPD_OPT' flag. Another observation is that there is a tight coupling between default values assigned to the two registers when one (or both) are omitted from the mnemonic. Namely, if Xt1 has a value of 0x1f (the zero register is specified), Xt2 defaults to the same value, otherwise Xt2 will be assigned Xt + 1. This meant that where you have default value validation, in checking the second optional operand's value, it is also necessary to look at the value assigned to the previously-processed operand value before deciding its validity. Thus `process_omitted_operand' needs not only access to its `operand' argument, but also to the global `inst' struct. --- gas/config/tc-aarch64.c | 19 +++++++++++++++++-- include/opcode/aarch64.h | 12 +++++++++++- 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 796a6da267b..12fb1740635 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6179,6 +6179,17 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode, case AARCH64_OPND_VnD1: operand->reg.regno = default_value; break; + case AARCH64_OPND_PAIRREG_OR_XZR: + if (inst.base.operands[idx - 1].reg.regno == 0x1f) + { + operand->reg.regno = 0x1f; + break; + } + operand->reg.regno = inst.base.operands[idx - 1].reg.regno + 1; + break; + case AARCH64_OPND_PAIRREG: + operand->reg.regno = inst.base.operands[idx - 1].reg.regno + 1; + break; case AARCH64_OPND_Ed: case AARCH64_OPND_En: @@ -7875,6 +7886,12 @@ parse_operands (char *str, const aarch64_opcode *opcode) /* If we get here, this operand was successfully parsed. */ inst.base.operands[i].present = 1; + + /* As instructions can have multiple optional operands, it is imporant to + reset the backtrack_pos variable once we finish processing an operand + successfully. */ + backtrack_pos = 0; + continue; failure: @@ -7896,8 +7913,6 @@ parse_operands (char *str, const aarch64_opcode *opcode) char *tmp = backtrack_pos; char endchar = END_OF_INSN; - if (i != (aarch64_num_of_operands (opcode) - 1)) - endchar = ','; skip_past_char (&tmp, ','); if (*tmp != endchar) diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index d3db252e5c2..c69f85557d0 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1220,7 +1220,11 @@ extern const aarch64_opcode aarch64_opcode_table[]; /* This instruction has an extra constraint on it that imposes a requirement on subsequent instructions. */ #define F_SCAN (1ULL << 31) -/* Next bit is 32. */ +/* Instruction takes a pair of optional operands. If we specify the Nth operand + to be optional, then we also implicitly specify (N+1)th operand to also be + optional. */ +#define F_OPD_PAIR_OPT (1ULL << 32) +/* Next bit is 33. */ /* Instruction constraints. */ /* This instruction has a predication constraint on the instruction at PC+4. */ @@ -1259,9 +1263,15 @@ pseudo_opcode_p (const aarch64_opcode *opcode) return (opcode->flags & F_PSEUDO) != 0lu; } +/* Deal with two possible scenarios: If F_OP_PAIR_OPT not set, as is the case + by default, F_OPDn_OPT must equal IDX + 1, else F_OPDn_OPT must be in range + [IDX, IDX + 1]. */ static inline bool optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) { + if (opcode->flags & F_OPD_PAIR_OPT) + return (((opcode->flags >> 12) & 0x7) == idx + || ((opcode->flags >> 12) & 0x7) == idx + 1); return ((opcode->flags >> 12) & 0x7) == idx + 1; } From patchwork Wed Jan 3 01:17:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Do Nascimento X-Patchwork-Id: 83175 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8919D3857C56 for ; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF0000A7DD.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB6044 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Mirroring the use of the `sys' - System Instruction assembly instruction, this implements its 128-bit counterpart, `sysp'. This optionally takes two contiguous general-purpose registers starting at an even number or, when these are omitted, by default sets both of these to xzr. Syntax: sysp #, , , #{, , } --- gas/testsuite/gas/aarch64/illegal-sys128.l | 4 ++++ gas/testsuite/gas/aarch64/illegal-sys128.s | 5 +++++ opcodes/aarch64-dis.c | 3 ++- opcodes/aarch64-opc.c | 2 +- opcodes/aarch64-tbl.h | 9 ++++++++- 5 files changed, 20 insertions(+), 3 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/illegal-sys128.l create mode 100644 gas/testsuite/gas/aarch64/illegal-sys128.s diff --git a/gas/testsuite/gas/aarch64/illegal-sys128.l b/gas/testsuite/gas/aarch64/illegal-sys128.l new file mode 100644 index 00000000000..b86fbc86af0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-sys128.l @@ -0,0 +1,4 @@ +.*: Assembler messages: +.*: Error: C8 - C9 expected at operand 2 -- `sysp #0,C7,C0,#0,x0,x1' +.*: Error: C8 - C9 expected at operand 2 -- `sysp #0,C10,C0,#0,x0,x1' +.*: Error: C0 - C7 expected at operand 3 -- `sysp #6,C9,C8,#7,x27,x28' diff --git a/gas/testsuite/gas/aarch64/illegal-sys128.s b/gas/testsuite/gas/aarch64/illegal-sys128.s new file mode 100644 index 00000000000..42473c9b40e --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-sys128.s @@ -0,0 +1,5 @@ + .arch armv8-a+d128 + + sysp #0, C7, C0, #0, x0, x1 + sysp #0, C10, C0, #0, x0, x1 + sysp #6, C9, C8, #7, x27, x28 diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index e9f47807654..32831e855cd 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -302,7 +302,8 @@ aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_op aarch64_operand_error *errors ATTRIBUTE_UNUSED) { assert (info->idx == 1 - || info->idx == 3); + || info->idx == 3 + || info->idx == 5); unsigned prev_regno = inst->operands[info->idx - 1].reg.regno; info->reg.regno = (prev_regno == 0x1f) ? 0x1f diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 4530591b329..38a377110de 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1710,7 +1710,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, else if (type == AARCH64_OPND_PAIRREG || type == AARCH64_OPND_PAIRREG_OR_XZR) { - assert (idx == 1 || idx == 3); + assert (idx == 1 || idx == 3 || idx == 5); if (opnds[idx - 1].reg.regno % 2 != 0) { set_syntax_error (mismatch_detail, idx - 1, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 1dfbee25786..79830e007d5 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -42,7 +42,7 @@ #define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)} #define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)} #define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)} -#define QLF6(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e), QLF(f)} +#define QLF6(a,b,c,d,e,f) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e), QLF(f)} /* Qualifiers list. */ @@ -70,6 +70,12 @@ QLF5(X,NIL,CR,CR,NIL), \ } +/* e.g. SYSP #, , , #{, , }. */ +#define QL_SYSP \ +{ \ + QLF6(NIL,CR,CR,NIL,X,X), \ +} + /* e.g. ADRP ,