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Date: Fri, 29 Dec 2023 10:12:22 +0800 Message-Id: <20231229021222.24002-1-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxG+QJK45ldAcPAA--.50158S4 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAABWWM2y8T0wAAsZ X-Coremail-Antispam: 1Uk129KBj9fXoWfKr4fGF4kWFy8JryrCr4fXrc_yoW5GFW7Jo WYgFWY9r4Iq3yftryFkw12gryUWrn7Xrs5XFy7CrsrCF9rXr4rJFW5Wr1vvFy7Jay3WFZ5 JFZ2gF4kAFyxtF47l-sFpf9Il3svdjkaLaAFLSUrUUUUbb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUYb7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5McIj6I8E87Iv 67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07josjUUUUUU= Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenxiaolong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org In order to improve and check the function of vector quantization in LoongArch architecture, tests on vector instruction set are provided in target-support.exp. gcc/testsuite/ChangeLog: * lib/target-supports.exp:Add LoongArch to the list of supported targets. --- gcc/testsuite/lib/target-supports.exp | 219 +++++++++++++++++++------- 1 file changed, 161 insertions(+), 58 deletions(-) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 14e3e119792..b90aaf8cabe 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3811,7 +3811,11 @@ proc add_options_for_bfloat16 { flags } { # (fma, fms, fnma, and fnms) for both float and double. proc check_effective_target_scalar_all_fma { } { - return [istarget aarch64*-*-*] + if { [istarget aarch64*-*-*] + || [istarget loongarch*-*-*]} { + return 1 + } + return 0 } # Return 1 if the target supports compiling fixed-point, @@ -4017,7 +4021,7 @@ proc check_effective_target_vect_cmdline_needed { } { || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) || [istarget aarch64*-*-*] || [istarget amdgcn*-*-*] - || [istarget riscv*-*-*]} { + || [istarget riscv*-*-*] } { return 0 } else { return 1 @@ -4047,6 +4051,8 @@ proc check_effective_target_vect_int { } { && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } @@ -4176,7 +4182,9 @@ proc check_effective_target_vect_intfloat_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports signed double->int conversion @@ -4197,7 +4205,9 @@ proc check_effective_target_vect_doubleint_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports signed int->double conversion @@ -4218,7 +4228,9 @@ proc check_effective_target_vect_intdouble_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } #Return 1 if we're supporting __int128 for target, 0 otherwise. @@ -4251,7 +4263,9 @@ proc check_effective_target_vect_uintfloat_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } @@ -4270,7 +4284,9 @@ proc check_effective_target_vect_floatint_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports unsigned float->int conversion @@ -4287,7 +4303,9 @@ proc check_effective_target_vect_floatuint_cvt { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector integer char -> long long extend optab @@ -4296,7 +4314,9 @@ proc check_effective_target_vect_floatuint_cvt { } { proc check_effective_target_vect_ext_char_longlong { } { return [check_cached_effective_target_indexed vect_ext_char_longlong { expr { ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if peeling for alignment might be profitable on the target @@ -7420,7 +7440,9 @@ proc check_effective_target_vect_shift { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports hardware vector shift by register operation. @@ -7432,6 +7454,8 @@ proc check_effective_target_vect_var_shift { } { || [istarget aarch64*-*-*] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } @@ -7448,7 +7472,9 @@ proc check_effective_target_whole_vector_shift { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) } { + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) } { set answer 1 } else { set answer 0 @@ -7465,6 +7491,7 @@ proc check_effective_target_vect_bswap { } { expr { ([istarget aarch64*-*-*] || [is-effective-target arm_neon] || [istarget amdgcn-*-*]) + || [istarget loongarch*-*-*] || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) }}] } @@ -7478,7 +7505,9 @@ proc check_effective_target_vect_bool_cmp { } { || [istarget aarch64*-*-*] || [is-effective-target arm_neon] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports addition of char vectors for at least @@ -7501,6 +7530,8 @@ proc check_effective_target_vect_char_add { } { && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } @@ -7517,7 +7548,9 @@ proc check_effective_target_vect_shift_char { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports hardware vectors of long, 0 otherwise. @@ -7538,7 +7571,9 @@ proc check_effective_target_vect_long { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) } { + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) } { set answer 1 } else { set answer 0 @@ -7568,7 +7603,9 @@ proc check_effective_target_vect_float { } { && [check_effective_target_s390_vxe]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports hardware vectors of float without @@ -7599,7 +7636,9 @@ proc check_effective_target_vect_double { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v])} }] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports conditional addition, subtraction, @@ -7627,7 +7666,9 @@ proc check_effective_target_vect_long_long { } { && [check_effective_target_has_arch_pwr8]) || [istarget aarch64*-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v])}}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx])}}] } @@ -7682,7 +7723,9 @@ proc check_effective_target_vect_perm { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if, for some VF: @@ -7777,7 +7820,9 @@ proc check_effective_target_vect_perm_byte { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports SLP permutation of 3 vectors when each @@ -7808,7 +7853,9 @@ proc check_effective_target_vect_perm_short { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports SLP permutation of 3 vectors when each @@ -7856,6 +7903,7 @@ proc check_effective_target_vect_widen_sum_hi_to_si { } { expr { [check_effective_target_vect_unpack] || [istarget powerpc*-*-*] || [istarget ia64-*-*] + || [istarget loongarch*-*-*] || [istarget riscv*-*-*] }}] } @@ -7871,7 +7919,8 @@ proc check_effective_target_vect_widen_sum_qi_to_hi { } { expr { [check_effective_target_vect_unpack] || [is-effective-target arm_neon] || [istarget ia64-*-*] - || [istarget riscv*-*-*] }}] + || [istarget riscv*-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target plus current options supports a vector @@ -7882,6 +7931,7 @@ proc check_effective_target_vect_widen_sum_qi_to_hi { } { proc check_effective_target_vect_widen_sum_qi_to_si { } { return [check_cached_effective_target_indexed vect_widen_sum_qi_to_si { expr { [istarget powerpc*-*-*] + || [istarget loongarch*-*-*] || [istarget riscv*-*-*] }}] } @@ -7902,6 +7952,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi { } { || ([istarget aarch64*-*-*] && ![check_effective_target_aarch64_sve]) || [is-effective-target arm_neon] + || [is-effective-target loongarch*-*-*] || ([istarget s390*-*-*] && [check_effective_target_s390_vx])) || [istarget amdgcn-*-*] }}] @@ -7926,6 +7977,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si { } { && ![check_effective_target_aarch64_sve]) || [istarget i?86-*-*] || [istarget x86_64-*-*] || [is-effective-target arm_neon] + || [is-effective-target loongarch*-*-*] || ([istarget s390*-*-*] && [check_effective_target_s390_vx])) || [istarget amdgcn-*-*] }}] @@ -7943,6 +7995,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi_pattern { } { && [check_effective_target_arm_little_endian]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) + || [istarget loongarch*-*-*] || [istarget amdgcn-*-*] }}] } @@ -7955,6 +8008,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } { return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si_pattern { expr { [istarget powerpc*-*-*] || [istarget ia64-*-*] + || [istarget loongarch*-*-*] || [istarget i?86-*-*] || [istarget x86_64-*-*] || ([is-effective-target arm_neon] && [check_effective_target_arm_little_endian]) @@ -7972,6 +8026,7 @@ proc check_effective_target_vect_widen_mult_si_to_di_pattern { } { return [check_cached_effective_target_indexed vect_widen_mult_si_to_di_pattern { expr { [istarget ia64-*-*] || [istarget i?86-*-*] || [istarget x86_64-*-*] + || [istarget loongarch*-*-*] || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) }}] } @@ -7999,7 +8054,9 @@ proc check_effective_target_vect_sdot_qi { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options supports a vector @@ -8016,7 +8073,9 @@ proc check_effective_target_vect_udot_qi { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options supports a vector @@ -8045,7 +8104,9 @@ proc check_effective_target_vect_sdot_hi { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options supports a vector @@ -8059,7 +8120,9 @@ proc check_effective_target_vect_udot_hi { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options supports a vector @@ -8076,7 +8139,9 @@ proc check_effective_target_vect_usad_char { } { || ([istarget powerpc*-*-*] && [check_p9vector_hw_available]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options supports both signed @@ -8086,7 +8151,9 @@ proc check_effective_target_vect_avg_qi {} { return [expr { ([istarget aarch64*-*-*] && ![check_effective_target_aarch64_sve1_only]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }] } # Return 1 if the target plus current options supports both signed @@ -8125,7 +8192,9 @@ proc check_effective_target_vect_pack_trunc { } { && [check_effective_target_s390_vx]) || [istarget amdgcn*-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options supports a vector @@ -8147,7 +8216,9 @@ proc check_effective_target_vect_unpack { } { && [check_effective_target_s390_vx]) || [istarget amdgcn*-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target plus current options does not guarantee @@ -8188,7 +8259,8 @@ proc check_effective_target_vect_hw_misalign { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || ([istarget riscv*-*-*]) } { + || ([istarget riscv*-*-*]) + || ([istarget loongarch*-*-*]) } { return 1 } if { [istarget arm*-*-*] @@ -8807,7 +8879,8 @@ proc check_effective_target_vect_gather_load_ifn { } { proc check_effective_target_vect_scatter_store { } { return [expr { [check_effective_target_aarch64_sve] || [istarget amdgcn*-*-*] - || [check_effective_target_riscv_v] }] + || [check_effective_target_riscv_v] + || [check_effective_target_loongarch_sx] }] } # Return 1 if the target supports vector conditional operations, 0 otherwise. @@ -8826,7 +8899,9 @@ proc check_effective_target_vect_condition { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector conditional operations where @@ -8845,7 +8920,9 @@ proc check_effective_target_vect_cond_mixed { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector char multiplication, 0 otherwise. @@ -8863,7 +8940,9 @@ proc check_effective_target_vect_char_mult { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector short multiplication, 0 otherwise. @@ -8882,7 +8961,9 @@ proc check_effective_target_vect_short_mult { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector int multiplication, 0 otherwise. @@ -8900,7 +8981,9 @@ proc check_effective_target_vect_int_mult { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports 64 bit hardware vector @@ -8919,7 +9002,9 @@ proc check_effective_target_vect_long_mult { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) } { + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) } { set answer 1 } else { set answer 0 @@ -8936,8 +9021,6 @@ proc check_effective_target_vect_int_mod { } { expr { ([istarget powerpc*-*-*] && [check_effective_target_has_arch_pwr10]) || [istarget amdgcn-*-*] - || ([istarget loongarch*-*-*] - && [check_effective_target_loongarch_sx]) || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) }}] } @@ -8957,7 +9040,9 @@ proc check_effective_target_vect_extract_even_odd { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector interleaving, 0 otherwise. @@ -8975,7 +9060,9 @@ proc check_effective_target_vect_interleave { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } foreach N {2 3 4 5 6 7 8} { @@ -9100,7 +9187,9 @@ proc check_effective_target_vect_call_copysignf { } { || [istarget aarch64*-*-*] || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports hardware square root instructions. @@ -9139,7 +9228,9 @@ proc check_effective_target_vect_call_sqrtf { } { && [check_effective_target_s390_vx]) || [istarget amdgcn-*-*] || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] + && [check_effective_target_riscv_v]) + || ([istarget loongarch*-*-*] + && [check_effective_target_loongarch_sx]) }}] } # Return 1 if the target supports vector lrint calls. @@ -9148,7 +9239,8 @@ proc check_effective_target_vect_call_lrint { } { set et_vect_call_lrint 0 if { (([istarget i?86-*-*] || [istarget x86_64-*-*]) && [check_effective_target_ilp32]) - || [istarget amdgcn-*-*] } { + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] } { set et_vect_call_lrint 1 } @@ -9161,7 +9253,8 @@ proc check_effective_target_vect_call_lrint { } { proc check_effective_target_vect_call_btrunc { } { return [check_cached_effective_target_indexed vect_call_btrunc { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector btruncf calls. @@ -9169,7 +9262,8 @@ proc check_effective_target_vect_call_btrunc { } { proc check_effective_target_vect_call_btruncf { } { return [check_cached_effective_target_indexed vect_call_btruncf { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector ceil calls. @@ -9177,7 +9271,8 @@ proc check_effective_target_vect_call_btruncf { } { proc check_effective_target_vect_call_ceil { } { return [check_cached_effective_target_indexed vect_call_ceil { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector ceilf calls. @@ -9185,7 +9280,8 @@ proc check_effective_target_vect_call_ceil { } { proc check_effective_target_vect_call_ceilf { } { return [check_cached_effective_target_indexed vect_call_ceilf { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector floor calls. @@ -9193,7 +9289,8 @@ proc check_effective_target_vect_call_ceilf { } { proc check_effective_target_vect_call_floor { } { return [check_cached_effective_target_indexed vect_call_floor { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector floorf calls. @@ -9201,21 +9298,24 @@ proc check_effective_target_vect_call_floor { } { proc check_effective_target_vect_call_floorf { } { return [check_cached_effective_target_indexed vect_call_floorf { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [istarget amdgcn-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector lceil calls. proc check_effective_target_vect_call_lceil { } { return [check_cached_effective_target_indexed vect_call_lceil { - expr { [istarget aarch64*-*-*] }}] + expr { [istarget aarch64*-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector lfloor calls. proc check_effective_target_vect_call_lfloor { } { return [check_cached_effective_target_indexed vect_call_lfloor { - expr { [istarget aarch64*-*-*] }}] + expr { [istarget aarch64*-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports vector nearbyint calls. @@ -9252,6 +9352,7 @@ proc check_effective_target_vect_logical_reduc { } { return [expr { [check_effective_target_aarch64_sve] || [istarget amdgcn-*-*] || [check_effective_target_riscv_v] + || [check_effective_target_loongarch_sx] || [istarget i?86-*-*] || [istarget x86_64-*-*]}] } @@ -9269,7 +9370,8 @@ proc check_effective_target_section_anchors { } { return [check_cached_effective_target section_anchors { expr { [istarget powerpc*-*-*] || [istarget arm*-*-*] - || [istarget aarch64*-*-*] }}] + || [istarget aarch64*-*-*] + || [istarget loongarch*-*-*] }}] } # Return 1 if the target supports atomic operations on "int_128" values. @@ -11580,8 +11682,8 @@ proc check_vect_support_and_set_flags { } { set dg-do-what-default compile } } elseif [istarget loongarch*-*-*] { - lappend DEFAULT_VECTCFLAGS "-mdouble-float" "-mlasx" - if [check_effective_target_loongarch_asx_hw] { + lappend DEFAULT_VECTCFLAGS "-mdouble-float" "-mlsx" + if [check_effective_target_loongarch_sx_hw] { set dg-do-what-default run } else { set dg-do-what-default compile @@ -12147,7 +12249,8 @@ proc check_effective_target_builtin_eh_return { } { proc check_effective_target_vect_max_reduc { } { if { [istarget aarch64*-*-*] || [is-effective-target arm_neon] - || [check_effective_target_riscv_v] } { + || [check_effective_target_riscv_v] + || [check_effective_target_loongarch_sx] } { return 1 } return 0 @@ -13149,7 +13252,7 @@ proc check_effective_target_loongarch_sx { } { #if !defined(__loongarch_sx) #error "LSX not defined" #endif - }] + } "-mlsx"] } proc check_effective_target_loongarch_sx_hw { } { @@ -13169,7 +13272,7 @@ proc check_effective_target_loongarch_asx { } { #if !defined(__loongarch_asx) #error "LASX not defined" #endif - }] + } "-mlasx"] } proc check_effective_target_loongarch_asx_hw { } { From patchwork Fri Dec 29 02:12:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 82952 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 26ECC3858C31 for ; Fri, 29 Dec 2023 02:14:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 6F5663858D28 for ; Fri, 29 Dec 2023 02:12:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6F5663858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6F5663858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703815965; cv=none; b=qJ8GOLwj7OprEUebYajrT2D5c771WyuTvVkUIMzs1WTI8ZVOdsxWOXIJEAoCfVuJkjUb/5a89mdDf6bGyT3OtavebVvHSmEKu/9AfDO+jmsjDMyHD1fsUXzMG2VcqA9rgYhn6h+Z9CH+HNJDtEgSrfrlZahHviNOBlz0iR+mcZI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703815965; c=relaxed/simple; bh=xqDgw6TSc68/5oJGtb6r0gu1Yj/sr9SQaFBGeggfkHw=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=hF6iBnbRIJP3iY9quOXmV5R30/Ns+PDVS9CiyNyoy8Jud9D2WeKvH/cHhu5sgFNQ6Zv6dlMKUnhpx9FIVCJwBXCcBJ7eoRMjFWf0GuyzoY85optt7PAU4EAr52XhtUFkN+4wcnWUgJ4CDFM4AyiwhZoyhL4h36ASbhCZxDtMoyg= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rJ2Mc-0003vI-8F for gcc-patches@gcc.gnu.org; Thu, 28 Dec 2023 21:12:43 -0500 Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8DxfesXK45lIUwAAA--.1373S3; Fri, 29 Dec 2023 10:12:39 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxC74WK45lhAcPAA--.22262S4; Fri, 29 Dec 2023 10:12:38 +0800 (CST) From: chenxiaolong To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, tamar.christina@arm.com, burnus@net-b.de, rguenther@suse.de, chenxiaolong Subject: [PATCH v1 2/8] LoongArch: testsuite:Modify the test behavior of the vect-bic-bitmask-{12, 23}.c file. Date: Fri, 29 Dec 2023 10:12:35 +0800 Message-Id: <20231229021235.24065-1-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxC74WK45lhAcPAA--.22262S4 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAABWWM2y8T1QAAsf X-Coremail-Antispam: 1Uk129KBj93XoW7KFy7Kry8AFyrGrW3AF1rKrX_yoW8Zr4Upa n7Cr93Ar4rXF1UW3WDXFnrX3Z5Xan7GrZ8urZ7uw17CFyktr9IqFWxtr47tw13JFW2vrya vw4j9F1ruwnIvrgCm3ZEXasCq-sJn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE 14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVW8JVW5JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07j8CztUUUUU= Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenxiaolong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org When the toolchain is built using binutils that does not support vectorization and gcc that supports vectorization, the regression test results of GCC show that the vect-bic-bitmask-{12,23}.c file fails. The reason is that it carries out two stages of compilation and assembly test, in the assembly stage there is no identification of vector instructions, but in fact only need to carry out the compilation stage. To solve this problem, change the default set of assembly to compile only, so that other architectures do not have similar problems. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-bic-bitmask-12.c:Change the default setting of assembly to compile. * gcc.dg/vect/vect-bic-bitmask-23.c:Dito. --- gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c index 36ec5a8b19b..213e4c2a418 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c +++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c @@ -1,5 +1,5 @@ /* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */ -/* { dg-do assemble } */ +/* { dg-do compile } */ /* { dg-additional-options "-O3 -fdump-tree-dce -w" } */ #include diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c index 5b4c3b6e19b..5dceb4bbcb6 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c +++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c @@ -1,5 +1,5 @@ /* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */ -/* { dg-do assemble } */ +/* { dg-do compile } */ /* { dg-additional-options "-O1 -fdump-tree-dce -w" } */ #include From patchwork Fri Dec 29 02:12:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 82956 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C8FCA385829B for ; Fri, 29 Dec 2023 02:15:47 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id BF3E0385840C for ; Fri, 29 Dec 2023 02:12:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BF3E0385840C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BF3E0385840C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703815982; cv=none; b=cpX+3WCYE+V757Ktom1zHPSFy5+OYEE8qifhqRmD+KjZtoOV+1lyGJQdC6+5kJaQkQy9YzILJRBMnabEhXCoCHTIUXfWwmxVoJUnLHJEDA/uFD96Il9plclrV5/vQNJNz4lzH8SWM/gPyuaqRm+lxW8NtOEvMgg7P9SfqgbKdTA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703815982; c=relaxed/simple; bh=2uDElDdwuxasp3fixpJT2yHmKwjG2tpvje19n6g4JhQ=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=GS+lpLKx8E7ZRdG+4k2VVEF6RTB0bBKohnNBAA3yeUGxyBqk0kvBkNsuub7RiVdVKTYOgpV6sJeZLiMNrw8WXjOMjJh51igzYK1wqY8RX/y5eo8qLbbHCJ+6EVOBCykdW1Frm9ziU7VqhSN20/P+19MEpwKfidnIDYdewkDz3Vs= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8AxDOsiK45lKkwAAA--.1438S3; Fri, 29 Dec 2023 10:12:50 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cx2r0gK45lmwcPAA--.22227S4; Fri, 29 Dec 2023 10:12:49 +0800 (CST) From: chenxiaolong To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, tamar.christina@arm.com, burnus@net-b.de, rguenther@suse.de, chenxiaolong Subject: [PATCH v1 3/8] LoongArch: testsuite:Added test support for vect-{82, 83}.c. Date: Fri, 29 Dec 2023 10:12:46 +0800 Message-Id: <20231229021246.24122-1-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Cx2r0gK45lmwcPAA--.22227S4 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAABWWM2y8T2AAAsS X-Coremail-Antispam: 1Uk129KBj93XoW7CF47XF1DAF4DZw4UtryfXwc_yoW8Cr43p3 Z7CFyakw18WF1UWFnFvFn5Xr1rW3Z7JrZF9ry7KwnrCFyfJrnFvFy0yF42qr13AFWavF1S 9a18uw1ru3WYyrbCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE 14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVW8JVW5JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07jOdb8UUUUU= X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org When gcc enables the file test under gcc.dg/vect, it is found that vect-{82, 83}.c does not support the test. Through analysis, LoongArch architecture supports the detection function of this test case. Therefore, the detection of LoongArch architecture is added to the test rules to solve the situation that the test is not supported. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-82.c:Add the LoongArch architecture to the object detection framework. * gcc.dg/vect/vect-83.c:Dito. --- gcc/testsuite/gcc.dg/vect/vect-82.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-83.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.dg/vect/vect-82.c b/gcc/testsuite/gcc.dg/vect/vect-82.c index 4b2d5a8a464..5c761e92a3a 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-82.c +++ b/gcc/testsuite/gcc.dg/vect/vect-82.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "powerpc and integer vectorization only" { ! { powerpc*-*-* && vect_int } } } */ +/* { dg-skip-if "powerpc/loongarch and integer vectorization only" { ! { { powerpc*-*-* || loongarch*-*-* } && vect_int } } } */ /* { dg-additional-options "-fdump-tree-optimized-details-blocks" } */ #include diff --git a/gcc/testsuite/gcc.dg/vect/vect-83.c b/gcc/testsuite/gcc.dg/vect/vect-83.c index 1a173daa140..7fe1b050cee 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-83.c +++ b/gcc/testsuite/gcc.dg/vect/vect-83.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "powerpc and integer vectorization only" { ! { powerpc*-*-* && vect_int } } } */ +/* { dg-skip-if "powerpc/loongarch and integer vectorization only" { ! { { powerpc*-*-* || loongarch*-*-* } && vect_int } } } */ /* { dg-additional-options "-fdump-tree-optimized-details-blocks" } */ #include From patchwork Fri Dec 29 02:12:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 82957 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3CEC03858403 for ; Fri, 29 Dec 2023 02:16:12 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 40C853858D33 for ; Fri, 29 Dec 2023 02:13:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 40C853858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 40C853858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703816015; cv=none; b=eRDCC2sIs3v9PyNZtymUj1ssK5uG82QIxAFBAL1hSh/MTEViJFywawyrc4wSLm35+H+qgefzP7lbXR5VDTCFns4V1vHxpouzgONt8EyLShh1dIaHw/AsmF2soooTZKF7Swy2Z0Rn55J2ycXkXyZQQFA2/I2BLw2HynWiYlFM0d0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703816015; c=relaxed/simple; bh=qhQgXk2u3oJ/IeJxYNmzq48XprjgNXPK1ECdE2vG/S8=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=VGgL1D9XyJYI4hOAE7P6hVc2bHwZrakRKRb/p9FD8FY8Sb+ouVJsYKfDlm8jwPK4cydqwobugGiV+x6ne6GNCH8WKH0ae87kdYnS2F/ie4lsB/wwK/eqV9vIunaXEuWiYch5gy3OQr2feQrXpLi6OW8o1Y3G7WkYovShTKWaMLo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rJ2N0-0003ys-H0 for gcc-patches@gcc.gnu.org; Thu, 28 Dec 2023 21:13:12 -0500 Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8CxrustK45lMkwAAA--.1416S3; Fri, 29 Dec 2023 10:13:01 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxXOQtK45lpAcPAA--.50718S4; Fri, 29 Dec 2023 10:13:01 +0800 (CST) From: chenxiaolong To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, tamar.christina@arm.com, burnus@net-b.de, rguenther@suse.de, chenxiaolong Subject: [PATCH v1 4/8] LoongArch: testsuite:Fix FAIL in file bind_c_array_params_2.f90. Date: Fri, 29 Dec 2023 10:12:56 +0800 Message-Id: <20231229021256.24210-1-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxXOQtK45lpAcPAA--.50718S4 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAABWWM2y8T2wAAsR X-Coremail-Antispam: 1Uk129KBj93XoW7Aw17Jr4UZFyDJr1rCr1rGrX_yoW8tr4xp3 s3Aa4Ykr1DJF1Iyw1kJF4rWw4xurZrKF95uFWfG34UCanxta4Sgr4xKrW7J342ka1fWr4a vr4DZryxuFyqy3cCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE 14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07j8CztUUUUU= Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenxiaolong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org In the GCC regression test result, it is found that the bind_c_array_params_2.f90 test fails. After analysis, it is found that the reason why the test fails is that the regular expression in the test result cannot correctly detect the correct assembly code (such as bl %plt(myBindC)) generated on the LoongArch architecture, such as the assembly code generated on the x86 function call (call myBindC). gcc/testsuite/ChangeLog: * gfortran.dg/bind_c_array_params_2.f90:Add code test rules to support testing of the loongArch architecture. --- gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90 | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90 b/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90 index 0825efc7a2f..aa6a37b4850 100644 --- a/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90 +++ b/gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90 @@ -2,6 +2,7 @@ ! { dg-options "-std=f2008ts -fdump-tree-original" } ! { dg-additional-options "-mno-explicit-relocs" { target alpha*-*-* } } ! { dg-additional-options "-mno-relax-pic-calls" { target mips*-*-* } } +! { dg-additional-options "-fplt -mcmodel=normal" { target loongarch*-*-* } } ! ! Check that assumed-shape variables are correctly passed to BIND(C) ! as defined in TS 29913 @@ -16,7 +17,8 @@ integer :: aa(4,4) call test(aa) end -! { dg-final { scan-assembler-times "\[ \t\]\[$,_0-9\]*myBindC" 1 { target { ! { hppa*-*-* s390*-*-* *-*-cygwin* amdgcn*-*-* powerpc-ibm-aix* *-*-ming* } } } } } +! { dg-final { scan-assembler-times "\[ \t\]\[$,_0-9\]*myBindC" 1 { target { ! { hppa*-*-* s390*-*-* *-*-cygwin* amdgcn*-*-* powerpc-ibm-aix* *-*-ming* loongarch*-*-* } } } } } +! { dg-final { scan-assembler-times "bl\t%plt\\(myBindC\\)" 1 { target loongarch*-*-* } } } ! { dg-final { scan-assembler-times "myBindC,%r2" 1 { target { hppa*-*-* } } } } ! { dg-final { scan-assembler-times "call\tmyBindC" 1 { target { *-*-cygwin* *-*-ming* } } } } ! { dg-final { scan-assembler-times "brasl\t%r\[0-9\]*,myBindC" 1 { target { s390*-*-* } } } } From patchwork Fri Dec 29 02:13:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 82953 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 122253858C50 for ; Fri, 29 Dec 2023 02:14:49 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 775133858CD1 for ; Fri, 29 Dec 2023 02:13:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 775133858CD1 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 775133858CD1 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703816015; cv=none; b=pG56r1yhinO6UJZNzmhuA/eAl04CmyijtwrEbvzMxvJYQ5V9uvyPyJ57l6pyTd2Uqt36oIXrq+dS7xxphhcrcUqTswYcFYbiiK0NpfOwMw+i7krJdhHTFgRcQ4sVt0wWcv5vhpNgeyovJQ2MXFkxncoG+EINeRBrPLVXKQO48Ig= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703816015; c=relaxed/simple; bh=7n11zR1nLS8W+hil3vZQBzGDDD/930nlpWv582WHKC8=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=PTL282C7zqtlG3rUNnJzBhb59TRd0A9DrtiXS0yOFsD82bZR9C4U68EL+pJS627HmhvAf0Agx78tKG6Bixi2sFjA8H2XaLRUcuCNZ/j4GD4/gXLDChjslIz3pHvgu/8m1fzjSCC/HYMF76D5ym3RBradHwMTgxzOiy+6WyqSFac= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rJ2N9-00048G-Jp for gcc-patches@gcc.gnu.org; Thu, 28 Dec 2023 21:13:17 -0500 Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8AxnvA3K45lPUwAAA--.1440S3; Fri, 29 Dec 2023 10:13:11 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cxfb42K45ltgcPAA--.43046S4; Fri, 29 Dec 2023 10:13:10 +0800 (CST) From: chenxiaolong To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, tamar.christina@arm.com, burnus@net-b.de, rguenther@suse.de, chenxiaolong Subject: [PATCH v1 5/8] LoongArch: testsuite:Modify the test behavior in file pr60510.f. Date: Fri, 29 Dec 2023 10:13:08 +0800 Message-Id: <20231229021308.24800-1-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Cxfb42K45ltgcPAA--.43046S4 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAABWWM2y8T3wAAsV X-Coremail-Antispam: 1Uk129KBj9xXoWrur1rZryrKr4xJFyfJry3KFX_yoWkKrcEva ykZF4xCw4UAws5Aw1xGw17Kr4vga90934fGF48Kw1xt3Wvqan8KrnrCFyxZF1UCFn3JFW7 GryfJF1Sk3sFgosvyTuYvTs0mTUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvT s0mT0YCTnIWjqI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUI cSsGvfJTRUUUb7AYFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20x vaj40_Wr0E3s1l1IIY67AEw4v_JrI_Jryl8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxS w2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxV W8JVWxJwA2z4x0Y4vEx4A2jsIE14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc 02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUtVWrXwAv7VC2z280aVAF wI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28IcxkI7V AKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCj r7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6x IIjxv20xvE14v26ryj6F1UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAI w20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x 0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8QJ57UUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenxiaolong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org When using binutils that does not support vectorization and gcc compiler toolchain that supports vectorization, regression tests found that pr60510.f had a FAIL entry. The reason is that the default setting of the program is the execution state, which will cause problems in the assembly stage when the vector instructions cannot be identified. In order to solve this problem, the default behavior set to run was removed, and the behavior of the program depends on whether the software supports vectorization or not. gcc/testsuite/ChangeLog: * gfortran.dg/vect/pr60510.f:Delete the default behavior of the program. --- gcc/testsuite/gfortran.dg/vect/pr60510.f | 1 - 1 file changed, 1 deletion(-) diff --git a/gcc/testsuite/gfortran.dg/vect/pr60510.f b/gcc/testsuite/gfortran.dg/vect/pr60510.f index 6cae82acece..d4fd42a664a 100644 --- a/gcc/testsuite/gfortran.dg/vect/pr60510.f +++ b/gcc/testsuite/gfortran.dg/vect/pr60510.f @@ -1,4 +1,3 @@ -! { dg-do run } ! { dg-require-effective-target vect_double } ! { dg-require-effective-target vect_intdouble_cvt } ! { dg-additional-options "-fno-inline -ffast-math" } From patchwork Fri Dec 29 02:13:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 82955 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8B7483858D28 for ; Fri, 29 Dec 2023 02:15:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 1AEBF3858C52 for ; Fri, 29 Dec 2023 02:13:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1AEBF3858C52 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1AEBF3858C52 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703816015; cv=none; b=r7lIp9vny/GYX1dRNnYmjoWXFVvUPizXo+Po7FWQhoZar9teAzxMzgxwkOqlsNQEyhLSDi0nme06pXZspWFdkBo21RyL7nKF+65mHE6GaQVgXqt2lhF1SACUHnYJtzenJ8y9CsP1tfNB0MDO09GybuZVh0kalxsRiQIT3nh9vdk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703816015; c=relaxed/simple; bh=YOV23xtXFzizMdb//Pb6ixKWFpWhWr+xQ1tgbHTN5r0=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=D9vAHvRzmyKkk7W4towQJzt6BL2gplRTnj4lIYoJMDmX2AslyjfwUe2S4dneAk3abSajpNRN8TIMh1fWCy63uv96dHqDWuWREPwlD0jSP06ke8LO9fAc5y17F0OPiGyh2CVnzKqMez1Po8x9yRxhMmcucz5MBdYTpsnFNQndpIU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rJ2NH-00049q-Sr for gcc-patches@gcc.gnu.org; Thu, 28 Dec 2023 21:13:25 -0500 Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8CxbetAK45lREwAAA--.1380S3; Fri, 29 Dec 2023 10:13:20 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxzuQ_K45lzAcPAA--.50803S4; Fri, 29 Dec 2023 10:13:19 +0800 (CST) From: chenxiaolong To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, tamar.christina@arm.com, burnus@net-b.de, rguenther@suse.de, chenxiaolong Subject: [PATCH v1 6/8] LoongArch: testsuite:Added additional vectorization "-mlasx" compilation option. Date: Fri, 29 Dec 2023 10:13:18 +0800 Message-Id: <20231229021318.28603-1-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxzuQ_K45lzAcPAA--.50803S4 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAABWWM2y8T4wAAsp X-Coremail-Antispam: 1Uk129KBj93XoW3WrWxWrW7Ar43ZF48ZF18WFX_yoW3WF18pa nxCFySkr1rWF1UurnruF93Zas3GasrWrZ09r1fKw4IkFy3KrnFvw18tr47JF13ZFWF9r1f Zw48ur1ru3WYvwbCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Wrv_ZF1lYx0Ex4A2jsIE 14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07jxKsUUUUUU= Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenxiaolong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org After the detection procedure under the gcc.dg/vect directory was added to GCC, FAIL entries of vector multiplication transformations of different types appeared in the gcc regression test results. After debugging analysis, the main problem is that the 128-bit vector of LoongArch architecture does not realize this function. To solve this problem, the "-mlasx" option is used to enable the 256-bit vectorization implementation. gcc/testsuite/ChangeLog: * gcc.dg/vect/bb-slp-pattern-1.c:If you are testing on the LoongArch architecture, you need to add the "-mlasx" compilation option to generate vectorized code. * gcc.dg/vect/slp-widen-mult-half.c:Dito. * gcc.dg/vect/vect-widen-mult-const-s16.c:Dito. * gcc.dg/vect/vect-widen-mult-const-u16.c:Dito. * gcc.dg/vect/vect-widen-mult-half-u8.c:Dito. * gcc.dg/vect/vect-widen-mult-half.c:Dito. * gcc.dg/vect/vect-widen-mult-u16.c:Dito. * gcc.dg/vect/vect-widen-mult-u8-s16-s32.c:Dito. * gcc.dg/vect/vect-widen-mult-u8-u32.c:Dito. * gcc.dg/vect/vect-widen-mult-u8.c:Dito. --- gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c | 1 + gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c | 1 + gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c | 1 + 10 files changed, 10 insertions(+) diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c index a3ff0f5b3da..5ae99225273 100644 --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c @@ -1,4 +1,5 @@ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-* } } */ #include #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c b/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c index 72811eb852e..b69ade33886 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c +++ b/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c @@ -1,6 +1,7 @@ /* Disabling epilogues until we find a better way to deal with scans. */ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-* } } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c index dfbb2171c00..53c9b84ca01 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c @@ -2,6 +2,7 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ /* { dg-additional-options "-fno-ipa-icf" } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c index c2ad58f69e7..e9db8285b66 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c @@ -2,6 +2,7 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ /* { dg-additional-options "-fno-ipa-icf" } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c index bfdcbaa09fb..607f3178f90 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c @@ -2,6 +2,7 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ /* { dg-additional-options "-fno-ipa-icf" } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c index e46b0cc3135..cd13d826937 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c @@ -1,6 +1,7 @@ /* Disabling epilogues until we find a better way to deal with scans. */ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c index 14411ef43ed..258d253f401 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c @@ -1,6 +1,7 @@ /* Disabling epilogues until we find a better way to deal with scans. */ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c index f40def5dddf..3baafca7b54 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-s16-s32.c @@ -1,6 +1,7 @@ /* Disabling epilogues until we find a better way to deal with scans. */ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c index 63866390835..bcfbe198a3f 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8-u32.c @@ -1,5 +1,6 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-* } } */ #include #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c index 78ad74b5d49..e3bf13b14fa 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c +++ b/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c @@ -1,5 +1,6 @@ /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ /* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-mlasx" { target loongarch*-*-*} } */ #include #include "tree-vect.h" From patchwork Fri Dec 29 02:13:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 82954 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with 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vectorization "-mlsx" compilation option. Date: Fri, 29 Dec 2023 10:13:27 +0800 Message-Id: <20231229021327.30356-1-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bxrr5JK45l3gcPAA--.43633S4 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAABWWM2y8T5gAAss X-Coremail-Antispam: 1Uk129KBj93XoWxurW3XFWrtrWDAFykXw17twc_yoW5tFW7pw nxuryxKw18GF1kWr17XrWIyF4rG392gFZ8uFyxKw4IvF4xJryIqa4rKFW3JF13ZFW3Xr1f Zw4Dury5Z3Wa9wbCm3ZEXasCq-sJn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkIb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Cr0_Gr1UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI 0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWrXVW3AwAv7VC2z280 aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26F1j6w1UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aV CY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU04v3UUUUUU== X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org When GCC is able to detect vectorized test cases in the common layer, FAIL entries appear in some test cases after regression testing. The cause of the error is that the vectorization option was not set when testing the program, and the vectorization code could not be generated, so additional support for the "-mlsx" option needed to be added back on the LoongArch architecture. gcc/testsuite/ChangeLog: * gcc.dg/signbit-2.c:Added additional "-mlsx" compilation options. * gcc.dg/tree-ssa/scev-16.c:Dito. * gfortran.dg/graphite/vect-pr40979.f90:Dito. * gfortran.dg/vect/fast-math-mgrid-resid.f:Dito. --- gcc/testsuite/gcc.dg/signbit-2.c | 1 + gcc/testsuite/gcc.dg/tree-ssa/scev-16.c | 1 + gcc/testsuite/gfortran.dg/graphite/vect-pr40979.f90 | 1 + gcc/testsuite/gfortran.dg/vect/fast-math-mgrid-resid.f | 1 + 4 files changed, 4 insertions(+) diff --git a/gcc/testsuite/gcc.dg/signbit-2.c b/gcc/testsuite/gcc.dg/signbit-2.c index 62bb4047d74..2f65df16e43 100644 --- a/gcc/testsuite/gcc.dg/signbit-2.c +++ b/gcc/testsuite/gcc.dg/signbit-2.c @@ -5,6 +5,7 @@ /* { dg-additional-options "-msse2 -mno-avx512f" { target { i?86-*-* x86_64-*-* } } } */ /* { dg-additional-options "-march=armv8-a" { target aarch64_sve } } */ /* { dg-additional-options "-maltivec" { target powerpc_altivec_ok } } */ +/* { dg-additional-options "-mlsx" { target loongarch*-*-* } } */ /* { dg-skip-if "no fallback for MVE" { arm_mve } } */ #include diff --git a/gcc/testsuite/gcc.dg/tree-ssa/scev-16.c b/gcc/testsuite/gcc.dg/tree-ssa/scev-16.c index 120f40c0b6c..acaa1156419 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/scev-16.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/scev-16.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target vect_int } */ /* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */ +/* { dg-additional-options "-mlsx" { target loongarch*-*-* } } */ int A[1024 * 2]; diff --git a/gcc/testsuite/gfortran.dg/graphite/vect-pr40979.f90 b/gcc/testsuite/gfortran.dg/graphite/vect-pr40979.f90 index a42290948c4..4c251aacbe3 100644 --- a/gcc/testsuite/gfortran.dg/graphite/vect-pr40979.f90 +++ b/gcc/testsuite/gfortran.dg/graphite/vect-pr40979.f90 @@ -1,6 +1,7 @@ ! { dg-do compile } ! { dg-require-effective-target vect_double } ! { dg-additional-options "-msse2" { target { { i?86-*-* x86_64-*-* } && ilp32 } } } +! { dg-additional-options "-mlsx" { target loongarch*-*-* } } module mqc_m integer, parameter, private :: longreal = selected_real_kind(15,90) diff --git a/gcc/testsuite/gfortran.dg/vect/fast-math-mgrid-resid.f b/gcc/testsuite/gfortran.dg/vect/fast-math-mgrid-resid.f index 08965cc5e20..97b88821731 100644 --- a/gcc/testsuite/gfortran.dg/vect/fast-math-mgrid-resid.f +++ b/gcc/testsuite/gfortran.dg/vect/fast-math-mgrid-resid.f @@ -2,6 +2,7 @@ ! { dg-require-effective-target vect_double } ! { dg-options "-O3 --param vect-max-peeling-for-alignment=0 -fpredictive-commoning -fdump-tree-pcom-details -std=legacy" } ! { dg-additional-options "-mprefer-avx128" { target { i?86-*-* x86_64-*-* } } } +! { dg-additional-options "-mlsx" { target { loongarch*-*-* } } } ! { dg-additional-options "-mzarch" { target { s390*-*-* } } } ******* RESID COMPUTES THE RESIDUAL: R = V - AU From patchwork Fri Dec 29 02:13:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 82958 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 48E313858421 for ; Fri, 29 Dec 2023 02:16:44 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 393093858409 for ; Fri, 29 Dec 2023 02:13:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 393093858409 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 393093858409 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703816029; cv=none; b=i+XKKlmbdsGIQhWlblLsBxZcOHfd7IkXpS+FSYaQEJUnwPuT7Gpas7w/KnbYRekTTehAuxZ4SIruE0iqRrldDcLPmSQqo/YnXL1UG7rlT6CHvAzuTbNspOIEwZtFB4OoRb+kEw3L+m8N9bIga6i3O45gqbLOvJVBVgXvu+qjiGk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703816029; c=relaxed/simple; bh=PVUnzv+Rqub8a4RHl7KwmbGfZ399jqObuENppDPzW7s=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Zs2HJu66D9jMrbiC4Ri4wm9FE2h5mQMs86FadQzt0nR6iUkjfbHHJMtTRd4E9XD2DObpnL9kWxsqtpRPDjPKUIAf5WQKnBfcuoLV7OdEZYd5slW5aRxLM+yLHxO6Fjjn7HRczjxx+RV+tZTumBH2/pkQQkXw5qW0eNa/FqQ/DAU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rJ2Na-0004IM-8e for gcc-patches@gcc.gnu.org; Thu, 28 Dec 2023 21:13:43 -0500 Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8CxbetUK45lV0wAAA--.1384S3; Fri, 29 Dec 2023 10:13:40 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxG+RTK45l8QcPAA--.50162S4; Fri, 29 Dec 2023 10:13:39 +0800 (CST) From: chenxiaolong To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, tamar.christina@arm.com, burnus@net-b.de, rguenther@suse.de, chenxiaolong Subject: [PATCH v1 8/8] LoongArch: testsuite:Modify the result check in the FMA file. Date: Fri, 29 Dec 2023 10:13:37 +0800 Message-Id: <20231229021337.32306-1-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxG+RTK45l8QcPAA--.50162S4 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAABWWM2y8T6AAAsi X-Coremail-Antispam: 1Uk129KBj93XoWxGryUGF4DZFWxXFyrZryktFc_yoW5ZrWxpa 1UXr9xKr1rGF1kGrn7Xrnrtw1rXanrKrW5uF1vyr42v3s3JF9FqayktF47XFy3JFW7Wryf Zr4Du3WUua4qk3XCm3ZEXasCq-sJn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkSb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Cr0_Gr1UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI 0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWrXVW3AwAv7VC2z280 aVAFwI0_Cr0_Gr1UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20x vY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I 3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIx AIcVC0I7IYx2IY67AKxVW7JVWDJwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAI cVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26F4j6r4UJwCI42IY6I8E87 Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxU4E_MDUUUU Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenxiaolong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org When gcc enabled the vectorization of the common layer, some FAIL items appeared in GCC regression tests, such as gcc.dg/fma-{3,4,6,7}.c. On LoongArch architecture, for example, the result of fmsub.s instruction is a*b-c, and there is a problem of positive and negative zero inequality between the result of c-a*b expected to be calculated, so the detection of such problems in LoongArch architecture needs to be set to unsupported state. gcc/testsuite/ChangeLog: * gcc.dg/fma-3.c:The intermediate file corresponding to the function does not produce the corresponding FNMA symbol, so the test rules should be skipped when testing. * gcc.dg/fma-4.c:The intermediate file corresponding to the function does not produce the corresponding FNMS symbol, so skip the test rules when testing. * gcc.dg/fma-6.c:The cause is the same as fma-3.c. * gcc.dg/fma-7.c:The cause is the same as fma-4.c --- gcc/testsuite/gcc.dg/fma-3.c | 2 +- gcc/testsuite/gcc.dg/fma-4.c | 2 +- gcc/testsuite/gcc.dg/fma-6.c | 2 +- gcc/testsuite/gcc.dg/fma-7.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.dg/fma-3.c b/gcc/testsuite/gcc.dg/fma-3.c index 699aa2c9530..6649b54b6f9 100644 --- a/gcc/testsuite/gcc.dg/fma-3.c +++ b/gcc/testsuite/gcc.dg/fma-3.c @@ -12,4 +12,4 @@ f2 (double a, double b, double c) return c - a * b; } -/* { dg-final { scan-tree-dump-times { = \.FNMA \(} 2 "widening_mul" { target scalar_all_fma } } } */ +/* { dg-final { scan-tree-dump-times { = \.FNMA \(} 2 "widening_mul" { target { scalar_all_fma && { ! loongarch*-*-* } } } } } */ diff --git a/gcc/testsuite/gcc.dg/fma-4.c b/gcc/testsuite/gcc.dg/fma-4.c index bff928f1fac..f1701c1961a 100644 --- a/gcc/testsuite/gcc.dg/fma-4.c +++ b/gcc/testsuite/gcc.dg/fma-4.c @@ -12,4 +12,4 @@ f2 (double a, double b, double c) return -(a * b) - c; } -/* { dg-final { scan-tree-dump-times { = \.FNMS \(} 2 "widening_mul" { target scalar_all_fma } } } */ +/* { dg-final { scan-tree-dump-times { = \.FNMS \(} 2 "widening_mul" { target { scalar_all_fma && { ! loongarch*-*-* } } } } } */ diff --git a/gcc/testsuite/gcc.dg/fma-6.c b/gcc/testsuite/gcc.dg/fma-6.c index 87258cec4a2..9e49b62b6de 100644 --- a/gcc/testsuite/gcc.dg/fma-6.c +++ b/gcc/testsuite/gcc.dg/fma-6.c @@ -64,4 +64,4 @@ f10 (double a, double b, double c) return -__builtin_fma (a, b, -c); } -/* { dg-final { scan-tree-dump-times { = \.FNMA \(} 14 "optimized" { target scalar_all_fma } } } */ +/* { dg-final { scan-tree-dump-times { = \.FNMA \(} 14 "optimized" { target { scalar_all_fma && { ! loongarch*-*-* } } } } } */ diff --git a/gcc/testsuite/gcc.dg/fma-7.c b/gcc/testsuite/gcc.dg/fma-7.c index f409cc8ee3c..86aacad7b90 100644 --- a/gcc/testsuite/gcc.dg/fma-7.c +++ b/gcc/testsuite/gcc.dg/fma-7.c @@ -64,4 +64,4 @@ f10 (double a, double b, double c) return -__builtin_fma (a, b, c); } -/* { dg-final { scan-tree-dump-times { = \.FNMS \(} 14 "optimized" { target scalar_all_fma } } } */ +/* { dg-final { scan-tree-dump-times { = \.FNMS \(} 14 "optimized" { target { scalar_all_fma && { ! loongarch*-*-* } } } } } */