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TI=SMTPD_---0Vz9bb.o_1703494169; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vz9bb.o_1703494169) by smtp.aliyun-inc.com; Mon, 25 Dec 2023 16:49:31 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, juzhe.zhong@rivai.ai, jeffreyalaw@gmail.com, cooper.qu@linux.alibaba.com, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH] RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extension Date: Mon, 25 Dec 2023 16:49:21 +0800 Message-Id: <20231225084921.2059-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Spam-Status: No, score=-20.6 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org In order to make it easier to complete the compiler's support for the XTheadVector extension and to be as compatible as possible with the programming model of the 'V' extension ([1]), we consider adding a few pseudo instructions ([2]). th.vmmv.m vd,vs => th.vmand.mm vd,vs,vs th.vneg.v vd,vs => th.vrsub.vx vd,vs,x0 th.vncvt.x.x.v vd,vs,vm => th.vnsrl.vx vd,vs,x0,vm th.vfneg.v vd,vs => th.vfsgnjn.vv vd,vs,vs th.vfabs.v vd,vs => th.vfsgnjx.vv vd,vs,vs Ref: [1] https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641302.html [2] https://github.com/T-head-Semi/thead-extension-spec/pull/40 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for new pseudoinstructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. opcodes/ChangeLog: * riscv-opc.c: Add new pseudoinstructions. --- gas/testsuite/gas/riscv/x-thead-vector.d | 9 +++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 15 +++++++++++++++ opcodes/riscv-opc.c | 5 +++++ 3 files changed, 29 insertions(+) diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index 17b30dd1064..836150a1498 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -983,6 +983,8 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+e3057207[ ]+th.vlseg8eff.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+e3057207[ ]+th.vlseg8eff.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+e1057207[ ]+th.vlseg8eff.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+0e804257[ ]+th.vneg.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+0c804257[ ]+th.vneg.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+02860257[ ]+th.vadd.vv[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+0285c257[ ]+th.vadd.vx[ ]+v4,v8,a1 [ ]+[0-9a-f]+:[ ]+0287b257[ ]+th.vadd.vi[ ]+v4,v8,15 @@ -1099,6 +1101,8 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a485c257[ ]+th.vsra.vx[ ]+v4,v8,a1,v0.t [ ]+[0-9a-f]+:[ ]+a480b257[ ]+th.vsra.vi[ ]+v4,v8,1,v0.t [ ]+[0-9a-f]+:[ ]+a48fb257[ ]+th.vsra.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+b2804257[ ]+th.vncvt.x.x.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+b0804257[ ]+th.vncvt.x.x.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+b2860257[ ]+th.vnsrl.vv[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+b285c257[ ]+th.vnsrl.vx[ ]+v4,v8,a1 [ ]+[0-9a-f]+:[ ]+b280b257[ ]+th.vnsrl.vi[ ]+v4,v8,1 @@ -1489,6 +1493,10 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+10865257[ ]+th.vfmin.vf[ ]+v4,v8,fa2,v0.t [ ]+[0-9a-f]+:[ ]+18861257[ ]+th.vfmax.vv[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+18865257[ ]+th.vfmax.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+26841257[ ]+th.vfneg.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+24841257[ ]+th.vfneg.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+2a841257[ ]+th.vfabs.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+28841257[ ]+th.vfabs.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+22861257[ ]+th.vfsgnj.vv[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+22865257[ ]+th.vfsgnj.vf[ ]+v4,v8,fa2 [ ]+[0-9a-f]+:[ ]+26861257[ ]+th.vfsgnjn.vv[ ]+v4,v8,v12 @@ -1594,6 +1602,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+cc861257[ ]+th.vfwredosum.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+c4861257[ ]+th.vfwredsum.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+66842257[ ]+th.vmcpy.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+66842257[ ]+th.vmcpy.m[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+6e422257[ ]+th.vmclr.m[ ]+v4 [ ]+[0-9a-f]+:[ ]+7e422257[ ]+th.vmset.m[ ]+v4 [ ]+[0-9a-f]+:[ ]+76842257[ ]+th.vmnot.m[ ]+v4,v8 diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index 43c63a45735..92315b52b44 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -1007,6 +1007,10 @@ th.vlseg8eff.v v4, 0(a0) th.vlseg8eff.v v4, (a0), v0.t + # Aliases + th.vneg.v v4, v8 + th.vneg.v v4, v8, v0.t + th.vadd.vv v4, v8, v12 th.vadd.vx v4, v8, a1 th.vadd.vi v4, v8, 15 @@ -1132,6 +1136,10 @@ th.vsra.vi v4, v8, 1, v0.t th.vsra.vi v4, v8, 31, v0.t + # Aliases + th.vncvt.x.x.v v4, v8 + th.vncvt.x.x.v v4, v8, v0.t + th.vnsrl.vv v4, v8, v12 th.vnsrl.vx v4, v8, a1 th.vnsrl.vi v4, v8, 1 @@ -1540,6 +1548,12 @@ th.vfmax.vv v4, v8, v12, v0.t th.vfmax.vf v4, v8, fa2, v0.t + # Aliases + th.vfneg.v v4, v8 + th.vfneg.v v4, v8, v0.t + th.vfabs.v v4, v8 + th.vfabs.v v4, v8, v0.t + th.vfsgnj.vv v4, v8, v12 th.vfsgnj.vf v4, v8, fa2 th.vfsgnjn.vv v4, v8, v12 @@ -1659,6 +1673,7 @@ th.vfwredsum.vs v4, v8, v12, v0.t # Aliases + th.vmmv.m v4, v8 th.vmcpy.m v4, v8 th.vmclr.m v4 th.vmset.m v4 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index d5619ddbc41..acb342ab7cf 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2591,6 +2591,7 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vamominud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUDV, MASK_TH_VAMOMINUDV, match_opcode, INSN_DREF}, {"th.vamomaxuw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUWV, MASK_TH_VAMOMAXUWV, match_opcode, INSN_DREF}, {"th.vamomaxud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUDV, MASK_TH_VAMOMAXUDV, match_opcode, INSN_DREF}, +{"th.vneg.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_opcode, INSN_ALIAS }, {"th.vadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_opcode, 0 }, {"th.vadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_opcode, 0 }, {"th.vadd.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_opcode, 0 }, @@ -2645,6 +2646,7 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vsra.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_opcode, 0 }, {"th.vsra.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_opcode, 0 }, {"th.vsra.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_opcode, 0 }, +{"th.vncvt.x.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_opcode, INSN_ALIAS }, {"th.vnsrl.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_opcode, 0 }, {"th.vnsrl.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_opcode, 0 }, {"th.vnsrl.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_opcode, 0 }, @@ -2819,6 +2821,8 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vfmin.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0}, {"th.vfmax.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0}, {"th.vfmax.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0}, +{"th.vfneg.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VuVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vs1_eq_vs2, INSN_ALIAS }, +{"th.vfabs.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VuVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vs1_eq_vs2, INSN_ALIAS }, {"th.vfsgnj.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0}, {"th.vfsgnj.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0}, {"th.vfsgnjn.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0}, @@ -2873,6 +2877,7 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vfwredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0}, {"th.vfwredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, 0}, {"th.vmcpy.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS}, +{"th.vmmv.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS}, {"th.vmclr.m", 0, INSN_CLASS_XTHEADVECTOR, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS}, {"th.vmset.m", 0, INSN_CLASS_XTHEADVECTOR, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS}, {"th.vmnot.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS},