From patchwork Fri Dec 22 10:14:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 82753 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9C96F3858C29 for ; Fri, 22 Dec 2023 10:14:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 2EA8E3858D28 for ; Fri, 22 Dec 2023 10:14:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2EA8E3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2EA8E3858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=162.254.253.69 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703240051; cv=none; b=fGwUNOo4ykZEc0gWBjHqMsHrrBIsD8Qn6KgjLmavpr4OQzF8P9NeLLGCbdkAkeu7Sl4wqS80uaF9xC/2PSrIt5UD8G8qPmvf9Z+kR/1Cu4MMvepuaUHxpFAyapgkoL4LRM0RtTo98pAz9R3I/mAkeghhrFAxlEgk3xZDoVaK0vo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703240051; c=relaxed/simple; bh=dsxS9AFh6e9T5LQR+qFO7LnsMGACr6uHdM5OeAbQZx0=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Pfos+/akMrMjk4A5NFmayc8izpKn2BI0qjAo+TmdTbd6P0Tsc1MyEywt927oIqOpLoV+e7rHH+iwTqliTN0TBI8fVurYG2vzKpfyf+2O+MHLHxyUZMCPyaHD5jg5FbaYexWIbZTK6K8IpmNtVj4E5KDvE3DNLSZYS0Yvexe+Bkc= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=uv0S2CYZqKyjy2pY0eTfR3UONbcIVWw8TXeeeQZFbVI=; b=YuI/X+A/25Kh3D4dE5s8WWYm1b zIFrzQicY4XNrXh1owIcSBKRcjki/8sYbp/KUPhThTDplkjnmjndvcPY3X6pA2lnpX+JlHnJekkeY AVkVJqJaS2Dda6xDfT7/wx6NOiYINREWg/fqlosmPgS9iNaO3CwCj44j7jWQz97aiYZWLhnT5jkjU sgShmV6zNsx9H1wrKgqinygFX8Wqw1/ixe72rlkY9FQniS2EFnHmB4bZ6T0O3UuZUmHybWP/m7z9c TwgbjVSn21xCi0y6+yVbz4tMB/zbY2Ci9wSmhHNYJ6bJFZQTkqaK86joi9TwHQEFL3pxQduSWdD90 /HY1652A==; Received: from [167.98.85.149] (port=64857 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1rGcXh-0001KU-0r; Fri, 22 Dec 2023 05:14:09 -0500 From: "Roger Sayle" To: Cc: "'Uros Bizjak'" Subject: [x86_PATCH] peephole2 to resolve failure of gcc.target/i386/pr43644-2.c Date: Fri, 22 Dec 2023 10:14:06 -0000 Message-ID: <026301da34bf$9992e5f0$ccb8b1d0$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: Ado0vw9SM0nt3Ze5QJuCL9WtyuH9/A== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_ABUSEAT, RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_SBL_CSS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org This patch resolves the failure of pr43644-2.c in the testsuite, a code quality test I added back in July, that started failing as the code GCC generates for 128-bit values (and their parameter passing) has been in flux. After a few attempts at tweaking pattern constraints in the hope of convincing reload to produce a more aggressive (but potentially unsafe) register allocation, I think the best solution is to use a peephole2 to catch/clean-up this specific case. Specifically, the function: unsigned __int128 foo(unsigned __int128 x, unsigned long long y) { return x+y; } currently generates: foo: movq %rdx, %rcx movq %rdi, %rax movq %rsi, %rdx addq %rcx, %rax adcq $0, %rdx ret and with this patch/peephole2 now generates: foo: movq %rdx, %rax movq %rsi, %rdx addq %rdi, %rax adcq $0, %rdx ret which I believe is optimal. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32} with no new failures. Ok for mainline? 2023-12-21 Roger Sayle gcc/ChangeLog PR target/43644 * config/i386/i386.md (define_peephole2): Tweak register allocation of *add3_doubleword_concat_zext. gcc/testsuite/ChangeLog PR target/43644 * gcc.target/i386/pr43644-2.c: Expect 2 movq instructions. Thanks in advance, and for your patience with this testsuite noise. Roger diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index e862368..5967208 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -6428,6 +6428,38 @@ (clobber (reg:CC FLAGS_REG))])] "split_double_mode (mode, &operands[0], 1, &operands[0], &operands[5]);") +(define_peephole2 + [(set (match_operand:SWI48 0 "general_reg_operand") + (match_operand:SWI48 1 "general_reg_operand")) + (set (match_operand:SWI48 2 "general_reg_operand") + (match_operand:SWI48 3 "general_reg_operand")) + (set (match_dup 1) (match_operand:SWI48 4 "general_reg_operand")) + (parallel [(set (reg:CCC FLAGS_REG) + (compare:CCC + (plus:SWI48 (match_dup 2) (match_dup 0)) + (match_dup 2))) + (set (match_dup 2) + (plus:SWI48 (match_dup 2) (match_dup 0)))])] + "REGNO (operands[0]) != REGNO (operands[1]) + && REGNO (operands[0]) != REGNO (operands[2]) + && REGNO (operands[0]) != REGNO (operands[3]) + && REGNO (operands[0]) != REGNO (operands[4]) + && REGNO (operands[1]) != REGNO (operands[2]) + && REGNO (operands[1]) != REGNO (operands[3]) + && REGNO (operands[1]) != REGNO (operands[4]) + && REGNO (operands[2]) != REGNO (operands[3]) + && REGNO (operands[2]) != REGNO (operands[4]) + && REGNO (operands[3]) != REGNO (operands[4]) + && peep2_reg_dead_p (4, operands[0])" + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 1) (match_dup 4)) + (parallel [(set (reg:CCC FLAGS_REG) + (compare:CCC + (plus:SWI48 (match_dup 2) (match_dup 3)) + (match_dup 2))) + (set (match_dup 2) + (plus:SWI48 (match_dup 2) (match_dup 3)))])]) + (define_insn "*add_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r,r,r,r,r,r") (plus:SWI48 diff --git a/gcc/testsuite/gcc.target/i386/pr43644-2.c b/gcc/testsuite/gcc.target/i386/pr43644-2.c index d470b0a..3316ac6 100644 --- a/gcc/testsuite/gcc.target/i386/pr43644-2.c +++ b/gcc/testsuite/gcc.target/i386/pr43644-2.c @@ -6,4 +6,4 @@ unsigned __int128 foo(unsigned __int128 x, unsigned long long y) return x+y; } -/* { dg-final { scan-assembler-times "movq" 1 } } */ +/* { dg-final { scan-assembler-times "movq" 2 } } */