From patchwork Thu Dec 21 11:11:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaydeep Patil X-Patchwork-Id: 82666 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 803AD3858C2A for ; Thu, 21 Dec 2023 11:12:16 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) by sourceware.org (Postfix) with ESMTPS id 35C173858C52 for ; Thu, 21 Dec 2023 11:12:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 35C173858C52 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=imgtec.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=imgtec.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 35C173858C52 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703157123; cv=none; b=T+jqsDcZFeLxR6bs01k2mrSyFVEgiOKMdqtaSorSapKBelHeWq59c4WXB68NEJGEuYDhNyRaDbNgPsar5xVg+qVRT3AkekmEd74y7OIAsc5Xjhq0b6MyYcrXck/+zUFuMskoQCI52rkes1lP58wL2iCiV66ka38FOl9q8RnshJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703157123; c=relaxed/simple; bh=46le165ZkaquqmTeFb72kEQj4H++UZPQ+kPETKfNMx4=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=ZQz2jZRpwU7c+yVddD4bCD1WAEVGnzRp783Sm7CbB0RdfCW65p/Pc+VEyORNcP/12uuLPVyZw9mehjMoNaHXP2H2RlhwL4WswfHxx5xa5JYfcc22v6NIOUK5P3qG1GbxuprPGMvNwmxU6Gj4OL1y/bhANmn3c/p3y76bIMFwTh8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BL90AEf021506; Thu, 21 Dec 2023 11:11:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= dk201812; bh=JRSCacYUZYV6UoWoCCPxmS6QGSMwvR1GDedaZ0nShaE=; b=dF7 qOFQv62fq3j793Gkk7LhOfjqKmo5y6xwXuPDVEd/zNL7NpKHwigAU2Dsvil+GBZF NU0AINncZm6Ehx1Z6ipdJbSnKeB7amW6LYwASFRxncx71i9OrOOHOem7Fb6Zm1d7 6xAN2C2/RKWhY6BTca1WkrFV6BNg771OVCj2mTjmxkGDtRTyk1fDmrUC/HP/oAKw Q3Ccu8xtReiISsGbAu/uczL8q8YX7Ni7/GpBLGfj8reSLKQhn4T/bw9pXGcfAk8H NyKVTOpvtzgCXwojaxJ6WG/kg9+Gly2hU07YKpY7Wz8VzPHMeHGNCBeAQouSwcDy E9MR5QoHzBh5JLxJHXA== Received: from hhmail05.hh.imgtec.org ([217.156.249.195]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 3v2kvm22v3-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Thu, 21 Dec 2023 11:11:50 +0000 (GMT) Received: from hhjpatil.hh.imgtec.org (10.100.136.70) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 21 Dec 2023 11:11:49 +0000 From: To: CC: , , , , Subject: [PATCH v4 1/2] [sim/riscv] Fix crash during instruction decoding Date: Thu, 21 Dec 2023 11:11:38 +0000 Message-ID: <20231221111139.26341-2-jaydeep.patil@imgtec.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231221111139.26341-1-jaydeep.patil@imgtec.com> References: <20231221111139.26341-1-jaydeep.patil@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.136.70] X-ClientProxiedBy: HHMAIL05.hh.imgtec.org (10.100.10.120) To HHMAIL05.hh.imgtec.org (10.100.10.120) X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-GUID: tX_TeY9Fe34w4bIVdwmiZK8V2xEQB8UD X-Proofpoint-ORIG-GUID: tX_TeY9Fe34w4bIVdwmiZK8V2xEQB8UD X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org From: Jaydeep Patil The match_never() function has been removed and thus step_once() crashes during instruction decoding. Fixed it by checking for null pointer before invoking function attached to match_func member of riscv_opcode structure. --- opcodes/riscv-dis.c | 2 +- sim/riscv/sim-main.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 68674380797..a89ebdd32ac 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -818,7 +818,7 @@ riscv_disassemble_insn (bfd_vma memaddr, if (op->pinfo == INSN_MACRO) continue; /* Does the opcode match? */ - if (! (op->match_func) (op, word)) + if (! op->match_func || ! (op->match_func) (op, word)) continue; /* Is this a pseudo-instruction and may we print it as such? */ if (no_aliases && (op->pinfo & INSN_ALIAS)) diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index afdfcf50656..8a23d2aa1f9 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -1041,7 +1041,7 @@ void step_once (SIM_CPU *cpu) for (; op->name; op++) { /* Does the opcode match? */ - if (! op->match_func (op, iw)) + if (! op->match_func || ! op->match_func (op, iw)) continue; /* Is this a pseudo-instruction and may we print it as such? */ if (op->pinfo & INSN_ALIAS) From patchwork Thu Dec 21 11:13:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaydeep Patil X-Patchwork-Id: 82667 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2BECE385E01F for ; Thu, 21 Dec 2023 11:14:10 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) by sourceware.org (Postfix) with ESMTPS id D3D963858C52 for ; Thu, 21 Dec 2023 11:13:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D3D963858C52 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=imgtec.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=imgtec.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D3D963858C52 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703157236; cv=none; b=pR8g83M9mi9a0wefPp+svezMGmQgpS7ixGzrwrIDf3jUhRrnjih6K8Tpdnw4K3AQKw/6rKgwtQ0iGgh73mwBE/07Zmf3JYKpiOnS6EY9sxil6JdapeEfA56D+0+xW+GKm4rO6zUXuGOFD/IS1lEY6h6xOmaXmPOVVkVqukpjojc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703157236; c=relaxed/simple; bh=qF75pbmWLYvN1M4rDFMKGmk1tRhh+2CWIfyQf/cszUE=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=MT1aBiWqYigWZ4K1x+FK7dWhYjV6UivuSqrZ3E/vD+4/0ANuRSD0MrJbKdUm88FA43/+Jhx1dwJGLXbQCumDIgkxRogMf81a2Dtx8K/o4hwu8SdQbfqz/KykkdWW1ViZIVR5QDxK6+V9AFAgNWyFPBQ8DyS1shF2psFby9+UJC0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BL90AEi021506; Thu, 21 Dec 2023 11:13:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h= from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding:content-type; s=dk201812; bh=haBv75id LJ2MGbGTDbGnqwICszGJ5tSe7djzcNteFXM=; b=PGYuONUIfnzmG3ICHB0DaJ+T v/EBjCBzV41ky2vNJr1ndHfpOollXBnImzC9ywM5oWmmEFqc2wV1pzgsfahoRhcu nNBBiAzVK+5xjqVzyr3W2JTDb1tzin1jDdhKK+fpgRGOV5cjOVqqKp51Smu8PGGg krVRLp9qcqHl0ns19EoPe0+RwOgpJMeRggSSTGyX6YPAp/Sq2B97iw5pu3prsnWM 0sM5gpuRORj3z+yAKbvPXKXb3OfD+KeFFxnjQ9MbqB0G59aNKVbL5rphsTiFlDBv 4Rpf7eEe580JfgzxTna4SC4swGBOmPEY+taSnbE9EU5K0ZjuIjoGV2RyBCbXpA== Received: from hhmail05.hh.imgtec.org ([217.156.249.195]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 3v2kvm22wv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Thu, 21 Dec 2023 11:13:48 +0000 (GMT) Received: from hhjpatil.hh.imgtec.org (10.100.136.70) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 21 Dec 2023 11:13:47 +0000 From: To: CC: , , , , Subject: [PATCH v4 2/2] [sim/riscv] Add support for compressed integer instructions Date: Thu, 21 Dec 2023 11:13:37 +0000 Message-ID: <20231221111337.26415-1-jaydeep.patil@imgtec.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.100.136.70] X-ClientProxiedBy: HHMAIL05.hh.imgtec.org (10.100.10.120) To HHMAIL05.hh.imgtec.org (10.100.10.120) X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-GUID: jHgOD2dirpYhXqDBtMjj2zyergKlPx7S X-Proofpoint-ORIG-GUID: jHgOD2dirpYhXqDBtMjj2zyergKlPx7S X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org From: Jaydeep Patil Added support for simulation of compressed integer instruction set ("c"). Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions. The compressed instructions are available for models implementing C extension. Such as RV32IC, RV64IC, RV32GC, RV64GC etc. --- sim/riscv/model_list.def | 9 + sim/riscv/sim-main.c | 336 +++++++++++++++++++++++++++++++- sim/testsuite/riscv/allinsn.exp | 19 ++ sim/testsuite/riscv/c-ext.s | 110 +++++++++++ 4 files changed, 464 insertions(+), 10 deletions(-) create mode 100644 sim/testsuite/riscv/c-ext.s diff --git a/sim/riscv/model_list.def b/sim/riscv/model_list.def index 5efd85ab280..b83557e5539 100644 --- a/sim/riscv/model_list.def +++ b/sim/riscv/model_list.def @@ -3,7 +3,16 @@ M(I) M(IM) M(IMA) M(IA) +M(GC) +M(IC) +M(IMC) +M(IMAC) +M(IAC) M(E) M(EM) M(EMA) M(EA) +M(EC) +M(EMC) +M(EMAC) +M(EAC) diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 8a23d2aa1f9..c2eef9bc1d5 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -974,6 +974,320 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) return pc; } +static sim_cia +execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) +{ + SIM_DESC sd = CPU_STATE (cpu); + struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu); + int rd = (iw >> OP_SH_RD) & OP_MASK_RD; + int rs1_c = ((iw >> OP_SH_CRS1S) & OP_MASK_CRS1S) + 8; + int rs2 = (iw >> OP_SH_CRS2) & OP_MASK_CRS2; + int rs2_c = ((iw >> OP_SH_CRS2S) & OP_MASK_CRS2S) + 8; + const char *rd_name = riscv_gpr_names_abi[rd]; + const char *rs1_c_name = riscv_gpr_names_abi[rs1_c]; + const char *rs2_name = riscv_gpr_names_abi[rs2]; + const char *rs2_c_name = riscv_gpr_names_abi[rs2_c]; + signed_word imm; + unsigned_word tmp; + sim_cia pc = riscv_cpu->pc + 2; + + switch (op->match) + { + case MATCH_C_JR | MATCH_C_MV: + switch (op->mask) + { + case MASK_C_MV: + TRACE_INSN (cpu, "c.mv %s, %s; // %s = %s", + rd_name, rs2_name, rd_name, rs2_name); + store_rd (cpu, rd, riscv_cpu->regs[rs2]); + break; + case MASK_C_JR: + TRACE_INSN (cpu, "c.jr %s;", + rd_name); + pc = riscv_cpu->regs[rd]; + TRACE_BRANCH (cpu, "to %#" PRIxTW, pc); + break; + } + break; + case MATCH_C_J: + imm = EXTRACT_CJTYPE_IMM (iw); + TRACE_INSN (cpu, "c.j %" PRIxTW, + imm); + pc = riscv_cpu->pc + imm; + TRACE_BRANCH (cpu, "to %#" PRIxTW, pc); + break; + case MATCH_C_JAL | MATCH_C_ADDIW: + /* JAL and ADDIW have the same mask, so switch based on op name. */ + switch (op->name[2]) + { + case 'j': + imm = EXTRACT_CJTYPE_IMM (iw); + TRACE_INSN (cpu, "c.jal %" PRIxTW, + imm); + store_rd (cpu, SIM_RISCV_RA_REGNUM, riscv_cpu->pc + 2); + pc = riscv_cpu->pc + imm; + TRACE_BRANCH (cpu, "to %#" PRIxTW, pc); + break; + case 'a': + imm = EXTRACT_CITYPE_IMM (iw); + TRACE_INSN (cpu, "c.addiw %s, %s, %#" PRIxTW "; // %s += %#" PRIxTW, + rd_name, rd_name, imm, rd_name, imm); + RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name); + store_rd (cpu, rd, EXTEND32 (riscv_cpu->regs[rd] + imm)); + break; + default: + TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name); + sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, + SIM_SIGILL); + } + break; + case MATCH_C_JALR | MATCH_C_ADD | MATCH_C_EBREAK: + switch (op->mask) + { + case MASK_C_ADD: + TRACE_INSN (cpu, "c.add %s, %s; // %s += %s", + rd_name, rs2_name, rd_name, rs2_name); + store_rd (cpu, rd, riscv_cpu->regs[rd] + riscv_cpu->regs[rs2]); + break; + case MASK_C_JALR: + TRACE_INSN (cpu, "c.jalr %s, %s;", + riscv_gpr_names_abi[SIM_RISCV_RA_REGNUM], rd_name); + store_rd (cpu, SIM_RISCV_RA_REGNUM, riscv_cpu->pc + 2); + pc = riscv_cpu->regs[rd]; + TRACE_BRANCH (cpu, "to %#" PRIxTW, pc); + break; + case MASK_C_EBREAK: + TRACE_INSN (cpu, "ebreak"); + sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_stopped, + SIM_SIGTRAP); + } + break; + case MATCH_C_BEQZ: + imm = EXTRACT_CBTYPE_IMM (iw); + TRACE_INSN (cpu, "c.beqz %s, %#" PRIxTW "; " + "// if (%s == 0) goto %#" PRIxTW, + rs1_c_name, imm, rs1_c_name, riscv_cpu->pc + imm); + if (riscv_cpu->regs[rs1_c] == riscv_cpu->regs[0]) + { + pc = riscv_cpu->pc + imm; + TRACE_BRANCH (cpu, "to %#" PRIxTW, pc); + } + break; + case MATCH_C_BNEZ: + imm = EXTRACT_CBTYPE_IMM (iw); + TRACE_INSN (cpu, "c.bnez %s, %#" PRIxTW "; " + "// if (%s != 0) goto %#" PRIxTW, + rs1_c_name, imm, rs1_c_name, riscv_cpu->pc + imm); + if (riscv_cpu->regs[rs1_c] != riscv_cpu->regs[0]) + { + pc = riscv_cpu->pc + imm; + TRACE_BRANCH (cpu, "to %#" PRIxTW, pc); + } + break; + case MATCH_C_LWSP: + imm = EXTRACT_CITYPE_LWSP_IMM (iw); + TRACE_INSN (cpu, "c.lwsp %s, %" PRIiTW "(sp);", + rd_name, imm); + store_rd (cpu, rd, EXTEND32 ( + sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map, + riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + + imm))); + break; + case MATCH_C_LW: + imm = EXTRACT_CLTYPE_LW_IMM (iw); + TRACE_INSN (cpu, "c.lw %s, %" PRIiTW "(%s);", + rs2_c_name, imm, rs1_c_name); + store_rd (cpu, rs2_c, EXTEND32 ( + sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map, + riscv_cpu->regs[rs1_c] + imm))); + break; + case MATCH_C_SWSP: + imm = EXTRACT_CSSTYPE_SWSP_IMM (iw); + TRACE_INSN (cpu, "c.swsp %s, %" PRIiTW "(sp);", + rs2_name, imm); + sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map, + riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + imm, + riscv_cpu->regs[rs2]); + break; + case MATCH_C_SW: + imm = EXTRACT_CLTYPE_LW_IMM (iw); + TRACE_INSN (cpu, "c.sw %s, %" PRIiTW "(%s);", + rs2_c_name, imm, rs1_c_name); + sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map, + riscv_cpu->regs[rs1_c] + (imm), + riscv_cpu->regs[rs2_c]); + break; + case MATCH_C_ADDI: + imm = EXTRACT_CITYPE_IMM (iw); + TRACE_INSN (cpu, "c.addi %s, %s, %#" PRIxTW "; // %s += %#" PRIxTW, + rd_name, rd_name, imm, rd_name, imm); + store_rd (cpu, rd, riscv_cpu->regs[rd] + imm); + break; + case MATCH_C_LUI: + imm = EXTRACT_CITYPE_LUI_IMM (iw); + TRACE_INSN (cpu, "c.lui %s, %#" PRIxTW ";", + rd_name, imm); + store_rd (cpu, rd, imm); + break; + case MATCH_C_LI: + imm = EXTRACT_CITYPE_IMM (iw); + TRACE_INSN (cpu, "c.li %s, %#" PRIxTW "; // %s = %#" PRIxTW, + rd_name, imm, rd_name, imm); + store_rd (cpu, rd, imm); + break; + case MATCH_C_ADDI4SPN: + imm = EXTRACT_CIWTYPE_ADDI4SPN_IMM (iw); + TRACE_INSN (cpu, "c.addi4spn %s, %" PRIiTW "; // %s = sp + %" PRIiTW, + rs2_c_name, imm, rs2_c_name, imm); + store_rd (cpu, rs2_c, riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + (imm)); + break; + case MATCH_C_ADDI16SP: + imm = EXTRACT_CITYPE_ADDI16SP_IMM (iw); + TRACE_INSN (cpu, "c.addi16sp %s, %" PRIiTW "; // %s = sp + %" PRIiTW, + rd_name, imm, rd_name, imm); + store_rd (cpu, rd, riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + imm); + break; + case MATCH_C_SUB: + TRACE_INSN (cpu, "c.sub %s, %s; // %s = %s - %s", + rs1_c_name, rs2_c_name, rs1_c_name, rs1_c_name, rs2_c_name); + store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] - riscv_cpu->regs[rs2_c]); + break; + case MATCH_C_AND: + TRACE_INSN (cpu, "c.and %s, %s; // %s = %s & %s", + rs1_c_name, rs2_c_name, rs1_c_name, rs1_c_name, rs2_c_name); + store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] & riscv_cpu->regs[rs2_c]); + break; + case MATCH_C_OR: + TRACE_INSN (cpu, "c.or %s, %s; // %s = %s | %s", + rs1_c_name, rs2_c_name, rs1_c_name, rs1_c_name, rs2_c_name); + store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] | riscv_cpu->regs[rs2_c]); + break; + case MATCH_C_XOR: + TRACE_INSN (cpu, "c.xor %s, %s; // %s = %s ^ %s", + rs1_c_name, rs2_c_name, rs1_c_name, rs1_c_name, rs2_c_name); + store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] ^ riscv_cpu->regs[rs2_c]); + break; + case MATCH_C_SLLI | MATCH_C_SLLI64: + if (op->mask == MASK_C_SLLI64) + { + /* Reserved for custom use. */ + TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name); + sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, + SIM_SIGILL); + break; + } + imm = EXTRACT_CITYPE_IMM (iw); + TRACE_INSN (cpu, "c.slli %s, %" PRIiTW "; // %s = %s << %#" PRIxTW, + rd_name, imm, rd_name, rd_name, imm); + store_rd (cpu, rd, riscv_cpu->regs[rd] << imm); + break; + case MATCH_C_SRLI | MATCH_C_SRLI64: + if (op->mask == MASK_C_SRLI64) + { + /* Reserved for custom use. */ + TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name); + sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, + SIM_SIGILL); + break; + } + imm = EXTRACT_CITYPE_IMM (iw); + TRACE_INSN (cpu, "c.srli %s, %" PRIiTW "; // %s = %s >> %#" PRIxTW, + rs1_c_name, imm, rs1_c_name, rs1_c_name, imm); + if (RISCV_XLEN (cpu) == 32) + store_rd (cpu, rs1_c, + EXTEND32 ((uint32_t) riscv_cpu->regs[rs1_c] >> imm)); + else + store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] >> imm); + break; + case MATCH_C_SRAI | MATCH_C_SRAI64: + if (op->mask == MASK_C_SRAI64) + { + /* Reserved for custom use. */ + TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name); + sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, + SIM_SIGILL); + break; + } + imm = EXTRACT_CITYPE_IMM (iw); + TRACE_INSN (cpu, "c.srai %s, %" PRIiTW "; // %s = %s >> %#" PRIxTW, + rs1_c_name, imm, rs1_c_name, rs1_c_name, imm); + if (RISCV_XLEN (cpu) == 32) + { + if (imm > 0x1f) + sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, + SIM_SIGILL); + tmp = ashiftrt (riscv_cpu->regs[rs1_c], imm); + } + else + tmp = ashiftrt64 (riscv_cpu->regs[rs1_c], imm); + store_rd (cpu, rd, tmp); + break; + case MATCH_C_ANDI: + imm = EXTRACT_CITYPE_IMM (iw); + TRACE_INSN (cpu, "c.andi %s, %" PRIiTW "; // %s = %s & %#" PRIxTW, + rs1_c_name, imm, rs1_c_name, rs1_c_name, imm); + store_rd (cpu, rs1_c, riscv_cpu->regs[rs1_c] & imm); + break; + case MATCH_C_ADDW: + TRACE_INSN (cpu, "c.addw %s, %s; // %s = %s + %s", + rs1_c_name, rs2_c_name, rs1_c_name, rs1_c_name, rs2_c_name); + RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name); + store_rd (cpu, rs1_c, + EXTEND32 (riscv_cpu->regs[rs1_c] + riscv_cpu->regs[rs2_c])); + break; + case MATCH_C_SUBW: + TRACE_INSN (cpu, "c.subw %s, %s; // %s = %s - %s", + rs1_c_name, rs2_c_name, rs1_c_name, rs1_c_name, rs2_c_name); + RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name); + store_rd (cpu, rs1_c, + EXTEND32 (riscv_cpu->regs[rs1_c] - riscv_cpu->regs[rs2_c])); + break; + case MATCH_C_LDSP: + imm = EXTRACT_CITYPE_LDSP_IMM (iw); + TRACE_INSN (cpu, "c.ldsp %s, %" PRIiTW "(sp);", + rd_name, imm); + RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name); + store_rd (cpu, rd, + sim_core_read_unaligned_8 (cpu, riscv_cpu->pc, read_map, + riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + + imm)); + break; + case MATCH_C_LD: + imm = EXTRACT_CLTYPE_LD_IMM (iw); + TRACE_INSN (cpu, "c.ld %s, %" PRIiTW "(%s);", + rs1_c_name, imm, rs2_c_name); + RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name); + store_rd (cpu, rs2_c, + sim_core_read_unaligned_8 (cpu, riscv_cpu->pc, read_map, + riscv_cpu->regs[rs1_c] + imm)); + break; + case MATCH_C_SDSP: + imm = EXTRACT_CSSTYPE_SDSP_IMM (iw); + TRACE_INSN (cpu, "c.sdsp %s, %" PRIiTW "(sp);", + rs2_name, imm); + RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name); + sim_core_write_unaligned_8 (cpu, riscv_cpu->pc, write_map, + riscv_cpu->regs[SIM_RISCV_SP_REGNUM] + imm, + riscv_cpu->regs[rs2]); + break; + case MATCH_C_SD: + imm = EXTRACT_CLTYPE_LD_IMM (iw); + TRACE_INSN (cpu, "c.sd %s, %" PRIiTW "(%s);", + rs2_c_name, imm, rs1_c_name); + RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name); + sim_core_write_unaligned_8 (cpu, riscv_cpu->pc, write_map, + riscv_cpu->regs[rs1_c] + imm, + riscv_cpu->regs[rs2_c]); + break; + default: + TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name); + sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, + SIM_SIGILL); + } + + return pc; +} + static sim_cia execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) { @@ -989,6 +1303,15 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) { case INSN_CLASS_A: return execute_a (cpu, iw, op); + case INSN_CLASS_C: + /* Check whether model with C extension is selected. */ + if ((riscv_cpu->csr.misa & 4) != 4) + { + TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class); + sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, + SIM_SIGILL); + } + return execute_c (cpu, iw, op); case INSN_CLASS_I: return execute_i (cpu, iw, op); case INSN_CLASS_M: @@ -1019,17 +1342,10 @@ void step_once (SIM_CPU *cpu) iw = sim_core_read_aligned_2 (cpu, pc, exec_map, pc); - /* Reject non-32-bit opcodes first. */ len = riscv_insn_length (iw); - if (len != 4) - { - sim_io_printf (sd, "sim: bad insn len %#x @ %#" PRIxTA ": %#" PRIxTW "\n", - len, pc, iw); - sim_engine_halt (sd, cpu, NULL, pc, sim_signalled, SIM_SIGILL); - } - - iw |= ((unsigned_word) sim_core_read_aligned_2 ( - cpu, pc, exec_map, pc + 2) << 16); + if (len == 4) + iw |= ((unsigned_word) sim_core_read_aligned_2 + (cpu, pc, exec_map, pc + 2) << 16); TRACE_CORE (cpu, "0x%08" PRIxTW, iw); diff --git a/sim/testsuite/riscv/allinsn.exp b/sim/testsuite/riscv/allinsn.exp index 972edf4d5ec..b76c45a2366 100644 --- a/sim/testsuite/riscv/allinsn.exp +++ b/sim/testsuite/riscv/allinsn.exp @@ -5,10 +5,29 @@ sim_init # all machines set all_machs "riscv" +# Detect model based on -dumpmachine option of the compiler +set result [target_compile $srcdir/lib/compilercheck.c \ + $objdir/compilercheck.x "preprocess" \ + "additional_flags=-dumpmachine"] +if { [string match "riscv32-*" $result] } { + set model "RV32IC" +} { + set model "RV64IC" +} + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { # If we're only testing specific files and this isn't one of them, skip it. if ![runtest_file_p $runtests $src] { continue } + + # The c-ext.s needs a model with C extension + global SIMFLAGS_FOR_TARGET + set SIMFLAGS_FOR_TARGET "" + set fname [file tail $src] + if {$fname == "c-ext.s"} { + set SIMFLAGS_FOR_TARGET "--model $model" + } + run_sim_test $src $all_machs } diff --git a/sim/testsuite/riscv/c-ext.s b/sim/testsuite/riscv/c-ext.s new file mode 100644 index 00000000000..049d2b4323e --- /dev/null +++ b/sim/testsuite/riscv/c-ext.s @@ -0,0 +1,110 @@ +# Basic load store tests. +# mach: riscv + +.include "testutils.inc" + + .data + .align 4 +_data: + .word 1234 + .word 0 + + start + la a0, _data + + # Test load-store instructions. + .option push + .option arch, +c + c.lw a1,0(a0) + c.sw a1,4(a0) + c.lw a2,4(a0) + .option pop + + li a5,1234 + bne a1,a5,test_fail + bne a2,a5,test_fail + + # Test basic arithmetic. + .option push + .option arch, +c + c.li a0,0 + c.li a1,1 + c.addi a0,1 + c.addi a0,-1 + c.addw a0,a1 + c.subw a0,a1 + .option pop + + li a5,1 + bne a0,x0,test_fail + bne a1,a5,test_fail + + # Test logical operations. + .option push + .option arch, +c + c.li a0,7 + c.li a1,7 + c.li a2,4 + c.li a3,3 + c.li a4,3 + c.andi a0,3 + c.and a1,a0 + c.or a2,a3 + c.xor a4,a4 + .option pop + + li a5,3 + bne a0,a5,test_fail + bne a1,a5,test_fail + bne a4,x0,test_fail + li a5,7 + bne a2,a5,test_fail + + # Test shift operations. + .option push + .option arch, +c + c.li a0,4 + c.li a1,4 + c.slli a0,1 + c.srli a1,1 + .option pop + + li a5,8 + bne a0,a5,test_fail + li a5,2 + bne a1,a5,test_fail + + # Test jump instruction. + .option push + .option arch, +c + c.j 1f + .option pop + + j test_fail +1: + la a0,2f + + # Test jump register instruction. + .option push + .option arch, +c + c.jr a0 + .option pop + + j test_fail + +2: + # Test branch instruction. + .option push + .option arch, +c + c.li a0,1 + c.beqz a0,test_fail + c.li a0,0 + c.bnez a0,test_fail + .option pop + +test_pass: + pass + fail + +test_fail: + fail