From patchwork Tue Dec 19 10:56:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 82468 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 37DA5386075A for ; Tue, 19 Dec 2023 10:57:00 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id E1EED3858439 for ; Tue, 19 Dec 2023 10:56:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E1EED3858439 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E1EED3858439 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.243.244.52 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702983404; cv=none; b=A0l0gge9PmsLAtqP4ABk5AB8GnRb17Ara9WhvYG0Gmo8ef/Do1coF/fVIrwMqy8rp+XSafyPJ5FK/IpxfPs6FWGNAR8NwJ68rh4zOGaH4OWIx1WxB7LyqUF5tpzvsh4mivkCxuGfip8I73ajwd6dtzICFpWp4TeHXly3aoSlurU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702983404; c=relaxed/simple; bh=F53oPZswbgJtFZlO4zYtnAOl8f4jfgG5R+9SiSdtL9k=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=EbR5seWQQLyIPZjK/IdPKrzHYvDGAfVMCd3icSLhM2EmgFkCNTn1ZAIiLsQFevhtq2PwQTxNiwcMvXaikEnSm50ZOz82SRM7GldrY3XW3Kh5Wcc6zXY79AFZ7rEPvpLy7kq1FW9Vz9HWQGVLvNcJUQZm9GGBLxMdLasbGPapsEc= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp77t1702983397tlldii94 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 19 Dec 2023 18:56:36 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: W+onFc5Tw4M4yc+emIEgEipyfEh6w09x3uIx0LmsudEnHZn+IaJZlkkU3v4o5 fXXEtzfF0geudYeVAA0nX9yUou3YBlhjv+ABRDkoMkJ+CVCaZunzYrMER46EW52zgIUfMGo h6FuWeUwZZQFm/6QxEpjPJo0cNs2TtHaXat11soUUPbMagqtBca4DxCxvYbxBtyrXj5w9eZ vR/zop1rJffes/r2XLj3BBGpP58sKItrX23w7dQ+FSzRzsCuV7ZF/ypsUUOaWXLUVICsF0l xjhc9uRgZPo8IKwi4dCw1vSPUamCqriCYogiiYZIXjWdgWK7LSTJCD1UYLXg0ULnEIVBLZL YYH3eUiLVxvi0Vsk/5g8u1DwN7J1zhqnkaWaTPV9VjQvc2WEbjff4co4gpF0ZzdNnJKcMNa rYD8iEEU2Hmb0KuQ2gnCqw== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 11255582315938381898 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed] RISC-V: Refine some codes of expand_const_vector [NFC] Date: Tue, 19 Dec 2023 18:56:35 +0800 Message-Id: <20231219105635.2566878-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Use builder.inner_mode (). --- gcc/config/riscv/riscv-v.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index d1eb7a0a9a5..486f5deb296 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1380,15 +1380,15 @@ expand_const_vector (rtx target, rtx src) rtx base1 = builder.elt (1); rtx base2 = builder.elt (2); - scalar_mode elem_mode = GET_MODE_INNER (mode); - rtx step = simplify_binary_operation (MINUS, elem_mode, base2, base1); + rtx step = simplify_binary_operation (MINUS, builder.inner_mode (), + base2, base1); /* Step 1 - { base1, base1 + step, base1 + step * 2, ... } */ rtx tmp = gen_reg_rtx (mode); expand_vec_series (tmp, base1, step); /* Step 2 - { base0, base1, base1 + step, base1 + step * 2, ... } */ if (!rtx_equal_p (base0, const0_rtx)) - base0 = force_reg (elem_mode, base0); + base0 = force_reg (builder.inner_mode (), base0); insn_code icode = optab_handler (vec_shl_insert_optab, mode); gcc_assert (icode != CODE_FOR_nothing);