From patchwork Tue Dec 19 06:59:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 82434 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E1B0C3861827 for ; Tue, 19 Dec 2023 07:00:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 04AD23858439 for ; Tue, 19 Dec 2023 07:00:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 04AD23858439 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 04AD23858439 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702969217; cv=none; b=JB4wKZRk45iCMY9C2RdlwiRSHZAhBOYQlkX9xY5sSPR99xV64HZWnqGSGb6jnRCJZKfBn4RkMHGAkoHwXin79U90SVJDbb3ZFZCz4K4iOhnSaJsCTe91daFbA1MyC6UGSJ/KDa38H046KDtgoIfkBIeLSm3lbZ+ctaS2ebm28wQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702969217; c=relaxed/simple; bh=MHso2PjCgQuAZK1DLuFZYq5WzhTY+ndj21jHD2nCKN0=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=xaqAv2jurSA85Bc2e9fXrQNH6XFgVEsIzWkAYv7xvoBm6iZoDFVXGBbdPJCePcVIiotfT/jKoZ9JsM6x3DbwB4kIx+SAhai4VMKbB7i67cP5CdcbRM7ID11r7vHLX/uGnQrANKgJSy7xlJP+cMPBmADWjunEe/01d9yO75Qtp88= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1702969215; bh=MHso2PjCgQuAZK1DLuFZYq5WzhTY+ndj21jHD2nCKN0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NbOk364s12MqpLcvGmnoAO418XPQAHW2yRAv25f4ChddB4ye21GODlHaIbTdzfbxy VVevqAmEK6qmiSqFUcBIv137cXov6rjYG/49mfp7gB33S38uMxjS6SWj2bPQtF6kQ3 CzzWji9GhpFjLl4CQwOHoR1e0JYUav314cRiWvLs= Received: from stargazer.. (unknown [IPv6:240e:358:119f:400:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 868EA66A05; Tue, 19 Dec 2023 02:00:12 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, c@jia.je, Xi Ruoyao Subject: [PATCH 1/2] LoongArch: Use force_reg instead of gen_reg_rtx + emit_move_insn in vec_init expander [PR113033] Date: Tue, 19 Dec 2023 14:59:56 +0800 Message-ID: <20231219065957.70665-2-xry111@xry111.site> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231219065957.70665-1-xry111@xry111.site> References: <20231219065957.70665-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Jakub says: Then that seems like a bug in the loongarch vec_init pattern(s). Those really don't have a predicate in any of the backends on the input operand, so they need to force_reg it if it is something it can't handle. I've looked e.g. at i386 vec_init and that is exactly what it does, see the various tests + force_reg calls in ix86_expand_vector_init*. So replace gen_reg_rtx + emit_move_insn with force_reg to fix PR 113033. gcc/ChangeLog: PR target/113033 * config/loongarch/loongarch.cc (loongarch_expand_vector_init_same): Replace gen_reg_rtx + emit_move_insn with force_reg. (loongarch_expand_vector_init): Likewise. gcc/testsuite/ChangeLog: PR target/113033 * gcc.target/loongarch/pr113033.c: New test. --- gcc/config/loongarch/loongarch.cc | 38 ++++++------------- gcc/testsuite/gcc.target/loongarch/pr113033.c | 23 +++++++++++ 2 files changed, 35 insertions(+), 26 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/pr113033.c diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 256fa7d048d..ef81414342d 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -10770,7 +10770,7 @@ loongarch_expand_vector_init_same (rtx target, rtx vals, unsigned nvar) gcc_unreachable (); } } - temp = gen_reg_rtx (imode); + if (imode == GET_MODE (same)) temp2 = same; else if (GET_MODE_SIZE (imode) >= UNITS_PER_WORD) @@ -10795,7 +10795,8 @@ loongarch_expand_vector_init_same (rtx target, rtx vals, unsigned nvar) else temp2 = lowpart_subreg (imode, same, GET_MODE (same)); } - emit_move_insn (temp, temp2); + + temp = force_reg (imode, temp2); switch (vmode) { @@ -11017,35 +11018,29 @@ loongarch_expand_vector_init (rtx target, rtx vals) to reduce the number of instructions. */ if (i == 1) { - op0 = gen_reg_rtx (imode); - emit_move_insn (op0, val_hi[0]); - op1 = gen_reg_rtx (imode); - emit_move_insn (op1, val_hi[1]); + op0 = force_reg (imode, val_hi[0]); + op1 = force_reg (imode, val_hi[1]); emit_insn ( loongarch_vec_repl2_256 (target_hi, op0, op1)); } else if (i > 1) { - op0 = gen_reg_rtx (imode); - emit_move_insn (op0, val_hi[i]); + op0 = force_reg (imode, val_hi[i]); emit_insn ( loongarch_vec_set256 (target_hi, op0, GEN_INT (i))); } } else { + op0 = force_reg (imode, val_hi[i]); /* Assign the lowest element of val_hi to all elements of target_hi. */ if (i == 0) { - op0 = gen_reg_rtx (imode); - emit_move_insn (op0, val_hi[0]); emit_insn (loongarch_vec_repl1_256 (target_hi, op0)); } else if (!rtx_equal_p (val_hi[i], val_hi[0])) { - op0 = gen_reg_rtx (imode); - emit_move_insn (op0, val_hi[i]); emit_insn ( loongarch_vec_set256 (target_hi, op0, GEN_INT (i))); } @@ -11053,18 +11048,15 @@ loongarch_expand_vector_init (rtx target, rtx vals) } if (!lo_same && !half_same) { + op0 = force_reg (imode, val_lo[i]); /* Assign the lowest element of val_lo to all elements of target_lo. */ if (i == 0) { - op0 = gen_reg_rtx (imode); - emit_move_insn (op0, val_lo[0]); emit_insn (loongarch_vec_repl1_128 (target_lo, op0)); } else if (!rtx_equal_p (val_lo[i], val_lo[0])) { - op0 = gen_reg_rtx (imode); - emit_move_insn (op0, val_lo[i]); emit_insn ( loongarch_vec_set128 (target_lo, op0, GEN_INT (i))); } @@ -11096,16 +11088,13 @@ loongarch_expand_vector_init (rtx target, rtx vals) reduce the number of instructions. */ if (i == 1) { - op0 = gen_reg_rtx (imode); - emit_move_insn (op0, val[0]); - op1 = gen_reg_rtx (imode); - emit_move_insn (op1, val[1]); + op0 = force_reg (imode, val[0]); + op1 = force_reg (imode, val[1]); emit_insn (loongarch_vec_repl2_128 (target, op0, op1)); } else if (i > 1) { - op0 = gen_reg_rtx (imode); - emit_move_insn (op0, val[i]); + op0 = force_reg (imode, val[i]); emit_insn ( loongarch_vec_set128 (target, op0, GEN_INT (i))); } @@ -11118,18 +11107,15 @@ loongarch_expand_vector_init (rtx target, rtx vals) loongarch_vec_mirror (target, target, const0_rtx)); return; } + op0 = force_reg (imode, val[i]); /* Assign the lowest element of val to all elements of target. */ if (i == 0) { - op0 = gen_reg_rtx (imode); - emit_move_insn (op0, val[0]); emit_insn (loongarch_vec_repl1_128 (target, op0)); } else if (!rtx_equal_p (val[i], val[0])) { - op0 = gen_reg_rtx (imode); - emit_move_insn (op0, val[i]); emit_insn ( loongarch_vec_set128 (target, op0, GEN_INT (i))); } diff --git a/gcc/testsuite/gcc.target/loongarch/pr113033.c b/gcc/testsuite/gcc.target/loongarch/pr113033.c new file mode 100644 index 00000000000..4ccd037d846 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr113033.c @@ -0,0 +1,23 @@ +/* PR target/113033: ICE with vector left rotate */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlasx" } */ + +typedef unsigned __attribute__ ((vector_size (16))) v4si; +typedef unsigned __attribute__ ((vector_size (32))) v8si; +typedef unsigned long long __attribute__ ((vector_size (16))) v2di; +typedef unsigned long long __attribute__ ((vector_size (32))) v4di; + +#define TEST(tp) \ +extern tp data_##tp; \ +tp \ +test_##tp (int x) \ +{ \ + const int bit = sizeof (data_##tp[0]) * __CHAR_BIT__; \ + data_##tp = data_##tp << (x & (bit - 1)) \ + | data_##tp >> (bit - x & (bit - 1)); \ +} + +TEST (v4si) +TEST (v8si) +TEST (v2di) +TEST (v4di) From patchwork Tue Dec 19 06:59:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 82435 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9C176386185E for ; Tue, 19 Dec 2023 07:00:36 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id A65033857437 for ; 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(unknown [IPv6:240e:358:119f:400:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 31F7A66A06; Tue, 19 Dec 2023 02:00:15 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, c@jia.je, Xi Ruoyao Subject: [PATCH 2/2] LoongArch: Clean up vec_init expander Date: Tue, 19 Dec 2023 14:59:57 +0800 Message-ID: <20231219065957.70665-3-xry111@xry111.site> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231219065957.70665-1-xry111@xry111.site> References: <20231219065957.70665-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Non functional change, clean up the code. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_expand_vector_init_same): Remove "temp2" and reuse "temp" instead. (loongarch_expand_vector_init): Use gcc_unreachable () instead of gcc_assert (0), and fix the comment for it. --- gcc/config/loongarch/loongarch.cc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index ef81414342d..5ffd06ce9be 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -10748,7 +10748,7 @@ loongarch_expand_vector_init_same (rtx target, rtx vals, unsigned nvar) machine_mode vmode = GET_MODE (target); machine_mode imode = GET_MODE_INNER (vmode); rtx same = XVECEXP (vals, 0, 0); - rtx temp, temp2; + rtx temp; if (CONST_INT_P (same) && nvar == 0 && loongarch_signed_immediate_p (INTVAL (same), 10, 0)) @@ -10772,17 +10772,17 @@ loongarch_expand_vector_init_same (rtx target, rtx vals, unsigned nvar) } if (imode == GET_MODE (same)) - temp2 = same; + temp = same; else if (GET_MODE_SIZE (imode) >= UNITS_PER_WORD) { if (GET_CODE (same) == MEM) { rtx reg_tmp = gen_reg_rtx (GET_MODE (same)); loongarch_emit_move (reg_tmp, same); - temp2 = simplify_gen_subreg (imode, reg_tmp, GET_MODE (reg_tmp), 0); + temp = simplify_gen_subreg (imode, reg_tmp, GET_MODE (reg_tmp), 0); } else - temp2 = simplify_gen_subreg (imode, same, GET_MODE (same), 0); + temp = simplify_gen_subreg (imode, same, GET_MODE (same), 0); } else { @@ -10790,13 +10790,13 @@ loongarch_expand_vector_init_same (rtx target, rtx vals, unsigned nvar) { rtx reg_tmp = gen_reg_rtx (GET_MODE (same)); loongarch_emit_move (reg_tmp, same); - temp2 = lowpart_subreg (imode, reg_tmp, GET_MODE (reg_tmp)); + temp = lowpart_subreg (imode, reg_tmp, GET_MODE (reg_tmp)); } else - temp2 = lowpart_subreg (imode, same, GET_MODE (same)); + temp = lowpart_subreg (imode, same, GET_MODE (same)); } - temp = force_reg (imode, temp2); + temp = force_reg (imode, temp); switch (vmode) { @@ -11142,8 +11142,8 @@ loongarch_expand_vector_init (rtx target, rtx vals) return; } - /* Loongson is the only cpu with vectors with more elements. */ - gcc_assert (0); + /* No LoongArch CPU supports vectors with more elements as at now. */ + gcc_unreachable (); } /* Implement HARD_REGNO_CALLER_SAVE_MODE. */