From patchwork Mon Dec 18 06:40:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Xu X-Patchwork-Id: 82369 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1CB4B38582BE for ; Mon, 18 Dec 2023 06:42:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from sgoci-sdnproxy-4.icoremail.net (sgoci-sdnproxy-4.icoremail.net [129.150.39.64]) by sourceware.org (Postfix) with ESMTP id 7964B3858424 for ; Mon, 18 Dec 2023 06:41:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7964B3858424 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7964B3858424 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=129.150.39.64 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702881705; cv=none; b=mb7WXIsaua715JZjWK3fpZd/K5N7GBhIdvLtR60c++4UfTe7dRfMxYy+MlDSg7h96bMsBT/EsAj9RCtGkYJLTb3r2VFSgmJIhnmKTMk8o3mveEJXmto8mLHj6Bi+L42Z3a4hy8VfFOOkBn+dTweK0jEqqaYRUJwFYmtrIQnbzBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702881705; c=relaxed/simple; bh=7FLT+Sku1kPBVdtZ9STRx2CN0TutOcVDOcRvE/k2rjA=; h=From:To:Subject:Date:Message-Id; b=hfy7V5ddqiqiuaA7yHtFXKk84dYM/efKYgsfj9RlbAadgNoNUakVa+AfSTVI0dbHh717aufXEuQEuTzyM5UYCDd1ZTo2rND1zI4HFLumAehLFfMLTUidUu1bzGxYKg+uycVJEr+3YXS1/FZ0LN4Wm3mVUysOu8QwiXZouXvoTeA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id TQJkCgBH1dNL6X9l+OYBAA--.15461S4; Mon, 18 Dec 2023 14:40:14 +0800 (CST) From: Li Xu To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, juzhe.zhong@rivai.ai, xuli Subject: [PATCH] testsuite: Fix cpymem-1.c dump checks under different riscv-sim for RVV. Date: Mon, 18 Dec 2023 06:40:35 +0000 Message-Id: <20231218064035.36034-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: TQJkCgBH1dNL6X9l+OYBAA--.15461S4 X-Coremail-Antispam: 1UD129KBjvJXoWxJF4Utw1ktw43trWfXF4DXFb_yoW5Gr1rpF W8Cw47Ary7JrZ7JF1S9F4DXr4Y9w48urWkuwsxWryUAF1F9FW8u3s2g3s7Wa15Xa1UAr4a qF4Skw1rZwsIqFUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkI14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbXdbUUUUUU== X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, RCVD_IN_VALIDITY_RPBL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org From: xuli gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/cpymem-1.c: Fix checks. --- .../gcc.target/riscv/rvv/base/cpymem-1.c | 27 +++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c index 549d6648104..aac81079650 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c @@ -50,11 +50,34 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) Use extern here so that we get a known alignment, lest DATA_ALIGNMENT force us to make the scan pattern accomodate code for different alignments depending on word size. -** f3: { target { any-opts "-mcmodel=medlow" } } +** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-preference=fixed-vlmax" } } } ** lui\s+[ta][0-7],%hi\(a_a\) +** addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\) ** lui\s+[ta][0-7],%hi\(a_b\) ** addi\s+a4,[ta][0-7],%lo\(a_b\) -** vsetivli\s+zero,16,e32,m4,ta,ma +** vsetivli\s+zero,16,e32,m8,ta,ma +** vle32.v\s+v\d+,0\([ta][0-7]\) +** vse32\.v\s+v\d+,0\([ta][0-7]\) +** ret +*/ + +/* +** f3: { target { { any-opts "-mcmodel=medlow --param=riscv-autovec-preference=fixed-vlmax" "-mcmodel=medlow -march=rv64gcv_zvl512b --param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" } } } +** lui\s+[ta][0-7],%hi\(a_a\) +** lui\s+[ta][0-7],%hi\(a_b\) +** addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\) +** addi\s+a4,[ta][0-7],%lo\(a_b\) +** vl(1|4|2)re32\.v\s+v\d+,0\([ta][0-7]\) +** vs(1|4|2)r\.v\s+v\d+,0\([ta][0-7]\) +** ret +*/ + +/* +** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" "-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } +** lui\s+[ta][0-7],%hi\(a_a\) +** lui\s+[ta][0-7],%hi\(a_b\) +** addi\s+a4,[ta][0-7],%lo\(a_b\) +** vsetivli\s+zero,16,e32,(m1|m4|mf2),ta,ma ** vle32.v\s+v\d+,0\([ta][0-7]\) ** addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\) ** vse32\.v\s+v\d+,0\([ta][0-7]\)