From patchwork Mon Dec 18 03:26:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 82365 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9D71C385802D for ; Mon, 18 Dec 2023 03:29:21 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 70E06385828F for ; Mon, 18 Dec 2023 03:29:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 70E06385828F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 70E06385828F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=134.134.136.31 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702870146; cv=none; b=JZ1bfgopusAUy98b45kAakJ5rHrUBimrx+Dz8a0GkqjadQADT6B5ZYJ+Mj1EZgruZmRNww05vjrV8ws0+KprqN+2ic+NK/xD2CTx8Pp0Re3VDAISlNMntiZNrLWEjDQD+CkAWCqeH+iz1YZjF23T2kflMqy81RtlAZaYzJz9oJk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702870146; c=relaxed/simple; bh=1Q9doE/DecLrz0EFU3B3gnUv6dJz+IgS5/fmiRYsgs4=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=UWLFjql4AUyZf2likff0vRP8Xad8DmwnDRXAhV3cDB3o6RM3Ht2oMvMjoqupkWzQvEvSRkVaIApTBk9Jcrx/YawG/xhxAm16EF1Ailm3GoqkyuUu/hDfGRa5zM66OcAkxpnqFeSa4gRlkOoen14CraIR2fCgAKJtOV700IL9+Yk= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702870143; x=1734406143; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=1Q9doE/DecLrz0EFU3B3gnUv6dJz+IgS5/fmiRYsgs4=; b=h5b45wtnVbhAnFu5ex5rrDXQIA7TVkMk/qY46qDlnUutras55yH3bHmv cZqRLlq55Vcb7usiSHMhbtr8G7iS4oYyBkY/gLxMOZN8PU9QnbsIc7zFj PvyQ18bPy6YW5WbZJjG99zo+H6J9iGPUQD/xMt0pBanSfo0YaBEwpMxGM PhLyfLFZcKYmkH7BZ0xwW3aZL0frACum5KYWNY7J/oALrai+MEps/CsxA IQ7gn+vN7ut6LF/e+bv19vP/BRy1bBZ9w9FRa4t7fX4i4x4Xaq/tmscIM vAsTmXHb0NlkVHKRTO1GupaOqglSolC7rIdprVlIz9gKzaEpMOezkBL3E g==; X-IronPort-AV: E=McAfee;i="6600,9927,10927"; a="459775499" X-IronPort-AV: E=Sophos;i="6.04,284,1695711600"; d="scan'208";a="459775499" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2023 19:29:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10927"; a="893659359" X-IronPort-AV: E=Sophos;i="6.04,284,1695711600"; d="scan'208";a="893659359" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 17 Dec 2023 19:28:57 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 0D3A910056EF; Mon, 18 Dec 2023 11:28:57 +0800 (CST) From: Haochen Jiang To: binutils@sourceware.org Cc: hjl.tools@gmail.com, jbeulich@suse.com Subject: [PATCH v2] x86: Remove the restriction for size of the mask register in AVX10 Date: Mon, 18 Dec 2023 11:26:56 +0800 Message-Id: <20231218032656.1591992-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Hi all, This is the v2 patch to remove the restiction for the size of the mask register in AVX10. Changes in v2: Remove attribute Vsz in opcode_modifier since it is no longer used. But I suppose we still need a similar enum in gas to check encoding is right. Thx, Haochen Messages in v1 patch: Sorry for the late change near the 2.42 branch freeze but there is a revision in AVX10 documentation, which allows 64 bit mask register instructions in AVX10/256, the documentation comes following: Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specification https://cdrdv2.intel.com/v1/dl/getContent/784267 The Converged Vector ISA: Intel Advanced Vector Extensions 10 Technical Paper https://cdrdv2.intel.com/v1/dl/getContent/784343 This patch aims to remove the mask register size restriction on all vector size in AVX10. Since mask registers size is not an issue, I also removed the testcases for them. But I have no objection to keep them. gas/ChangeLog: * config/tc-i386.c (Vsz): New. (VEX_check_encoding): Remove opcode_modifier check for vsz. * testsuite/gas/i386/avx10-vsz.l: Remove testcases for mask registers since they are not needed. * testsuite/gas/i386/avx10-vsz.s: Ditto. opcodes/ChangeLog: * i386-gen.c: Remove Vsz. * i386-opc.h: Ditto. * i386-opc.tbl: Remove kvsz. * i386-tbl.h: Regenerated. --- gas/config/tc-i386.c | 11 +- gas/testsuite/gas/i386/avx10-vsz.l | 231 +- gas/testsuite/gas/i386/avx10-vsz.s | 21 - opcodes/i386-gen.c | 1 - opcodes/i386-opc.h | 11 - opcodes/i386-opc.tbl | 41 +- opcodes/i386-tbl.h | 11241 +++++++++------------------ 7 files changed, 3798 insertions(+), 7759 deletions(-) diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 4f3864f2ba7..b34f1ef70f8 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -823,6 +823,11 @@ static unsigned int sse2avx; static unsigned int use_unaligned_vector_move; /* Maximum permitted vector size. */ +static enum { + VSZ128 = 0, + VSZ256, + VSZ512, +} Vsz; #define VSZ_DEFAULT VSZ512 static unsigned int vector_size = VSZ_DEFAULT; @@ -6967,12 +6972,10 @@ VEX_check_encoding (const insn_template *t) /* Vector size restrictions. */ if ((vector_size < VSZ512 - && (t->opcode_modifier.evex == EVEX512 - || t->opcode_modifier.vsz >= VSZ512)) + && t->opcode_modifier.evex == EVEX512) || (vector_size < VSZ256 && (t->opcode_modifier.evex == EVEX256 - || t->opcode_modifier.vex == VEX256 - || t->opcode_modifier.vsz >= VSZ256))) + || t->opcode_modifier.vex == VEX256))) { i.error = unsupported_vector_size; return 1; diff --git a/gas/testsuite/gas/i386/avx10-vsz.l b/gas/testsuite/gas/i386/avx10-vsz.l index d10ff55ee9d..f44ca46db66 100644 --- a/gas/testsuite/gas/i386/avx10-vsz.l +++ b/gas/testsuite/gas/i386/avx10-vsz.l @@ -1,115 +1,34 @@ .*: Assembler messages: .*:7: Warning: default -.*:46: Error: ambiguous operand size for `vcvtpd2ph' -.*:47: Error: ambiguous operand size for `vcvtpd2ps' -.*:48: Error: ambiguous operand size for `vfpclassps' +.*:25: Error: ambiguous operand size for `vcvtpd2ph' +.*:26: Error: ambiguous operand size for `vcvtpd2ps' +.*:27: Error: ambiguous operand size for `vfpclassps' .*:7: Warning: \.avx10\.1/256 -.*:12: Error: vector size .* `kunpckdq' -.*:16: Error: vector size .* `kaddq' -.*:17: Error: vector size .* `kandq' -.*:18: Error: vector size .* `kandnq' -.*:19: Error: vector size .* `kmovq' -.*:20: Error: vector size .* `kmovq' -.*:21: Error: vector size .* `kmovq' -.*:22: Error: vector size .* `knotq' -.*:23: Error: vector size .* `korq' -.*:24: Error: vector size .* `kortestq' -.*:25: Error: vector size .* `kshiftlq' -.*:26: Error: vector size .* `kshiftrq' -.*:27: Error: vector size .* `ktestq' -.*:28: Error: vector size .* `kxorq' -.*:29: Error: vector size .* `kxnorq' -.*:32: Error: vector size .* `vcvtpd2phz' -.*:34: Error: unsupported broadcast for `vcvtpd2ph' -.*:37: Error: vector size .* for `vcvtpd2ps' -.*:43: Error: vector size .* `vfpclasspsz' -.*:46: Error: ambiguous operand size for `vcvtpd2ph' -.*:47: Error: ambiguous operand size for `vcvtpd2ps' -.*:48: Error: ambiguous operand size for `vfpclassps' +.*:11: Error: vector size .* `vcvtpd2phz' +.*:13: Error: unsupported broadcast for `vcvtpd2ph' +.*:16: Error: vector size .* for `vcvtpd2ps' +.*:22: Error: vector size .* `vfpclasspsz' +.*:25: Error: ambiguous operand size for `vcvtpd2ph' +.*:26: Error: ambiguous operand size for `vcvtpd2ps' +.*:27: Error: ambiguous operand size for `vfpclassps' .*:7: Warning: \.avx10\.1/128 -.*:10: Error: vector size .* `kmovd' -.*:11: Error: vector size .* `kmovd' -.*:12: Error: vector size .* `kunpckdq' -.*:13: Error: vector size .* `kunpckwd' -.*:16: Error: vector size .* `kaddd' -.*:17: Error: vector size .* `kandd' -.*:18: Error: vector size .* `kandnd' -.*:19: Error: vector size .* `kmovd' -.*:20: Error: vector size .* `kmovd' -.*:21: Error: vector size .* `kmovd' -.*:22: Error: vector size .* `knotd' -.*:23: Error: vector size .* `kord' -.*:24: Error: vector size .* `kortestd' -.*:25: Error: vector size .* `kshiftld' -.*:26: Error: vector size .* `kshiftrd' -.*:27: Error: vector size .* `ktestd' -.*:28: Error: vector size .* `kxord' -.*:29: Error: vector size .* `kxnord' -.*:16: Error: vector size .* `kaddq' -.*:17: Error: vector size .* `kandq' -.*:18: Error: vector size .* `kandnq' -.*:19: Error: vector size .* `kmovq' -.*:20: Error: vector size .* `kmovq' -.*:21: Error: vector size .* `kmovq' -.*:22: Error: vector size .* `knotq' -.*:23: Error: vector size .* `korq' -.*:24: Error: vector size .* `kortestq' -.*:25: Error: vector size .* `kshiftlq' -.*:26: Error: vector size .* `kshiftrq' -.*:27: Error: vector size .* `ktestq' -.*:28: Error: vector size .* `kxorq' -.*:29: Error: vector size .* `kxnorq' -.*:32: Error: vector size .* `vcvtpd2phz' -.*:33: Error: vector size .* `vcvtpd2phy' -.*:34: Error: unsupported broadcast for `vcvtpd2ph' -.*:35: Error: unsupported broadcast for `vcvtpd2ph' -.*:37: Error: .* -.*:38: Error: vector size .* `vcvtpd2psy' -.*:39: Error: vector size .* `vcvtpd2psy' -.*:40: Error: unsupported broadcast for `vcvtpd2ps' -.*:42: Error: vector size .* `vfpclasspsy' -.*:43: Error: vector size .* `vfpclasspsz' +.*:11: Error: vector size .* `vcvtpd2phz' +.*:12: Error: vector size .* `vcvtpd2phy' +.*:13: Error: unsupported broadcast for `vcvtpd2ph' +.*:14: Error: unsupported broadcast for `vcvtpd2ph' +.*:16: Error: .* +.*:17: Error: vector size .* `vcvtpd2psy' +.*:18: Error: vector size .* `vcvtpd2psy' +.*:19: Error: unsupported broadcast for `vcvtpd2ps' +.*:21: Error: vector size .* `vfpclasspsy' +.*:22: Error: vector size .* `vfpclasspsz' .*:7: Warning: \.avx10\.1 -.*:46: Error: ambiguous operand size for `vcvtpd2ph' -.*:47: Error: ambiguous operand size for `vcvtpd2ps' -.*:48: Error: ambiguous operand size for `vfpclassps' +.*:25: Error: ambiguous operand size for `vcvtpd2ph' +.*:26: Error: ambiguous operand size for `vcvtpd2ps' +.*:27: Error: ambiguous operand size for `vfpclassps' #... [ ]*[0-9]+[ ]+> \.arch generic32 [ ]*[0-9]+[ ]+> \.arch default -[ ]*[0-9]+[ ]+\?+ C5FB93D1[ ]+> kmovd %k1,%edx -[ ]*[0-9]+[ ]+\?+ C5FB92D1[ ]+> kmovd %ecx,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1EC4B D9[ ]+> kunpckdq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C5EC4BD9[ ]+> kunpckwd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+> * -[ ]*[0-9]+[ ]+> \.irp sz,d,q -[ ]*[0-9]+[ ]+\?+ C4E1ED4A D9[ ]+>> kaddd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1ED41 D9[ ]+>> kandd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1ED42 D9[ ]+>> kandnd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F990 D1[ ]+>> kmovd %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1F991 0A[ ]+>> kmovd %k1,\(%edx\) -[ ]*[0-9]+[ ]+\?+ C4E1F990 11[ ]+>> kmovd \(%ecx\),%k2 -[ ]*[0-9]+[ ]+\?+ C4E1F944 D1[ ]+>> knotd %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1ED45 D9[ ]+>> kord %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F998 D1[ ]+>> kortestd %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E37933 DA01[ ]+>> kshiftld \$1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E37931 DA01[ ]+>> kshiftrd \$1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F999 D1[ ]+>> ktestd %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1ED47 D9[ ]+>> kxord %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1ED46 D9[ ]+>> kxnord %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1EC4A D9[ ]+>> kaddq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1EC41 D9[ ]+>> kandq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1EC42 D9[ ]+>> kandnq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F890 D1[ ]+>> kmovq %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1F891 0A[ ]+>> kmovq %k1,\(%edx\) -[ ]*[0-9]+[ ]+\?+ C4E1F890 11[ ]+>> kmovq \(%ecx\),%k2 -[ ]*[0-9]+[ ]+\?+ C4E1F844 D1[ ]+>> knotq %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1EC45 D9[ ]+>> korq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F898 D1[ ]+>> kortestq %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E3F933 DA01[ ]+>> kshiftlq \$1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E3F931 DA01[ ]+>> kshiftrq \$1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F899 D1[ ]+>> ktestq %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1EC47 D9[ ]+>> kxorq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1EC46 D9[ ]+>> kxnorq %k1,%k2,%k3 [ ]*[0-9]+[ ]+> * [ ]*[0-9]+[ ]+\?+ 62F5FD48 5A00[ ]+> vcvtpd2phz \(%eax\),%xmm0 [ ]*[0-9]+[ ]+\?+ 62F5FD28 5A00[ ]+> vcvtpd2phy \(%eax\),%xmm0 @@ -131,40 +50,6 @@ #... [ ]*[0-9]+[ ]+> \.arch generic32 [ ]*[0-9]+[ ]+> \.arch \.avx10\.1/256 -[ ]*[0-9]+[ ]+\?+ C5FB93D1[ ]+> kmovd %k1,%edx -[ ]*[0-9]+[ ]+\?+ C5FB92D1[ ]+> kmovd %ecx,%k2 -[ ]*[0-9]+[ ]+> kunpckdq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C5EC4BD9[ ]+> kunpckwd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+> * -[ ]*[0-9]+[ ]+> \.irp sz,d,q -[ ]*[0-9]+[ ]+\?+ C4E1ED4A D9[ ]+>> kaddd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1ED41 D9[ ]+>> kandd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1ED42 D9[ ]+>> kandnd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F990 D1[ ]+>> kmovd %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1F991 0A[ ]+>> kmovd %k1,\(%edx\) -[ ]*[0-9]+[ ]+\?+ C4E1F990 11[ ]+>> kmovd \(%ecx\),%k2 -[ ]*[0-9]+[ ]+\?+ C4E1F944 D1[ ]+>> knotd %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1ED45 D9[ ]+>> kord %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F998 D1[ ]+>> kortestd %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E37933 DA01[ ]+>> kshiftld \$1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E37931 DA01[ ]+>> kshiftrd \$1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F999 D1[ ]+>> ktestd %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1ED47 D9[ ]+>> kxord %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1ED46 D9[ ]+>> kxnord %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kaddq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kandq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kandnq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kmovq %k1,%k2 -[ ]*[0-9]+[ ]+>> kmovq %k1,\(%edx\) -[ ]*[0-9]+[ ]+>> kmovq \(%ecx\),%k2 -[ ]*[0-9]+[ ]+>> knotq %k1,%k2 -[ ]*[0-9]+[ ]+>> korq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kortestq %k1,%k2 -[ ]*[0-9]+[ ]+>> kshiftlq \$1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kshiftrq \$1,%k2,%k3 -[ ]*[0-9]+[ ]+>> ktestq %k1,%k2 -[ ]*[0-9]+[ ]+>> kxorq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kxnorq %k1,%k2,%k3 [ ]*[0-9]+[ ]+> * [ ]*[0-9]+[ ]+> vcvtpd2phz \(%eax\),%xmm0 [ ]*[0-9]+[ ]+\?+ 62F5FD28 5A00[ ]+> vcvtpd2phy \(%eax\),%xmm0 @@ -186,40 +71,6 @@ #... [ ]*[0-9]+[ ]+> \.arch generic32 [ ]*[0-9]+[ ]+> \.arch \.avx10\.1/128 -[ ]*[0-9]+[ ]+> kmovd %k1,%edx -[ ]*[0-9]+[ ]+> kmovd %ecx,%k2 -[ ]*[0-9]+[ ]+> kunpckdq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+> kunpckwd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+> * -[ ]*[0-9]+[ ]+> \.irp sz,d,q -[ ]*[0-9]+[ ]+>> kaddd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kandd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kandnd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kmovd %k1,%k2 -[ ]*[0-9]+[ ]+>> kmovd %k1,\(%edx\) -[ ]*[0-9]+[ ]+>> kmovd \(%ecx\),%k2 -[ ]*[0-9]+[ ]+>> knotd %k1,%k2 -[ ]*[0-9]+[ ]+>> kord %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kortestd %k1,%k2 -[ ]*[0-9]+[ ]+>> kshiftld \$1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kshiftrd \$1,%k2,%k3 -[ ]*[0-9]+[ ]+>> ktestd %k1,%k2 -[ ]*[0-9]+[ ]+>> kxord %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kxnord %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kaddq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kandq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kandnq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kmovq %k1,%k2 -[ ]*[0-9]+[ ]+>> kmovq %k1,\(%edx\) -[ ]*[0-9]+[ ]+>> kmovq \(%ecx\),%k2 -[ ]*[0-9]+[ ]+>> knotq %k1,%k2 -[ ]*[0-9]+[ ]+>> korq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kortestq %k1,%k2 -[ ]*[0-9]+[ ]+>> kshiftlq \$1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kshiftrq \$1,%k2,%k3 -[ ]*[0-9]+[ ]+>> ktestq %k1,%k2 -[ ]*[0-9]+[ ]+>> kxorq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+>> kxnorq %k1,%k2,%k3 [ ]*[0-9]+[ ]+> * [ ]*[0-9]+[ ]+> vcvtpd2phz \(%eax\),%xmm0 [ ]*[0-9]+[ ]+> vcvtpd2phy \(%eax\),%xmm0 @@ -239,40 +90,8 @@ [ ]*[0-9]+[ ]+\?+ C5F95A00[ ]+> vcvtpd2ps xmm0,\[eax\] [ ]*[0-9]+[ ]+\?+ 62F37D08 660000[ ]+> vfpclassps k0,\[eax\],0 #... -[ ]*[0-9]+[ ]+\?+ C5FB93D1[ ]+> kmovd %k1,%edx -[ ]*[0-9]+[ ]+\?+ C5FB92D1[ ]+> kmovd %ecx,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1EC4B D9[ ]+> kunpckdq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C5EC4BD9[ ]+> kunpckwd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+> * -[ ]*[0-9]+[ ]+> \.irp sz,d,q -[ ]*[0-9]+[ ]+\?+ C4E1ED4A D9[ ]+>> kaddd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1ED41 D9[ ]+>> kandd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1ED42 D9[ ]+>> kandnd %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F990 D1[ ]+>> kmovd %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1F991 0A[ ]+>> kmovd %k1,\(%edx\) -[ ]*[0-9]+[ ]+\?+ C4E1F990 11[ ]+>> kmovd \(%ecx\),%k2 -[ ]*[0-9]+[ ]+\?+ C4E1F944 D1[ ]+>> knotd %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1ED45 D9[ ]+>> kord %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F998 D1[ ]+>> kortestd %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E37933 DA01[ ]+>> kshiftld \$1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E37931 DA01[ ]+>> kshiftrd \$1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F999 D1[ ]+>> ktestd %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1ED47 D9[ ]+>> kxord %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1ED46 D9[ ]+>> kxnord %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1EC4A D9[ ]+>> kaddq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1EC41 D9[ ]+>> kandq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1EC42 D9[ ]+>> kandnq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F890 D1[ ]+>> kmovq %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1F891 0A[ ]+>> kmovq %k1,\(%edx\) -[ ]*[0-9]+[ ]+\?+ C4E1F890 11[ ]+>> kmovq \(%ecx\),%k2 -[ ]*[0-9]+[ ]+\?+ C4E1F844 D1[ ]+>> knotq %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1EC45 D9[ ]+>> korq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F898 D1[ ]+>> kortestq %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E3F933 DA01[ ]+>> kshiftlq \$1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E3F931 DA01[ ]+>> kshiftrq \$1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1F899 D1[ ]+>> ktestq %k1,%k2 -[ ]*[0-9]+[ ]+\?+ C4E1EC47 D9[ ]+>> kxorq %k1,%k2,%k3 -[ ]*[0-9]+[ ]+\?+ C4E1EC46 D9[ ]+>> kxnorq %k1,%k2,%k3 +[ ]*[0-9]+[ ]+> \.arch generic32 +[ ]*[0-9]+[ ]+> \.arch \.avx10\.1 [ ]*[0-9]+[ ]+> * [ ]*[0-9]+[ ]+\?+ 62F5FD48 5A00[ ]+> vcvtpd2phz \(%eax\),%xmm0 [ ]*[0-9]+[ ]+\?+ 62F5FD28 5A00[ ]+> vcvtpd2phy \(%eax\),%xmm0 diff --git a/gas/testsuite/gas/i386/avx10-vsz.s b/gas/testsuite/gas/i386/avx10-vsz.s index 0023253e760..47692e85f46 100644 --- a/gas/testsuite/gas/i386/avx10-vsz.s +++ b/gas/testsuite/gas/i386/avx10-vsz.s @@ -7,27 +7,6 @@ .warning "\isa" .arch generic32 .arch \isa - kmovd %k1, %edx - kmovd %ecx, %k2 - kunpckdq %k1, %k2, %k3 - kunpckwd %k1, %k2, %k3 - - .irp sz, d, q - kadd\sz %k1, %k2, %k3 - kand\sz %k1, %k2, %k3 - kandn\sz %k1, %k2, %k3 - kmov\sz %k1, %k2 - kmov\sz %k1, (%edx) - kmov\sz (%ecx), %k2 - knot\sz %k1, %k2 - kor\sz %k1, %k2, %k3 - kortest\sz %k1, %k2 - kshiftl\sz $1, %k2, %k3 - kshiftr\sz $1, %k2, %k3 - ktest\sz %k1, %k2 - kxor\sz %k1, %k2, %k3 - kxnor\sz %k1, %k2, %k3 - .endr vcvtpd2phz (%eax), %xmm0 vcvtpd2phy (%eax), %xmm0 diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index e86402a2d48..d7346e17683 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -480,7 +480,6 @@ static bitfield opcode_modifiers[] = BITFIELD (StaticRounding), BITFIELD (SAE), BITFIELD (Disp8MemShift), - BITFIELD (Vsz), BITFIELD (Optimize), BITFIELD (ATTMnemonic), BITFIELD (ATTSyntax), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 7bb8084b291..8bf4c4d1b3b 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -716,16 +716,6 @@ enum #define DISP8_SHIFT_VL 7 Disp8MemShift, - /* insn has vector size restrictions, requiring a minimum of: - 0: 128 bits. - 1: 256 bits. - 2: 512 bits. - */ -#define VSZ128 0 /* Not to be used in templates. */ -#define VSZ256 1 -#define VSZ512 2 - Vsz, - /* Support encoding optimization. */ Optimize, @@ -786,7 +776,6 @@ typedef struct i386_opcode_modifier unsigned int staticrounding:1; unsigned int sae:1; unsigned int disp8memshift:3; - unsigned int vsz:3; unsigned int optimize:1; unsigned int attmnemonic:1; unsigned int attsyntax:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index f89c4cb5bcd..a5f49bc0559 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -135,9 +135,6 @@ #define Disp8ShiftVL Disp8MemShift=DISP8_SHIFT_VL -#define Vsz256 Vsz=VSZ256 -#define Vsz512 Vsz=VSZ512 - // The EVEX purpose of StaticRounding appears only together with SAE. Re-use // the bit to mark commutative VEX encodings where swapping the source // operands may allow to switch from 3-byte to 2-byte VEX encoding. @@ -996,9 +993,9 @@ pause, 0xf390, i186, NoSuf, {} b:0:VexW0:Byte:AVX512DQ:66:AVX512VBMI, + w:1:VexW1:Word:AVX512F::AVX512BW> - + emms, 0xf77, MMX, NoSuf, {} // These really shouldn't allow for Reg64 (movq is the right mnemonic for @@ -2590,22 +2587,22 @@ vpmovzxdq, 0x6635, AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift // AVX512BW instructions. -kadd, 0x4a, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf, { RegMask, RegMask, RegMask } -kand, 0x41, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf, { RegMask, RegMask, RegMask } -kandn, 0x42, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf|Optimize, { RegMask, RegMask, RegMask } -kmov, 0x90, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } -kmov, 0x91, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, |Unspecified|BaseIndex } -kmov, 0xf292, AVX512BW, D|Modrm|Vex128|Space0F|||NoSuf, { , RegMask } -knot, 0x44, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, RegMask } -kor, 0x45, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf, { RegMask, RegMask, RegMask } -kortest, 0x98, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, RegMask } -ktest, 0x99, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, RegMask } -kxnor, 0x46, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf, { RegMask, RegMask, RegMask } -kxor, 0x47, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf|Optimize, { RegMask, RegMask, RegMask } -kunpckdq, 0x4B, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|Vsz512|NoSuf, { RegMask, RegMask, RegMask } -kunpckwd, 0x4B, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW0|Vsz256|NoSuf, { RegMask, RegMask, RegMask } -kshiftl, 0x6633, AVX512BW, Modrm|Vex128|Space0F3A|||NoSuf, { Imm8, RegMask, RegMask } -kshiftr, 0x6631, AVX512BW, Modrm|Vex128|Space0F3A|||NoSuf, { Imm8, RegMask, RegMask } +kadd, 0x4a, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } +kand, 0x41, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } +kandn, 0x42, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } +kmov, 0x90, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } +kmov, 0x91, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, |Unspecified|BaseIndex } +kmov, 0xf292, AVX512BW, D|Modrm|Vex128|Space0F||NoSuf, { , RegMask } +knot, 0x44, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } +kor, 0x45, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } +kortest, 0x98, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } +ktest, 0x99, AVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } +kxnor, 0x46, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } +kxor, 0x47, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } +kunpckdq, 0x4B, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } +kunpckwd, 0x4B, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } +kshiftl, 0x6633, AVX512BW, Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } +kshiftr, 0x6631, AVX512BW, Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } vdbpsadbw, 0x6642, AVX512BW, Modrm|Masking|Space0F3A|VexVVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }