From patchwork Tue Dec 12 02:06:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 81941 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A4BA43858006 for ; Tue, 12 Dec 2023 02:07:05 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id B3FC83858C2F for ; Tue, 12 Dec 2023 02:06:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B3FC83858C2F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B3FC83858C2F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.243.244.52 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702346810; cv=none; b=FZJfyA10mczUYf6LptqcTDAWSJHmLoMNPWSSLBNQCrsGJfcyZO+2Nas3wzl63DDXEK8jvGg/q27o2BgzdBh/a9oPKbnHTZwenm9HRa8JKm1VaPPiJw9/2poW3fLc+PtvEOZQySRdnBWtdxH9HpbRuLRtn4LTLRsf0sp4kT727dc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702346810; c=relaxed/simple; bh=rc9DaTnTjqxCYOxrJBwqUw1oeJyWYwcJxp9Kx+DlUzs=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=NfTsPUOZ82q6X1gP+UdglirJfO9kVEil2OzVnh1KuJjq3vR+/OpvG1zNHd09ata/tnS3N2L5FHgx9aK0nLCFMg89JoJbTTCMvp5Gsl6zdD+xghWuhnKka5uVL1XS3ALAOQ5/JQmI3gXZzPP8fmcVxgnVmN5qyFBio7x5CNQMM0s= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp78t1702346801tmod2ux6 Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 12 Dec 2023 10:06:40 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: +ynUkgUhZJmcHHXOrDpsUQdVTsQ376ynDAMV4aeDz6boxyLLqvYElW/YPaO+g 1lbZCXDsVZvQAPdY0eFZJWSwLqOAt0zPNZ/x2qvxKKv7fSXiRnCQ0RHbKuxIfx8JxW8F/Ka ehRoyHc7k0cLmR/kwjUzZFpnNGgvJuJsOw6tlQgluV0SHGNRoeM0EHeGr4nftZT1258B1V8 OKRAiecJTkp9/1T1VgxhIOxEqj0Ij067ePFQfak8/RP2zwoiAofA6MEsK1IwDgDkZnwOdgS zuf18+VvFFoXdjd/DQZookuDwUGoh/iMV5dqziWuLDV5UJ6wRkSlUCmC3tyjRqwWFpAVGsD BdXEkbHQZd7Sq+sfkrwlqUv06N+gUYt1R/8rSUC X-QQ-GoodBg: 2 X-BIZMAIL-ID: 1616714858603679786 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed] RISC-V: Move RVV POLY VALUE estimation from riscv.cc to riscv-v.cc[NFC] Date: Tue, 12 Dec 2023 10:06:38 +0800 Message-Id: <20231212020638.4131759-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org This patch moves RVV POLY VALUE estimation from riscv.cc to riscv-v.cc for future better maintain like other target hook implementation. Committed as it is obviously a code refinement. gcc/ChangeLog: * config/riscv/riscv-protos.h (estimated_poly_value): New function. * config/riscv/riscv-v.cc (estimated_poly_value): Ditto. * config/riscv/riscv.cc (riscv_estimated_poly_value): Move RVV POLY VALUE estimation to riscv-v.cc --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 47 +++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv.cc | 44 +++--------------------------- 3 files changed, 52 insertions(+), 40 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 20bbb5b859c..85ab1db2088 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -608,6 +608,7 @@ int count_regno_occurrences (rtx_insn *, unsigned int); bool imm_avl_p (machine_mode); bool can_be_broadcasted_p (rtx); bool gather_scatter_valid_offset_p (machine_mode); +HOST_WIDE_INT estimated_poly_value (poly_int64, unsigned int); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 944b37b5df7..01898cb4b8d 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4927,4 +4927,51 @@ gather_scatter_valid_offset_p (machine_mode mode) return true; } +/* Implement TARGET_ESTIMATED_POLY_VALUE. + Look into the tuning structure for an estimate. + KIND specifies the type of requested estimate: min, max or likely. + For cores with a known VLA width all three estimates are the same. + For generic VLA tuning we want to distinguish the maximum estimate from + the minimum and likely ones. + The likely estimate is the same as the minimum in that case to give a + conservative behavior of auto-vectorizing with VLA when it is a win + even for VLA vectorization. + When VLA width information is available VAL.coeffs[1] is multiplied by + the number of VLA chunks over the initial VLS bits. */ +HOST_WIDE_INT +estimated_poly_value (poly_int64 val, unsigned int kind) +{ + unsigned int width_source + = BITS_PER_RISCV_VECTOR.is_constant () + ? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant () + : (unsigned int) RVV_SCALABLE; + + /* If there is no core-specific information then the minimum and likely + values are based on TARGET_MIN_VLEN vectors and the maximum is based on + the architectural maximum of 65536 bits. */ + unsigned int min_vlen_bytes = TARGET_MIN_VLEN / 8 - 1; + if (width_source == RVV_SCALABLE) + switch (kind) + { + case POLY_VALUE_MIN: + case POLY_VALUE_LIKELY: + return val.coeffs[0]; + + case POLY_VALUE_MAX: + return val.coeffs[0] + val.coeffs[1] * min_vlen_bytes; + } + + /* Allow BITS_PER_RISCV_VECTOR to be a bitmask of different VL, treating the + lowest as likely. This could be made more general if future -mtune + options need it to be. */ + if (kind == POLY_VALUE_MAX) + width_source = 1 << floor_log2 (width_source); + else + width_source = least_bit_hwi (width_source); + + /* If the core provides width information, use that. */ + HOST_WIDE_INT over_min_vlen = width_source - TARGET_MIN_VLEN; + return val.coeffs[0] + val.coeffs[1] * over_min_vlen / TARGET_MIN_VLEN; +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 3f111fa0393..69a8a503f30 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -9604,51 +9604,15 @@ riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor, return RISCV_DWARF_VLENB; } -/* Implement TARGET_ESTIMATED_POLY_VALUE. - Look into the tuning structure for an estimate. - KIND specifies the type of requested estimate: min, max or likely. - For cores with a known RVV width all three estimates are the same. - For generic RVV tuning we want to distinguish the maximum estimate from - the minimum and likely ones. - The likely estimate is the same as the minimum in that case to give a - conservative behavior of auto-vectorizing with RVV when it is a win - even for 128-bit RVV. - When RVV width information is available VAL.coeffs[1] is multiplied by - the number of VQ chunks over the initial Advanced SIMD 128 bits. */ +/* Implement TARGET_ESTIMATED_POLY_VALUE. */ static HOST_WIDE_INT riscv_estimated_poly_value (poly_int64 val, poly_value_estimate_kind kind = POLY_VALUE_LIKELY) { - unsigned int width_source = BITS_PER_RISCV_VECTOR.is_constant () - ? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant () - : (unsigned int) RVV_SCALABLE; - - /* If there is no core-specific information then the minimum and likely - values are based on 128-bit vectors and the maximum is based on - the architectural maximum of 65536 bits. */ - if (width_source == RVV_SCALABLE) - switch (kind) - { - case POLY_VALUE_MIN: - case POLY_VALUE_LIKELY: - return val.coeffs[0]; - - case POLY_VALUE_MAX: - return val.coeffs[0] + val.coeffs[1] * 15; - } - - /* Allow BITS_PER_RISCV_VECTOR to be a bitmask of different VL, treating the - lowest as likely. This could be made more general if future -mtune - options need it to be. */ - if (kind == POLY_VALUE_MAX) - width_source = 1 << floor_log2 (width_source); - else - width_source = least_bit_hwi (width_source); - - /* If the core provides width information, use that. */ - HOST_WIDE_INT over_128 = width_source - 128; - return val.coeffs[0] + val.coeffs[1] * over_128 / 128; + if (TARGET_VECTOR) + return riscv_vector::estimated_poly_value (val, kind); + return default_estimated_poly_value (val, kind); } /* Return true if the vector misalignment factor is supported by the