From patchwork Mon Dec 11 06:49:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 81879 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1ADBE3858409 for ; Mon, 11 Dec 2023 06:52:00 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 112903858D32 for ; Mon, 11 Dec 2023 06:51:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 112903858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 112903858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=134.134.136.20 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702277504; cv=none; b=iSfxiXroLA/OUNMJG8G6ATX9AGh66Kfm8ipi9rjpxUgeV1oO9T3d4KlTko3sYSA8MC2ztcR25xQaMX4NixNNjvkS7vM8YqtlUMYLGeBaAIgiPNDVrjmCt9jCfDTLrpwU32OLlic6pg3Wvcqmo0PIk45v7eE1V6r/kJwRrwziPOo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702277504; c=relaxed/simple; bh=Lm8hQ+qATcZ7SKwEiD390TccSIP4+912TtUZoeRmJLg=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=rNRW4auZFdB/lBz2QlrPaofEQ9FaK2RNpAyeDeWKAMuG5oLh47xxr2KnE9bM77TPYFZY7RaCqu5pieeffJYOorJFIVYA8rWlXQ7oHq4Aog2jKTKSgJyNIm+Ozz3TcQc1zZZa3EPbs9wW1qi/JuCRlVIVWmKCgb5OcBfwZ/KFUcI= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702277503; x=1733813503; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Lm8hQ+qATcZ7SKwEiD390TccSIP4+912TtUZoeRmJLg=; b=M4RRlNmjDcQGKnOTfT3biypoqWjCoOH2Qldm3o+X3pmKEOXK4kqj0ljp Bgq5e0IrhNShjkzi697gefuPNqaVgYKklI+NLOLNdjn/mCalDlDjkrT5T GvERmyyg1eOvkJholKoJYy+VKVBQF4llRAeWTK6HVRaJRp7O9Deq1nDjw dcDFdY7cf8fHs7/qt5j++iNDcAQboE4YIYpCdBgPHAVxcI/jmtrEQa/eO UpFdgVtqEDh1vXEoQURFXZvLN8PlG52ZKaDIsIojBJ3awAlYGlDDoVvLf 2ZGhIB+akH9HdXmhiThxKOmOaFN0dyH6EpiKxz00IQyk+VEDrOSlIYaO5 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10920"; a="385012122" X-IronPort-AV: E=Sophos;i="6.04,267,1695711600"; d="scan'208";a="385012122" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2023 22:51:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10920"; a="749162281" X-IronPort-AV: E=Sophos;i="6.04,267,1695711600"; d="scan'208";a="749162281" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga006.jf.intel.com with ESMTP; 10 Dec 2023 22:51:40 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 7025F10079B6; Mon, 11 Dec 2023 14:51:39 +0800 (CST) From: liuhongt To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com Subject: [v3 PATCH] Simplify vector ((VCE (a cmp b ? -1 : 0)) < 0) ? c : d to just (VCE ((a cmp b) ? (VCE c) : (VCE d))). Date: Mon, 11 Dec 2023 14:49:39 +0800 Message-Id: <20231211064939.1751320-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org > since you are looking at TYPE_PRECISION below you want > VECTOR_INTIEGER_TYPE_P here as well? The alternative > would be to compare TYPE_SIZE. > > Some of the checks feel redundant but are probably good for > documentation purposes. > > OK with using VECTOR_INTIEGER_TYPE_P Actually, the data type doens't need to integer, .i.e x86 support vblendvps so I'm using TYPE_SIZE here, the code is adjusted to && tree_fits_uhwi_p (TYPE_SIZE (TREE_TYPE (type))) && (tree_to_uhwi (TYPE_SIZE (TREE_TYPE (type))) <= TYPE_PRECISION (TREE_TYPE (TREE_TYPE (@6)))) Here's the updated patch. Ok for trunk? When I'm working on PR112443, I notice there's some misoptimizations: after we fold _mm{,256}_blendv_epi8/pd/ps into gimple, the backend fails to combine it back to v{,p}blendv{v,ps,pd} since the pattern is too complicated, so I think maybe we should hanlde it in the gimple level. The dump is like _1 = c_3(D) >= { 0, 0, 0, 0 }; _2 = VEC_COND_EXPR <_1, { -1, -1, -1, -1 }, { 0, 0, 0, 0 }>; _7 = VIEW_CONVERT_EXPR(_2); _8 = VIEW_CONVERT_EXPR(b_6(D)); _9 = VIEW_CONVERT_EXPR(a_5(D)); _10 = _7 < { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; _11 = VEC_COND_EXPR <_10, _8, _9>; It can be optimized to _1 = c_2(D) >= { 0, 0, 0, 0 }; _6 = VEC_COND_EXPR <_1, b_5(D), a_4(D)>; since _7 is either -1 or 0, the selection of _7 < 0 ? _8 : _9 should be euqal to _1 ? b : a as long as TYPE_PRECISION of the component type of the second VEC_COND_EXPR is less equal to the first one. The patch add a gimple pattern to handle that. gcc/ChangeLog: * match.pd (VCE (a cmp b ? -1 : 0) < 0) ? c : d ---> (VCE ((a cmp b) ? (VCE:c) : (VCE:d))): New gimple simplication. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512vl-blendv-3.c: New test. * gcc.target/i386/blendv-3.c: New test. --- gcc/match.pd | 23 ++++++++++ .../gcc.target/i386/avx512vl-blendv-3.c | 6 +++ gcc/testsuite/gcc.target/i386/blendv-3.c | 46 +++++++++++++++++++ 3 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-blendv-3.c create mode 100644 gcc/testsuite/gcc.target/i386/blendv-3.c diff --git a/gcc/match.pd b/gcc/match.pd index 4d554ba4721..359c7b07dc3 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -5190,6 +5190,29 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (if (optimize_vectors_before_lowering_p () && types_match (@0, @3)) (vec_cond (bit_and @0 (bit_not @3)) @2 @1))) +/* ((VCE (a cmp b ? -1 : 0)) < 0) ? c : d is just + (VCE ((a cmp b) ? (VCE c) : (VCE d))) when TYPE_PRECISION of the + component type of the outer vec_cond is greater equal the inner one. */ +(for cmp (simple_comparison) + (simplify + (vec_cond + (lt (view_convert@5 (vec_cond@6 (cmp@4 @0 @1) + integer_all_onesp + integer_zerop)) + integer_zerop) @2 @3) + (if (VECTOR_INTEGER_TYPE_P (TREE_TYPE (@0)) + && VECTOR_INTEGER_TYPE_P (TREE_TYPE (@5)) + && !TYPE_UNSIGNED (TREE_TYPE (@5)) + && VECTOR_TYPE_P (TREE_TYPE (@6)) + && VECTOR_TYPE_P (type) + && tree_fits_uhwi_p (TYPE_SIZE (TREE_TYPE (type))) + && (tree_to_uhwi (TYPE_SIZE (TREE_TYPE (type))) + <= TYPE_PRECISION (TREE_TYPE (TREE_TYPE (@6)))) + && TYPE_SIZE (type) == TYPE_SIZE (TREE_TYPE (@6))) + (with { tree vtype = TREE_TYPE (@6);} + (view_convert:type + (vec_cond @4 (view_convert:vtype @2) (view_convert:vtype @3))))))) + /* c1 ? c2 ? a : b : b --> (c1 & c2) ? a : b */ (simplify (vec_cond @0 (vec_cond:s @1 @2 @3) @3) diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-blendv-3.c b/gcc/testsuite/gcc.target/i386/avx512vl-blendv-3.c new file mode 100644 index 00000000000..2777e72ab5f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-blendv-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vl -mavx512bw -O2" } */ +/* { dg-final { scan-assembler-times {vp?blendv(?:b|p[sd])[ \t]*} 6 } } */ +/* { dg-final { scan-assembler-not {vpcmp} } } */ + +#include "blendv-3.c" diff --git a/gcc/testsuite/gcc.target/i386/blendv-3.c b/gcc/testsuite/gcc.target/i386/blendv-3.c new file mode 100644 index 00000000000..fa0fb067a73 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/blendv-3.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler-times {vp?blendv(?:b|p[sd])[ \t]*} 6 } } */ +/* { dg-final { scan-assembler-not {vpcmp} } } */ + +#include + +__m256i +foo (__m256i a, __m256i b, __m256i c) +{ + return _mm256_blendv_epi8 (a, b, ~c < 0); +} + +__m256d +foo1 (__m256d a, __m256d b, __m256i c) +{ + __m256i d = ~c < 0; + return _mm256_blendv_pd (a, b, (__m256d)d); +} + +__m256 +foo2 (__m256 a, __m256 b, __m256i c) +{ + __m256i d = ~c < 0; + return _mm256_blendv_ps (a, b, (__m256)d); +} + +__m128i +foo4 (__m128i a, __m128i b, __m128i c) +{ + return _mm_blendv_epi8 (a, b, ~c < 0); +} + +__m128d +foo5 (__m128d a, __m128d b, __m128i c) +{ + __m128i d = ~c < 0; + return _mm_blendv_pd (a, b, (__m128d)d); +} + +__m128 +foo6 (__m128 a, __m128 b, __m128i c) +{ + __m128i d = ~c < 0; + return _mm_blendv_ps (a, b, (__m128)d); +}