From patchwork Mon Dec 4 04:39:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 81246 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 75A183857C4D for ; Mon, 4 Dec 2023 04:40:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id A9E243858039 for ; Mon, 4 Dec 2023 04:39:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A9E243858039 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A9E243858039 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=18.169.211.239 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701664803; cv=none; b=SGtTyLN0rUcAWEK7k/glavvAM/Gfg16KTzXeXoMrMemz52iO/gDDFkV8G99FW+n0gEg+JYO1A8yAlI8NprrAzYmCzkCYFhH+PeYTF7ZEpS95guuSfM5/bHa3joOD/GqP6gBMSZTaz8/eDg94wIBjEeaKVVOeluZC+A76CAHG8k4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701664803; c=relaxed/simple; bh=noyEk2Eu4Fj//3qLg+UNWbjgjXeNTDjrNYRU690WVZc=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=oqbIzwTu23znYjZuGOLQg8BT9R2Z83253JeGzc99OZ/JiMDUCA4HH1zwH42B/pLXzMpmFh25rLOHcnP2Fr5WBWlu3978diBhP8YoJrC56oIWhSQk/iNSRavqKEcfwY4bnmikFuFE2puKvcG1k2xMi92mfD8ZWrA3BcQK30UMttc= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp86t1701664787tpoiwm0b Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 04 Dec 2023 12:39:46 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: znfcQSa1hKa/cWl+ZrciIeYn76Mc0+I+2xD5GXTPrgrxYqXOln4FFo+YVKtPC 8TmVlkpqAccqB7EHh9SBN0GioexEyB3joPAapPM9xlRL92tdd0WZBLhwhwil8aSZH/C3Y/Y zmBtSSjWicePIqNb/8z/gje+6xZ+sIEU8nPYWgA+9p271i9oBX6gnA1r+nErDVaJ3O8mr+O Nvp87VPL33NVUZGHdXPFJARFW6TsPtJQUOIB7sT79d3DkDgvjeWNwjRF8vGppkkRhS7UaRo Iqk/C0XwJTwJL8UPmVWwe7R9pcNScGr/834bqhMXJOyai7OBJj7+bu4LdS3nEnA85wHXBug WOjyee/iAIO4rUR/SCe1DLZKUGSuhEWqRwGXSXn1KVrwWes9aOWiKkAr4Iacggj9XudxCgJ 3Hy6bsMFwyomb70EIUyj4w== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 16862032969376819245 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix overlap group incorrect overlap on v0 Date: Mon, 4 Dec 2023 12:39:45 +0800 Message-Id: <20231204043945.367103-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_35_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org In serious high register pressure case (appended in this patch): We see vluxei8.v v0,(s1),v1,v0.t which is not allowed. Since according to RVV ISA: +;; The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0), +;; unless the destination vector register is being written with a mask value (e.g., compares) or the scalar result of a reduction. Such case doesn't have spillings, however, we expect such case should be spilled and reload data. The rootcause is I made a mistake in previous patch on matching dest operand and mask operand constraints: dest: "=vr" mask: "vmWc1" After this patch: dest: "vd,vr" mask: "vm,Wc1" make EEW widening pattern are same as other instruction patterns. PR target/112431 gcc/ChangeLog: * config/riscv/vector-iterators.md: New attributes. * config/riscv/vector.md: Fix incorrect overlap. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-34.c: New test. --- gcc/config/riscv/vector-iterators.md | 1077 +++++++++++++++++ gcc/config/riscv/vector.md | 268 ++-- .../gcc.target/riscv/rvv/base/pr112431-34.c | 101 ++ 3 files changed, 1312 insertions(+), 134 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 56080ed1f5f..f97f33f98ee 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -3916,3 +3916,1080 @@ (V1024BI "riscv_vector::vls_mode_valid_p (V1024BImode) && TARGET_MIN_VLEN >= 1024") (V2048BI "riscv_vector::vls_mode_valid_p (V2048BImode) && TARGET_MIN_VLEN >= 2048") (V4096BI "riscv_vector::vls_mode_valid_p (V4096BImode) && TARGET_MIN_VLEN >= 4096")]) + +;; The following attributes are used by EEW widening instructions. +;; Since according to RVV ISA: +;; The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0), +;; unless the destination vector register is being written with a mask value (e.g., compares) or the scalar result of a reduction. +;; We don't allow v v0,...v0.t happens for widening instructions. + +(define_mode_attr widen_eew_dest_constraint [ + (RVVM8QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM4QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM2QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM1QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVMF2QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVMF4QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVMF8QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM8HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM4HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM2HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM1HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVMF2HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVMF4HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM8HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM4HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM2HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM1HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVMF2HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVMF4HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM8SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM4SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM2SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM1SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVMF2SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM8SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM4SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM2SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM1SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVMF2SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM8DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM4DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM2DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM1DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM8DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM4DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM2DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (RVVM1DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V1QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V2QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V4QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V8QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V16QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V32QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V64QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V128QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V256QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V512QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V1024QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V2048QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V4096QI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V1HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V2HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V4HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V8HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V16HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V32HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V64HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V128HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V256HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V512HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V1024HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V2048HI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V1SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V2SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V4SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V8SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V16SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V32SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V64SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V128SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V256SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V512SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V1024SI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V1DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V2DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V4DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V8DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V16DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V32DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V64DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V128DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V256DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V512DI "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V1HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V2HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V4HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V8HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V16HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V32HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V64HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V128HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V256HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V512HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V1024HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V2048HF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V1SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V2SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V4SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V8SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V16SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V32SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V64SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V128SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V256SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V512SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V1024SF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V1DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V2DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V4DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V8DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V16DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V32DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V64DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V128DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V256DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + (V512DF "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") +]) + +(define_mode_attr widen_eew_mask_constraint [ + (RVVM8QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM4QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM2QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM1QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVMF2QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVMF4QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVMF8QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM8HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM4HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM2HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM1HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVMF2HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVMF4HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM8HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM4HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM2HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM1HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVMF2HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVMF4HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM8SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM4SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM2SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM1SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVMF2SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM8SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM4SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM2SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM1SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVMF2SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM8DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM4DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM2DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM1DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM8DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM4DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM2DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (RVVM1DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V1QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V2QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V4QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V8QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V16QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V32QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V64QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V128QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V256QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V512QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V1024QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V2048QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V4096QI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V1HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V2HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V4HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V8HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V16HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V32HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V64HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V128HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V256HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V512HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V1024HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V2048HI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V1SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V2SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V4SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V8SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V16SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V32SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V64SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V128SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V256SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V512SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V1024SI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V1DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V2DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V4DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V8DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V16DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V32DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V64DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V128DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V256DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V512DI " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V1HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V2HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V4HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V8HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V16HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V32HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V64HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V128HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V256HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V512HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V1024HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V2048HF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V1SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V2SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V4SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V8SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V16SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V32SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V64SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V128SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V256SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V512SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V1024SF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V1DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V2DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V4DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V8DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V16DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V32DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V64DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V128DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V256DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (V512DF " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") +]) + +(define_mode_attr widen_eew_len_constraint [ + (RVVM8QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM4QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM2QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM1QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVMF2QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVMF4QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVMF8QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM8HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM4HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM2HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM1HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVMF2HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVMF4HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM8HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM4HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM2HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM1HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVMF2HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVMF4HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM8SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM4SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM2SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM1SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVMF2SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM8SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM4SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM2SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM1SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVMF2SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM8DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM4DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM2DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM1DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM8DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM4DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM2DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (RVVM1DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V1QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V2QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V4QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V8QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V16QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V32QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V64QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V128QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V256QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V512QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V1024QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V2048QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V4096QI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V1HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V2HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V4HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V8HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V16HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V32HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V64HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V128HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V256HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V512HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V1024HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V2048HI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V1SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V2SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V4SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V8SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V16SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V32SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V64SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V128SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V256SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V512SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V1024SI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V1DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V2DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V4DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V8DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V16DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V32DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V64DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V128DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V256DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V512DI " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V1HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V2HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V4HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V8HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V16HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V32HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V64HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V128HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V256HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V512HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V1024HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V2048HF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V1SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V2SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V4SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V8SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V16SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V32SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V64SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V128SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V256SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V512SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V1024SF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V1DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V2DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V4DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V8DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V16DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V32DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V64DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V128DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V256DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (V512DF " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") +]) + +(define_mode_attr widen_eew_const_int_constraint [ + (RVVM8QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM4QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM2QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM1QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVMF2QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVMF4QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVMF8QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM8HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM4HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM2HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM1HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVMF2HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVMF4HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM8HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM4HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM2HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM1HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVMF2HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVMF4HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM8SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM4SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM2SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM1SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVMF2SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM8SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM4SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM2SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM1SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVMF2SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM8DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM4DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM2DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM1DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM8DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM4DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM2DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (RVVM1DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V1QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V2QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V4QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V8QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V16QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V32QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V64QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V128QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V256QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V512QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V1024QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V2048QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V4096QI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V1HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V2HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V4HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V8HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V16HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V32HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V64HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V128HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V256HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V512HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V1024HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V2048HI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V1SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V2SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V4SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V8SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V16SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V32SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V64SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V128SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V256SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V512SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V1024SI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V1DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V2DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V4DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V8DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V16DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V32DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V64DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V128DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V256DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V512DI "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V1HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V2HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V4HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V8HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V16HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V32HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V64HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V128HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V256HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V512HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V1024HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V2048HF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V1SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V2SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V4SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V8SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V16SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V32SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V64SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V128SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V256SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V512SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V1024SF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V1DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V2DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V4DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V8DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V16DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V32DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V64DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V128DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V256DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") + (V512DF "i, i, i, i, i, i, i, i, i, i, i, i, i, i") +]) + +(define_mode_attr widen_eew_scalar_constraint [ + (RVVM8QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM4QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM2QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM1QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVMF2QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVMF4QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVMF8QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM8HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM4HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM2HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM1HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVMF2HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVMF4HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM8HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM4HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM2HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM1HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVMF2HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVMF4HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM8SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM4SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM2SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM1SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVMF2SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM8SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM4SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM2SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM1SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVMF2SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM8DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM4DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM2DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM1DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM8DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM4DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM2DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (RVVM1DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V1QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V2QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V4QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V8QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V16QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V32QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V64QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V128QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V256QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V512QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V1024QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V2048QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V4096QI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V1HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V2HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V4HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V8HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V16HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V32HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V64HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V128HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V256HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V512HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V1024HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V2048HI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V1SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V2SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V4SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V8SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V16SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V32SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V64SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V128SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V256SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V512SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V1024SI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V1DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V2DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V4DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V8DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V16DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V32DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V64DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V128DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V256DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V512DI " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V1HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V2HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V4HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V8HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V16HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V32HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V64HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V128HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V256HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V512HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V1024HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V2048HF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V1SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V2SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V4SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V8SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V16SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V32SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V64SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V128SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V256SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V512SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V1024SF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V1DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V2DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V4DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V8DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V16DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V32DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V64DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V128DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V256DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + (V512DF " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") +]) + +(define_mode_attr widen_eew_fp_scalar_constraint [ + (RVVM8QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM4QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM2QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM1QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVMF2QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVMF4QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVMF8QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM8HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM4HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM2HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM1HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVMF2HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVMF4HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM8HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM4HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM2HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM1HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVMF2HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVMF4HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM8SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM4SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM2SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM1SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVMF2SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM8SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM4SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM2SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM1SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVMF2SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM8DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM4DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM2DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM1DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM8DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM4DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM2DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (RVVM1DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V1QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V2QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V4QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V8QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V16QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V32QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V64QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V128QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V256QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V512QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V1024QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V2048QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V4096QI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V1HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V2HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V4HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V8HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V16HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V32HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V64HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V128HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V256HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V512HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V1024HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V2048HI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V1SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V2SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V4SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V8SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V16SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V32SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V64SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V128SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V256SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V512SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V1024SI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V1DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V2DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V4DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V8DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V16DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V32DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V64DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V128DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V256DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V512DI " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V1HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V2HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V4HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V8HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V16HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V32HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V64HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V128HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V256HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V512HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V1024HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V2048HF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V1SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V2SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V4SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V8SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V16SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V32SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V64SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V128SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V256SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V512SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V1024SF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V1DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V2DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V4DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V8DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V16DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V32DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V64DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V128DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V256DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") + (V512DF " f, f, f, f, f, f, f, f, f, f, f, f, f, f") +]) + +(define_mode_attr widen_eew_source_constraint [ + (RVVM8QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM4QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM2QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM1QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVMF2QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVMF4QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVMF8QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM8HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM4HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM2HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM1HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVMF2HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVMF4HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM8HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM4HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM2HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM1HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVMF2HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVMF4HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM8SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM4SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM2SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM1SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVMF2SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM8SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM4SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM2SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM1SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVMF2SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM8DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM4DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM2DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM1DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM8DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM4DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM2DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (RVVM1DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V1QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V2QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V4QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V8QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V16QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V32QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V64QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V128QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V256QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V512QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V1024QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V2048QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V4096QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V1HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V2HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V4HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V8HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V16HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V32HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V64HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V128HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V256HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V512HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V1024HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V2048HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V1SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V2SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V4SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V8SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V16SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V32SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V64SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V128SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V256SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V512SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V1024SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V1DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V2DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V4DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V8DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V16DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V32DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V64DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V128DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V256DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V512DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V1HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V2HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V4HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V8HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V16HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V32HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V64HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V128HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V256HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V512HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V1024HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V2048HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V1SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V2SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V4SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V8SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V16SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V32SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V64SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V128SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V256SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V512SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V1024SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V1DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V2DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V4DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V8DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V16DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V32DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V64DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V128DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V256DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") + (V512DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr") +]) + +(define_mode_attr widen_eew_merge_constraint [ + (RVVM8QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM4QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM2QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM1QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVMF2QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVMF4QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVMF8QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM8HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM4HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM2HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM1HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVMF2HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVMF4HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM8HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM4HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM2HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM1HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVMF2HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVMF4HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM8SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM4SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM2SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM1SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVMF2SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM8SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM4SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM2SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM1SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVMF2SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM8DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM4DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM2DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM1DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM8DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM4DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM2DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (RVVM1DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V1QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V2QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V4QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V8QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V16QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V32QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V64QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V128QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V256QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V512QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V1024QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V2048QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V4096QI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V1HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V2HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V4HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V8HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V16HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V32HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V64HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V128HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V256HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V512HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V1024HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V2048HI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V1SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V2SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V4SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V8SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V16SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V32SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V64SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V128SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V256SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V512SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V1024SI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V1DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V2DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V4DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V8DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V16DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V32DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V64DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V128DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V256DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V512DI " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V1HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V2HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V4HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V8HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V16HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V32HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V64HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V128HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V256HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V512HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V1024HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V2048HF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V1SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V2SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V4SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V8SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V16SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V32SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V64SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V128SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V256SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V512SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V1024SF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V1DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V2DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V4DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V8DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V16DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V32DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V64DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V128DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V256DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") + (V512DF " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0") +]) + +(define_mode_attr widen_eew_group_overlap [ + (RVVM8QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM4QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM2QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM1QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVMF2QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVMF4QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVMF8QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM8HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM4HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM2HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM1HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVMF2HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVMF4HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM8HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM4HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM2HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM1HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVMF2HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVMF4HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM8SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM4SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM2SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM1SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVMF2SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM8SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM4SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM2SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM1SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVMF2SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM8DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM4DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM2DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM1DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM8DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM4DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM2DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (RVVM1DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V1QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V2QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V4QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V8QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V16QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V32QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V64QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V128QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V256QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V512QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V1024QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V2048QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V4096QI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V1HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V2HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V4HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V8HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V16HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V32HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V64HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V128HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V256HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V512HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V1024HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V2048HI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V1SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V2SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V4SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V8SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V16SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V32SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V64SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V128SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V256SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V512SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V1024SI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V1DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V2DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V4DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V8DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V16DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V32DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V64DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V128DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V256DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V512DI "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V1HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V2HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V4HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V8HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V16HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V32HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V64HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V128HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V256HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V512HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V1024HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V2048HF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V1SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V2SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V4SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V8SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V16SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V32SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V64SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V128SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V256SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V512SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V1024SF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V1DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V2DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V4DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V8DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V16DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V32DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V64DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V128DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V256DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") + (V512DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none") +]) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index acb812593a0..731057416cd 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -2223,70 +2223,70 @@ ;; DEST eew is greater than SOURCE eew. (define_insn "@pred_indexed_load_x2_greater_eew" - [(set (match_operand:VEEWEXT2 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VEEWEXT2 0 "register_operand" "") (if_then_else:VEEWEXT2 (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "") + (match_operand 5 "vector_length_operand" "") + (match_operand 6 "const_int_operand" "") + (match_operand 7 "const_int_operand" "") + (match_operand 8 "const_int_operand" "") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VEEWEXT2 - [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") + [(match_operand 3 "pmode_reg_or_0_operand" "") (mem:BLK (scratch)) - (match_operand: 4 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")] ORDER) - (match_operand:VEEWEXT2 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 4 "register_operand" "")] ORDER) + (match_operand:VEEWEXT2 2 "vector_merge_operand" "")))] "TARGET_VECTOR" "vlxei.v\t%0,(%z3),%4%p1" [(set_attr "type" "vldx") (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "group_overlap" "")]) (define_insn "@pred_indexed_load_x4_greater_eew" - [(set (match_operand:VEEWEXT4 0 "register_operand" "=vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VEEWEXT4 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") (if_then_else:VEEWEXT4 (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VEEWEXT4 - [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ") + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ") (mem:BLK (scratch)) - (match_operand: 4 "register_operand" " W43, W43, W86, W86, vr, vr")] ORDER) - (match_operand:VEEWEXT4 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] + (match_operand: 4 "register_operand" "W43,W43,W43,W43,W86,W86,W86,W86, vr, vr")] ORDER) + (match_operand:VEEWEXT4 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] "TARGET_VECTOR" "vlxei.v\t%0,(%z3),%4%p1" [(set_attr "type" "vldx") (set_attr "mode" "") - (set_attr "group_overlap" "W43,W43,W86,W86,none,none")]) + (set_attr "group_overlap" "W43,W43,W43,W43,W86,W86,W86,W86,none,none")]) (define_insn "@pred_indexed_load_x8_greater_eew" - [(set (match_operand:VEEWEXT8 0 "register_operand" "=vr, vr, ?&vr, ?&vr") + [(set (match_operand:VEEWEXT8 0 "register_operand" "=vd, vr, vd, vr, ?&vr, ?&vr") (if_then_else:VEEWEXT8 (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VEEWEXT8 - [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ") + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ") (mem:BLK (scratch)) - (match_operand: 4 "register_operand" " W87, W87, vr, vr")] ORDER) - (match_operand:VEEWEXT8 2 "vector_merge_operand" " vu, 0, vu, 0")))] + (match_operand: 4 "register_operand" "W87,W87,W87,W87, vr, vr")] ORDER) + (match_operand:VEEWEXT8 2 "vector_merge_operand" " vu, vu, 0, 0, vu, 0")))] "TARGET_VECTOR" "vlxei.v\t%0,(%z3),%4%p1" [(set_attr "type" "vldx") (set_attr "mode" "") - (set_attr "group_overlap" "W87,W87,none,none")]) + (set_attr "group_overlap" "W87,W87,W87,W87,none,none")]) ;; DEST eew is smaller than SOURCE eew. (define_insn "@pred_indexed_load_x2_smaller_eew" @@ -3686,66 +3686,66 @@ ;; Vector Double-Widening Sign-extend and Zero-extend. (define_insn "@pred__vf2" - [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "") + (match_operand 4 "vector_length_operand" "") + (match_operand 5 "const_int_operand" "") + (match_operand 6 "const_int_operand" "") + (match_operand 7 "const_int_operand" "") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_extend:VWEXTI - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 3 "register_operand" "")) + (match_operand:VWEXTI 2 "vector_merge_operand" "")))] "TARGET_VECTOR" "vext.vf2\t%0,%3%p1" [(set_attr "type" "vext") (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "group_overlap" "")]) ;; Vector Quad-Widening Sign-extend and Zero-extend. (define_insn "@pred__vf4" - [(set (match_operand:VQEXTI 0 "register_operand" "=vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VQEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") (if_then_else:VQEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_extend:VQEXTI - (match_operand: 3 "register_operand" " W43, W43, W86, W86, vr, vr")) - (match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] + (match_operand: 3 "register_operand" "W43,W43,W43,W43,W86,W86,W86,W86, vr, vr")) + (match_operand:VQEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] "TARGET_VECTOR" "vext.vf4\t%0,%3%p1" [(set_attr "type" "vext") (set_attr "mode" "") - (set_attr "group_overlap" "W43,W43,W86,W86,none,none")]) + (set_attr "group_overlap" "W43,W43,W43,W43,W86,W86,W86,W86,none,none")]) ;; Vector Oct-Widening Sign-extend and Zero-extend. (define_insn "@pred__vf8" - [(set (match_operand:VOEXTI 0 "register_operand" "=vr, vr, ?&vr, ?&vr") + [(set (match_operand:VOEXTI 0 "register_operand" "=vd, vr, vd, vr, ?&vr, ?&vr") (if_then_else:VOEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_extend:VOEXTI - (match_operand: 3 "register_operand" " W87, W87, vr, vr")) - (match_operand:VOEXTI 2 "vector_merge_operand" " vu, 0, vu, 0")))] + (match_operand: 3 "register_operand" "W87,W87,W87,W87, vr, vr")) + (match_operand:VOEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, 0")))] "TARGET_VECTOR" "vext.vf8\t%0,%3%p1" [(set_attr "type" "vext") (set_attr "mode" "") - (set_attr "group_overlap" "W87,W87,none,none")]) + (set_attr "group_overlap" "W87,W87,W87,W87,none,none")]) ;; Vector Widening Add/Subtract/Multiply. (define_insn "@pred_dual_widen_" @@ -3771,28 +3771,28 @@ (set_attr "mode" "")]) (define_insn "@pred_dual_widen__scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "") + (match_operand 5 "vector_length_operand" "") + (match_operand 6 "const_int_operand" "") + (match_operand 7 "const_int_operand" "") + (match_operand 8 "const_int_operand" "") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_widen_binop:VWEXTI (any_extend:VWEXTI - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) + (match_operand: 3 "register_operand" "")) (any_extend:VWEXTI (vec_duplicate: - (match_operand: 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")))) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 4 "reg_or_0_operand" "")))) + (match_operand:VWEXTI 2 "vector_merge_operand" "")))] "TARGET_VECTOR" "vw.vx\t%0,%3,%z4%p1" [(set_attr "type" "vi") (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "group_overlap" "")]) (define_insn "@pred_single_widen_sub" [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr") @@ -3881,47 +3881,47 @@ (set_attr "mode" "")]) (define_insn "@pred_widen_mulsu_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "") + (match_operand 5 "vector_length_operand" "") + (match_operand 6 "const_int_operand" "") + (match_operand 7 "const_int_operand" "") + (match_operand 8 "const_int_operand" "") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (mult:VWEXTI (sign_extend:VWEXTI - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) + (match_operand: 3 "register_operand" "")) (zero_extend:VWEXTI (vec_duplicate: - (match_operand: 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")))) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 4 "reg_or_0_operand" "")))) + (match_operand:VWEXTI 2 "vector_merge_operand" "")))] "TARGET_VECTOR" "vwmulsu.vx\t%0,%3,%z4%p1" [(set_attr "type" "viwmul") (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "group_overlap" "")]) ;; vwcvt.x.x.v (define_insn "@pred_" - [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "") + (match_operand 4 "vector_length_operand" "") + (match_operand 5 "const_int_operand" "") + (match_operand 6 "const_int_operand" "") + (match_operand 7 "const_int_operand" "") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (any_extend:VWEXTI - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) + (match_operand: 3 "register_operand" "")) (vec_duplicate:VWEXTI (reg: X0_REGNUM))) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand:VWEXTI 2 "vector_merge_operand" "")))] "TARGET_VECTOR" "vwcvt.x.x.v\t%0,%3%p1" [(set_attr "type" "viwalu") @@ -3930,7 +3930,7 @@ (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) (set (attr "avl_type_idx") (const_int 7)) - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "group_overlap" "")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated integer Narrowing operations @@ -7042,32 +7042,32 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_dual_widen__scalar" - [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "") (if_then_else:VWEXTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "") + (match_operand 5 "vector_length_operand" "") + (match_operand 6 "const_int_operand" "") + (match_operand 7 "const_int_operand" "") + (match_operand 8 "const_int_operand" "") + (match_operand 9 "const_int_operand" "") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_widen_binop:VWEXTF (float_extend:VWEXTF - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) + (match_operand: 3 "register_operand" "")) (float_extend:VWEXTF (vec_duplicate: - (match_operand: 4 "register_operand" " f, f, f, f, f, f, f, f")))) - (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 4 "register_operand" "")))) + (match_operand:VWEXTF 2 "vector_merge_operand" "")))] "TARGET_VECTOR" "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vf") (set_attr "mode" "") (set (attr "frm_mode") (symbol_ref "riscv_vector::get_frm_mode (operands[9])")) - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "group_overlap" "")]) (define_insn "@pred_single_widen_add" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") @@ -7630,88 +7630,88 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_widen_fcvt_x_f" - [(set (match_operand:VWCONVERTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWCONVERTI 0 "register_operand" "") (if_then_else:VWCONVERTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "") + (match_operand 4 "vector_length_operand" "") + (match_operand 5 "const_int_operand" "") + (match_operand 6 "const_int_operand" "") + (match_operand 7 "const_int_operand" "") + (match_operand 8 "const_int_operand" "") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (unspec:VWCONVERTI - [(match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")] VFCVTS) - (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + [(match_operand: 3 "register_operand" "")] VFCVTS) + (match_operand:VWCONVERTI 2 "vector_merge_operand" "")))] "TARGET_VECTOR" "vfwcvt.x.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftoi") (set_attr "mode" "") (set (attr "frm_mode") (symbol_ref "riscv_vector::get_frm_mode (operands[8])")) - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "group_overlap" "")]) (define_insn "@pred_widen_" - [(set (match_operand:VWCONVERTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWCONVERTI 0 "register_operand" "") (if_then_else:VWCONVERTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "") + (match_operand 4 "vector_length_operand" "") + (match_operand 5 "const_int_operand" "") + (match_operand 6 "const_int_operand" "") + (match_operand 7 "const_int_operand" "") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix:VWCONVERTI - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) - (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 3 "register_operand" "")) + (match_operand:VWCONVERTI 2 "vector_merge_operand" "")))] "TARGET_VECTOR" "vfwcvt.rtz.x.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftoi") (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "group_overlap" "")]) (define_insn "@pred_widen_" - [(set (match_operand:V_VLSF 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:V_VLSF 0 "register_operand" "") (if_then_else:V_VLSF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "") + (match_operand 4 "vector_length_operand" "") + (match_operand 5 "const_int_operand" "") + (match_operand 6 "const_int_operand" "") + (match_operand 7 "const_int_operand" "") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_float:V_VLSF - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) - (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 3 "register_operand" "")) + (match_operand:V_VLSF 2 "vector_merge_operand" "")))] "TARGET_VECTOR" "vfwcvt.f.x.v\t%0,%3%p1" [(set_attr "type" "vfwcvtitof") (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "group_overlap" "")]) (define_insn "@pred_extend" - [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "") (if_then_else:VWEXTF_ZVFHMIN (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "") + (match_operand 4 "vector_length_operand" "") + (match_operand 5 "const_int_operand" "") + (match_operand 6 "const_int_operand" "") + (match_operand 7 "const_int_operand" "") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (float_extend:VWEXTF_ZVFHMIN - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) - (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 3 "register_operand" "")) + (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" "")))] "TARGET_VECTOR" "vfwcvt.f.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftof") (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "group_overlap" "")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point narrow conversions diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c new file mode 100644 index 00000000000..80ea65b85ff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c @@ -0,0 +1,101 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +size_t __attribute__ ((noinline)) +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, + size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9, + size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14, + size_t sum15) +{ + return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9 + + sum10 + sum11 + sum12 + sum13 + sum14 + sum15; +} + +size_t +foo (char const *buf, size_t len) +{ + size_t sum = 0; + size_t vl = __riscv_vsetvlmax_e8m8 (); + size_t step = vl * 4; + const char *it = buf, *end = buf + len; + for (; it + step <= end;) + { + vuint8m1_t v0 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v1 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v2 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v3 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v4 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v5 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v6 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v7 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v8 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v9 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v10 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v11 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v12 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v13 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v14 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + vuint8m1_t v15 = __riscv_vle8_v_u8m1 ((void *) it, vl); + it += vl; + + asm volatile("nop" ::: "memory"); + vint16m2_t vw0 = __riscv_vluxei8_v_i16m2 ((void *) it, v0, vl); + vint16m2_t vw1 = __riscv_vluxei8_v_i16m2 ((void *) it, v1, vl); + vint16m2_t vw2 = __riscv_vluxei8_v_i16m2 ((void *) it, v2, vl); + vint16m2_t vw3 = __riscv_vluxei8_v_i16m2 ((void *) it, v3, vl); + vint16m2_t vw4 = __riscv_vluxei8_v_i16m2 ((void *) it, v4, vl); + vint16m2_t vw5 = __riscv_vluxei8_v_i16m2 ((void *) it, v5, vl); + vint16m2_t vw6 = __riscv_vluxei8_v_i16m2 ((void *) it, v6, vl); + vint16m2_t vw7 = __riscv_vluxei8_v_i16m2 ((void *) it, v7, vl); + vint16m2_t vw8 = __riscv_vluxei8_v_i16m2 ((void *) it, v8, vl); + vint16m2_t vw9 = __riscv_vluxei8_v_i16m2 ((void *) it, v9, vl); + vint16m2_t vw10 = __riscv_vluxei8_v_i16m2 ((void *) it, v10, vl); + vint16m2_t vw11 = __riscv_vluxei8_v_i16m2 ((void *) it, v11, vl); + vint16m2_t vw12 = __riscv_vluxei8_v_i16m2 ((void *) it, v12, vl); + vint16m2_t vw13 = __riscv_vluxei8_v_i16m2 ((void *) it, v13, vl); + vint16m2_t vw14 = __riscv_vluxei8_v_i16m2 ((void *) it, v14, vl); + vbool8_t mask = *(vbool8_t*)it; + vint16m2_t vw15 = __riscv_vluxei8_v_i16m2_m (mask, (void *) it, v15, vl); + + asm volatile("nop" ::: "memory"); + size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0); + size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1); + size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2); + size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3); + size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4); + size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5); + size_t sum6 = __riscv_vmv_x_s_i16m2_i16 (vw6); + size_t sum7 = __riscv_vmv_x_s_i16m2_i16 (vw7); + size_t sum8 = __riscv_vmv_x_s_i16m2_i16 (vw8); + size_t sum9 = __riscv_vmv_x_s_i16m2_i16 (vw9); + size_t sum10 = __riscv_vmv_x_s_i16m2_i16 (vw10); + size_t sum11 = __riscv_vmv_x_s_i16m2_i16 (vw11); + size_t sum12 = __riscv_vmv_x_s_i16m2_i16 (vw12); + size_t sum13 = __riscv_vmv_x_s_i16m2_i16 (vw13); + size_t sum14 = __riscv_vmv_x_s_i16m2_i16 (vw14); + size_t sum15 = __riscv_vmv_x_s_i16m2_i16 (vw15); + + sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8, + sum9, sum10, sum11, sum12, sum13, sum14, sum15); + } + return sum; +} + +/* { dg-final { scan-assembler-not {vluxei8\.v\tv0,\s*\([a-x0-9]+\),\s*v[0-9]+,\s*v0.t} } } */