From patchwork Fri Dec 1 07:52:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 81077 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BEFD4385AC37 for ; Fri, 1 Dec 2023 07:53:03 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by sourceware.org (Postfix) with ESMTPS id C78903858C30 for ; Fri, 1 Dec 2023 07:52:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C78903858C30 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C78903858C30 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701417164; cv=none; b=bIzC0zHOJjZy0vF3J0X/s1t4I+dBLKoZySrR5vDNGRFxuwhll+0Ekg/f/b2ftitm2TJI9kWiTPa55Bp4gvAUMPtkOlG33ttJXPJj781wvrWm/FlXaXHz9XgMxODJInshvvnTKXNU1OUxmzRRlhcURKQB9qHqCMlLr1zRALZYkDQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701417164; c=relaxed/simple; bh=yJiJNyW7aF7/PLHXnZ3z2ynoY8wV/Te+UqUTPfjOLg8=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=k6N/XmGkUIsgxAODCVI14nVuAiqKIxaOWCCxBw3jlPn63gBP1JKyCpHe8yKyHVKBZDYvQ2w6Bmr7cFgJhVx1gR2I2DF6vh0jBEc91OFTHB+ZFgw888AwKawBw1Covq853+wvB9ztQBIFvqEwJV3Z7gKNqlaE9SbxFNld9iK5sT0= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701417162; x=1732953162; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yJiJNyW7aF7/PLHXnZ3z2ynoY8wV/Te+UqUTPfjOLg8=; b=HiW7H18bkpxh42L+44YYMCOGIKMr/lA4VhWQroCcctJ0PV4i3DyslWk7 ODDQ8ZM3wGPboHqhN0cEcig7hL256Y6ZRApOReY2Z6FvbDClo+/VwieX/ 8RaJLJ8x4qUVYomB4kKBya3Z2B41QuJGERdGMfGB/LbX+HWNAXY/1X3YW DZnSxVLWLytsKuDk1iZTAwMWRvvyWzY3e5MolfjI9MD+CXVJb5YYD2faR 5L0qymqg0YHsCw2ZXEgrAx6F7IHhxgA83PO9TVAPiCZjD3DHOgkUGKYbO tI5ZzDxYlSckB7nXoGWTJzr0d5nNjRvfclYF7bjFeJg3kYY2tmRA3isNV g==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="6699965" X-IronPort-AV: E=Sophos;i="6.04,241,1695711600"; d="scan'208";a="6699965" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 23:52:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="763052613" X-IronPort-AV: E=Sophos;i="6.04,241,1695711600"; d="scan'208";a="763052613" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga007.jf.intel.com with ESMTP; 30 Nov 2023 23:52:37 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 8BCB61005686; Fri, 1 Dec 2023 15:52:36 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v2] RISC-V: Bugfix for legitimize move when get vec mode in zve32f Date: Fri, 1 Dec 2023 15:52:35 +0800 Message-Id: <20231201075235.2345384-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130072105.2462309-1-pan2.li@intel.com> References: <20231130072105.2462309-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org From: Pan Li If we want to extract 64bit value but ELEN < 64, we use RVV vector mode with EEW = 32 to extract the highpart and lowpart. However, this approach doesn't honor DFmode when movdf pattern when ZVE32f and of course results in ICE when zve32f. This patch would like to reuse the approach with some additional handing, consider lowpart bits is meaningless for FP mode, we need one int reg as bridge here. For example: rtx tmp = gen_rtx_reg (DImode) reg:DI = reg:DF (fmv.d.x) // Move DF reg to DI ... perform the extract for high and low parts ... reg:DF = reg:DI (fmv.x.d) // Move DI reg back to DF after all done PR target/112743 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_move): Take the exist (U *mode) and handle DFmode like DImode when EEW is 32bits like ZVE32F. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112743-2.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/riscv.cc | 67 +++++++++++++------ .../gcc.target/riscv/rvv/base/pr112743-2.c | 52 ++++++++++++++ 2 files changed, 99 insertions(+), 20 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-2.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index a4fc858fb50..996347ee3fd 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2605,41 +2605,68 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) unsigned int nunits = vmode_size > mode_size ? vmode_size / mode_size : 1; scalar_mode smode = as_a (mode); unsigned int index = SUBREG_BYTE (src).to_constant () / mode_size; - unsigned int num = smode == DImode && !TARGET_VECTOR_ELEN_64 ? 2 : 1; + unsigned int num = (smode == DImode || smode == DFmode) + && !TARGET_VECTOR_ELEN_64 ? 2 : 1; + bool need_int_reg_p = false; if (num == 2) { /* If we want to extract 64bit value but ELEN < 64, we use RVV vector mode with EEW = 32 to extract the highpart and lowpart. */ + need_int_reg_p = smode == DFmode; smode = SImode; nunits = nunits * 2; } - vmode = riscv_vector::get_vector_mode (smode, nunits).require (); - rtx v = gen_lowpart (vmode, SUBREG_REG (src)); - for (unsigned int i = 0; i < num; i++) + opt_machine_mode opt_mode = riscv_vector::get_vector_mode (smode, nunits); + + if (opt_mode.exists (&vmode)) { - rtx result; - if (num == 1) - result = dest; - else if (i == 0) - result = gen_lowpart (smode, dest); - else - result = gen_reg_rtx (smode); - riscv_vector::emit_vec_extract (result, v, index + i); + rtx v = gen_lowpart (vmode, SUBREG_REG (src)); + rtx int_reg = dest; - if (i == 1) + if (need_int_reg_p) { - rtx tmp - = expand_binop (Pmode, ashl_optab, gen_lowpart (Pmode, result), - gen_int_mode (32, Pmode), NULL_RTX, 0, - OPTAB_DIRECT); - rtx tmp2 = expand_binop (Pmode, ior_optab, tmp, dest, NULL_RTX, 0, - OPTAB_DIRECT); - emit_move_insn (dest, tmp2); + int_reg = gen_reg_rtx (DImode); + emit_insn ( + gen_movdi (int_reg, gen_lowpart (GET_MODE (int_reg), dest))); + } + + for (unsigned int i = 0; i < num; i++) + { + rtx result; + if (num == 1) + result = int_reg; + else if (i == 0) + result = gen_lowpart (smode, int_reg); + else + result = gen_reg_rtx (smode); + + riscv_vector::emit_vec_extract (result, v, index + i); + + if (i == 1) + { + rtx tmp = expand_binop (Pmode, ashl_optab, + gen_lowpart (Pmode, result), + gen_int_mode (32, Pmode), NULL_RTX, 0, + OPTAB_DIRECT); + rtx tmp2 = expand_binop (Pmode, ior_optab, tmp, int_reg, + NULL_RTX, 0, + OPTAB_DIRECT); + emit_move_insn (int_reg, tmp2); + } } + + if (need_int_reg_p) + emit_insn ( + gen_movdf (dest, gen_lowpart (GET_MODE (dest), int_reg))); + else + emit_move_insn (dest, int_reg); } + else + gcc_unreachable (); + return true; } /* Expand diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-2.c new file mode 100644 index 00000000000..fdb35fd70f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-2.c @@ -0,0 +1,52 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvfh_zfh -mabi=lp64 -O2" } */ + +#include + +union double_union +{ + double d; + __uint32_t i[2]; +}; + +#define word0(x) (x.i[1]) +#define word1(x) (x.i[0]) + +#define P 53 +#define Exp_shift 20 +#define Exp_msk1 ((__uint32_t)0x100000L) +#define Exp_mask ((__uint32_t)0x7ff00000L) + +double ulp (double _x) +{ + union double_union x, a; + register int L; + + x.d = _x; + L = (word0 (x) & Exp_mask) - (P - 1) * Exp_msk1; + + if (L > 0) + { + L |= Exp_msk1 >> 4; + word0 (a) = L; + word1 (a) = 0; + } + else + { + L = -L >> Exp_shift; + if (L < Exp_shift) + { + word0 (a) = 0x80000 >> L; + word1 (a) = 0; + } + else + { + word0 (a) = 0; + L -= Exp_shift; + word1 (a) = L >= 31 ? 1 : 1 << (31 - L); + } + } + + return a.d; +}