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Fri, 1 Dec 2023 02:41:44 +0000 (GMT) Message-ID: <770bdc23-24cc-4699-af13-38eab3f32b80@linux.ibm.com> Date: Fri, 1 Dec 2023 10:41:43 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: gcc-patches Cc: Segher Boessenkool , David , "Kewen.Lin" , Peter Bergner From: HAO CHEN GUI Subject: [patch-1, rs6000] enable fctiw on old archs [PR112707] X-TM-AS-GCONF: 00 X-Proofpoint-GUID: V298KrpaHrukCiS01LsUhnHBjX6Ev99L X-Proofpoint-ORIG-GUID: MdPFHIswo-shIKvJvn0khpYuKHN6JAE2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-30_25,2023-11-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 impostorscore=0 adultscore=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 mlxlogscore=913 mlxscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2312010015 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Hi, SImode in float register is supported on P7 above. It causes "fctiw" can be generated on old 32-bit processors as the output operand of fctiw insn is a SImode in float/double register. This patch fixes the problem by adding an expand and an insn pattern for fctiw. The output of new pattern is SFmode. When the target doesn't support SImode in float register, it calls the new pattern and convert the SFmode to SImode via stack. Bootstrapped and tested on x86 and powerpc64-linux BE and LE with no regressions. Is this OK for trunk? Thanks Gui Haochen ChangeLog rs6000: enable fctiw on old archs The powerpc 32-bit processors (e.g. 5470) supports "fctiw" instruction, but the instruction can't be generated on such platforms as the insn is guard by TARGET_POPCNTD. The root cause is SImode in float register is supported from Power7. Actually implementation of "fctiw" only needs stfiwx which is supported by the old 320-bit processors. This patch enables "fctiw" expand for these processors. gcc/ PR target/112707 * config/rs6000/rs6000.md (UNSPEC_STFIWX_SF, UNSPEC_FCTIW_SF): New. (expand lrintsi2): New. (insn lrintsi2): Rename to... (lrintsi_internal): ...this, and remove guard TARGET_POPCNTD. (lrintsi_internal2): New. (stfiwx_sf): New. gcc/testsuite/ PR target/112707 * gcc.target/powerpc/pr112707-1.c: New. patch.diff diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d4337ce42a9..1b207522ad5 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -90,6 +90,7 @@ (define_c_enum "unspec" UNSPEC_TLSTLS_PCREL UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero UNSPEC_STFIWX + UNSPEC_STFIWX_SF UNSPEC_POPCNTB UNSPEC_FRES UNSPEC_SP_SET @@ -111,6 +112,7 @@ (define_c_enum "unspec" UNSPEC_PARITY UNSPEC_CMPB UNSPEC_FCTIW + UNSPEC_FCTIW_SF UNSPEC_FCTID UNSPEC_LFIWAX UNSPEC_LFIWZX @@ -6722,11 +6724,39 @@ (define_insn "lrintdi2" "fctid %0,%1" [(set_attr "type" "fp")]) -(define_insn "lrintsi2" +(define_expand "lrintsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=d") (unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "")] UNSPEC_FCTIW))] - "TARGET_HARD_FLOAT && TARGET_POPCNTD" + "TARGET_HARD_FLOAT && TARGET_STFIWX" +{ + /* For those old archs in which SImode can't be hold in float registers, + call lrintsi_internal2 to put the result in SFmode then + convert it via stack. */ + if (!TARGET_POPCNTD) + { + rtx tmp = gen_reg_rtx (SFmode); + emit_insn (gen_lrintsi_internal2 (tmp, operands[1])); + rtx stack = rs6000_allocate_stack_temp (SImode, false, true); + emit_insn (gen_stfiwx_sf (stack, tmp)); + emit_move_insn (operands[0], stack); + DONE; + } +}) + +(define_insn "lrintsi_internal" + [(set (match_operand:SI 0 "gpc_reg_operand" "=d") + (unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "")] + UNSPEC_FCTIW))] + "TARGET_HARD_FLOAT" + "fctiw %0,%1" + [(set_attr "type" "fp")]) + +(define_insn "lrintsi_internal2" + [(set (match_operand:SF 0 "gpc_reg_operand" "=d") + (unspec:SF [(match_operand:SFDF 1 "gpc_reg_operand" "")] + UNSPEC_FCTIW_SF))] + "TARGET_HARD_FLOAT" "fctiw %0,%1" [(set_attr "type" "fp")]) @@ -6801,6 +6831,14 @@ (define_insn "stfiwx" [(set_attr "type" "fpstore") (set_attr "isa" "*,p8v")]) +(define_insn "stfiwx_sf" + [(set (match_operand:SI 0 "memory_operand" "=Z") + (unspec:SI [(match_operand:SF 1 "gpc_reg_operand" "d")] + UNSPEC_STFIWX_SF))] + "TARGET_STFIWX" + "stfiwx %1,%y0" + [(set_attr "type" "fpstore")]) + ;; If we don't have a direct conversion to single precision, don't enable this ;; conversion for 32-bit without fast math, because we don't have the insn to ;; generate the fixup swizzle to avoid double rounding problems. diff --git a/gcc/testsuite/gcc.target/powerpc/pr112707-1.c b/gcc/testsuite/gcc.target/powerpc/pr112707-1.c new file mode 100644 index 00000000000..32f708c5402 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr112707-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* && be } } } */ +/* { dg-options "-O2 -mdejagnu-cpu=7450 -m32 -fno-math-errno" } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-final { scan-assembler-times {\mfctiw\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstfiwx\M} 2 } } */ + +int test1 (double a) +{ + return __builtin_irint (a); +} + +int test2 (float a) +{ + return __builtin_irint (a); +}