From patchwork Wed Nov 29 23:14:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juzhe-Zhong X-Patchwork-Id: 80993 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 88EB7385C424 for ; Wed, 29 Nov 2023 23:15:15 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id F28833858D39 for ; Wed, 29 Nov 2023 23:14:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F28833858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F28833858D39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.254.200.92 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701299697; cv=none; b=o8/d4svsH5lYxqem5i8EA3Wh9jIcRqELun56JioluaF15/n3BDFxmnWQyxB6Y+9fq+FUQL0z2+P+SW26lTF9xCMn/wFr21K72sbdDYxTWe5g+ZnYg/6vtArnky+83fDXrwjBDiQLFdn/yti4JuxGJwV3EdbESAnjrjnHoUCGORQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701299697; c=relaxed/simple; bh=xTdrjLc6eBTCjATY1JoJJpQ1tlpdbJ2vTG5gdfg8iUY=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=kPZ60WAAC314JzP1OQIQUOSllIULfGOoeztkk2VUjHqDYRZkCWikVpxr9ZnicGO8yLa6wVZICjmWTDMfGdRCm4TQ/Ej0kK0i9YFYtlIzY3JX4G5ZtCaQzE+Lh50oxGEJwAFkiXf8/lTcaFMCh2aRT2PI2SRwCR64FM3k4xuv9Rs= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp65t1701299688t4hmjxj4 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 30 Nov 2023 07:14:47 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: RrZlkntZBflGvVK4G3vSvzdXgn0Q75jTCAFdrmpuHXerX7ehI3VEf/J+MBeHa lrlYnIpJ0ULoLl25RfaeoQOodnx/nV2cNl71T3ZhlvYiaE08tk/3K39nObxBvUI5sWmqn05 L75Vcv4nNcyXdtBj1I+YllO33Q9Nc/JaBzfmv91eoPZArxZEtDovshougARjHq8KYPKHP36 DK0C2HU0v8Vy1W4+nF4sb/Pe+JHVJWiWbVu60nN6IYwzeMdOjEIc6wlx6ilwe9iJreZpP9I Ky1oKkEuaCymUdZpBWKDDgs32eoXAZLwBok9z2K37jgxWkmZPUR/xbLnBZIP3wE/PxAlUU+ aYqTNZ8zRyruJUiTh6nC7W9aSPMCiY9zxLI3dem X-QQ-GoodBg: 2 X-BIZMAIL-ID: 15041413198488321647 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed] RISC-V: Rename vconstraint into group_overlap Date: Thu, 30 Nov 2023 07:14:46 +0800 Message-Id: <20231129231446.204221-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Fix for Robin's suggestion. gcc/ChangeLog: * config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Fix constraint. * config/riscv/riscv.md (no,W21,W42,W84,W41,W81,W82): Rename vconstraint into group_overlap. (no,yes): Ditto. (none,W21,W42,W84,W43,W86,W87): Ditto. * config/riscv/vector.md: Ditto. --- gcc/config/riscv/constraints.md | 12 ++++++------ gcc/config/riscv/riscv.md | 21 ++++++++++++--------- gcc/config/riscv/vector.md | 4 ++-- 3 files changed, 20 insertions(+), 17 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 19bb36616bf..9836fd34460 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -183,14 +183,14 @@ (define_register_constraint "W84" "TARGET_VECTOR ? V_REGS : NO_REGS" "A vector register has register number % 8 == 4." "regno % 8 == 4") -(define_register_constraint "W41" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 4 == 1." "regno % 4 == 1") +(define_register_constraint "W43" "TARGET_VECTOR ? V_REGS : NO_REGS" + "A vector register has register number % 4 == 3." "regno % 4 == 3") -(define_register_constraint "W81" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 8 == 1." "regno % 8 == 1") +(define_register_constraint "W86" "TARGET_VECTOR ? V_REGS : NO_REGS" + "A vector register has register number % 8 == 6." "regno % 8 == 6") -(define_register_constraint "W82" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 8 == 2." "regno % 8 == 2") +(define_register_constraint "W87" "TARGET_VECTOR ? V_REGS : NO_REGS" + "A vector register has register number % 8 == 7." "regno % 8 == 7") ;; This constraint is used to match instruction "csrr %0, vlenb" which is generated in "mov". ;; VLENB is a run-time constant which represent the vector register length in bytes. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 6bf2dfdf9b4..4c6f63677df 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -501,22 +501,25 @@ ] (const_string "no"))) -(define_attr "vconstraint" "no,W21,W42,W84,W41,W81,W82" - (const_string "no")) - -(define_attr "vconstraint_enabled" "no,yes" - (cond [(eq_attr "vconstraint" "no") +;; Widening instructions have group-overlap constraints. Those are only +;; valid for certain register-group sizes. This attribute marks the +;; alternatives not matching the required register-group size as disabled. +(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87" + (const_string "none")) + +(define_attr "group_overlap_valid" "no,yes" + (cond [(eq_attr "group_overlap" "none") (const_string "yes") - (and (eq_attr "vconstraint" "W21") + (and (eq_attr "group_overlap" "W21") (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 2")) (const_string "no") - (and (eq_attr "vconstraint" "W42,W41") + (and (eq_attr "group_overlap" "W42,W43") (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 4")) (const_string "no") - (and (eq_attr "vconstraint" "W84,W81,W82") + (and (eq_attr "group_overlap" "W84,W86,W87") (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 8")) (const_string "no") ] @@ -531,7 +534,7 @@ (eq_attr "fp_vector_disabled" "yes") (const_string "no") - (eq_attr "vconstraint_enabled" "no") + (eq_attr "group_overlap_valid" "no") (const_string "no") ] (const_string "yes"))) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 5667f8bd2b6..74716c73e98 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -3700,7 +3700,7 @@ "vext.vf2\t%0,%3%p1" [(set_attr "type" "vext") (set_attr "mode" "") - (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) ;; Vector Quad-Widening Sign-extend and Zero-extend. (define_insn "@pred__vf4" @@ -3923,7 +3923,7 @@ (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) (set (attr "avl_type_idx") (const_int 7)) - (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")]) + (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated integer Narrowing operations