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Wed, 22 Nov 2023 10:20:28 +0000 Date: Wed, 22 Nov 2023 10:20:26 +0000 From: Tamar Christina To: gcc-patches@gcc.gnu.org Cc: nd@arm.com, Richard.Earnshaw@arm.com, Marcus.Shawcroft@arm.com, Kyrylo.Tkachov@arm.com, richard.sandiford@arm.com Subject: [PATCH]AArch64: fix aarch64_usubw pattern Message-ID: Content-Disposition: inline X-ClientProxiedBy: LO4P123CA0425.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:18b::16) To VI1PR08MB5325.eurprd08.prod.outlook.com (2603:10a6:803:13e::17) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: VI1PR08MB5325:EE_|DU0PR08MB8906:EE_|DU6PEPF0000B622:EE_|AM9PR08MB6673:EE_ X-MS-Office365-Filtering-Correlation-Id: f4accbcf-d5a2-4da0-5f60-08dbeb44b0cb x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: o8xt2Jxw08TE+mHuvTMNLwP/Y7m2Z57P725Ete2Bo1gCn32ScF+x2MHXB1i5xX31Pm3WLT56J4l3gvbrG8Z3smPzHXF5JJsf+aCAcleABOSPLtpRrT6NhxfpKUi16g24ZmAcA1KrH6dap93VfKVGOLFUrjSlpd+i4fJmW02MfngQosbqeU3rAr6c/b/aFtF4wXjoqYQcQYUDtSzJtyogGvf92QGDoQDJg8yDiQgT9Zhc+8d9c3ddjPQ9rTlbyjUlBUAgjCkkEBw/OxOfhLlqfUP/PeEjhm+48GRW7ZyutOtMZzSEdh9oIVi2EPHf78GMhWZefkLPoLNhA1/C7NAtPilINCTMQdzglGmXyK8ckYb6ZslF6n0Mo1uQU/Za2RZdNXNWpNk+8bGt7McMYSgnZMUm4lITyuBM/lCBsuMyPOPjI9xzTgELyiBnzVyshmMa0KpfOLaty9cKpgpCIzA/D+dBbnLRbrtpblNV83wtjoYMufmXyC+ksScX6zv0ec+h5Fnjzz41okhmzriRv+I09HIOP9EhNLP9AywDoGZt56zz7LWP19PHaASMSkb3ME0LdD6GyG5FjsNIzE8GEi9uJTlr78dJBZvFtHz0JM2jMcl8kRgsUNLeqsFuHSZ6Gk7qBLhGQJZ0eo7m3/pFgLDA1mCHU1insV/8dCNdyCEEYVE= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF0000B622.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6673 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Hi All, It looks like during my pre-commit testrun I forgot to apply this patch to the patch stack. It had a typo in the element size. It also looks like since the hi/lo operations take different element counts for the assembler syntax that I can't have a unified pattern. This splits it into two each :( Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Sorry for the breakage, Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_uaddw__zip, aarch64_usubw__zip): Split into... (aarch64_uaddw_lo_zip, aarch64_uaddw_hi_zip, "aarch64_usubw_lo_zip, "aarch64_usubw_hi_zip): ... This. gcc/testsuite/ChangeLog: * gcc.target/aarch64/uxtl-combine-4.c: Fix typo. * gcc.target/aarch64/uxtl-combine-5.c: Likewise. * gcc.target/aarch64/uxtl-combine-6.c: Likewise. --- inline copy of patch -- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 75ee659871080ed28b9887990b7431682c283502..80e338bb8952140dd8be178cc8aed0c47b81c775 100644 --- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 75ee659871080ed28b9887990b7431682c283502..80e338bb8952140dd8be178cc8aed0c47b81c775 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4810,7 +4810,7 @@ (define_insn "aarch64_subw2_internal" [(set_attr "type" "neon_sub_widen")] ) -(define_insn "aarch64_usubw__zip" +(define_insn "aarch64_usubw_lo_zip" [(set (match_operand: 0 "register_operand" "=w") (minus: (match_operand: 1 "register_operand" "w") @@ -4818,23 +4818,51 @@ (define_insn "aarch64_usubw__zip" (unspec: [ (match_operand:VQW 2 "register_operand" "w") (match_operand:VQW 3 "aarch64_simd_imm_zero") - ] PERM_EXTEND) 0)))] + ] UNSPEC_ZIP1) 0)))] "TARGET_SIMD" - "usubw\\t%0., %1., %2." + "usubw\\t%0., %1., %2." [(set_attr "type" "neon_sub_widen")] ) -(define_insn "aarch64_uaddw__zip" +(define_insn "aarch64_uaddw_lo_zip" [(set (match_operand: 0 "register_operand" "=w") (plus: (subreg: (unspec: [ (match_operand:VQW 2 "register_operand" "w") (match_operand:VQW 3 "aarch64_simd_imm_zero") - ] PERM_EXTEND) 0) + ] UNSPEC_ZIP1) 0) (match_operand: 1 "register_operand" "w")))] "TARGET_SIMD" - "uaddw\\t%0., %1., %2." + "uaddw\\t%0., %1., %2." + [(set_attr "type" "neon_add_widen")] +) + +(define_insn "aarch64_usubw_hi_zip" + [(set (match_operand: 0 "register_operand" "=w") + (minus: + (match_operand: 1 "register_operand" "w") + (subreg: + (unspec: [ + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "aarch64_simd_imm_zero") + ] UNSPEC_ZIP2) 0)))] + "TARGET_SIMD" + "usubw2\\t%0., %1., %2." + [(set_attr "type" "neon_sub_widen")] +) + +(define_insn "aarch64_uaddw_hi_zip" + [(set (match_operand: 0 "register_operand" "=w") + (plus: + (subreg: + (unspec: [ + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "aarch64_simd_imm_zero") + ] UNSPEC_ZIP2) 0) + (match_operand: 1 "register_operand" "w")))] + "TARGET_SIMD" + "uaddw2\\t%0., %1., %2." [(set_attr "type" "neon_add_widen")] ) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 2354315d7d249ccee46625d13b32678f1da1f087..a920de99ffca378ce518f378a35cbe2766877ee8 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -2645,9 +2645,6 @@ (define_int_iterator PERMUTEQ [UNSPEC_ZIP1Q UNSPEC_ZIP2Q (define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 UNSPEC_UZP1 UNSPEC_UZP2]) -;; Permutes for zero extends -(define_int_iterator PERM_EXTEND [UNSPEC_ZIP1 UNSPEC_ZIP2]) - (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16]) (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM @@ -3470,10 +3467,7 @@ (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32") (UNSPEC_REV16 "16")]) (define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi") - (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo") - (UNSPEC_ZIP2 "hi") (UNSPEC_ZIP1 "lo")]) - -(define_int_attr perm_index [(UNSPEC_ZIP2 "2") (UNSPEC_ZIP1 "")]) + (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")]) ;; Return true if the associated optab refers to the high-numbered lanes, ;; false if it refers to the low-numbered lanes. The convention is for diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-4.c b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-4.c index e1a9c4f5661a36ec7b2c5dc6f0fd85c42fcaac39..67944f70ecceff7ed833de86b76606547f3db76c 100755 --- a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-4.c +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-4.c @@ -16,5 +16,5 @@ void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) /* { dg-final { scan-assembler-not {\tzip1\t} } } */ /* { dg-final { scan-assembler-not {\tzip2\t} } } */ /* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */ -/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */ +/* { dg-final { scan-assembler-times {\tsxtl2\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-5.c b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-5.c index 92b09ba4abba80f240ac175be2ef880968534975..e691c4f0b595d1a60b445415970c5a67d7dd0419 100755 --- a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-5.c +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-5.c @@ -16,5 +16,5 @@ void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) /* { dg-final { scan-assembler-not {\tzip1\t} } } */ /* { dg-final { scan-assembler-not {\tzip2\t} } } */ /* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */ -/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */ +/* { dg-final { scan-assembler-times {\tsxtl2\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-6.c b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-6.c index 5c6e635f29d1e52f51f5b75a477f7d8744f32ca3..9383f7ebf9355ff471c48549fc0e4c07706601f1 100755 --- a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-6.c +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-6.c @@ -16,5 +16,5 @@ void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) /* { dg-final { scan-assembler-not {\tzip1\t} } } */ /* { dg-final { scan-assembler-not {\tzip2\t} } } */ /* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */ -/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */ +/* { dg-final { scan-assembler-times {\tsxtl2\t} 1 } } */ --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4810,7 +4810,7 @@ (define_insn "aarch64_subw2_internal" [(set_attr "type" "neon_sub_widen")] ) -(define_insn "aarch64_usubw__zip" +(define_insn "aarch64_usubw_lo_zip" [(set (match_operand: 0 "register_operand" "=w") (minus: (match_operand: 1 "register_operand" "w") @@ -4818,23 +4818,51 @@ (define_insn "aarch64_usubw__zip" (unspec: [ (match_operand:VQW 2 "register_operand" "w") (match_operand:VQW 3 "aarch64_simd_imm_zero") - ] PERM_EXTEND) 0)))] + ] UNSPEC_ZIP1) 0)))] "TARGET_SIMD" - "usubw\\t%0., %1., %2." + "usubw\\t%0., %1., %2." [(set_attr "type" "neon_sub_widen")] ) -(define_insn "aarch64_uaddw__zip" +(define_insn "aarch64_uaddw_lo_zip" [(set (match_operand: 0 "register_operand" "=w") (plus: (subreg: (unspec: [ (match_operand:VQW 2 "register_operand" "w") (match_operand:VQW 3 "aarch64_simd_imm_zero") - ] PERM_EXTEND) 0) + ] UNSPEC_ZIP1) 0) (match_operand: 1 "register_operand" "w")))] "TARGET_SIMD" - "uaddw\\t%0., %1., %2." + "uaddw\\t%0., %1., %2." + [(set_attr "type" "neon_add_widen")] +) + +(define_insn "aarch64_usubw_hi_zip" + [(set (match_operand: 0 "register_operand" "=w") + (minus: + (match_operand: 1 "register_operand" "w") + (subreg: + (unspec: [ + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "aarch64_simd_imm_zero") + ] UNSPEC_ZIP2) 0)))] + "TARGET_SIMD" + "usubw2\\t%0., %1., %2." + [(set_attr "type" "neon_sub_widen")] +) + +(define_insn "aarch64_uaddw_hi_zip" + [(set (match_operand: 0 "register_operand" "=w") + (plus: + (subreg: + (unspec: [ + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "aarch64_simd_imm_zero") + ] UNSPEC_ZIP2) 0) + (match_operand: 1 "register_operand" "w")))] + "TARGET_SIMD" + "uaddw2\\t%0., %1., %2." [(set_attr "type" "neon_add_widen")] ) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 2354315d7d249ccee46625d13b32678f1da1f087..a920de99ffca378ce518f378a35cbe2766877ee8 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -2645,9 +2645,6 @@ (define_int_iterator PERMUTEQ [UNSPEC_ZIP1Q UNSPEC_ZIP2Q (define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 UNSPEC_UZP1 UNSPEC_UZP2]) -;; Permutes for zero extends -(define_int_iterator PERM_EXTEND [UNSPEC_ZIP1 UNSPEC_ZIP2]) - (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16]) (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM @@ -3470,10 +3467,7 @@ (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32") (UNSPEC_REV16 "16")]) (define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi") - (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo") - (UNSPEC_ZIP2 "hi") (UNSPEC_ZIP1 "lo")]) - -(define_int_attr perm_index [(UNSPEC_ZIP2 "2") (UNSPEC_ZIP1 "")]) + (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")]) ;; Return true if the associated optab refers to the high-numbered lanes, ;; false if it refers to the low-numbered lanes. The convention is for diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-4.c b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-4.c index e1a9c4f5661a36ec7b2c5dc6f0fd85c42fcaac39..67944f70ecceff7ed833de86b76606547f3db76c 100755 --- a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-4.c +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-4.c @@ -16,5 +16,5 @@ void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) /* { dg-final { scan-assembler-not {\tzip1\t} } } */ /* { dg-final { scan-assembler-not {\tzip2\t} } } */ /* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */ -/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */ +/* { dg-final { scan-assembler-times {\tsxtl2\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-5.c b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-5.c index 92b09ba4abba80f240ac175be2ef880968534975..e691c4f0b595d1a60b445415970c5a67d7dd0419 100755 --- a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-5.c +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-5.c @@ -16,5 +16,5 @@ void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) /* { dg-final { scan-assembler-not {\tzip1\t} } } */ /* { dg-final { scan-assembler-not {\tzip2\t} } } */ /* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */ -/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */ +/* { dg-final { scan-assembler-times {\tsxtl2\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-6.c b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-6.c index 5c6e635f29d1e52f51f5b75a477f7d8744f32ca3..9383f7ebf9355ff471c48549fc0e4c07706601f1 100755 --- a/gcc/testsuite/gcc.target/aarch64/uxtl-combine-6.c +++ b/gcc/testsuite/gcc.target/aarch64/uxtl-combine-6.c @@ -16,5 +16,5 @@ void d2 (SIGN TYPE2 * restrict a, SIGN TYPE1 *b, int n) /* { dg-final { scan-assembler-not {\tzip1\t} } } */ /* { dg-final { scan-assembler-not {\tzip2\t} } } */ /* { dg-final { scan-assembler-times {\tsxtl\t} 1 } } */ -/* { dg-final { scan-assembler-time {\tsxtl2\t} 1 } } */ +/* { dg-final { scan-assembler-times {\tsxtl2\t} 1 } } */