From patchwork Fri Nov 17 08:33:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 80102 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1156D3857BBF for ; Fri, 17 Nov 2023 08:35:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 2FE6E3858C2C for ; Fri, 17 Nov 2023 08:34:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2FE6E3858C2C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2FE6E3858C2C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700210065; cv=none; b=TCasTTpST9o8YzXtutAkFLSYyui1FsWAzJbgYDpGOINqjkfreLG76PuwFYeDL4mjgqQ1IXknzqQLxPhPpc0h3ykC6G0VuL7rgMYIDR6qtSXJFGNd9A3v5nS/qx7eoLVqaGN3c0vgBtvbFTr/2MFucpt5WiBFQQsznQDb+Ng6nGU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700210065; c=relaxed/simple; bh=aWGb368jPGNea63O5zxIG2XSLjtyn6sfnPnXnaRkMZI=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=LA/ZeG5+E1wc3KKbasntFtiR6MPktWOprPvW10dpFZhq9/TZ2+cSiJPyQchM+dHySe465UDL+lIxr9pb3kC62qaiNzPRckuzDL3dr4adFo0hicz3u0XVMHDDqAWI4nVzd6kME8ZFaMYLRY1TnrCepIOK3gfA43sBhWahm3wiWfY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r3uIs-0006PN-Go for gcc-patches@gcc.gnu.org; Fri, 17 Nov 2023 03:34:20 -0500 Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8DxfeuGJVdl4cI6AA--.47660S3; Fri, 17 Nov 2023 16:34:14 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxbS9rJVdlSSVFAA--.20530S3; Fri, 17 Nov 2023 16:34:11 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, Lulu Cheng Subject: [PATCH v1 1/3] LoongArch: Add LA664 support. Date: Fri, 17 Nov 2023 16:33:42 +0800 Message-Id: <20231117083344.29037-2-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20231117083344.29037-1-chenglulu@loongson.cn> References: <20231117083344.29037-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8CxbS9rJVdlSSVFAA--.20530S3 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW3tFyUWFWrCr1kuFWDAr4xGrX_yoWkKFyxp3 4DZwsxtF48WrZagr1Dt34Ygw1DJwnrGr12qa13tr18Ca13WryUZFn5Kr9rZF1UXa1fW342 qr1rKa1ava1UKacCm3ZEXasCq-sJn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUk2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv 67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxU7tx6UUUUU Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenglulu@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Define ISA_BASE_LA64V110, which represents the base instruction set defined in LoongArch1.1. Support the configure setting --with-arch =la664, and support -march=la664,-mtune=la664. gcc/ChangeLog: * config.gcc: Support LA664. * config/loongarch/genopts/loongarch-strings: Likewise. * config/loongarch/genopts/loongarch.opt.in: Likewise. * config/loongarch/loongarch-cpu.cc (fill_native_cpu_config): Likewise. * config/loongarch/loongarch-def.c: Likewise. * config/loongarch/loongarch-def.h (N_ISA_BASE_TYPES): Likewise. (ISA_BASE_LA64V110): Define macro. (N_ARCH_TYPES): Update value. (N_TUNE_TYPES): Update value. (CPU_LA664): New macro. * config/loongarch/loongarch-opts.cc (isa_default_abi): Likewise. (isa_base_compat_p): Likewise. * config/loongarch/loongarch-opts.h (TARGET_64BIT): This parameter is enabled when la_target.isa.base is equal to ISA_BASE_LA64V100 or ISA_BASE_LA64V110. (TARGET_uARCH_LA664): Define macro. * config/loongarch/loongarch-str.h (STR_CPU_LA664): Likewise. * config/loongarch/loongarch.cc (loongarch_cpu_sched_reassociation_width): Add LA664 support. * config/loongarch/loongarch.opt: Regenerate. --- gcc/config.gcc | 10 ++++----- .../loongarch/genopts/loongarch-strings | 1 + gcc/config/loongarch/genopts/loongarch.opt.in | 3 +++ gcc/config/loongarch/loongarch-cpu.cc | 4 ++++ gcc/config/loongarch/loongarch-def.c | 21 +++++++++++++++++++ gcc/config/loongarch/loongarch-def.h | 8 ++++--- gcc/config/loongarch/loongarch-opts.cc | 8 +++---- gcc/config/loongarch/loongarch-opts.h | 4 +++- gcc/config/loongarch/loongarch-str.h | 1 + gcc/config/loongarch/loongarch.cc | 1 + gcc/config/loongarch/loongarch.opt | 3 +++ 11 files changed, 51 insertions(+), 13 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 6d51bd93f3f..b88591b6fd8 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -5039,7 +5039,7 @@ case "${target}" in # Perform initial sanity checks on --with-* options. case ${with_arch} in - "" | abi-default | loongarch64 | la464) ;; # OK, append here. + "" | abi-default | loongarch64 | la[46]64) ;; # OK, append here. native) if test x${host} != x${target}; then echo "--with-arch=native is illegal for cross-compiler." 1>&2 @@ -5088,7 +5088,7 @@ case "${target}" in case ${abi_base}/${abi_ext} in lp64*/base) # architectures that support lp64* ABI - arch_pattern="native|abi-default|loongarch64|la464" + arch_pattern="native|abi-default|loongarch64|la[46]64" # default architecture for lp64* ABI arch_default="abi-default" ;; @@ -5163,7 +5163,7 @@ case "${target}" in # Check default with_tune configuration using with_arch. case ${with_arch} in loongarch64) - tune_pattern="native|abi-default|loongarch64|la464" + tune_pattern="native|abi-default|loongarch64|la[46]64" ;; *) # By default, $with_tune == $with_arch @@ -5219,7 +5219,7 @@ case "${target}" in # Fixed: use the default gcc configuration for all multilib # builds by default. with_multilib_default="" ;; - arch,native|arch,loongarch64|arch,la464) # OK, append here. + arch,native|arch,loongarch64|arch,la[46]64) # OK, append here. with_multilib_default="/march=${component}" ;; arch,*) with_multilib_default="/march=abi-default" @@ -5307,7 +5307,7 @@ case "${target}" in if test x${parse_state} = x"arch"; then # -march option case ${component} in - native | abi-default | loongarch64 | la464) # OK, append here. + native | abi-default | loongarch64 | la[46]64) # OK, append here. # Append -march spec for each multilib variant. loongarch_multilib_list_make="${loongarch_multilib_list_make}/march=${component}" parse_state="opts" diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings index 8e412f7536e..7bc4824007e 100644 --- a/gcc/config/loongarch/genopts/loongarch-strings +++ b/gcc/config/loongarch/genopts/loongarch-strings @@ -26,6 +26,7 @@ STR_CPU_NATIVE native STR_CPU_ABI_DEFAULT abi-default STR_CPU_LOONGARCH64 loongarch64 STR_CPU_LA464 la464 +STR_CPU_LA664 la664 # Base architecture STR_ISA_BASE_LA64V100 la64 diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index 158701d327a..00b4733d75b 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -107,6 +107,9 @@ Enum(cpu_type) String(@@STR_CPU_LOONGARCH64@@) Value(CPU_LOONGARCH64) EnumValue Enum(cpu_type) String(@@STR_CPU_LA464@@) Value(CPU_LA464) +EnumValue +Enum(cpu_type) String(@@STR_CPU_LA664@@) Value(CPU_LA664) + m@@OPTSTR_ARCH@@= Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPT_UNSET) -m@@OPTSTR_ARCH@@=PROCESSOR Generate code for the given PROCESSOR ISA. diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc index 7a2866f60f9..f3a13414143 100644 --- a/gcc/config/loongarch/loongarch-cpu.cc +++ b/gcc/config/loongarch/loongarch-cpu.cc @@ -106,6 +106,10 @@ fill_native_cpu_config (struct loongarch_target *tgt) native_cpu_type = CPU_LA464; break; + case 0x0014d000: /* LA664 */ + native_cpu_type = CPU_LA664; + break; + default: /* Unknown PRID. */ if (tune_native_p) diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c index 430ef8b2d95..067629141b6 100644 --- a/gcc/config/loongarch/loongarch-def.c +++ b/gcc/config/loongarch/loongarch-def.c @@ -28,6 +28,7 @@ loongarch_cpu_strings[N_TUNE_TYPES] = { [CPU_ABI_DEFAULT] = STR_CPU_ABI_DEFAULT, [CPU_LOONGARCH64] = STR_CPU_LOONGARCH64, [CPU_LA464] = STR_CPU_LA464, + [CPU_LA664] = STR_CPU_LA664, }; struct loongarch_isa @@ -42,6 +43,11 @@ loongarch_cpu_default_isa[N_ARCH_TYPES] = { .fpu = ISA_EXT_FPU64, .simd = ISA_EXT_SIMD_LASX, }, + [CPU_LA664] = { + .base = ISA_BASE_LA64V110, + .fpu = ISA_EXT_FPU64, + .simd = ISA_EXT_SIMD_LASX, + }, }; struct loongarch_cache @@ -58,6 +64,12 @@ loongarch_cpu_cache[N_TUNE_TYPES] = { .l2d_size = 256, .simultaneous_prefetches = 4, }, + [CPU_LA664] = { + .l1d_line_size = 64, + .l1d_size = 64, + .l2d_size = 256, + .simultaneous_prefetches = 4, + }, }; struct loongarch_align @@ -70,6 +82,10 @@ loongarch_cpu_align[N_TUNE_TYPES] = { .function = "32", .label = "16", }, + [CPU_LA664] = { + .function = "32", + .label = "16", + }, }; @@ -104,6 +120,9 @@ loongarch_cpu_rtx_cost_data[N_TUNE_TYPES] = { [CPU_LA464] = { DEFAULT_COSTS }, + [CPU_LA664] = { + DEFAULT_COSTS + }, }; /* RTX costs to use when optimizing for size. */ @@ -127,6 +146,7 @@ loongarch_cpu_issue_rate[N_TUNE_TYPES] = { [CPU_NATIVE] = 4, [CPU_LOONGARCH64] = 4, [CPU_LA464] = 4, + [CPU_LA664] = 6, }; int @@ -134,6 +154,7 @@ loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = { [CPU_NATIVE] = 4, [CPU_LOONGARCH64] = 4, [CPU_LA464] = 4, + [CPU_LA664] = 6, }; /* Wiring string definitions from loongarch-str.h to global arrays diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index 6e2a6987910..db497f3ffe2 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -55,7 +55,8 @@ extern "C" { /* enum isa_base */ extern const char* loongarch_isa_base_strings[]; #define ISA_BASE_LA64V100 0 -#define N_ISA_BASE_TYPES 1 +#define ISA_BASE_LA64V110 1 +#define N_ISA_BASE_TYPES 2 /* enum isa_ext_* */ extern const char* loongarch_isa_ext_strings[]; @@ -141,8 +142,9 @@ struct loongarch_target #define CPU_ABI_DEFAULT 1 #define CPU_LOONGARCH64 2 #define CPU_LA464 3 -#define N_ARCH_TYPES 4 -#define N_TUNE_TYPES 4 +#define CPU_LA664 4 +#define N_ARCH_TYPES 5 +#define N_TUNE_TYPES 5 /* parallel tables. */ extern const char* loongarch_cpu_strings[]; diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc index e5921189a06..67a59152a01 100644 --- a/gcc/config/loongarch/loongarch-opts.cc +++ b/gcc/config/loongarch/loongarch-opts.cc @@ -552,17 +552,17 @@ isa_default_abi (const struct loongarch_isa *isa) switch (isa->fpu) { case ISA_EXT_FPU64: - if (isa->base == ISA_BASE_LA64V100) + if (isa->base >= ISA_BASE_LA64V100) abi.base = ABI_BASE_LP64D; break; case ISA_EXT_FPU32: - if (isa->base == ISA_BASE_LA64V100) + if (isa->base >= ISA_BASE_LA64V100) abi.base = ABI_BASE_LP64F; break; case ISA_EXT_NONE: - if (isa->base == ISA_BASE_LA64V100) + if (isa->base >= ISA_BASE_LA64V100) abi.base = ABI_BASE_LP64S; break; @@ -582,7 +582,7 @@ isa_base_compat_p (const struct loongarch_isa *set1, switch (set2->base) { case ISA_BASE_LA64V100: - return (set1->base == ISA_BASE_LA64V100); + return (set1->base >= ISA_BASE_LA64V100); default: gcc_unreachable (); diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index 8de41bbc4f7..bd2e86a5aa7 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -76,7 +76,8 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target, #define TARGET_DOUBLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU64) #define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D) -#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100) +#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100 \ + || la_target.isa.base == ISA_BASE_LA64V110) #define TARGET_ABI_LP64 (la_target.abi.base == ABI_BASE_LP64D \ || la_target.abi.base == ABI_BASE_LP64F \ || la_target.abi.base == ABI_BASE_LP64S) @@ -88,6 +89,7 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target, /* TARGET_ macros for use in *.md template conditionals */ #define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464) +#define TARGET_uARCH_LA664 (la_target.cpu_tune == CPU_LA664) /* Note: optimize_size may vary across functions, while -m[no]-memcpy imposes a global constraint. */ diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index 072558c28f1..fc4f41bfc1e 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -30,6 +30,7 @@ along with GCC; see the file COPYING3. If not see #define STR_CPU_ABI_DEFAULT "abi-default" #define STR_CPU_LOONGARCH64 "loongarch64" #define STR_CPU_LA464 "la464" +#define STR_CPU_LA664 "la664" #define STR_ISA_BASE_LA64V100 "la64" diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index d05743bec87..464f6c4dd63 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -10173,6 +10173,7 @@ loongarch_cpu_sched_reassociation_width (struct loongarch_target *target, { case CPU_LOONGARCH64: case CPU_LA464: + case CPU_LA664: /* Vector part. */ if (LSX_SUPPORTED_MODE_P (mode) || LASX_SUPPORTED_MODE_P (mode)) { diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index a5988411fbb..7f129e53ba5 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -114,6 +114,9 @@ Enum(cpu_type) String(loongarch64) Value(CPU_LOONGARCH64) EnumValue Enum(cpu_type) String(la464) Value(CPU_LA464) +EnumValue +Enum(cpu_type) String(la664) Value(CPU_LA664) + march= Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPT_UNSET) -march=PROCESSOR Generate code for the given PROCESSOR ISA. From patchwork Fri Nov 17 08:33:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 80103 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 11A0B3857831 for ; Fri, 17 Nov 2023 08:35:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 836B13858404 for ; Fri, 17 Nov 2023 08:34:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 836B13858404 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 836B13858404 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700210061; cv=none; b=bSrHJUjgToyqzlUYhhNyNb9S6M/Ui3MPsjuHkStfn2Hii9HmWD0IkafTXvY58YoTDEHJx5RSCEPSj+guxSeiQNwWp8jlus5VgG3j3ZBi/d2WsuLkyJch/5J6RBYR86K2aKq+PA7JdKU4wwEJFGRyIu7mLdA1e23/XpurUmSHPXI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700210061; c=relaxed/simple; bh=AGNhBnRF7aTaMvrkhFEM9xPluDfpXYJ3AMqqFhn36kI=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Gm3YSHTVKIZm1Q58Ttl4kxQpMa23m3n/cJzK6C7aVgGS0Yl1GA5aOpJJ7kF2NTfMl/zmlv6SZkguvp6nJzN/VYO0VdWgUI0T6sMfIVrSDgkdaUsf0q7tMUPgke1JfFjW+iyOJkQ8zLkDcB31jorFVVpDggr8/hOxhgODeugffng= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8AxZ+iHJVdl5MI6AA--.14753S3; Fri, 17 Nov 2023 16:34:15 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxbS9rJVdlSSVFAA--.20530S4; Fri, 17 Nov 2023 16:34:14 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, Lulu Cheng Subject: [PATCH v1 2/3] LoongArch: Implement atomic operations using LoongArch1.1 instructions. Date: Fri, 17 Nov 2023 16:33:43 +0800 Message-Id: <20231117083344.29037-3-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20231117083344.29037-1-chenglulu@loongson.cn> References: <20231117083344.29037-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8CxbS9rJVdlSSVFAA--.20530S4 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj9fXoW3Kw1ktF43Gry8KF4xZw4UJrc_yoW8Jw4kJo WrtFWDXw18JryY9wsxKr1rAr1vqF4UAF4xAa4avw1YyaykZrZ8JryDGa15Za43JF4DW348 AryIkas8JF97Jw4rl-sFpf9Il3svdjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUY87kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUAVWUZwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI 0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUAVWUtwAv7VC2z280 aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aV CY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8SksDUUUUU== X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org 1. short and char type calls for atomic_add_fetch and __atomic_fetch_add are implemented using amadd{_db}.{b/h}. 2. Use amcas{_db}.{b/h/w/d} to implement __atomic_compare_exchange_n and __atomic_compare_exchange. 3. The short and char types of the functions __atomic_exchange and __atomic_exchange_n are implemented using amswap{_db}.{b/h}. gcc/ChangeLog: * config/loongarch/loongarch-def.h: Add comments. * config/loongarch/loongarch-opts.h (ISA_BASE_IS_LA64V110): Define macro. * config/loongarch/loongarch.cc (loongarch_memmodel_needs_rel_acq_fence): Remove redundant code implementations. * config/loongarch/sync.md (d): Added QI, HI support. (atomic_add): New template. (atomic_exchange_short): Likewise. (atomic_cas_value_strong_amcas): Likewise.. (atomic_fetch_add_short): Likewise. --- gcc/config/loongarch/loongarch-def.h | 2 + gcc/config/loongarch/loongarch-opts.h | 2 +- gcc/config/loongarch/loongarch.cc | 6 +- gcc/config/loongarch/sync.md | 186 ++++++++++++++++++++------ 4 files changed, 147 insertions(+), 49 deletions(-) diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index db497f3ffe2..b319cded456 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -54,7 +54,9 @@ extern "C" { /* enum isa_base */ extern const char* loongarch_isa_base_strings[]; +/* LoongArch V1.00. */ #define ISA_BASE_LA64V100 0 +/* LoongArch V1.10. */ #define ISA_BASE_LA64V110 1 #define N_ISA_BASE_TYPES 2 diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h index bd2e86a5aa7..e8645d9ad5c 100644 --- a/gcc/config/loongarch/loongarch-opts.h +++ b/gcc/config/loongarch/loongarch-opts.h @@ -86,10 +86,10 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target, || la_target.isa.simd == ISA_EXT_SIMD_LASX) #define ISA_HAS_LASX (la_target.isa.simd == ISA_EXT_SIMD_LASX) - /* TARGET_ macros for use in *.md template conditionals */ #define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464) #define TARGET_uARCH_LA664 (la_target.cpu_tune == CPU_LA664) +#define ISA_BASE_IS_LA64V110 (la_target.isa.base == ISA_BASE_LA64V110) /* Note: optimize_size may vary across functions, while -m[no]-memcpy imposes a global constraint. */ diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 464f6c4dd63..5bec10d7418 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -5813,16 +5813,12 @@ loongarch_print_operand_punct_valid_p (unsigned char code) static bool loongarch_memmodel_needs_rel_acq_fence (enum memmodel model) { - switch (model) + switch (memmodel_base (model)) { case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: case MEMMODEL_ACQUIRE: - case MEMMODEL_CONSUME: - case MEMMODEL_SYNC_ACQUIRE: return true; case MEMMODEL_RELAXED: diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md index c112091a60f..66e316d80f5 100644 --- a/gcc/config/loongarch/sync.md +++ b/gcc/config/loongarch/sync.md @@ -38,7 +38,7 @@ (define_code_attr atomic_optab [(plus "add") (ior "or") (xor "xor") (and "and")]) ;; This attribute gives the format suffix for atomic memory operations. -(define_mode_attr amo [(SI "w") (DI "d")]) +(define_mode_attr amo [(QI "b") (HI "h") (SI "w") (DI "d")]) ;; expands to the name of the atomic operand that implements a ;; particular code. @@ -123,7 +123,18 @@ (define_insn "atomic_" UNSPEC_SYNC_OLD_OP))] "" "am%A2.\t$zero,%z1,%0" - [(set (attr "length") (const_int 8))]) + [(set (attr "length") (const_int 4))]) + +(define_insn "atomic_add" + [(set (match_operand:SHORT 0 "memory_operand" "+ZB") + (unspec_volatile:SHORT + [(plus:SHORT (match_dup 0) + (match_operand:SHORT 1 "reg_or_0_operand" "rJ")) + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_SYNC_OLD_OP))] + "ISA_BASE_IS_LA64V110" + "amadd%A2.\t$zero,%z1,%0" + [(set (attr "length") (const_int 4))]) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -131,12 +142,12 @@ (define_insn "atomic_fetch_" (set (match_dup 1) (unspec_volatile:GPR [(any_atomic:GPR (match_dup 1) - (match_operand:GPR 2 "reg_or_0_operand" "rJ")) + (match_operand:GPR 2 "reg_or_0_operand" "rJ")) (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "" "am%A3.\t%0,%z2,%1" - [(set (attr "length") (const_int 8))]) + [(set (attr "length") (const_int 4))]) (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -148,7 +159,19 @@ (define_insn "atomic_exchange" (match_operand:GPR 2 "register_operand" "r"))] "" "amswap%A3.\t%0,%z2,%1" - [(set (attr "length") (const_int 8))]) + [(set (attr "length") (const_int 4))]) + +(define_insn "atomic_exchange_short" + [(set (match_operand:SHORT 0 "register_operand" "=&r") + (unspec_volatile:SHORT + [(match_operand:SHORT 1 "memory_operand" "+ZB") + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_SYNC_EXCHANGE)) + (set (match_dup 1) + (match_operand:SHORT 2 "register_operand" "r"))] + "ISA_BASE_IS_LA64V110" + "amswap%A3.\t%0,%z2,%1" + [(set (attr "length") (const_int 4))]) (define_insn "atomic_cas_value_strong" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -156,25 +179,36 @@ (define_insn "atomic_cas_value_strong" (set (match_dup 1) (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "rJ") (match_operand:GPR 3 "reg_or_0_operand" "rJ") - (match_operand:SI 4 "const_int_operand") ;; mod_s - (match_operand:SI 5 "const_int_operand")] ;; mod_f + (match_operand:SI 4 "const_int_operand")] ;; mod_s UNSPEC_COMPARE_AND_SWAP)) - (clobber (match_scratch:GPR 6 "=&r"))] + (clobber (match_scratch:GPR 5 "=&r"))] "" { return "1:\\n\\t" "ll.\\t%0,%1\\n\\t" "bne\\t%0,%z2,2f\\n\\t" - "or%i3\\t%6,$zero,%3\\n\\t" - "sc.\\t%6,%1\\n\\t" - "beqz\\t%6,1b\\n\\t" + "or%i3\\t%5,$zero,%3\\n\\t" + "sc.\\t%5,%1\\n\\t" + "beqz\\t%5,1b\\n\\t" "b\\t3f\\n\\t" "2:\\n\\t" - "%G5\\n\\t" + "%G4\\n\\t" "3:\\n\\t"; } [(set (attr "length") (const_int 28))]) +(define_insn "atomic_cas_value_strong_amcas" + [(set (match_operand:QHWD 0 "register_operand" "=&r") + (match_operand:QHWD 1 "memory_operand" "+ZB")) + (set (match_dup 1) + (unspec_volatile:QHWD [(match_operand:QHWD 2 "reg_or_0_operand" "rJ") + (match_operand:QHWD 3 "reg_or_0_operand" "rJ") + (match_operand:SI 4 "const_int_operand")] ;; mod_s + UNSPEC_COMPARE_AND_SWAP))] + "ISA_BASE_IS_LA64V110" + "ori\t%0,%z2,0\n\tamcas%A4.\t%0,%z3,%1" + [(set (attr "length") (const_int 8))]) + (define_expand "atomic_compare_and_swap" [(match_operand:SI 0 "register_operand" "") ;; bool output (match_operand:GPR 1 "register_operand" "") ;; val output @@ -186,9 +220,29 @@ (define_expand "atomic_compare_and_swap" (match_operand:SI 7 "const_int_operand" "")] ;; mod_f "" { - emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2], - operands[3], operands[4], - operands[6], operands[7])); + rtx mod_s, mod_f; + + mod_s = operands[6]; + mod_f = operands[7]; + + /* Normally the succ memory model must be stronger than fail, but in the + unlikely event of fail being ACQUIRE and succ being RELEASE we need to + promote succ to ACQ_REL so that we don't lose the acquire semantics. */ + + if (is_mm_acquire (memmodel_base (INTVAL (mod_f))) + && is_mm_release (memmodel_base (INTVAL (mod_s)))) + mod_s = GEN_INT (MEMMODEL_ACQ_REL); + + operands[6] = mod_s; + + if (ISA_BASE_IS_LA64V110) + emit_insn (gen_atomic_cas_value_strong_amcas (operands[1], operands[2], + operands[3], operands[4], + operands[6])); + else + emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2], + operands[3], operands[4], + operands[6])); rtx compare = operands[1]; if (operands[3] != const0_rtx) @@ -292,31 +346,53 @@ (define_expand "atomic_compare_and_swap" (match_operand:SI 7 "const_int_operand" "")] ;; mod_f "" { - union loongarch_gen_fn_ptrs generator; - generator.fn_7 = gen_atomic_cas_value_cmp_and_7_si; - loongarch_expand_atomic_qihi (generator, operands[1], operands[2], - operands[3], operands[4], operands[7]); + rtx mod_s, mod_f; - rtx compare = operands[1]; - if (operands[3] != const0_rtx) - { - machine_mode mode = GET_MODE (operands[3]); - rtx op1 = convert_modes (SImode, mode, operands[1], true); - rtx op3 = convert_modes (SImode, mode, operands[3], true); - rtx difference = gen_rtx_MINUS (SImode, op1, op3); - compare = gen_reg_rtx (SImode); - emit_insn (gen_rtx_SET (compare, difference)); - } + mod_s = operands[6]; + mod_f = operands[7]; - if (word_mode != mode) + /* Normally the succ memory model must be stronger than fail, but in the + unlikely event of fail being ACQUIRE and succ being RELEASE we need to + promote succ to ACQ_REL so that we don't lose the acquire semantics. */ + + if (is_mm_acquire (memmodel_base (INTVAL (mod_f))) + && is_mm_release (memmodel_base (INTVAL (mod_s)))) + mod_s = GEN_INT (MEMMODEL_ACQ_REL); + + operands[6] = mod_s; + + if (ISA_BASE_IS_LA64V110) + emit_insn (gen_atomic_cas_value_strong_amcas (operands[1], operands[2], + operands[3], operands[4], + operands[6])); + else { - rtx reg = gen_reg_rtx (word_mode); - emit_insn (gen_rtx_SET (reg, gen_rtx_SIGN_EXTEND (word_mode, compare))); - compare = reg; + union loongarch_gen_fn_ptrs generator; + generator.fn_7 = gen_atomic_cas_value_cmp_and_7_si; + loongarch_expand_atomic_qihi (generator, operands[1], operands[2], + operands[3], operands[4], operands[6]); } - emit_insn (gen_rtx_SET (operands[0], - gen_rtx_EQ (SImode, compare, const0_rtx))); + rtx compare = operands[1]; + if (operands[3] != const0_rtx) + { + machine_mode mode = GET_MODE (operands[3]); + rtx op1 = convert_modes (SImode, mode, operands[1], true); + rtx op3 = convert_modes (SImode, mode, operands[3], true); + rtx difference = gen_rtx_MINUS (SImode, op1, op3); + compare = gen_reg_rtx (SImode); + emit_insn (gen_rtx_SET (compare, difference)); + } + + if (word_mode != mode) + { + rtx reg = gen_reg_rtx (word_mode); + emit_insn (gen_rtx_SET (reg, gen_rtx_SIGN_EXTEND (word_mode, compare))); + compare = reg; + } + + emit_insn (gen_rtx_SET (operands[0], + gen_rtx_EQ (SImode, compare, const0_rtx))); DONE; }) @@ -505,13 +581,31 @@ (define_expand "atomic_exchange" (match_operand:SHORT 2 "register_operand"))] "" { - union loongarch_gen_fn_ptrs generator; - generator.fn_7 = gen_atomic_cas_value_exchange_7_si; - loongarch_expand_atomic_qihi (generator, operands[0], operands[1], - const0_rtx, operands[2], operands[3]); + if (ISA_BASE_IS_LA64V110) + emit_insn (gen_atomic_exchange_short (operands[0], operands[1], operands[2], operands[3])); + else + { + union loongarch_gen_fn_ptrs generator; + generator.fn_7 = gen_atomic_cas_value_exchange_7_si; + loongarch_expand_atomic_qihi (generator, operands[0], operands[1], + const0_rtx, operands[2], operands[3]); + } DONE; }) +(define_insn "atomic_fetch_add_short" + [(set (match_operand:SHORT 0 "register_operand" "=&r") + (match_operand:SHORT 1 "memory_operand" "+ZB")) + (set (match_dup 1) + (unspec_volatile:SHORT + [(plus:SHORT (match_dup 1) + (match_operand:SHORT 2 "reg_or_0_operand" "rJ")) + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_SYNC_OLD_OP))] + "ISA_BASE_IS_LA64V110" + "amadd%A3.\t%0,%z2,%1" + [(set (attr "length") (const_int 4))]) + (define_expand "atomic_fetch_add" [(set (match_operand:SHORT 0 "register_operand" "=&r") (match_operand:SHORT 1 "memory_operand" "+ZB")) @@ -523,10 +617,16 @@ (define_expand "atomic_fetch_add" UNSPEC_SYNC_OLD_OP))] "" { - union loongarch_gen_fn_ptrs generator; - generator.fn_7 = gen_atomic_cas_value_add_7_si; - loongarch_expand_atomic_qihi (generator, operands[0], operands[1], - operands[1], operands[2], operands[3]); + if (ISA_BASE_IS_LA64V110) + emit_insn (gen_atomic_fetch_add_short (operands[0], operands[1], + operands[2], operands[3])); + else + { + union loongarch_gen_fn_ptrs generator; + generator.fn_7 = gen_atomic_cas_value_add_7_si; + loongarch_expand_atomic_qihi (generator, operands[0], operands[1], + operands[1], operands[2], operands[3]); + } DONE; }) From patchwork Fri Nov 17 08:33:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 80101 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 35A3E3857828 for ; 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c=relaxed/simple; bh=FuKaMT/ZGKAC7925bDM7b7mc8jaSYoNgAkLs9p3ZicI=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=HWfxEWe+c2gVBc7+VDFjHNdewwJSuQxNvz9Og1mbixoDEfBSSPCVY4dPpdU/dwAOyzy5jdlSeyZuqKYWfQ0HD09hmwAOPb0DbyjCDg0ag52JBs7j3WeNVREQb64LToYJaXI9TWnzuv3yEfwMPdkfzxoQZrb8Z57WhXpf+sRIJbA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r3uIt-0006Pq-EJ for gcc-patches@gcc.gnu.org; Fri, 17 Nov 2023 03:34:22 -0500 Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8Dx_+uIJVdl5sI6AA--.49141S3; Fri, 17 Nov 2023 16:34:16 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxbS9rJVdlSSVFAA--.20530S5; Fri, 17 Nov 2023 16:34:15 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, Lulu Cheng Subject: [PATCH v1 3/3] LoongArch: atomic_load and atomic_store are implemented using dbar grading. Date: Fri, 17 Nov 2023 16:33:44 +0800 Message-Id: <20231117083344.29037-4-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20231117083344.29037-1-chenglulu@loongson.cn> References: <20231117083344.29037-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8CxbS9rJVdlSSVFAA--.20530S5 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoWxXFWxWrW7ury3uFyxCFy3Awc_yoWrCF4rpr WDWa15tr4rX39293s3AFWUJw45Jw1kAFW7JF9rJr9rur9rWw15Z3W0kF9F9FyUGw1rKw4f AFW5ZFW5u3W7CrXCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUk2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5McIj6I8E87Iv 67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxUcCD7UUUUU Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenglulu@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_FAIL, SPF_HELO_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Because the la464 memory model design allows the same address load out of order, so in the following test example, the Load of 23 lines may be executed first over the load of 21 lines, resulting in an error. So when memmodel is MEMMODEL_RELAXED, the load instruction will be followed by "dbar 0x700" when implementing _atomic_load. 1 void * 2 gomp_ptrlock_get_slow (gomp_ptrlock_t *ptrlock) 3 { 4 int *intptr; 5 uintptr_t oldval = 1; 6 7 __atomic_compare_exchange_n (ptrlock, &oldval, 2, false, 8 MEMMODEL_RELAXED, MEMMODEL_RELAXED); 9 10 /* futex works on ints, not pointers. 11 But a valid work share pointer will be at least 12 8 byte aligned, so it is safe to assume the low 13 32-bits of the pointer won't contain values 1 or 2. */ 14 __asm volatile ("" : "=r" (intptr) : "0" (ptrlock)); 15 #if __BYTE_ORDER == __BIG_ENDIAN 16 if (sizeof (*ptrlock) > sizeof (int)) 17 intptr += (sizeof (*ptrlock) / sizeof (int)) - 1; 18 #endif 19 do 20 do_wait (intptr, 2); 21 while (__atomic_load_n (intptr, MEMMODEL_RELAXED) == 2); 22 __asm volatile ("" : : : "memory"); 23 return (void *) __atomic_load_n (ptrlock, MEMMODEL_ACQUIRE); 24 } gcc/ChangeLog: * config/loongarch/sync.md (atomic_load): New template. --- gcc/config/loongarch/sync.md | 70 +++++++++++++++++++++++++++++++++--- 1 file changed, 65 insertions(+), 5 deletions(-) diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md index 66e316d80f5..67848d72b87 100644 --- a/gcc/config/loongarch/sync.md +++ b/gcc/config/loongarch/sync.md @@ -30,6 +30,7 @@ (define_c_enum "unspec" [ UNSPEC_SYNC_OLD_OP UNSPEC_SYNC_EXCHANGE UNSPEC_ATOMIC_STORE + UNSPEC_ATOMIC_LOAD UNSPEC_MEMORY_BARRIER ]) @@ -103,16 +104,75 @@ (define_insn "mem_thread_fence_1" ;; Atomic memory operations. +(define_insn "atomic_load" + [(set (match_operand:QHWD 0 "register_operand" "=r") + (unspec_volatile:QHWD + [(match_operand:QHWD 1 "memory_operand" "+m") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "" +{ + enum memmodel model = memmodel_base (INTVAL (operands[2])); + + switch (model) + { + case MEMMODEL_SEQ_CST: + return "dbar\t0x11\\n\\t" + "ld.\t%0,%1\\n\\t" + "dbar\t0x14\\n\\t"; + case MEMMODEL_ACQUIRE: + return "ld.\t%0,%1\\n\\t" + "dbar\t0x14\\n\\t"; + case MEMMODEL_RELAXED: + return "ld.\t%0,%1\\n\\t" + "dbar\t0x700\\n\\t"; + + default: + /* The valid memory order variants are __ATOMIC_RELAXED, __ATOMIC_SEQ_CST, + __ATOMIC_CONSUME and __ATOMIC_ACQUIRE. + The expand_builtin_atomic_store function converts all invalid memmodels + to MEMMODEL_SEQ_CST. + + __atomic builtins doc: "Consume is implemented using the + stronger acquire memory order because of a deficiency in C++11's + semantics." See PR 59448 and get_memmodel in builtins.cc. */ + gcc_unreachable (); + } +} + [(set (attr "length") (const_int 12))]) + ;; Implement atomic stores with amoswap. Fall back to fences for atomic loads. (define_insn "atomic_store" - [(set (match_operand:GPR 0 "memory_operand" "+ZB") - (unspec_volatile:GPR - [(match_operand:GPR 1 "reg_or_0_operand" "rJ") + [(set (match_operand:QHWD 0 "memory_operand" "+m") + (unspec_volatile:QHWD + [(match_operand:QHWD 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "" - "amswap%A2.\t$zero,%z1,%0" - [(set (attr "length") (const_int 8))]) +{ + enum memmodel model = memmodel_base (INTVAL (operands[2])); + + switch (model) + { + case MEMMODEL_SEQ_CST: + return "dbar\t0x12\\n\\t" + "st.\t%z1,%0\\n\\t" + "dbar\t0x18\\n\\t"; + case MEMMODEL_RELEASE: + return "dbar\t0x12\\n\\t" + "st.\t%z1,%0\\n\\t"; + case MEMMODEL_RELAXED: + return "st.\t%z1,%0"; + + default: + /* The valid memory order variants are __ATOMIC_RELAXED, __ATOMIC_SEQ_CST, + and __ATOMIC_RELEASE. + The expand_builtin_atomic_store function converts all invalid memmodels + to MEMMODEL_SEQ_CST. */ + gcc_unreachable (); + } +} + [(set (attr "length") (const_int 12))]) (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+ZB")