From patchwork Fri Nov 10 07:17:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 79532 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3E1A7385700C for ; Fri, 10 Nov 2023 07:18:47 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from out30-97.freemail.mail.aliyun.com (out30-97.freemail.mail.aliyun.com [115.124.30.97]) by sourceware.org (Postfix) with ESMTPS id 5362B3858D38 for ; Fri, 10 Nov 2023 07:18:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5362B3858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5362B3858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.97 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699600713; cv=none; b=t4mAw+KH4UEqDDED8Gmdzr1cdz80DecfMxFl8kBNY5r2LkNFFXWkCZiYOZ3Zo/2FQ8IyjN5HPj86hkfZ/UC1+wlrvdug+zExqit4nFAgutfj4DcXl1M2VUL5iROgwO9rqN4egDkxh9PDrE1SR509v5DGlfMNYz9HYp4tYG+VDto= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699600713; c=relaxed/simple; bh=ix6vcjlhc1gVq3c6iBZy0Gvnz2wsnCIV9QSaxofIaxY=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=JQdhbY9Ku9C8mVcpYK9RzlsaFxpUzQrzRg+EvYwifxHFlLFNdHmHgZSH1sLKeTHmXoUkKVtdXzWWyPpGokkqCRl7bqsH1E6545fd8YvDDfucT5dUKQ/trRNY1/twM3KbwtFCSiP/vJUGDCkcjcy5R6QtRNAfYVoees9qta/7YpM= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R171e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045176; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=6; SR=0; TI=SMTPD_---0Vw3j9Ew_1699600692; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw3j9Ew_1699600692) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:18:13 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 01/12] RISC-V: Add T-Head VECTOR vendor extension. Date: Fri, 10 Nov 2023 15:17:59 +0800 Message-Id: <20231110071759.1640-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Spam-Status: No, score=-20.3 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the "XTheadVector" extension, a collection of T-Head-specific vector instructions. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). Here are some things that need to be explained: The "XTheadVector" extension is not a custom-extension, but a non-standard non-conforming extension. The encoding space of the "TheadVector" instructions overlaps with those of the 'V' extension. This encoding space conflict is not on purpose, but the result of issues in the past that have been resolved since. Therefore, the "XTheadVector" extension and the 'V' extension are in conflict. [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): The "XTheadVector" extension and the 'V' extension are in conflict. (riscv_multi_subset_supports): Likewise.. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: * testsuite/gas/riscv/x-thead-vector-fail.d: New test. * testsuite/gas/riscv/x-thead-vector-fail.l: New test. * testsuite/gas/riscv/x-thead-vector.s: New test. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): --- bfd/elfxx-riscv.c | 12 ++++++++++++ gas/NEWS | 3 +++ gas/doc/c-riscv.texi | 5 +++++ gas/testsuite/gas/riscv/x-thead-vector-fail.d | 3 +++ gas/testsuite/gas/riscv/x-thead-vector-fail.l | 2 ++ gas/testsuite/gas/riscv/x-thead-vector.s | 0 include/opcode/riscv.h | 1 + 7 files changed, 26 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index c9acf124626..e2c3ffe4b4f 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1373,6 +1373,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadvector", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -1984,6 +1985,13 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps) (_("`zfinx' is conflict with the `f/d/q/zfh/zfhmin' extension")); no_conflict = false; } + if (riscv_lookup_subset (rps->subset_list, "xtheadvector", &subset) + && riscv_lookup_subset (rps->subset_list, "v", &subset)) + { + rps->error_handler + (_("`xtheadvector' is conflict with the `v' extension")); + no_conflict = false; + } bool support_zve = false; bool support_zvl = false; @@ -2580,6 +2588,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadmempair"); case INSN_CLASS_XTHEADSYNC: return riscv_subset_supports (rps, "xtheadsync"); + case INSN_CLASS_XTHEADVECTOR: + return riscv_subset_supports (rps, "xtheadvector"); case INSN_CLASS_XVENTANACONDOPS: return riscv_subset_supports (rps, "xventanacondops"); default: @@ -2824,6 +2834,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadmempair"; case INSN_CLASS_XTHEADSYNC: return "xtheadsync"; + case INSN_CLASS_XTHEADVECTOR: + return "xtheadvector"; default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/gas/NEWS b/gas/NEWS index ddf48fca37b..aae0c6b71c0 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -28,6 +28,9 @@ * Add support for Cortex-X4 for AArch64. +* Add support for various T-Head extensions (XTheadVector, XTheadZvlsseg + and XTheadZvamo) from version 2.3.0 of the T-Head ISA manual. + Changes in 2.41: * Add support for the KVX instruction set. diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index b23504648bd..a7c9420bd86 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -814,6 +814,11 @@ The XTheadSync extension provides instructions for multi-processor synchronizati It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadVector +The XTheadVector extension provides instructions for thead vector. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}. + @item XVentanaCondOps XVentanaCondOps extension provides instructions for branchless sequences that perform conditional arithmetic, conditional diff --git a/gas/testsuite/gas/riscv/x-thead-vector-fail.d b/gas/testsuite/gas/riscv/x-thead-vector-fail.d new file mode 100644 index 00000000000..ac99c3f5398 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64gcv_xtheadvector +#source: x-thead-vector.s +#error_output: x-thead-vector-fail.l diff --git a/gas/testsuite/gas/riscv/x-thead-vector-fail.l b/gas/testsuite/gas/riscv/x-thead-vector-fail.l new file mode 100644 index 00000000000..7dd88e317ce --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-fail.l @@ -0,0 +1,2 @@ +Assembler messages: +Error: `xtheadvector' is conflict with the `v' extension \ No newline at end of file diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s new file mode 100644 index 00000000000..e69de29bb2d diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 710a9b73189..a26ef8abf12 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -467,6 +467,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADMEMIDX, INSN_CLASS_XTHEADMEMPAIR, INSN_CLASS_XTHEADSYNC, + INSN_CLASS_XTHEADVECTOR, INSN_CLASS_XVENTANACONDOPS, }; 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Fri, 10 Nov 2023 15:21:07 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 02/12] RISC-V: Add CSRs for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:20:15 +0800 Message-Id: <20231110072015.1684-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.2 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the CSRs for XTheadVector. Because of the conflict between encoding and teh 'V' extension, it is implemented by alias. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add the class for the CSRs of the "XTheadVector" extension. (riscv_csr_address): Likewise. * testsuite/gas/riscv/x-thead-vector-csr-warn.d: New test. * testsuite/gas/riscv/x-thead-vector-csr-warn.l: New test. * testsuite/gas/riscv/x-thead-vector-csr.d: New test. * testsuite/gas/riscv/x-thead-vector-csr.s: New test. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_CSR_ALIAS): Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Prefix the CSRs disassembly with 'th'. --- gas/config/tc-riscv.c | 4 ++++ .../gas/riscv/x-thead-vector-csr-warn.d | 3 +++ .../gas/riscv/x-thead-vector-csr-warn.l | 16 ++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector-csr.d | 21 +++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector-csr.s | 13 ++++++++++++ include/opcode/riscv-opc.h | 7 +++++++ opcodes/riscv-dis.c | 14 +++++++++++-- 7 files changed, 76 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.d create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.s diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 402c46ad753..af9a34a2185 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -91,6 +91,7 @@ enum riscv_csr_class CSR_CLASS_SSTC_AND_H, /* Sstc only (with H) */ CSR_CLASS_SSTC_32, /* Sstc RV32 only */ CSR_CLASS_SSTC_AND_H_32, /* Sstc RV32 only (with H) */ + CSR_CLASS_XTHEADVECTOR, /* xtheadvector only */ }; /* This structure holds all restricted conditions for a CSR. */ @@ -1104,6 +1105,9 @@ riscv_csr_address (const char *csr_name, break; case CSR_CLASS_DEBUG: break; + case CSR_CLASS_XTHEADVECTOR: + extension = "xtheadvector"; + break; default: as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class); } diff --git a/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d b/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d new file mode 100644 index 00000000000..17c707ddc7e --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d @@ -0,0 +1,3 @@ +#as: -march=rv64gc -mcsr-check +#source: x-thead-vector-csr.s +#warning_output: x-thead-vector-csr-warn.l diff --git a/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l b/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l new file mode 100644 index 00000000000..4dd867ce2ee --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l @@ -0,0 +1,16 @@ +.*Assembler messages: +.*Warning: invalid CSR `th.vstart', needs `xtheadvector' extension +.*Warning: invalid CSR `th.vxsat', needs `xtheadvector' extension +.*Warning: invalid CSR `th.vxrm', needs `xtheadvector' extension +.*Warning: invalid CSR `th.vl', needs `xtheadvector' extension +.*Warning: invalid CSR `th.vtype', needs `xtheadvector' extension +.*Warning: invalid CSR `th.vlenb', needs `xtheadvector' extension +.*Warning: invalid CSR `th.vstart', needs `xtheadvector' extension +.*Warning: invalid CSR `th.vxsat', needs `xtheadvector' extension +.*Warning: invalid CSR `th.vxrm', needs `xtheadvector' extension +.*Warning: invalid CSR `th.vl', needs `xtheadvector' extension +.*Warning: read-only CSR is written `csrw th.vl,a0' +.*Warning: invalid CSR `th.vtype', needs `xtheadvector' extension +.*Warning: read-only CSR is written `csrw th.vtype,a0' +.*Warning: invalid CSR `th.vlenb', needs `xtheadvector' extension +.*Warning: read-only CSR is written `csrw th.vlenb,a0' \ No newline at end of file diff --git a/gas/testsuite/gas/riscv/x-thead-vector-csr.d b/gas/testsuite/gas/riscv/x-thead-vector-csr.d new file mode 100644 index 00000000000..75357b204cc --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-csr.d @@ -0,0 +1,21 @@ +#as: -march=rv32if_xtheadvector +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,th.vstart +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,th.vxsat +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,th.vxrm +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,th.vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,th.vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,th.vlenb +[ ]+[0-9a-f]+:[ ]+00851073[ ]+csrw[ ]+th.vstart,a0 +[ ]+[0-9a-f]+:[ ]+00951073[ ]+csrw[ ]+th.vxsat,a0 +[ ]+[0-9a-f]+:[ ]+00a51073[ ]+csrw[ ]+th.vxrm,a0 +[ ]+[0-9a-f]+:[ ]+c2051073[ ]+csrw[ ]+th.vl,a0 +[ ]+[0-9a-f]+:[ ]+c2151073[ ]+csrw[ ]+th.vtype,a0 +[ ]+[0-9a-f]+:[ ]+c2251073[ ]+csrw[ ]+th.vlenb,a0 diff --git a/gas/testsuite/gas/riscv/x-thead-vector-csr.s b/gas/testsuite/gas/riscv/x-thead-vector-csr.s new file mode 100644 index 00000000000..e11f87f1a07 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-csr.s @@ -0,0 +1,13 @@ + csrr a0, th.vstart + csrr a0, th.vxsat + csrr a0, th.vxrm + csrr a0, th.vl + csrr a0, th.vtype + csrr a0, th.vlenb + + csrw th.vstart, a0 + csrw th.vxsat, a0 + csrw th.vxrm, a0 + csrw th.vl, a0 # read-only CSR + csrw th.vtype, a0 # read-only CSR + csrw th.vlenb, a0 # read-only CSR diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 24217062edc..ed29384e825 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -4121,4 +4121,11 @@ DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, P DECLARE_CSR_ALIAS(tmexttrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +/* Unprivileged T-Head Vector CSRs. */ +DECLARE_CSR_ALIAS(th.vstart, CSR_VSTART, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR_ALIAS(th.vxsat, CSR_VXSAT, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR_ALIAS(th.vxrm, CSR_VXRM, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR_ALIAS(th.vl, CSR_VL, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR_ALIAS(th.vtype, CSR_VTYPE, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR_ALIAS(th.vlenb, CSR_VLENB, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) #endif /* DECLARE_CSR_ALIAS */ diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index ca328b4c997..2d7c154cc3d 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -568,8 +568,18 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info } if (riscv_csr_hash[csr] != NULL) - print (info->stream, dis_style_register, "%s", - riscv_csr_hash[csr]); + if (riscv_subset_supports (&riscv_rps_dis, "xtheadvector") + && (csr == CSR_VSTART + || csr == CSR_VXSAT + || csr == CSR_VXRM + || csr == CSR_VL + || csr == CSR_VTYPE + || csr == CSR_VLENB)) + print (info->stream, dis_style_register, "%s", + concat ("th.", riscv_csr_hash[csr], NULL)); + else + print (info->stream, dis_style_register, "%s", + riscv_csr_hash[csr]); else print (info->stream, dis_style_immediate, "0x%x", csr); break; From patchwork Fri Nov 10 07:22:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 79534 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EEF5F385771B for ; Fri, 10 Nov 2023 07:22:55 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from out30-113.freemail.mail.aliyun.com (out30-113.freemail.mail.aliyun.com [115.124.30.113]) by sourceware.org (Postfix) with ESMTPS id 10CB53858D38 for ; Fri, 10 Nov 2023 07:22:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 10CB53858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass 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MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=6; SR=0; TI=SMTPD_---0Vw3jXbb_1699600954; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw3jXbb_1699600954) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:22:35 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 03/12] RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:22:24 +0800 Message-Id: <20231110072224.1735-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.3 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds configuration-setting instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: New test. * testsuite/gas/riscv/x-thead-vector.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VSETVL): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.. --- gas/testsuite/gas/riscv/x-thead-vector.d | 12 ++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 3 +++ include/opcode/riscv-opc.h | 5 +++++ opcodes/riscv-opc.c | 4 ++++ 4 files changed, 24 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.d diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d new file mode 100644 index 00000000000..e509ed0971b --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -0,0 +1,12 @@ +#as: -march=rv32if_xtheadvector +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+th.vsetvl[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+th.vsetvli[ ]+a0,a1,e8,m1,tu,mu +[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+th.vsetvli[ ]+a0,a1,2047 diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index e69de29bb2d..ffea0a6f9f9 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -0,0 +1,3 @@ + th.vsetvl a0, a1, a2 + th.vsetvli a0, a1, 0 + th.vsetvli a0, a1, 0x7ff diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index ed29384e825..dc18dd9f04c 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2648,6 +2648,11 @@ #define MASK_TH_SYNC_IS 0xffffffff #define MATCH_TH_SYNC_S 0x0190000b #define MASK_TH_SYNC_S 0xffffffff +/* Vendor-specific (T-Head) XTheadVector instructions. */ +#define MATCH_TH_VSETVL 0x80007057 +#define MASK_TH_VSETVL 0xfe00707f +#define MATCH_TH_VSETVLI 0x00007057 +#define MASK_TH_VSETVLI 0x8000707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 72d727cd77e..2fb7cf1e14a 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2234,6 +2234,10 @@ const struct riscv_opcode riscv_opcodes[] = {"th.sync.is", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS, match_opcode, 0}, {"th.sync.s", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_S, MASK_TH_SYNC_S, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadVector instructions. */ +{"th.vsetvl", 0, INSN_CLASS_XTHEADVECTOR, "d,s,t", MATCH_TH_VSETVL, MASK_TH_VSETVL, match_opcode, 0}, +{"th.vsetvli", 0, INSN_CLASS_XTHEADVECTOR, "d,s,Vc", MATCH_TH_VSETVLI, MASK_TH_VSETVLI, match_opcode, 0}, + /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, {"vt.maskcn", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 }, From patchwork Fri Nov 10 07:23:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 79535 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4AD2E385703F for ; Fri, 10 Nov 2023 07:24:15 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from out30-124.freemail.mail.aliyun.com (out30-124.freemail.mail.aliyun.com [115.124.30.124]) by sourceware.org (Postfix) with ESMTPS id AA3FD3858D38 for ; Fri, 10 Nov 2023 07:23:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AA3FD3858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AA3FD3858D38 Authentication-Results: server2.sourceware.org; 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Fri, 10 Nov 2023 15:23:49 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 04/12] RISC-V: Add load/store instructions for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:23:33 +0800 Message-Id: <20231110072334.1782-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.3 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds load/store instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for load/store instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VLBV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise. --- gas/testsuite/gas/riscv/x-thead-vector.d | 132 ++++++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 136 +++++++++++++++++++++++ include/opcode/riscv-opc.h | 88 +++++++++++++++ opcodes/riscv-opc.c | 44 ++++++++ 4 files changed, 400 insertions(+) diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index e509ed0971b..d7cb1e1a457 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -10,3 +10,135 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+80c5f557[ ]+th.vsetvl[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+0005f557[ ]+th.vsetvli[ ]+a0,a1,e8,m1,tu,mu [ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+th.vsetvli[ ]+a0,a1,2047 +[ ]+[0-9a-f]+:[ ]+12050207[ ]+th.vlb.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+12050207[ ]+th.vlb.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+10050207[ ]+th.vlb.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+12055207[ ]+th.vlh.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+12055207[ ]+th.vlh.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+10055207[ ]+th.vlh.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+12056207[ ]+th.vlw.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+12056207[ ]+th.vlw.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+10056207[ ]+th.vlw.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+02050207[ ]+th.vlbu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02050207[ ]+th.vlbu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+00050207[ ]+th.vlbu.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+02055207[ ]+th.vlhu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02055207[ ]+th.vlhu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+00055207[ ]+th.vlhu.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+02056207[ ]+th.vlwu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02056207[ ]+th.vlwu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+00056207[ ]+th.vlwu.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+02057207[ ]+th.vle.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02057207[ ]+th.vle.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+00057207[ ]+th.vle.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+02050227[ ]+th.vsb.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02050227[ ]+th.vsb.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+00050227[ ]+th.vsb.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+02055227[ ]+th.vsh.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02055227[ ]+th.vsh.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+00055227[ ]+th.vsh.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+02056227[ ]+th.vsw.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02056227[ ]+th.vsw.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+00056227[ ]+th.vsw.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+02057227[ ]+th.vse.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02057227[ ]+th.vse.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+00057227[ ]+th.vse.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+1ab50207[ ]+th.vlsb.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+1ab50207[ ]+th.vlsb.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+18b50207[ ]+th.vlsb.v[ ]+v4,\(a0\),a1,v0.t +[ ]+[0-9a-f]+:[ ]+1ab55207[ ]+th.vlsh.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+1ab55207[ ]+th.vlsh.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+18b55207[ ]+th.vlsh.v[ ]+v4,\(a0\),a1,v0.t +[ ]+[0-9a-f]+:[ ]+1ab56207[ ]+th.vlsw.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+1ab56207[ ]+th.vlsw.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+18b56207[ ]+th.vlsw.v[ ]+v4,\(a0\),a1,v0.t +[ ]+[0-9a-f]+:[ ]+0ab50207[ ]+th.vlsbu.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+0ab50207[ ]+th.vlsbu.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+08b50207[ ]+th.vlsbu.v[ ]+v4,\(a0\),a1,v0.t +[ ]+[0-9a-f]+:[ ]+0ab55207[ ]+th.vlshu.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+0ab55207[ ]+th.vlshu.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+08b55207[ ]+th.vlshu.v[ ]+v4,\(a0\),a1,v0.t +[ ]+[0-9a-f]+:[ ]+0ab56207[ ]+th.vlswu.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+0ab56207[ ]+th.vlswu.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+08b56207[ ]+th.vlswu.v[ ]+v4,\(a0\),a1,v0.t +[ ]+[0-9a-f]+:[ ]+0ab57207[ ]+th.vlse.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+0ab57207[ ]+th.vlse.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+08b57207[ ]+th.vlse.v[ ]+v4,\(a0\),a1,v0.t +[ ]+[0-9a-f]+:[ ]+0ab50227[ ]+th.vssb.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+0ab50227[ ]+th.vssb.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+08b50227[ ]+th.vssb.v[ ]+v4,\(a0\),a1,v0.t +[ ]+[0-9a-f]+:[ ]+0ab55227[ ]+th.vssh.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+0ab55227[ ]+th.vssh.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+08b55227[ ]+th.vssh.v[ ]+v4,\(a0\),a1,v0.t +[ ]+[0-9a-f]+:[ ]+0ab56227[ ]+th.vssw.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+0ab56227[ ]+th.vssw.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+08b56227[ ]+th.vssw.v[ ]+v4,\(a0\),a1,v0.t +[ ]+[0-9a-f]+:[ ]+0ab57227[ ]+th.vsse.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+0ab57227[ ]+th.vsse.v[ ]+v4,\(a0\),a1 +[ ]+[0-9a-f]+:[ ]+08b57227[ ]+th.vsse.v[ ]+v4,\(a0\),a1,v0.t +[ ]+[0-9a-f]+:[ ]+1ec50207[ ]+th.vlxb.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1ec50207[ ]+th.vlxb.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1cc50207[ ]+th.vlxb.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+1ec55207[ ]+th.vlxh.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1ec55207[ ]+th.vlxh.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1cc55207[ ]+th.vlxh.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+1ec56207[ ]+th.vlxw.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1ec56207[ ]+th.vlxw.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1cc56207[ ]+th.vlxw.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+0ec50207[ ]+th.vlxbu.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0ec50207[ ]+th.vlxbu.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0cc50207[ ]+th.vlxbu.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+0ec55207[ ]+th.vlxhu.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0ec55207[ ]+th.vlxhu.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0cc55207[ ]+th.vlxhu.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+0ec56207[ ]+th.vlxwu.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0ec56207[ ]+th.vlxwu.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0cc56207[ ]+th.vlxwu.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+0ec57207[ ]+th.vlxe.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0ec57207[ ]+th.vlxe.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0cc57207[ ]+th.vlxe.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+0ec50227[ ]+th.vsxb.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0ec50227[ ]+th.vsxb.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0cc50227[ ]+th.vsxb.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+0ec55227[ ]+th.vsxh.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0ec55227[ ]+th.vsxh.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0cc55227[ ]+th.vsxh.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+0ec56227[ ]+th.vsxw.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0ec56227[ ]+th.vsxw.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0cc56227[ ]+th.vsxw.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+0ec57227[ ]+th.vsxe.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0ec57227[ ]+th.vsxe.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+0cc57227[ ]+th.vsxe.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+1ec50227[ ]+th.vsuxb.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1ec50227[ ]+th.vsuxb.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1cc50227[ ]+th.vsuxb.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+1ec55227[ ]+th.vsuxh.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1ec55227[ ]+th.vsuxh.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1cc55227[ ]+th.vsuxh.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+1ec56227[ ]+th.vsuxw.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1ec56227[ ]+th.vsuxw.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1cc56227[ ]+th.vsuxw.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+1ec57227[ ]+th.vsuxe.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1ec57227[ ]+th.vsuxe.v[ ]+v4,\(a0\),v12 +[ ]+[0-9a-f]+:[ ]+1cc57227[ ]+th.vsuxe.v[ ]+v4,\(a0\),v12,v0.t +[ ]+[0-9a-f]+:[ ]+13050207[ ]+th.vlbff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+13050207[ ]+th.vlbff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+11050207[ ]+th.vlbff.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+13055207[ ]+th.vlhff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+13055207[ ]+th.vlhff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+11055207[ ]+th.vlhff.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+13056207[ ]+th.vlwff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+13056207[ ]+th.vlwff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+11056207[ ]+th.vlwff.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+03050207[ ]+th.vlbuff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+03050207[ ]+th.vlbuff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+01050207[ ]+th.vlbuff.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+03055207[ ]+th.vlhuff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+03055207[ ]+th.vlhuff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+01055207[ ]+th.vlhuff.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+03056207[ ]+th.vlwuff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+03056207[ ]+th.vlwuff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+01056207[ ]+th.vlwuff.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+03057207[ ]+th.vleff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+03057207[ ]+th.vleff.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+01057207[ ]+th.vleff.v[ ]+v4,\(a0\),v0.t diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index ffea0a6f9f9..c65e9e8790c 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -1,3 +1,139 @@ th.vsetvl a0, a1, a2 th.vsetvli a0, a1, 0 th.vsetvli a0, a1, 0x7ff + + th.vlb.v v4, (a0) + th.vlb.v v4, 0(a0) + th.vlb.v v4, (a0), v0.t + th.vlh.v v4, (a0) + th.vlh.v v4, 0(a0) + th.vlh.v v4, (a0), v0.t + th.vlw.v v4, (a0) + th.vlw.v v4, 0(a0) + th.vlw.v v4, (a0), v0.t + th.vlbu.v v4, (a0) + th.vlbu.v v4, 0(a0) + th.vlbu.v v4, (a0), v0.t + th.vlhu.v v4, (a0) + th.vlhu.v v4, 0(a0) + th.vlhu.v v4, (a0), v0.t + th.vlwu.v v4, (a0) + th.vlwu.v v4, 0(a0) + th.vlwu.v v4, (a0), v0.t + th.vle.v v4, (a0) + th.vle.v v4, 0(a0) + th.vle.v v4, (a0), v0.t + th.vsb.v v4, (a0) + th.vsb.v v4, 0(a0) + th.vsb.v v4, (a0), v0.t + th.vsh.v v4, (a0) + th.vsh.v v4, 0(a0) + th.vsh.v v4, (a0), v0.t + th.vsw.v v4, (a0) + th.vsw.v v4, 0(a0) + th.vsw.v v4, (a0), v0.t + th.vse.v v4, (a0) + th.vse.v v4, 0(a0) + th.vse.v v4, (a0), v0.t + + th.vlsb.v v4, (a0), a1 + th.vlsb.v v4, 0(a0), a1 + th.vlsb.v v4, (a0), a1, v0.t + th.vlsh.v v4, (a0), a1 + th.vlsh.v v4, 0(a0), a1 + th.vlsh.v v4, (a0), a1, v0.t + th.vlsw.v v4, (a0), a1 + th.vlsw.v v4, 0(a0), a1 + th.vlsw.v v4, (a0), a1, v0.t + th.vlsbu.v v4, (a0), a1 + th.vlsbu.v v4, 0(a0), a1 + th.vlsbu.v v4, (a0), a1, v0.t + th.vlshu.v v4, (a0), a1 + th.vlshu.v v4, 0(a0), a1 + th.vlshu.v v4, (a0), a1, v0.t + th.vlswu.v v4, (a0), a1 + th.vlswu.v v4, 0(a0), a1 + th.vlswu.v v4, (a0), a1, v0.t + th.vlse.v v4, (a0), a1 + th.vlse.v v4, 0(a0), a1 + th.vlse.v v4, (a0), a1, v0.t + th.vssb.v v4, (a0), a1 + th.vssb.v v4, 0(a0), a1 + th.vssb.v v4, (a0), a1, v0.t + th.vssh.v v4, (a0), a1 + th.vssh.v v4, 0(a0), a1 + th.vssh.v v4, (a0), a1, v0.t + th.vssw.v v4, (a0), a1 + th.vssw.v v4, 0(a0), a1 + th.vssw.v v4, (a0), a1, v0.t + th.vsse.v v4, (a0), a1 + th.vsse.v v4, 0(a0), a1 + th.vsse.v v4, (a0), a1, v0.t + + th.vlxb.v v4, (a0), v12 + th.vlxb.v v4, 0(a0), v12 + th.vlxb.v v4, (a0), v12, v0.t + th.vlxh.v v4, (a0), v12 + th.vlxh.v v4, 0(a0), v12 + th.vlxh.v v4, (a0), v12, v0.t + th.vlxw.v v4, (a0), v12 + th.vlxw.v v4, 0(a0), v12 + th.vlxw.v v4, (a0), v12, v0.t + th.vlxbu.v v4, (a0), v12 + th.vlxbu.v v4, 0(a0), v12 + th.vlxbu.v v4, (a0), v12, v0.t + th.vlxhu.v v4, (a0), v12 + th.vlxhu.v v4, 0(a0), v12 + th.vlxhu.v v4, (a0), v12, v0.t + th.vlxwu.v v4, (a0), v12 + th.vlxwu.v v4, 0(a0), v12 + th.vlxwu.v v4, (a0), v12, v0.t + th.vlxe.v v4, (a0), v12 + th.vlxe.v v4, 0(a0), v12 + th.vlxe.v v4, (a0), v12, v0.t + th.vsxb.v v4, (a0), v12 + th.vsxb.v v4, 0(a0), v12 + th.vsxb.v v4, (a0), v12, v0.t + th.vsxh.v v4, (a0), v12 + th.vsxh.v v4, 0(a0), v12 + th.vsxh.v v4, (a0), v12, v0.t + th.vsxw.v v4, (a0), v12 + th.vsxw.v v4, 0(a0), v12 + th.vsxw.v v4, (a0), v12, v0.t + th.vsxe.v v4, (a0), v12 + th.vsxe.v v4, 0(a0), v12 + th.vsxe.v v4, (a0), v12, v0.t + th.vsuxb.v v4, (a0), v12 + th.vsuxb.v v4, 0(a0), v12 + th.vsuxb.v v4, (a0), v12, v0.t + th.vsuxh.v v4, (a0), v12 + th.vsuxh.v v4, 0(a0), v12 + th.vsuxh.v v4, (a0), v12, v0.t + th.vsuxw.v v4, (a0), v12 + th.vsuxw.v v4, 0(a0), v12 + th.vsuxw.v v4, (a0), v12, v0.t + th.vsuxe.v v4, (a0), v12 + th.vsuxe.v v4, 0(a0), v12 + th.vsuxe.v v4, (a0), v12, v0.t + + th.vlbff.v v4, (a0) + th.vlbff.v v4, 0(a0) + th.vlbff.v v4, (a0), v0.t + th.vlhff.v v4, (a0) + th.vlhff.v v4, 0(a0) + th.vlhff.v v4, (a0), v0.t + th.vlwff.v v4, (a0) + th.vlwff.v v4, 0(a0) + th.vlwff.v v4, (a0), v0.t + th.vlbuff.v v4, (a0) + th.vlbuff.v v4, 0(a0) + th.vlbuff.v v4, (a0), v0.t + th.vlhuff.v v4, (a0) + th.vlhuff.v v4, 0(a0) + th.vlhuff.v v4, (a0), v0.t + th.vlwuff.v v4, (a0) + th.vlwuff.v v4, 0(a0) + th.vlwuff.v v4, (a0), v0.t + th.vleff.v v4, (a0) + th.vleff.v v4, 0(a0) + th.vleff.v v4, (a0), v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index dc18dd9f04c..a0de7a59676 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2653,6 +2653,94 @@ #define MASK_TH_VSETVL 0xfe00707f #define MATCH_TH_VSETVLI 0x00007057 #define MASK_TH_VSETVLI 0x8000707f +#define MATCH_TH_VLBV 0x10000007 +#define MASK_TH_VLBV 0xfdf0707f +#define MATCH_TH_VLHV 0x10005007 +#define MASK_TH_VLHV 0xfdf0707f +#define MATCH_TH_VLWV 0x10006007 +#define MASK_TH_VLWV 0xfdf0707f +#define MATCH_TH_VLBUV 0x00000007 +#define MASK_TH_VLBUV 0xfdf0707f +#define MATCH_TH_VLHUV 0x00005007 +#define MASK_TH_VLHUV 0xfdf0707f +#define MATCH_TH_VLWUV 0x00006007 +#define MASK_TH_VLWUV 0xfdf0707f +#define MATCH_TH_VLEV 0x00007007 +#define MASK_TH_VLEV 0xfdf0707f +#define MATCH_TH_VSBV 0x00000027 +#define MASK_TH_VSBV 0xfdf0707f +#define MATCH_TH_VSHV 0x00005027 +#define MASK_TH_VSHV 0xfdf0707f +#define MATCH_TH_VSWV 0x00006027 +#define MASK_TH_VSWV 0xfdf0707f +#define MATCH_TH_VSEV 0x00007027 +#define MASK_TH_VSEV 0xfdf0707f +#define MATCH_TH_VLSBV 0x18000007 +#define MASK_TH_VLSBV 0xfc00707f +#define MATCH_TH_VLSHV 0x18005007 +#define MASK_TH_VLSHV 0xfc00707f +#define MATCH_TH_VLSWV 0x18006007 +#define MASK_TH_VLSWV 0xfc00707f +#define MATCH_TH_VLSBUV 0x08000007 +#define MASK_TH_VLSBUV 0xfc00707f +#define MATCH_TH_VLSHUV 0x08005007 +#define MASK_TH_VLSHUV 0xfc00707f +#define MATCH_TH_VLSWUV 0x08006007 +#define MASK_TH_VLSWUV 0xfc00707f +#define MATCH_TH_VLSEV 0x08007007 +#define MASK_TH_VLSEV 0xfc00707f +#define MATCH_TH_VSSBV 0x08000027 +#define MASK_TH_VSSBV 0xfc00707f +#define MATCH_TH_VSSHV 0x08005027 +#define MASK_TH_VSSHV 0xfc00707f +#define MATCH_TH_VSSWV 0x08006027 +#define MASK_TH_VSSWV 0xfc00707f +#define MATCH_TH_VSSEV 0x08007027 +#define MASK_TH_VSSEV 0xfc00707f +#define MATCH_TH_VLXBV 0x1c000007 +#define MASK_TH_VLXBV 0xfc00707f +#define MATCH_TH_VLXHV 0x1c005007 +#define MASK_TH_VLXHV 0xfc00707f +#define MATCH_TH_VLXWV 0x1c006007 +#define MASK_TH_VLXWV 0xfc00707f +#define MATCH_TH_VLXBUV 0x0c000007 +#define MASK_TH_VLXBUV 0xfc00707f +#define MATCH_TH_VLXHUV 0x0c005007 +#define MASK_TH_VLXHUV 0xfc00707f +#define MATCH_TH_VLXWUV 0x0c006007 +#define MASK_TH_VLXWUV 0xfc00707f +#define MATCH_TH_VLXEV 0x0c007007 +#define MASK_TH_VLXEV 0xfc00707f +#define MATCH_TH_VSXBV 0x0c000027 +#define MASK_TH_VSXBV 0xfc00707f +#define MATCH_TH_VSXHV 0x0c005027 +#define MASK_TH_VSXHV 0xfc00707f +#define MATCH_TH_VSXWV 0x0c006027 +#define MASK_TH_VSXWV 0xfc00707f +#define MATCH_TH_VSXEV 0x0c007027 +#define MASK_TH_VSXEV 0xfc00707f +#define MATCH_TH_VSUXBV 0x1c000027 +#define MASK_TH_VSUXBV 0xfc00707f +#define MATCH_TH_VSUXHV 0x1c005027 +#define MASK_TH_VSUXHV 0xfc00707f +#define MATCH_TH_VSUXWV 0x1c006027 +#define MASK_TH_VSUXWV 0xfc00707f +#define MATCH_TH_VSUXEV 0x1c007027 +#define MASK_TH_VSUXEV 0xfc00707f +#define MATCH_TH_VLBFFV 0x11000007 +#define MASK_TH_VLBFFV 0xfdf0707f +#define MATCH_TH_VLHFFV 0x11005007 +#define MASK_TH_VLHFFV 0xfdf0707f +#define MATCH_TH_VLWFFV 0x11006007 +#define MASK_TH_VLWFFV 0xfdf0707f +#define MATCH_TH_VLBUFFV 0x01000007 +#define MASK_TH_VLBUFFV 0xfdf0707f +#define MATCH_TH_VLHUFFV 0x01005007 +#define MASK_TH_VLHUFFV 0xfdf0707f +#define MATCH_TH_VLWUFFV 0x01006007 +#define MASK_TH_VLWUFFV 0xfdf0707f +#define MATCH_TH_VLEFFV 0x01007007 +#define MASK_TH_VLEFFV 0xfdf0707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 2fb7cf1e14a..05bdce449f4 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2237,6 +2237,50 @@ const struct riscv_opcode riscv_opcodes[] = /* Vendor-specific (T-Head) XTheadVector instructions. */ {"th.vsetvl", 0, INSN_CLASS_XTHEADVECTOR, "d,s,t", MATCH_TH_VSETVL, MASK_TH_VSETVL, match_opcode, 0}, {"th.vsetvli", 0, INSN_CLASS_XTHEADVECTOR, "d,s,Vc", MATCH_TH_VSETVLI, MASK_TH_VSETVLI, match_opcode, 0}, +{"th.vlb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLBV, MASK_TH_VLBV, match_opcode, INSN_DREF }, +{"th.vlh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLHV, MASK_TH_VLHV, match_opcode, INSN_DREF }, +{"th.vlw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLWV, MASK_TH_VLWV, match_opcode, INSN_DREF }, +{"th.vlbu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLBUV, MASK_TH_VLBUV, match_opcode, INSN_DREF }, +{"th.vlhu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLHUV, MASK_TH_VLHUV, match_opcode, INSN_DREF }, +{"th.vlwu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLWUV, MASK_TH_VLWUV, match_opcode, INSN_DREF }, +{"th.vle.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLEV, MASK_TH_VLEV, match_opcode, INSN_DREF }, +{"th.vsb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VSBV, MASK_TH_VSBV, match_opcode, INSN_DREF }, +{"th.vsh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VSHV, MASK_TH_VSHV, match_opcode, INSN_DREF }, +{"th.vsw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VSWV, MASK_TH_VSWV, match_opcode, INSN_DREF }, +{"th.vse.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VSEV, MASK_TH_VSEV, match_opcode, INSN_DREF }, +{"th.vlsb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSBV, MASK_TH_VLSBV, match_opcode, INSN_DREF }, +{"th.vlsh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSHV, MASK_TH_VLSHV, match_opcode, INSN_DREF }, +{"th.vlsw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSWV, MASK_TH_VLSWV, match_opcode, INSN_DREF }, +{"th.vlsbu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSBUV, MASK_TH_VLSBUV, match_opcode, INSN_DREF }, +{"th.vlshu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSHUV, MASK_TH_VLSHUV, match_opcode, INSN_DREF }, +{"th.vlswu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSWUV, MASK_TH_VLSWUV, match_opcode, INSN_DREF }, +{"th.vlse.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VLSEV, MASK_TH_VLSEV, match_opcode, INSN_DREF }, +{"th.vssb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VSSBV, MASK_TH_VSSBV, match_opcode, INSN_DREF }, +{"th.vssh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VSSHV, MASK_TH_VSSHV, match_opcode, INSN_DREF }, +{"th.vssw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VSSWV, MASK_TH_VSSWV, match_opcode, INSN_DREF }, +{"th.vsse.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VSSEV, MASK_TH_VSSEV, match_opcode, INSN_DREF }, +{"th.vlxb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXBV, MASK_TH_VLXBV, match_opcode, INSN_DREF }, +{"th.vlxh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXHV, MASK_TH_VLXHV, match_opcode, INSN_DREF }, +{"th.vlxw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXWV, MASK_TH_VLXWV, match_opcode, INSN_DREF }, +{"th.vlxbu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXBUV, MASK_TH_VLXBUV, match_opcode, INSN_DREF }, +{"th.vlxhu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXHUV, MASK_TH_VLXHUV, match_opcode, INSN_DREF }, +{"th.vlxwu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXWUV, MASK_TH_VLXWUV, match_opcode, INSN_DREF }, +{"th.vlxe.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VLXEV, MASK_TH_VLXEV, match_opcode, INSN_DREF }, +{"th.vsxb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VSXBV, MASK_TH_VSXBV, match_opcode, INSN_DREF }, +{"th.vsxh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VSXHV, MASK_TH_VSXHV, match_opcode, INSN_DREF }, +{"th.vsxw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VSXWV, MASK_TH_VSXWV, match_opcode, INSN_DREF }, +{"th.vsxe.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VSXEV, MASK_TH_VSXEV, match_opcode, INSN_DREF }, +{"th.vsuxb.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VSUXBV, MASK_TH_VSUXBV, match_opcode, INSN_DREF }, +{"th.vsuxh.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VSUXHV, MASK_TH_VSUXHV, match_opcode, INSN_DREF }, +{"th.vsuxw.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VSUXWV, MASK_TH_VSUXWV, match_opcode, INSN_DREF }, +{"th.vsuxe.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),VtVm", MATCH_TH_VSUXEV, MASK_TH_VSUXEV, match_opcode, INSN_DREF }, +{"th.vlbff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLBFFV, MASK_TH_VLBFFV, match_opcode, INSN_DREF }, +{"th.vlhff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLHFFV, MASK_TH_VLHFFV, match_opcode, INSN_DREF }, +{"th.vlwff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLWFFV, MASK_TH_VLWFFV, match_opcode, INSN_DREF }, +{"th.vlbuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLBUFFV, MASK_TH_VLBUFFV, match_opcode, INSN_DREF }, +{"th.vlhuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLHUFFV, MASK_TH_VLHUFFV, match_opcode, INSN_DREF }, +{"th.vlwuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLWUFFV, MASK_TH_VLWUFFV, match_opcode, INSN_DREF }, +{"th.vleff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLEFFV, MASK_TH_VLEFFV, match_opcode, INSN_DREF }, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, From patchwork Fri Nov 10 07:24:59 2023 Content-Type: text/plain; charset="utf-8" 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fp:SMTPD_---0Vw3jBTV_1699601112) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:25:15 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 05/12] RISC-V: Add the sub-extension "XTheadZvlsseg" for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:24:59 +0800 Message-Id: <20231110072459.1826-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.5 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the sub-extension "XTheadZvlsseg" for the "XTheadVector" extension, and it provides load/store segment instructions for T-Head VECTOR vendor extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add support for "XTheadZvlsseg" extensions. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector-zvlsseg.d: New test. * testsuite/gas/riscv/x-thead-vector-zvlsseg.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VLSEG2BV): New. * opcode/riscv.h (enum riscv_insn_class): Add insn class. opcodes/ChangeLog: * riscv-opc.c: Likewise. --- bfd/elfxx-riscv.c | 6 + gas/doc/c-riscv.texi | 6 + .../gas/riscv/x-thead-vector-zvlsseg.d | 849 +++++++++++++++++ .../gas/riscv/x-thead-vector-zvlsseg.s | 867 ++++++++++++++++++ include/opcode/riscv-opc.h | 560 +++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 280 ++++++ 7 files changed, 2569 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvlsseg.d create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvlsseg.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index e2c3ffe4b4f..2d2ab040674 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1199,6 +1199,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"ssstateen", "zicsr", check_implicit_always}, {"sstc", "zicsr", check_implicit_always}, {"svadu", "zicsr", check_implicit_always}, + {"xtheadvector", "xtheadzvlsseg", check_implicit_always}, {NULL, NULL, NULL} }; @@ -1374,6 +1375,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadvector", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadzvlsseg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2590,6 +2592,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadsync"); case INSN_CLASS_XTHEADVECTOR: return riscv_subset_supports (rps, "xtheadvector"); + case INSN_CLASS_XTHEADZVLSSEG: + return riscv_subset_supports (rps, "xtheadzvlsseg"); case INSN_CLASS_XVENTANACONDOPS: return riscv_subset_supports (rps, "xventanacondops"); default: @@ -2836,6 +2840,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadsync"; case INSN_CLASS_XTHEADVECTOR: return "xtheadvector"; + case INSN_CLASS_XTHEADZVLSSEG: + return "xtheadzvlsseg"; default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index a7c9420bd86..e47200faaf6 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -819,6 +819,12 @@ The XTheadVector extension provides instructions for thead vector. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}. +@item XTheadZvlsseg +The XTheadZvlsseg extension is a subextension of the XTheadVector extension, +and it provides load/store segment instructions for thead vector. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}. + @item XVentanaCondOps XVentanaCondOps extension provides instructions for branchless sequences that perform conditional arithmetic, conditional diff --git a/gas/testsuite/gas/riscv/x-thead-vector-zvlsseg.d b/gas/testsuite/gas/riscv/x-thead-vector-zvlsseg.d new file mode 100644 index 00000000000..0821b040a94 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-zvlsseg.d @@ -0,0 +1,849 @@ +#as: -march=rv32if_xtheadvector_xtheadzvlsseg +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+32050207[ 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th.vlseg2e.v v4, 0(a0) + th.vlseg2e.v v4, (a0), v0.t + th.vsseg2b.v v4, (a0) + th.vsseg2b.v v4, 0(a0) + th.vsseg2b.v v4, (a0), v0.t + th.vsseg2h.v v4, (a0) + th.vsseg2h.v v4, 0(a0) + th.vsseg2h.v v4, (a0), v0.t + th.vsseg2w.v v4, (a0) + th.vsseg2w.v v4, 0(a0) + th.vsseg2w.v v4, (a0), v0.t + th.vsseg2e.v v4, (a0) + th.vsseg2e.v v4, 0(a0) + th.vsseg2e.v v4, (a0), v0.t + + th.vlseg3b.v v4, (a0) + th.vlseg3b.v v4, 0(a0) + th.vlseg3b.v v4, (a0), v0.t + th.vlseg3h.v v4, (a0) + th.vlseg3h.v v4, 0(a0) + th.vlseg3h.v v4, (a0), v0.t + th.vlseg3w.v v4, (a0) + th.vlseg3w.v v4, 0(a0) + th.vlseg3w.v v4, (a0), v0.t + th.vlseg3bu.v v4, (a0) + th.vlseg3bu.v v4, 0(a0) + th.vlseg3bu.v v4, (a0), v0.t + th.vlseg3hu.v v4, (a0) + th.vlseg3hu.v v4, 0(a0) + th.vlseg3hu.v v4, (a0), v0.t + th.vlseg3wu.v v4, (a0) + th.vlseg3wu.v v4, 0(a0) + th.vlseg3wu.v v4, (a0), v0.t + th.vlseg3e.v v4, (a0) + th.vlseg3e.v v4, 0(a0) + th.vlseg3e.v v4, (a0), v0.t + th.vsseg3b.v v4, (a0) + th.vsseg3b.v v4, 0(a0) + th.vsseg3b.v v4, (a0), v0.t + th.vsseg3h.v v4, (a0) + th.vsseg3h.v v4, 0(a0) + th.vsseg3h.v v4, (a0), v0.t + th.vsseg3w.v v4, (a0) + th.vsseg3w.v v4, 0(a0) + th.vsseg3w.v v4, (a0), v0.t + th.vsseg3e.v v4, (a0) + th.vsseg3e.v v4, 0(a0) + th.vsseg3e.v v4, (a0), v0.t + + th.vlseg4b.v v4, (a0) + th.vlseg4b.v v4, 0(a0) + th.vlseg4b.v v4, (a0), v0.t + th.vlseg4h.v v4, (a0) + th.vlseg4h.v v4, 0(a0) + th.vlseg4h.v v4, (a0), v0.t + th.vlseg4w.v v4, (a0) + th.vlseg4w.v v4, 0(a0) + th.vlseg4w.v v4, (a0), v0.t + th.vlseg4bu.v v4, (a0) + th.vlseg4bu.v v4, 0(a0) + th.vlseg4bu.v v4, (a0), v0.t + th.vlseg4hu.v v4, (a0) + th.vlseg4hu.v v4, 0(a0) + th.vlseg4hu.v v4, (a0), v0.t + th.vlseg4wu.v v4, (a0) + th.vlseg4wu.v v4, 0(a0) + th.vlseg4wu.v v4, (a0), v0.t + th.vlseg4e.v v4, (a0) + th.vlseg4e.v v4, 0(a0) + th.vlseg4e.v v4, (a0), v0.t + th.vsseg4b.v v4, (a0) + th.vsseg4b.v v4, 0(a0) + th.vsseg4b.v v4, (a0), v0.t + th.vsseg4h.v v4, (a0) + th.vsseg4h.v v4, 0(a0) + th.vsseg4h.v v4, (a0), v0.t + th.vsseg4w.v v4, (a0) + th.vsseg4w.v v4, 0(a0) + th.vsseg4w.v v4, (a0), v0.t + th.vsseg4e.v v4, (a0) + th.vsseg4e.v v4, 0(a0) + th.vsseg4e.v v4, (a0), v0.t + + th.vlseg5b.v v4, (a0) + th.vlseg5b.v v4, 0(a0) + th.vlseg5b.v v4, (a0), v0.t + th.vlseg5h.v v4, (a0) + th.vlseg5h.v v4, 0(a0) + th.vlseg5h.v v4, (a0), v0.t + th.vlseg5w.v v4, (a0) + th.vlseg5w.v v4, 0(a0) + th.vlseg5w.v v4, (a0), v0.t + th.vlseg5bu.v v4, (a0) + th.vlseg5bu.v v4, 0(a0) + th.vlseg5bu.v v4, (a0), v0.t + th.vlseg5hu.v v4, (a0) + th.vlseg5hu.v v4, 0(a0) + th.vlseg5hu.v v4, (a0), v0.t + th.vlseg5wu.v v4, (a0) + th.vlseg5wu.v v4, 0(a0) + th.vlseg5wu.v v4, (a0), v0.t + th.vlseg5e.v v4, (a0) + th.vlseg5e.v v4, 0(a0) + th.vlseg5e.v v4, (a0), v0.t + th.vsseg5b.v v4, (a0) + th.vsseg5b.v v4, 0(a0) + th.vsseg5b.v v4, (a0), v0.t + th.vsseg5h.v v4, (a0) + th.vsseg5h.v v4, 0(a0) + th.vsseg5h.v v4, (a0), v0.t + th.vsseg5w.v v4, (a0) + th.vsseg5w.v v4, 0(a0) + th.vsseg5w.v v4, (a0), v0.t + th.vsseg5e.v v4, (a0) + th.vsseg5e.v v4, 0(a0) + th.vsseg5e.v v4, (a0), v0.t + + th.vlseg6b.v v4, (a0) + th.vlseg6b.v v4, 0(a0) + th.vlseg6b.v v4, (a0), v0.t + th.vlseg6h.v v4, (a0) + th.vlseg6h.v v4, 0(a0) + th.vlseg6h.v v4, (a0), v0.t + th.vlseg6w.v v4, (a0) + th.vlseg6w.v v4, 0(a0) + th.vlseg6w.v v4, (a0), v0.t + th.vlseg6bu.v v4, (a0) + th.vlseg6bu.v v4, 0(a0) + th.vlseg6bu.v v4, (a0), v0.t + th.vlseg6hu.v v4, (a0) + th.vlseg6hu.v v4, 0(a0) + th.vlseg6hu.v v4, (a0), v0.t + th.vlseg6wu.v v4, (a0) + th.vlseg6wu.v v4, 0(a0) + th.vlseg6wu.v v4, (a0), v0.t + th.vlseg6e.v v4, (a0) + th.vlseg6e.v v4, 0(a0) + th.vlseg6e.v v4, (a0), v0.t + th.vsseg6b.v v4, (a0) + th.vsseg6b.v v4, 0(a0) + th.vsseg6b.v v4, (a0), v0.t + th.vsseg6h.v v4, (a0) + th.vsseg6h.v v4, 0(a0) + th.vsseg6h.v v4, (a0), v0.t + th.vsseg6w.v v4, (a0) + th.vsseg6w.v v4, 0(a0) + th.vsseg6w.v v4, (a0), v0.t + th.vsseg6e.v v4, (a0) + th.vsseg6e.v v4, 0(a0) + th.vsseg6e.v v4, (a0), v0.t + + th.vlseg7b.v v4, (a0) + th.vlseg7b.v v4, 0(a0) + th.vlseg7b.v v4, (a0), v0.t + th.vlseg7h.v v4, (a0) + th.vlseg7h.v v4, 0(a0) + th.vlseg7h.v v4, (a0), v0.t + th.vlseg7w.v v4, (a0) + th.vlseg7w.v v4, 0(a0) + th.vlseg7w.v v4, (a0), v0.t + th.vlseg7bu.v v4, (a0) + th.vlseg7bu.v v4, 0(a0) + th.vlseg7bu.v v4, (a0), v0.t + th.vlseg7hu.v v4, (a0) + th.vlseg7hu.v v4, 0(a0) + th.vlseg7hu.v v4, (a0), v0.t + th.vlseg7wu.v v4, (a0) + th.vlseg7wu.v v4, 0(a0) + th.vlseg7wu.v v4, (a0), v0.t + th.vlseg7e.v v4, (a0) + th.vlseg7e.v v4, 0(a0) + th.vlseg7e.v v4, (a0), v0.t + th.vsseg7b.v v4, (a0) + th.vsseg7b.v v4, 0(a0) + th.vsseg7b.v v4, (a0), v0.t + th.vsseg7h.v v4, (a0) + th.vsseg7h.v v4, 0(a0) + th.vsseg7h.v v4, (a0), v0.t + th.vsseg7w.v v4, (a0) + th.vsseg7w.v v4, 0(a0) + th.vsseg7w.v v4, (a0), v0.t + th.vsseg7e.v v4, (a0) + th.vsseg7e.v v4, 0(a0) + th.vsseg7e.v v4, (a0), v0.t + + th.vlseg8b.v v4, (a0) + th.vlseg8b.v v4, 0(a0) + th.vlseg8b.v v4, (a0), v0.t + th.vlseg8h.v v4, (a0) + th.vlseg8h.v v4, 0(a0) + th.vlseg8h.v v4, (a0), v0.t + th.vlseg8w.v v4, (a0) + th.vlseg8w.v v4, 0(a0) + th.vlseg8w.v v4, (a0), v0.t + th.vlseg8bu.v v4, (a0) + th.vlseg8bu.v v4, 0(a0) + th.vlseg8bu.v v4, (a0), v0.t + th.vlseg8hu.v v4, (a0) + th.vlseg8hu.v v4, 0(a0) + th.vlseg8hu.v v4, (a0), v0.t + th.vlseg8wu.v v4, (a0) + th.vlseg8wu.v v4, 0(a0) + th.vlseg8wu.v v4, (a0), v0.t + th.vlseg8e.v v4, (a0) + th.vlseg8e.v v4, 0(a0) + th.vlseg8e.v v4, (a0), v0.t + th.vsseg8b.v v4, (a0) + th.vsseg8b.v v4, 0(a0) + th.vsseg8b.v v4, (a0), v0.t + th.vsseg8h.v v4, (a0) + th.vsseg8h.v v4, 0(a0) + th.vsseg8h.v v4, (a0), v0.t + th.vsseg8w.v v4, (a0) + th.vsseg8w.v v4, 0(a0) + th.vsseg8w.v v4, (a0), v0.t + th.vsseg8e.v v4, (a0) + th.vsseg8e.v v4, 0(a0) + th.vsseg8e.v v4, (a0), v0.t + + th.vlsseg2b.v v4, (a0), a1 + th.vlsseg2b.v v4, 0(a0), a1 + th.vlsseg2b.v v4, (a0), a1, v0.t + th.vlsseg2h.v v4, (a0), a1 + th.vlsseg2h.v v4, 0(a0), a1 + th.vlsseg2h.v v4, (a0), a1, v0.t + th.vlsseg2w.v v4, (a0), a1 + th.vlsseg2w.v v4, 0(a0), a1 + th.vlsseg2w.v v4, (a0), a1, v0.t + th.vlsseg2bu.v v4, (a0), a1 + th.vlsseg2bu.v v4, 0(a0), a1 + th.vlsseg2bu.v v4, (a0), a1, v0.t + th.vlsseg2hu.v v4, (a0), a1 + th.vlsseg2hu.v v4, 0(a0), a1 + th.vlsseg2hu.v v4, (a0), a1, v0.t + th.vlsseg2wu.v v4, (a0), a1 + th.vlsseg2wu.v v4, 0(a0), a1 + th.vlsseg2wu.v v4, (a0), a1, v0.t + th.vlsseg2e.v v4, (a0), a1 + th.vlsseg2e.v v4, 0(a0), a1 + th.vlsseg2e.v v4, (a0), a1, v0.t + th.vssseg2b.v v4, (a0), a1 + th.vssseg2b.v v4, 0(a0), a1 + th.vssseg2b.v v4, (a0), a1, v0.t + th.vssseg2h.v v4, (a0), a1 + th.vssseg2h.v v4, 0(a0), a1 + th.vssseg2h.v v4, (a0), a1, v0.t + th.vssseg2w.v v4, (a0), a1 + th.vssseg2w.v v4, 0(a0), a1 + th.vssseg2w.v v4, (a0), a1, v0.t + th.vssseg2e.v v4, (a0), a1 + th.vssseg2e.v v4, 0(a0), a1 + th.vssseg2e.v v4, (a0), a1, v0.t + + th.vlsseg3b.v v4, (a0), a1 + th.vlsseg3b.v v4, 0(a0), a1 + th.vlsseg3b.v v4, (a0), a1, v0.t + th.vlsseg3h.v v4, (a0), a1 + th.vlsseg3h.v v4, 0(a0), a1 + th.vlsseg3h.v v4, (a0), a1, v0.t + th.vlsseg3w.v v4, (a0), a1 + th.vlsseg3w.v v4, 0(a0), a1 + th.vlsseg3w.v v4, (a0), a1, v0.t + th.vlsseg3bu.v v4, (a0), a1 + th.vlsseg3bu.v v4, 0(a0), a1 + th.vlsseg3bu.v v4, (a0), a1, v0.t + th.vlsseg3hu.v v4, (a0), a1 + th.vlsseg3hu.v v4, 0(a0), a1 + th.vlsseg3hu.v v4, (a0), a1, v0.t + th.vlsseg3wu.v v4, (a0), a1 + th.vlsseg3wu.v v4, 0(a0), a1 + th.vlsseg3wu.v v4, (a0), a1, v0.t + th.vlsseg3e.v v4, (a0), a1 + th.vlsseg3e.v v4, 0(a0), a1 + th.vlsseg3e.v v4, (a0), a1, v0.t + th.vssseg3b.v v4, (a0), a1 + th.vssseg3b.v v4, 0(a0), a1 + th.vssseg3b.v v4, (a0), a1, v0.t + th.vssseg3h.v v4, (a0), a1 + th.vssseg3h.v v4, 0(a0), a1 + th.vssseg3h.v v4, (a0), a1, v0.t + th.vssseg3w.v v4, (a0), a1 + th.vssseg3w.v v4, 0(a0), a1 + th.vssseg3w.v v4, (a0), a1, v0.t + th.vssseg3e.v v4, (a0), a1 + th.vssseg3e.v v4, 0(a0), a1 + th.vssseg3e.v v4, (a0), a1, v0.t + + th.vlsseg4b.v v4, (a0), a1 + th.vlsseg4b.v v4, 0(a0), a1 + th.vlsseg4b.v v4, (a0), a1, v0.t + th.vlsseg4h.v v4, (a0), a1 + th.vlsseg4h.v v4, 0(a0), a1 + th.vlsseg4h.v v4, (a0), a1, v0.t + th.vlsseg4w.v v4, (a0), a1 + th.vlsseg4w.v v4, 0(a0), a1 + th.vlsseg4w.v v4, (a0), a1, v0.t + th.vlsseg4bu.v v4, (a0), a1 + th.vlsseg4bu.v v4, 0(a0), a1 + th.vlsseg4bu.v v4, (a0), a1, v0.t + th.vlsseg4hu.v v4, (a0), a1 + th.vlsseg4hu.v v4, 0(a0), a1 + th.vlsseg4hu.v v4, (a0), a1, v0.t + th.vlsseg4wu.v v4, (a0), a1 + th.vlsseg4wu.v v4, 0(a0), a1 + th.vlsseg4wu.v v4, (a0), a1, v0.t + th.vlsseg4e.v v4, (a0), a1 + th.vlsseg4e.v v4, 0(a0), a1 + th.vlsseg4e.v v4, (a0), a1, v0.t + th.vssseg4b.v v4, (a0), a1 + th.vssseg4b.v v4, 0(a0), a1 + th.vssseg4b.v v4, (a0), a1, v0.t + th.vssseg4h.v v4, (a0), a1 + th.vssseg4h.v v4, 0(a0), a1 + th.vssseg4h.v v4, (a0), a1, v0.t + th.vssseg4w.v v4, (a0), a1 + th.vssseg4w.v v4, 0(a0), a1 + th.vssseg4w.v v4, (a0), a1, v0.t + th.vssseg4e.v v4, (a0), a1 + th.vssseg4e.v v4, 0(a0), a1 + th.vssseg4e.v v4, (a0), a1, v0.t + + th.vlsseg5b.v v4, (a0), a1 + th.vlsseg5b.v v4, 0(a0), a1 + th.vlsseg5b.v v4, (a0), a1, v0.t + th.vlsseg5h.v v4, (a0), a1 + th.vlsseg5h.v v4, 0(a0), a1 + th.vlsseg5h.v v4, (a0), a1, v0.t + th.vlsseg5w.v v4, (a0), a1 + th.vlsseg5w.v v4, 0(a0), a1 + th.vlsseg5w.v v4, (a0), a1, v0.t + th.vlsseg5bu.v v4, (a0), a1 + th.vlsseg5bu.v v4, 0(a0), a1 + th.vlsseg5bu.v v4, (a0), a1, v0.t + th.vlsseg5hu.v v4, (a0), a1 + th.vlsseg5hu.v v4, 0(a0), a1 + th.vlsseg5hu.v v4, (a0), a1, v0.t + th.vlsseg5wu.v v4, (a0), a1 + th.vlsseg5wu.v v4, 0(a0), a1 + th.vlsseg5wu.v v4, (a0), a1, v0.t + th.vlsseg5e.v v4, (a0), a1 + th.vlsseg5e.v v4, 0(a0), a1 + th.vlsseg5e.v v4, (a0), a1, v0.t + th.vssseg5b.v v4, (a0), a1 + th.vssseg5b.v v4, 0(a0), a1 + th.vssseg5b.v v4, (a0), a1, v0.t + th.vssseg5h.v v4, (a0), a1 + th.vssseg5h.v v4, 0(a0), a1 + th.vssseg5h.v v4, (a0), a1, v0.t + th.vssseg5w.v v4, (a0), a1 + th.vssseg5w.v v4, 0(a0), a1 + th.vssseg5w.v v4, (a0), a1, v0.t + th.vssseg5e.v v4, (a0), a1 + th.vssseg5e.v v4, 0(a0), a1 + th.vssseg5e.v v4, (a0), a1, v0.t + + th.vlsseg6b.v v4, (a0), a1 + th.vlsseg6b.v v4, 0(a0), a1 + th.vlsseg6b.v v4, (a0), a1, v0.t + th.vlsseg6h.v v4, (a0), a1 + th.vlsseg6h.v v4, 0(a0), a1 + th.vlsseg6h.v v4, (a0), a1, v0.t + th.vlsseg6w.v v4, (a0), a1 + th.vlsseg6w.v v4, 0(a0), a1 + th.vlsseg6w.v v4, (a0), a1, v0.t + th.vlsseg6bu.v v4, (a0), a1 + th.vlsseg6bu.v v4, 0(a0), a1 + th.vlsseg6bu.v v4, (a0), a1, v0.t + th.vlsseg6hu.v v4, (a0), a1 + th.vlsseg6hu.v v4, 0(a0), a1 + th.vlsseg6hu.v v4, (a0), a1, v0.t + th.vlsseg6wu.v v4, (a0), a1 + th.vlsseg6wu.v v4, 0(a0), a1 + th.vlsseg6wu.v v4, (a0), a1, v0.t + th.vlsseg6e.v v4, (a0), a1 + th.vlsseg6e.v v4, 0(a0), a1 + th.vlsseg6e.v v4, (a0), a1, v0.t + th.vssseg6b.v v4, (a0), a1 + th.vssseg6b.v v4, 0(a0), a1 + th.vssseg6b.v v4, (a0), a1, v0.t + th.vssseg6h.v v4, (a0), a1 + th.vssseg6h.v v4, 0(a0), a1 + th.vssseg6h.v v4, (a0), a1, v0.t + th.vssseg6w.v v4, (a0), a1 + th.vssseg6w.v v4, 0(a0), a1 + th.vssseg6w.v v4, (a0), a1, v0.t + th.vssseg6e.v v4, (a0), a1 + th.vssseg6e.v v4, 0(a0), a1 + th.vssseg6e.v v4, (a0), a1, v0.t + + th.vlsseg7b.v v4, (a0), a1 + th.vlsseg7b.v v4, 0(a0), a1 + th.vlsseg7b.v v4, (a0), a1, v0.t + th.vlsseg7h.v v4, (a0), a1 + th.vlsseg7h.v v4, 0(a0), a1 + th.vlsseg7h.v v4, (a0), a1, v0.t + th.vlsseg7w.v v4, (a0), a1 + th.vlsseg7w.v v4, 0(a0), a1 + th.vlsseg7w.v v4, (a0), a1, v0.t + th.vlsseg7bu.v v4, (a0), a1 + th.vlsseg7bu.v v4, 0(a0), a1 + th.vlsseg7bu.v v4, (a0), a1, v0.t + th.vlsseg7hu.v v4, (a0), a1 + th.vlsseg7hu.v v4, 0(a0), a1 + th.vlsseg7hu.v v4, (a0), a1, v0.t + th.vlsseg7wu.v v4, (a0), a1 + th.vlsseg7wu.v v4, 0(a0), a1 + th.vlsseg7wu.v v4, (a0), a1, v0.t + th.vlsseg7e.v v4, (a0), a1 + th.vlsseg7e.v v4, 0(a0), a1 + th.vlsseg7e.v v4, (a0), a1, v0.t + th.vssseg7b.v v4, (a0), a1 + th.vssseg7b.v v4, 0(a0), a1 + th.vssseg7b.v v4, (a0), a1, v0.t + th.vssseg7h.v v4, (a0), a1 + th.vssseg7h.v v4, 0(a0), a1 + th.vssseg7h.v v4, (a0), a1, v0.t + th.vssseg7w.v v4, (a0), a1 + th.vssseg7w.v v4, 0(a0), a1 + th.vssseg7w.v v4, (a0), a1, v0.t + th.vssseg7e.v v4, (a0), a1 + th.vssseg7e.v v4, 0(a0), a1 + th.vssseg7e.v v4, (a0), a1, v0.t + + th.vlsseg8b.v v4, (a0), a1 + th.vlsseg8b.v v4, 0(a0), a1 + th.vlsseg8b.v v4, (a0), a1, v0.t + th.vlsseg8h.v v4, (a0), a1 + th.vlsseg8h.v v4, 0(a0), a1 + th.vlsseg8h.v v4, (a0), a1, v0.t + th.vlsseg8w.v v4, (a0), a1 + th.vlsseg8w.v v4, 0(a0), a1 + th.vlsseg8w.v v4, (a0), a1, v0.t + th.vlsseg8bu.v v4, (a0), a1 + th.vlsseg8bu.v v4, 0(a0), a1 + th.vlsseg8bu.v v4, (a0), a1, v0.t + th.vlsseg8hu.v v4, (a0), a1 + th.vlsseg8hu.v v4, 0(a0), a1 + th.vlsseg8hu.v v4, (a0), a1, v0.t + th.vlsseg8wu.v v4, (a0), a1 + th.vlsseg8wu.v v4, 0(a0), a1 + th.vlsseg8wu.v v4, (a0), a1, v0.t + th.vlsseg8e.v v4, (a0), a1 + th.vlsseg8e.v v4, 0(a0), a1 + th.vlsseg8e.v v4, (a0), a1, v0.t + th.vssseg8b.v v4, (a0), a1 + th.vssseg8b.v v4, 0(a0), a1 + th.vssseg8b.v v4, (a0), a1, v0.t + th.vssseg8h.v v4, (a0), a1 + th.vssseg8h.v v4, 0(a0), a1 + th.vssseg8h.v v4, (a0), a1, v0.t + th.vssseg8w.v v4, (a0), a1 + th.vssseg8w.v v4, 0(a0), a1 + th.vssseg8w.v v4, (a0), a1, v0.t + th.vssseg8e.v v4, (a0), a1 + th.vssseg8e.v v4, 0(a0), a1 + th.vssseg8e.v v4, (a0), a1, v0.t + + th.vlxseg2b.v v4, (a0), v12 + th.vlxseg2b.v v4, 0(a0), v12 + th.vlxseg2b.v v4, (a0), v12, v0.t + th.vlxseg2h.v v4, (a0), v12 + th.vlxseg2h.v v4, 0(a0), v12 + th.vlxseg2h.v v4, (a0), v12, v0.t + th.vlxseg2w.v v4, (a0), v12 + th.vlxseg2w.v v4, 0(a0), v12 + th.vlxseg2w.v v4, (a0), v12, v0.t + th.vlxseg2bu.v v4, (a0), v12 + th.vlxseg2bu.v v4, 0(a0), v12 + th.vlxseg2bu.v v4, (a0), v12, v0.t + th.vlxseg2hu.v v4, (a0), v12 + th.vlxseg2hu.v v4, 0(a0), v12 + th.vlxseg2hu.v v4, (a0), v12, v0.t + th.vlxseg2wu.v v4, (a0), v12 + th.vlxseg2wu.v v4, 0(a0), v12 + th.vlxseg2wu.v v4, (a0), v12, v0.t + th.vlxseg2e.v v4, (a0), v12 + th.vlxseg2e.v v4, 0(a0), v12 + th.vlxseg2e.v v4, (a0), v12, v0.t + th.vsxseg2b.v v4, (a0), v12 + th.vsxseg2b.v v4, 0(a0), v12 + th.vsxseg2b.v v4, (a0), v12, v0.t + th.vsxseg2h.v v4, (a0), v12 + th.vsxseg2h.v v4, 0(a0), v12 + th.vsxseg2h.v v4, (a0), v12, v0.t + th.vsxseg2w.v v4, (a0), v12 + th.vsxseg2w.v v4, 0(a0), v12 + th.vsxseg2w.v v4, (a0), v12, v0.t + th.vsxseg2e.v v4, (a0), v12 + th.vsxseg2e.v v4, 0(a0), v12 + th.vsxseg2e.v v4, (a0), v12, v0.t + + th.vlxseg3b.v v4, (a0), v12 + th.vlxseg3b.v v4, 0(a0), v12 + th.vlxseg3b.v v4, (a0), v12, v0.t + th.vlxseg3h.v v4, (a0), v12 + th.vlxseg3h.v v4, 0(a0), v12 + th.vlxseg3h.v v4, (a0), v12, v0.t + th.vlxseg3w.v v4, (a0), v12 + th.vlxseg3w.v v4, 0(a0), v12 + th.vlxseg3w.v v4, (a0), v12, v0.t + th.vlxseg3bu.v v4, (a0), v12 + th.vlxseg3bu.v v4, 0(a0), v12 + th.vlxseg3bu.v v4, (a0), v12, v0.t + th.vlxseg3hu.v v4, (a0), v12 + th.vlxseg3hu.v v4, 0(a0), v12 + th.vlxseg3hu.v v4, (a0), v12, v0.t + th.vlxseg3wu.v v4, (a0), v12 + th.vlxseg3wu.v v4, 0(a0), v12 + th.vlxseg3wu.v v4, (a0), v12, v0.t + th.vlxseg3e.v v4, (a0), v12 + th.vlxseg3e.v v4, 0(a0), v12 + th.vlxseg3e.v v4, (a0), v12, v0.t + th.vsxseg3b.v v4, (a0), v12 + th.vsxseg3b.v v4, 0(a0), v12 + th.vsxseg3b.v v4, (a0), v12, v0.t + th.vsxseg3h.v v4, (a0), v12 + th.vsxseg3h.v v4, 0(a0), v12 + th.vsxseg3h.v v4, (a0), v12, v0.t + th.vsxseg3w.v v4, (a0), v12 + th.vsxseg3w.v v4, 0(a0), v12 + th.vsxseg3w.v v4, (a0), v12, v0.t + th.vsxseg3e.v v4, (a0), v12 + th.vsxseg3e.v v4, 0(a0), v12 + th.vsxseg3e.v v4, (a0), v12, v0.t + + th.vlxseg4b.v v4, (a0), v12 + th.vlxseg4b.v v4, 0(a0), v12 + th.vlxseg4b.v v4, (a0), v12, v0.t + th.vlxseg4h.v v4, (a0), v12 + th.vlxseg4h.v v4, 0(a0), v12 + th.vlxseg4h.v v4, (a0), v12, v0.t + th.vlxseg4w.v v4, (a0), v12 + th.vlxseg4w.v v4, 0(a0), v12 + th.vlxseg4w.v v4, (a0), v12, v0.t + th.vlxseg4bu.v v4, (a0), v12 + th.vlxseg4bu.v v4, 0(a0), v12 + th.vlxseg4bu.v v4, (a0), v12, v0.t + th.vlxseg4hu.v v4, (a0), v12 + th.vlxseg4hu.v v4, 0(a0), v12 + th.vlxseg4hu.v v4, (a0), v12, v0.t + th.vlxseg4wu.v v4, (a0), v12 + th.vlxseg4wu.v v4, 0(a0), v12 + th.vlxseg4wu.v v4, (a0), v12, v0.t + th.vlxseg4e.v v4, (a0), v12 + th.vlxseg4e.v v4, 0(a0), v12 + th.vlxseg4e.v v4, (a0), v12, v0.t + th.vsxseg4b.v v4, (a0), v12 + th.vsxseg4b.v v4, 0(a0), v12 + th.vsxseg4b.v v4, (a0), v12, v0.t + th.vsxseg4h.v v4, (a0), v12 + th.vsxseg4h.v v4, 0(a0), v12 + th.vsxseg4h.v v4, (a0), v12, v0.t + th.vsxseg4w.v v4, (a0), v12 + th.vsxseg4w.v v4, 0(a0), v12 + th.vsxseg4w.v v4, (a0), v12, v0.t + th.vsxseg4e.v v4, (a0), v12 + th.vsxseg4e.v v4, 0(a0), v12 + th.vsxseg4e.v v4, (a0), v12, v0.t + + th.vlxseg5b.v v4, (a0), v12 + th.vlxseg5b.v v4, 0(a0), v12 + th.vlxseg5b.v v4, (a0), v12, v0.t + th.vlxseg5h.v v4, (a0), v12 + th.vlxseg5h.v v4, 0(a0), v12 + th.vlxseg5h.v v4, (a0), v12, v0.t + th.vlxseg5w.v v4, (a0), v12 + th.vlxseg5w.v v4, 0(a0), v12 + th.vlxseg5w.v v4, (a0), v12, v0.t + th.vlxseg5bu.v v4, (a0), v12 + th.vlxseg5bu.v v4, 0(a0), v12 + th.vlxseg5bu.v v4, (a0), v12, v0.t + th.vlxseg5hu.v v4, (a0), v12 + th.vlxseg5hu.v v4, 0(a0), v12 + th.vlxseg5hu.v v4, (a0), v12, v0.t + th.vlxseg5wu.v v4, (a0), v12 + th.vlxseg5wu.v v4, 0(a0), v12 + th.vlxseg5wu.v v4, (a0), v12, v0.t + th.vlxseg5e.v v4, (a0), v12 + th.vlxseg5e.v v4, 0(a0), v12 + th.vlxseg5e.v v4, (a0), v12, v0.t + th.vsxseg5b.v v4, (a0), v12 + th.vsxseg5b.v v4, 0(a0), v12 + th.vsxseg5b.v v4, (a0), v12, v0.t + th.vsxseg5h.v v4, (a0), v12 + th.vsxseg5h.v v4, 0(a0), v12 + th.vsxseg5h.v v4, (a0), v12, v0.t + th.vsxseg5w.v v4, (a0), v12 + th.vsxseg5w.v v4, 0(a0), v12 + th.vsxseg5w.v v4, (a0), v12, v0.t + th.vsxseg5e.v v4, (a0), v12 + th.vsxseg5e.v v4, 0(a0), v12 + th.vsxseg5e.v v4, (a0), v12, v0.t + + th.vlxseg6b.v v4, (a0), v12 + th.vlxseg6b.v v4, 0(a0), v12 + th.vlxseg6b.v v4, (a0), v12, v0.t + th.vlxseg6h.v v4, (a0), v12 + th.vlxseg6h.v v4, 0(a0), v12 + th.vlxseg6h.v v4, (a0), v12, v0.t + th.vlxseg6w.v v4, (a0), v12 + th.vlxseg6w.v v4, 0(a0), v12 + th.vlxseg6w.v v4, (a0), v12, v0.t + th.vlxseg6bu.v v4, (a0), v12 + th.vlxseg6bu.v v4, 0(a0), v12 + th.vlxseg6bu.v v4, (a0), v12, v0.t + th.vlxseg6hu.v v4, (a0), v12 + th.vlxseg6hu.v v4, 0(a0), v12 + th.vlxseg6hu.v v4, (a0), v12, v0.t + th.vlxseg6wu.v v4, (a0), v12 + th.vlxseg6wu.v v4, 0(a0), v12 + th.vlxseg6wu.v v4, (a0), v12, v0.t + th.vlxseg6e.v v4, (a0), v12 + th.vlxseg6e.v v4, 0(a0), v12 + th.vlxseg6e.v v4, (a0), v12, v0.t + th.vsxseg6b.v v4, (a0), v12 + th.vsxseg6b.v v4, 0(a0), v12 + th.vsxseg6b.v v4, (a0), v12, v0.t + th.vsxseg6h.v v4, (a0), v12 + th.vsxseg6h.v v4, 0(a0), v12 + th.vsxseg6h.v v4, (a0), v12, v0.t + th.vsxseg6w.v v4, (a0), v12 + th.vsxseg6w.v v4, 0(a0), v12 + th.vsxseg6w.v v4, (a0), v12, v0.t + th.vsxseg6e.v v4, (a0), v12 + th.vsxseg6e.v v4, 0(a0), v12 + th.vsxseg6e.v v4, (a0), v12, v0.t + + th.vlxseg7b.v v4, (a0), v12 + th.vlxseg7b.v v4, 0(a0), v12 + th.vlxseg7b.v v4, (a0), v12, v0.t + th.vlxseg7h.v v4, (a0), v12 + th.vlxseg7h.v v4, 0(a0), v12 + th.vlxseg7h.v v4, (a0), v12, v0.t + th.vlxseg7w.v v4, (a0), v12 + th.vlxseg7w.v v4, 0(a0), v12 + th.vlxseg7w.v v4, (a0), v12, v0.t + th.vlxseg7bu.v v4, (a0), v12 + th.vlxseg7bu.v v4, 0(a0), v12 + th.vlxseg7bu.v v4, (a0), v12, v0.t + th.vlxseg7hu.v v4, (a0), v12 + th.vlxseg7hu.v v4, 0(a0), v12 + th.vlxseg7hu.v v4, (a0), v12, v0.t + th.vlxseg7wu.v v4, (a0), v12 + th.vlxseg7wu.v v4, 0(a0), v12 + th.vlxseg7wu.v v4, (a0), v12, v0.t + th.vlxseg7e.v v4, (a0), v12 + th.vlxseg7e.v v4, 0(a0), v12 + th.vlxseg7e.v v4, (a0), v12, v0.t + th.vsxseg7b.v v4, (a0), v12 + th.vsxseg7b.v v4, 0(a0), v12 + th.vsxseg7b.v v4, (a0), v12, v0.t + th.vsxseg7h.v v4, (a0), v12 + th.vsxseg7h.v v4, 0(a0), v12 + th.vsxseg7h.v v4, (a0), v12, v0.t + th.vsxseg7w.v v4, (a0), v12 + th.vsxseg7w.v v4, 0(a0), v12 + th.vsxseg7w.v v4, (a0), v12, v0.t + th.vsxseg7e.v v4, (a0), v12 + th.vsxseg7e.v v4, 0(a0), v12 + th.vsxseg7e.v v4, (a0), v12, v0.t + + th.vlxseg8b.v v4, (a0), v12 + th.vlxseg8b.v v4, 0(a0), v12 + th.vlxseg8b.v v4, (a0), v12, v0.t + th.vlxseg8h.v v4, (a0), v12 + th.vlxseg8h.v v4, 0(a0), v12 + th.vlxseg8h.v v4, (a0), v12, v0.t + th.vlxseg8w.v v4, (a0), v12 + th.vlxseg8w.v v4, 0(a0), v12 + th.vlxseg8w.v v4, (a0), v12, v0.t + th.vlxseg8bu.v v4, (a0), v12 + th.vlxseg8bu.v v4, 0(a0), v12 + th.vlxseg8bu.v v4, (a0), v12, v0.t + th.vlxseg8hu.v v4, (a0), v12 + th.vlxseg8hu.v v4, 0(a0), v12 + th.vlxseg8hu.v v4, (a0), v12, v0.t + th.vlxseg8wu.v v4, (a0), v12 + th.vlxseg8wu.v v4, 0(a0), v12 + th.vlxseg8wu.v v4, (a0), v12, v0.t + th.vlxseg8e.v v4, (a0), v12 + th.vlxseg8e.v v4, 0(a0), v12 + th.vlxseg8e.v v4, (a0), v12, v0.t + th.vsxseg8b.v v4, (a0), v12 + th.vsxseg8b.v v4, 0(a0), v12 + th.vsxseg8b.v v4, (a0), v12, v0.t + th.vsxseg8h.v v4, (a0), v12 + th.vsxseg8h.v v4, 0(a0), v12 + th.vsxseg8h.v v4, (a0), v12, v0.t + th.vsxseg8w.v v4, (a0), v12 + th.vsxseg8w.v v4, 0(a0), v12 + th.vsxseg8w.v v4, (a0), v12, v0.t + th.vsxseg8e.v v4, (a0), v12 + th.vsxseg8e.v v4, 0(a0), v12 + th.vsxseg8e.v v4, (a0), v12, v0.t + + th.vlseg2bff.v v4, (a0) + th.vlseg2bff.v v4, 0(a0) + th.vlseg2bff.v v4, (a0), v0.t + th.vlseg2hff.v v4, (a0) + th.vlseg2hff.v v4, 0(a0) + th.vlseg2hff.v v4, (a0), v0.t + th.vlseg2wff.v v4, (a0) + th.vlseg2wff.v v4, 0(a0) + th.vlseg2wff.v v4, (a0), v0.t + th.vlseg2buff.v v4, (a0) + th.vlseg2buff.v v4, 0(a0) + th.vlseg2buff.v v4, (a0), v0.t + th.vlseg2huff.v v4, (a0) + th.vlseg2huff.v v4, 0(a0) + th.vlseg2huff.v v4, (a0), v0.t + th.vlseg2wuff.v v4, (a0) + th.vlseg2wuff.v v4, 0(a0) + th.vlseg2wuff.v v4, (a0), v0.t + th.vlseg2eff.v v4, (a0) + th.vlseg2eff.v v4, 0(a0) + th.vlseg2eff.v v4, (a0), v0.t + + th.vlseg3bff.v v4, (a0) + th.vlseg3bff.v v4, 0(a0) + th.vlseg3bff.v v4, (a0), v0.t + th.vlseg3hff.v v4, (a0) + th.vlseg3hff.v v4, 0(a0) + th.vlseg3hff.v v4, (a0), v0.t + th.vlseg3wff.v v4, (a0) + th.vlseg3wff.v v4, 0(a0) + th.vlseg3wff.v v4, (a0), v0.t + th.vlseg3buff.v v4, (a0) + th.vlseg3buff.v v4, 0(a0) + th.vlseg3buff.v v4, (a0), v0.t + th.vlseg3huff.v v4, (a0) + th.vlseg3huff.v v4, 0(a0) + th.vlseg3huff.v v4, (a0), v0.t + th.vlseg3wuff.v v4, (a0) + th.vlseg3wuff.v v4, 0(a0) + th.vlseg3wuff.v v4, (a0), v0.t + th.vlseg3eff.v v4, (a0) + th.vlseg3eff.v v4, 0(a0) + th.vlseg3eff.v v4, (a0), v0.t + + th.vlseg4bff.v v4, (a0) + th.vlseg4bff.v v4, 0(a0) + th.vlseg4bff.v v4, (a0), v0.t + th.vlseg4hff.v v4, (a0) + th.vlseg4hff.v v4, 0(a0) + th.vlseg4hff.v v4, (a0), v0.t + th.vlseg4wff.v v4, (a0) + th.vlseg4wff.v v4, 0(a0) + th.vlseg4wff.v v4, (a0), v0.t + th.vlseg4buff.v v4, (a0) + th.vlseg4buff.v v4, 0(a0) + th.vlseg4buff.v v4, (a0), v0.t + th.vlseg4huff.v v4, (a0) + th.vlseg4huff.v v4, 0(a0) + th.vlseg4huff.v v4, (a0), v0.t + th.vlseg4wuff.v v4, (a0) + th.vlseg4wuff.v v4, 0(a0) + th.vlseg4wuff.v v4, (a0), v0.t + th.vlseg4eff.v v4, (a0) + th.vlseg4eff.v v4, 0(a0) + th.vlseg4eff.v v4, (a0), v0.t + + th.vlseg5bff.v v4, (a0) + th.vlseg5bff.v v4, 0(a0) + th.vlseg5bff.v v4, (a0), v0.t + th.vlseg5hff.v v4, (a0) + th.vlseg5hff.v v4, 0(a0) + th.vlseg5hff.v v4, (a0), v0.t + th.vlseg5wff.v v4, (a0) + th.vlseg5wff.v v4, 0(a0) + th.vlseg5wff.v v4, (a0), v0.t + th.vlseg5buff.v v4, (a0) + th.vlseg5buff.v v4, 0(a0) + th.vlseg5buff.v v4, (a0), v0.t + th.vlseg5huff.v v4, (a0) + th.vlseg5huff.v v4, 0(a0) + th.vlseg5huff.v v4, (a0), v0.t + th.vlseg5wuff.v v4, (a0) + th.vlseg5wuff.v v4, 0(a0) + th.vlseg5wuff.v v4, (a0), v0.t + th.vlseg5eff.v v4, (a0) + th.vlseg5eff.v v4, 0(a0) + th.vlseg5eff.v v4, (a0), v0.t + + th.vlseg6bff.v v4, (a0) + th.vlseg6bff.v v4, 0(a0) + th.vlseg6bff.v v4, (a0), v0.t + th.vlseg6hff.v v4, (a0) + th.vlseg6hff.v v4, 0(a0) + th.vlseg6hff.v v4, (a0), v0.t + th.vlseg6wff.v v4, (a0) + th.vlseg6wff.v v4, 0(a0) + th.vlseg6wff.v v4, (a0), v0.t + th.vlseg6buff.v v4, (a0) + th.vlseg6buff.v v4, 0(a0) + th.vlseg6buff.v v4, (a0), v0.t + th.vlseg6huff.v v4, (a0) + th.vlseg6huff.v v4, 0(a0) + th.vlseg6huff.v v4, (a0), v0.t + th.vlseg6wuff.v v4, (a0) + th.vlseg6wuff.v v4, 0(a0) + th.vlseg6wuff.v v4, (a0), v0.t + th.vlseg6eff.v v4, (a0) + th.vlseg6eff.v v4, 0(a0) + th.vlseg6eff.v v4, (a0), v0.t + + th.vlseg7bff.v v4, (a0) + th.vlseg7bff.v v4, 0(a0) + th.vlseg7bff.v v4, (a0), v0.t + th.vlseg7hff.v v4, (a0) + th.vlseg7hff.v v4, 0(a0) + th.vlseg7hff.v v4, (a0), v0.t + th.vlseg7wff.v v4, (a0) + th.vlseg7wff.v v4, 0(a0) + th.vlseg7wff.v v4, (a0), v0.t + th.vlseg7buff.v v4, (a0) + th.vlseg7buff.v v4, 0(a0) + th.vlseg7buff.v v4, (a0), v0.t + th.vlseg7huff.v v4, (a0) + th.vlseg7huff.v v4, 0(a0) + th.vlseg7huff.v v4, (a0), v0.t + th.vlseg7wuff.v v4, (a0) + th.vlseg7wuff.v v4, 0(a0) + th.vlseg7wuff.v v4, (a0), v0.t + th.vlseg7eff.v v4, (a0) + th.vlseg7eff.v v4, 0(a0) + th.vlseg7eff.v v4, (a0), v0.t + + th.vlseg8bff.v v4, (a0) + th.vlseg8bff.v v4, 0(a0) + th.vlseg8bff.v v4, (a0), v0.t + th.vlseg8hff.v v4, (a0) + th.vlseg8hff.v v4, 0(a0) + th.vlseg8hff.v v4, (a0), v0.t + th.vlseg8wff.v v4, (a0) + th.vlseg8wff.v v4, 0(a0) + th.vlseg8wff.v v4, (a0), v0.t + th.vlseg8buff.v v4, (a0) + th.vlseg8buff.v v4, 0(a0) + th.vlseg8buff.v v4, (a0), v0.t + th.vlseg8huff.v v4, (a0) + th.vlseg8huff.v v4, 0(a0) + th.vlseg8huff.v v4, (a0), v0.t + th.vlseg8wuff.v v4, (a0) + th.vlseg8wuff.v v4, 0(a0) + th.vlseg8wuff.v v4, (a0), v0.t + th.vlseg8eff.v v4, (a0) + th.vlseg8eff.v v4, 0(a0) + th.vlseg8eff.v v4, (a0), v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index a0de7a59676..c1f94f484d8 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2741,6 +2741,566 @@ #define MASK_TH_VLWUFFV 0xfdf0707f #define MATCH_TH_VLEFFV 0x01007007 #define MASK_TH_VLEFFV 0xfdf0707f +#define MATCH_TH_VLSEG2BV 0x30000007 +#define MASK_TH_VLSEG2BV 0xfdf0707f +#define MATCH_TH_VLSEG2HV 0x30005007 +#define MASK_TH_VLSEG2HV 0xfdf0707f +#define MATCH_TH_VLSEG2WV 0x30006007 +#define MASK_TH_VLSEG2WV 0xfdf0707f +#define MATCH_TH_VLSEG2BUV 0x20000007 +#define MASK_TH_VLSEG2BUV 0xfdf0707f +#define MATCH_TH_VLSEG2HUV 0x20005007 +#define MASK_TH_VLSEG2HUV 0xfdf0707f +#define MATCH_TH_VLSEG2WUV 0x20006007 +#define MASK_TH_VLSEG2WUV 0xfdf0707f +#define MATCH_TH_VLSEG2EV 0x20007007 +#define MASK_TH_VLSEG2EV 0xfdf0707f +#define MATCH_TH_VSSEG2BV 0x20000027 +#define MASK_TH_VSSEG2BV 0xfdf0707f +#define MATCH_TH_VSSEG2HV 0x20005027 +#define MASK_TH_VSSEG2HV 0xfdf0707f +#define MATCH_TH_VSSEG2WV 0x20006027 +#define MASK_TH_VSSEG2WV 0xfdf0707f +#define MATCH_TH_VSSEG2EV 0x20007027 +#define MASK_TH_VSSEG2EV 0xfdf0707f +#define MATCH_TH_VLSEG3BV 0x50000007 +#define MASK_TH_VLSEG3BV 0xfdf0707f +#define MATCH_TH_VLSEG3HV 0x50005007 +#define MASK_TH_VLSEG3HV 0xfdf0707f +#define MATCH_TH_VLSEG3WV 0x50006007 +#define MASK_TH_VLSEG3WV 0xfdf0707f +#define MATCH_TH_VLSEG3BUV 0x40000007 +#define MASK_TH_VLSEG3BUV 0xfdf0707f +#define MATCH_TH_VLSEG3HUV 0x40005007 +#define MASK_TH_VLSEG3HUV 0xfdf0707f +#define MATCH_TH_VLSEG3WUV 0x40006007 +#define MASK_TH_VLSEG3WUV 0xfdf0707f +#define MATCH_TH_VLSEG3EV 0x40007007 +#define MASK_TH_VLSEG3EV 0xfdf0707f +#define MATCH_TH_VSSEG3BV 0x40000027 +#define MASK_TH_VSSEG3BV 0xfdf0707f +#define MATCH_TH_VSSEG3HV 0x40005027 +#define MASK_TH_VSSEG3HV 0xfdf0707f +#define MATCH_TH_VSSEG3WV 0x40006027 +#define MASK_TH_VSSEG3WV 0xfdf0707f +#define MATCH_TH_VSSEG3EV 0x40007027 +#define MASK_TH_VSSEG3EV 0xfdf0707f +#define MATCH_TH_VLSEG4BV 0x70000007 +#define MASK_TH_VLSEG4BV 0xfdf0707f +#define MATCH_TH_VLSEG4HV 0x70005007 +#define MASK_TH_VLSEG4HV 0xfdf0707f +#define MATCH_TH_VLSEG4WV 0x70006007 +#define MASK_TH_VLSEG4WV 0xfdf0707f +#define MATCH_TH_VLSEG4BUV 0x60000007 +#define MASK_TH_VLSEG4BUV 0xfdf0707f +#define MATCH_TH_VLSEG4HUV 0x60005007 +#define MASK_TH_VLSEG4HUV 0xfdf0707f +#define MATCH_TH_VLSEG4WUV 0x60006007 +#define MASK_TH_VLSEG4WUV 0xfdf0707f +#define MATCH_TH_VLSEG4EV 0x60007007 +#define MASK_TH_VLSEG4EV 0xfdf0707f +#define MATCH_TH_VSSEG4BV 0x60000027 +#define MASK_TH_VSSEG4BV 0xfdf0707f +#define MATCH_TH_VSSEG4HV 0x60005027 +#define MASK_TH_VSSEG4HV 0xfdf0707f +#define MATCH_TH_VSSEG4WV 0x60006027 +#define MASK_TH_VSSEG4WV 0xfdf0707f +#define MATCH_TH_VSSEG4EV 0x60007027 +#define MASK_TH_VSSEG4EV 0xfdf0707f +#define MATCH_TH_VLSEG5BV 0x90000007 +#define MASK_TH_VLSEG5BV 0xfdf0707f +#define MATCH_TH_VLSEG5HV 0x90005007 +#define MASK_TH_VLSEG5HV 0xfdf0707f +#define MATCH_TH_VLSEG5WV 0x90006007 +#define MASK_TH_VLSEG5WV 0xfdf0707f +#define MATCH_TH_VLSEG5BUV 0x80000007 +#define MASK_TH_VLSEG5BUV 0xfdf0707f +#define MATCH_TH_VLSEG5HUV 0x80005007 +#define MASK_TH_VLSEG5HUV 0xfdf0707f +#define MATCH_TH_VLSEG5WUV 0x80006007 +#define MASK_TH_VLSEG5WUV 0xfdf0707f +#define MATCH_TH_VLSEG5EV 0x80007007 +#define MASK_TH_VLSEG5EV 0xfdf0707f +#define MATCH_TH_VSSEG5BV 0x80000027 +#define MASK_TH_VSSEG5BV 0xfdf0707f +#define MATCH_TH_VSSEG5HV 0x80005027 +#define MASK_TH_VSSEG5HV 0xfdf0707f +#define MATCH_TH_VSSEG5WV 0x80006027 +#define MASK_TH_VSSEG5WV 0xfdf0707f +#define MATCH_TH_VSSEG5EV 0x80007027 +#define MASK_TH_VSSEG5EV 0xfdf0707f +#define MATCH_TH_VLSEG6BV 0xb0000007 +#define MASK_TH_VLSEG6BV 0xfdf0707f +#define MATCH_TH_VLSEG6HV 0xb0005007 +#define MASK_TH_VLSEG6HV 0xfdf0707f +#define MATCH_TH_VLSEG6WV 0xb0006007 +#define MASK_TH_VLSEG6WV 0xfdf0707f +#define MATCH_TH_VLSEG6BUV 0xa0000007 +#define MASK_TH_VLSEG6BUV 0xfdf0707f +#define MATCH_TH_VLSEG6HUV 0xa0005007 +#define MASK_TH_VLSEG6HUV 0xfdf0707f +#define MATCH_TH_VLSEG6WUV 0xa0006007 +#define MASK_TH_VLSEG6WUV 0xfdf0707f +#define MATCH_TH_VLSEG6EV 0xa0007007 +#define MASK_TH_VLSEG6EV 0xfdf0707f +#define MATCH_TH_VSSEG6BV 0xa0000027 +#define MASK_TH_VSSEG6BV 0xfdf0707f +#define MATCH_TH_VSSEG6HV 0xa0005027 +#define MASK_TH_VSSEG6HV 0xfdf0707f +#define MATCH_TH_VSSEG6WV 0xa0006027 +#define MASK_TH_VSSEG6WV 0xfdf0707f +#define MATCH_TH_VSSEG6EV 0xa0007027 +#define MASK_TH_VSSEG6EV 0xfdf0707f +#define MATCH_TH_VLSEG7BV 0xd0000007 +#define MASK_TH_VLSEG7BV 0xfdf0707f +#define MATCH_TH_VLSEG7HV 0xd0005007 +#define MASK_TH_VLSEG7HV 0xfdf0707f +#define MATCH_TH_VLSEG7WV 0xd0006007 +#define MASK_TH_VLSEG7WV 0xfdf0707f +#define MATCH_TH_VLSEG7BUV 0xc0000007 +#define MASK_TH_VLSEG7BUV 0xfdf0707f +#define MATCH_TH_VLSEG7HUV 0xc0005007 +#define MASK_TH_VLSEG7HUV 0xfdf0707f +#define MATCH_TH_VLSEG7WUV 0xc0006007 +#define MASK_TH_VLSEG7WUV 0xfdf0707f +#define MATCH_TH_VLSEG7EV 0xc0007007 +#define MASK_TH_VLSEG7EV 0xfdf0707f +#define MATCH_TH_VSSEG7BV 0xc0000027 +#define MASK_TH_VSSEG7BV 0xfdf0707f +#define MATCH_TH_VSSEG7HV 0xc0005027 +#define MASK_TH_VSSEG7HV 0xfdf0707f +#define MATCH_TH_VSSEG7WV 0xc0006027 +#define MASK_TH_VSSEG7WV 0xfdf0707f +#define MATCH_TH_VSSEG7EV 0xc0007027 +#define MASK_TH_VSSEG7EV 0xfdf0707f +#define MATCH_TH_VLSEG8BV 0xf0000007 +#define MASK_TH_VLSEG8BV 0xfdf0707f +#define MATCH_TH_VLSEG8HV 0xf0005007 +#define MASK_TH_VLSEG8HV 0xfdf0707f +#define MATCH_TH_VLSEG8WV 0xf0006007 +#define MASK_TH_VLSEG8WV 0xfdf0707f +#define MATCH_TH_VLSEG8BUV 0xe0000007 +#define MASK_TH_VLSEG8BUV 0xfdf0707f +#define MATCH_TH_VLSEG8HUV 0xe0005007 +#define MASK_TH_VLSEG8HUV 0xfdf0707f +#define MATCH_TH_VLSEG8WUV 0xe0006007 +#define MASK_TH_VLSEG8WUV 0xfdf0707f +#define MATCH_TH_VLSEG8EV 0xe0007007 +#define MASK_TH_VLSEG8EV 0xfdf0707f +#define MATCH_TH_VSSEG8BV 0xe0000027 +#define MASK_TH_VSSEG8BV 0xfdf0707f +#define MATCH_TH_VSSEG8HV 0xe0005027 +#define MASK_TH_VSSEG8HV 0xfdf0707f +#define MATCH_TH_VSSEG8WV 0xe0006027 +#define MASK_TH_VSSEG8WV 0xfdf0707f +#define MATCH_TH_VSSEG8EV 0xe0007027 +#define MASK_TH_VSSEG8EV 0xfdf0707f +#define MATCH_TH_VLSSEG2BV 0x38000007 +#define MASK_TH_VLSSEG2BV 0xfc00707f +#define MATCH_TH_VLSSEG2HV 0x38005007 +#define MASK_TH_VLSSEG2HV 0xfc00707f +#define MATCH_TH_VLSSEG2WV 0x38006007 +#define MASK_TH_VLSSEG2WV 0xfc00707f +#define MATCH_TH_VLSSEG2BUV 0x28000007 +#define MASK_TH_VLSSEG2BUV 0xfc00707f +#define MATCH_TH_VLSSEG2HUV 0x28005007 +#define MASK_TH_VLSSEG2HUV 0xfc00707f +#define MATCH_TH_VLSSEG2WUV 0x28006007 +#define MASK_TH_VLSSEG2WUV 0xfc00707f +#define MATCH_TH_VLSSEG2EV 0x28007007 +#define MASK_TH_VLSSEG2EV 0xfc00707f +#define MATCH_TH_VSSSEG2BV 0x28000027 +#define MASK_TH_VSSSEG2BV 0xfc00707f +#define MATCH_TH_VSSSEG2HV 0x28005027 +#define MASK_TH_VSSSEG2HV 0xfc00707f +#define MATCH_TH_VSSSEG2WV 0x28006027 +#define MASK_TH_VSSSEG2WV 0xfc00707f +#define MATCH_TH_VSSSEG2EV 0x28007027 +#define MASK_TH_VSSSEG2EV 0xfc00707f +#define MATCH_TH_VLSSEG3BV 0x58000007 +#define MASK_TH_VLSSEG3BV 0xfc00707f +#define MATCH_TH_VLSSEG3HV 0x58005007 +#define MASK_TH_VLSSEG3HV 0xfc00707f +#define MATCH_TH_VLSSEG3WV 0x58006007 +#define MASK_TH_VLSSEG3WV 0xfc00707f +#define MATCH_TH_VLSSEG3BUV 0x48000007 +#define MASK_TH_VLSSEG3BUV 0xfc00707f +#define MATCH_TH_VLSSEG3HUV 0x48005007 +#define MASK_TH_VLSSEG3HUV 0xfc00707f +#define MATCH_TH_VLSSEG3WUV 0x48006007 +#define MASK_TH_VLSSEG3WUV 0xfc00707f +#define MATCH_TH_VLSSEG3EV 0x48007007 +#define MASK_TH_VLSSEG3EV 0xfc00707f +#define MATCH_TH_VSSSEG3BV 0x48000027 +#define MASK_TH_VSSSEG3BV 0xfc00707f +#define MATCH_TH_VSSSEG3HV 0x48005027 +#define MASK_TH_VSSSEG3HV 0xfc00707f +#define MATCH_TH_VSSSEG3WV 0x48006027 +#define MASK_TH_VSSSEG3WV 0xfc00707f +#define MATCH_TH_VSSSEG3EV 0x48007027 +#define MASK_TH_VSSSEG3EV 0xfc00707f +#define MATCH_TH_VLSSEG4BV 0x78000007 +#define MASK_TH_VLSSEG4BV 0xfc00707f +#define MATCH_TH_VLSSEG4HV 0x78005007 +#define MASK_TH_VLSSEG4HV 0xfc00707f +#define MATCH_TH_VLSSEG4WV 0x78006007 +#define MASK_TH_VLSSEG4WV 0xfc00707f +#define MATCH_TH_VLSSEG4BUV 0x68000007 +#define MASK_TH_VLSSEG4BUV 0xfc00707f +#define MATCH_TH_VLSSEG4HUV 0x68005007 +#define MASK_TH_VLSSEG4HUV 0xfc00707f +#define MATCH_TH_VLSSEG4WUV 0x68006007 +#define MASK_TH_VLSSEG4WUV 0xfc00707f +#define MATCH_TH_VLSSEG4EV 0x68007007 +#define MASK_TH_VLSSEG4EV 0xfc00707f +#define MATCH_TH_VSSSEG4BV 0x68000027 +#define MASK_TH_VSSSEG4BV 0xfc00707f +#define MATCH_TH_VSSSEG4HV 0x68005027 +#define MASK_TH_VSSSEG4HV 0xfc00707f +#define MATCH_TH_VSSSEG4WV 0x68006027 +#define MASK_TH_VSSSEG4WV 0xfc00707f +#define MATCH_TH_VSSSEG4EV 0x68007027 +#define MASK_TH_VSSSEG4EV 0xfc00707f +#define MATCH_TH_VLSSEG5BV 0x98000007 +#define MASK_TH_VLSSEG5BV 0xfc00707f +#define MATCH_TH_VLSSEG5HV 0x98005007 +#define MASK_TH_VLSSEG5HV 0xfc00707f +#define MATCH_TH_VLSSEG5WV 0x98006007 +#define MASK_TH_VLSSEG5WV 0xfc00707f +#define MATCH_TH_VLSSEG5BUV 0x88000007 +#define MASK_TH_VLSSEG5BUV 0xfc00707f +#define MATCH_TH_VLSSEG5HUV 0x88005007 +#define MASK_TH_VLSSEG5HUV 0xfc00707f +#define MATCH_TH_VLSSEG5WUV 0x88006007 +#define MASK_TH_VLSSEG5WUV 0xfc00707f +#define MATCH_TH_VLSSEG5EV 0x88007007 +#define MASK_TH_VLSSEG5EV 0xfc00707f +#define MATCH_TH_VSSSEG5BV 0x88000027 +#define MASK_TH_VSSSEG5BV 0xfc00707f +#define MATCH_TH_VSSSEG5HV 0x88005027 +#define MASK_TH_VSSSEG5HV 0xfc00707f +#define MATCH_TH_VSSSEG5WV 0x88006027 +#define MASK_TH_VSSSEG5WV 0xfc00707f +#define MATCH_TH_VSSSEG5EV 0x88007027 +#define MASK_TH_VSSSEG5EV 0xfc00707f +#define MATCH_TH_VLSSEG6BV 0xb8000007 +#define MASK_TH_VLSSEG6BV 0xfc00707f +#define MATCH_TH_VLSSEG6HV 0xb8005007 +#define MASK_TH_VLSSEG6HV 0xfc00707f +#define MATCH_TH_VLSSEG6WV 0xb8006007 +#define MASK_TH_VLSSEG6WV 0xfc00707f +#define MATCH_TH_VLSSEG6BUV 0xa8000007 +#define MASK_TH_VLSSEG6BUV 0xfc00707f +#define MATCH_TH_VLSSEG6HUV 0xa8005007 +#define MASK_TH_VLSSEG6HUV 0xfc00707f +#define MATCH_TH_VLSSEG6WUV 0xa8006007 +#define MASK_TH_VLSSEG6WUV 0xfc00707f +#define MATCH_TH_VLSSEG6EV 0xa8007007 +#define MASK_TH_VLSSEG6EV 0xfc00707f +#define MATCH_TH_VSSSEG6BV 0xa8000027 +#define MASK_TH_VSSSEG6BV 0xfc00707f +#define MATCH_TH_VSSSEG6HV 0xa8005027 +#define MASK_TH_VSSSEG6HV 0xfc00707f +#define MATCH_TH_VSSSEG6WV 0xa8006027 +#define MASK_TH_VSSSEG6WV 0xfc00707f +#define MATCH_TH_VSSSEG6EV 0xa8007027 +#define MASK_TH_VSSSEG6EV 0xfc00707f +#define MATCH_TH_VLSSEG7BV 0xd8000007 +#define MASK_TH_VLSSEG7BV 0xfc00707f +#define MATCH_TH_VLSSEG7HV 0xd8005007 +#define MASK_TH_VLSSEG7HV 0xfc00707f +#define MATCH_TH_VLSSEG7WV 0xd8006007 +#define MASK_TH_VLSSEG7WV 0xfc00707f +#define MATCH_TH_VLSSEG7BUV 0xc8000007 +#define MASK_TH_VLSSEG7BUV 0xfc00707f +#define MATCH_TH_VLSSEG7HUV 0xc8005007 +#define MASK_TH_VLSSEG7HUV 0xfc00707f +#define MATCH_TH_VLSSEG7WUV 0xc8006007 +#define MASK_TH_VLSSEG7WUV 0xfc00707f +#define MATCH_TH_VLSSEG7EV 0xc8007007 +#define MASK_TH_VLSSEG7EV 0xfc00707f +#define MATCH_TH_VSSSEG7BV 0xc8000027 +#define MASK_TH_VSSSEG7BV 0xfc00707f +#define MATCH_TH_VSSSEG7HV 0xc8005027 +#define MASK_TH_VSSSEG7HV 0xfc00707f +#define MATCH_TH_VSSSEG7WV 0xc8006027 +#define MASK_TH_VSSSEG7WV 0xfc00707f +#define MATCH_TH_VSSSEG7EV 0xc8007027 +#define MASK_TH_VSSSEG7EV 0xfc00707f +#define MATCH_TH_VLSSEG8BV 0xf8000007 +#define MASK_TH_VLSSEG8BV 0xfc00707f +#define MATCH_TH_VLSSEG8HV 0xf8005007 +#define MASK_TH_VLSSEG8HV 0xfc00707f +#define MATCH_TH_VLSSEG8WV 0xf8006007 +#define MASK_TH_VLSSEG8WV 0xfc00707f +#define MATCH_TH_VLSSEG8BUV 0xe8000007 +#define MASK_TH_VLSSEG8BUV 0xfc00707f +#define MATCH_TH_VLSSEG8HUV 0xe8005007 +#define MASK_TH_VLSSEG8HUV 0xfc00707f +#define MATCH_TH_VLSSEG8WUV 0xe8006007 +#define MASK_TH_VLSSEG8WUV 0xfc00707f +#define MATCH_TH_VLSSEG8EV 0xe8007007 +#define MASK_TH_VLSSEG8EV 0xfc00707f +#define MATCH_TH_VSSSEG8BV 0xe8000027 +#define MASK_TH_VSSSEG8BV 0xfc00707f +#define MATCH_TH_VSSSEG8HV 0xe8005027 +#define MASK_TH_VSSSEG8HV 0xfc00707f +#define MATCH_TH_VSSSEG8WV 0xe8006027 +#define MASK_TH_VSSSEG8WV 0xfc00707f +#define MATCH_TH_VSSSEG8EV 0xe8007027 +#define MASK_TH_VSSSEG8EV 0xfc00707f +#define MATCH_TH_VLXSEG2BV 0x3c000007 +#define MASK_TH_VLXSEG2BV 0xfc00707f +#define MATCH_TH_VLXSEG2HV 0x3c005007 +#define MASK_TH_VLXSEG2HV 0xfc00707f +#define MATCH_TH_VLXSEG2WV 0x3c006007 +#define MASK_TH_VLXSEG2WV 0xfc00707f +#define MATCH_TH_VLXSEG2BUV 0x2c000007 +#define MASK_TH_VLXSEG2BUV 0xfc00707f +#define MATCH_TH_VLXSEG2HUV 0x2c005007 +#define MASK_TH_VLXSEG2HUV 0xfc00707f +#define MATCH_TH_VLXSEG2WUV 0x2c006007 +#define MASK_TH_VLXSEG2WUV 0xfc00707f +#define MATCH_TH_VLXSEG2EV 0x2c007007 +#define MASK_TH_VLXSEG2EV 0xfc00707f +#define MATCH_TH_VSXSEG2BV 0x2c000027 +#define MASK_TH_VSXSEG2BV 0xfc00707f +#define MATCH_TH_VSXSEG2HV 0x2c005027 +#define MASK_TH_VSXSEG2HV 0xfc00707f +#define MATCH_TH_VSXSEG2WV 0x2c006027 +#define MASK_TH_VSXSEG2WV 0xfc00707f +#define MATCH_TH_VSXSEG2EV 0x2c007027 +#define MASK_TH_VSXSEG2EV 0xfc00707f +#define MATCH_TH_VLXSEG3BV 0x5c000007 +#define MASK_TH_VLXSEG3BV 0xfc00707f +#define MATCH_TH_VLXSEG3HV 0x5c005007 +#define MASK_TH_VLXSEG3HV 0xfc00707f +#define MATCH_TH_VLXSEG3WV 0x5c006007 +#define MASK_TH_VLXSEG3WV 0xfc00707f +#define MATCH_TH_VLXSEG3BUV 0x4c000007 +#define MASK_TH_VLXSEG3BUV 0xfc00707f +#define MATCH_TH_VLXSEG3HUV 0x4c005007 +#define MASK_TH_VLXSEG3HUV 0xfc00707f +#define MATCH_TH_VLXSEG3WUV 0x4c006007 +#define MASK_TH_VLXSEG3WUV 0xfc00707f +#define MATCH_TH_VLXSEG3EV 0x4c007007 +#define MASK_TH_VLXSEG3EV 0xfc00707f +#define MATCH_TH_VSXSEG3BV 0x4c000027 +#define MASK_TH_VSXSEG3BV 0xfc00707f +#define MATCH_TH_VSXSEG3HV 0x4c005027 +#define MASK_TH_VSXSEG3HV 0xfc00707f +#define MATCH_TH_VSXSEG3WV 0x4c006027 +#define MASK_TH_VSXSEG3WV 0xfc00707f +#define MATCH_TH_VSXSEG3EV 0x4c007027 +#define MASK_TH_VSXSEG3EV 0xfc00707f +#define MATCH_TH_VLXSEG4BV 0x7c000007 +#define MASK_TH_VLXSEG4BV 0xfc00707f +#define MATCH_TH_VLXSEG4HV 0x7c005007 +#define MASK_TH_VLXSEG4HV 0xfc00707f +#define MATCH_TH_VLXSEG4WV 0x7c006007 +#define MASK_TH_VLXSEG4WV 0xfc00707f +#define MATCH_TH_VLXSEG4BUV 0x6c000007 +#define MASK_TH_VLXSEG4BUV 0xfc00707f +#define MATCH_TH_VLXSEG4HUV 0x6c005007 +#define MASK_TH_VLXSEG4HUV 0xfc00707f +#define MATCH_TH_VLXSEG4WUV 0x6c006007 +#define MASK_TH_VLXSEG4WUV 0xfc00707f +#define MATCH_TH_VLXSEG4EV 0x6c007007 +#define MASK_TH_VLXSEG4EV 0xfc00707f +#define MATCH_TH_VSXSEG4BV 0x6c000027 +#define MASK_TH_VSXSEG4BV 0xfc00707f +#define MATCH_TH_VSXSEG4HV 0x6c005027 +#define MASK_TH_VSXSEG4HV 0xfc00707f +#define MATCH_TH_VSXSEG4WV 0x6c006027 +#define MASK_TH_VSXSEG4WV 0xfc00707f +#define MATCH_TH_VSXSEG4EV 0x6c007027 +#define MASK_TH_VSXSEG4EV 0xfc00707f +#define MATCH_TH_VLXSEG5BV 0x9c000007 +#define MASK_TH_VLXSEG5BV 0xfc00707f +#define MATCH_TH_VLXSEG5HV 0x9c005007 +#define MASK_TH_VLXSEG5HV 0xfc00707f +#define MATCH_TH_VLXSEG5WV 0x9c006007 +#define MASK_TH_VLXSEG5WV 0xfc00707f +#define MATCH_TH_VLXSEG5BUV 0x8c000007 +#define MASK_TH_VLXSEG5BUV 0xfc00707f +#define MATCH_TH_VLXSEG5HUV 0x8c005007 +#define MASK_TH_VLXSEG5HUV 0xfc00707f +#define MATCH_TH_VLXSEG5WUV 0x8c006007 +#define MASK_TH_VLXSEG5WUV 0xfc00707f +#define MATCH_TH_VLXSEG5EV 0x8c007007 +#define MASK_TH_VLXSEG5EV 0xfc00707f +#define MATCH_TH_VSXSEG5BV 0x8c000027 +#define MASK_TH_VSXSEG5BV 0xfc00707f +#define MATCH_TH_VSXSEG5HV 0x8c005027 +#define MASK_TH_VSXSEG5HV 0xfc00707f +#define MATCH_TH_VSXSEG5WV 0x8c006027 +#define MASK_TH_VSXSEG5WV 0xfc00707f +#define MATCH_TH_VSXSEG5EV 0x8c007027 +#define MASK_TH_VSXSEG5EV 0xfc00707f +#define MATCH_TH_VLXSEG6BV 0xbc000007 +#define MASK_TH_VLXSEG6BV 0xfc00707f +#define MATCH_TH_VLXSEG6HV 0xbc005007 +#define MASK_TH_VLXSEG6HV 0xfc00707f +#define MATCH_TH_VLXSEG6WV 0xbc006007 +#define MASK_TH_VLXSEG6WV 0xfc00707f +#define MATCH_TH_VLXSEG6BUV 0xac000007 +#define MASK_TH_VLXSEG6BUV 0xfc00707f +#define MATCH_TH_VLXSEG6HUV 0xac005007 +#define MASK_TH_VLXSEG6HUV 0xfc00707f +#define MATCH_TH_VLXSEG6WUV 0xac006007 +#define MASK_TH_VLXSEG6WUV 0xfc00707f +#define MATCH_TH_VLXSEG6EV 0xac007007 +#define MASK_TH_VLXSEG6EV 0xfc00707f +#define MATCH_TH_VSXSEG6BV 0xac000027 +#define MASK_TH_VSXSEG6BV 0xfc00707f +#define MATCH_TH_VSXSEG6HV 0xac005027 +#define MASK_TH_VSXSEG6HV 0xfc00707f +#define MATCH_TH_VSXSEG6WV 0xac006027 +#define MASK_TH_VSXSEG6WV 0xfc00707f +#define MATCH_TH_VSXSEG6EV 0xac007027 +#define MASK_TH_VSXSEG6EV 0xfc00707f +#define MATCH_TH_VLXSEG7BV 0xdc000007 +#define MASK_TH_VLXSEG7BV 0xfc00707f +#define MATCH_TH_VLXSEG7HV 0xdc005007 +#define MASK_TH_VLXSEG7HV 0xfc00707f +#define MATCH_TH_VLXSEG7WV 0xdc006007 +#define MASK_TH_VLXSEG7WV 0xfc00707f +#define MATCH_TH_VLXSEG7BUV 0xcc000007 +#define MASK_TH_VLXSEG7BUV 0xfc00707f +#define MATCH_TH_VLXSEG7HUV 0xcc005007 +#define MASK_TH_VLXSEG7HUV 0xfc00707f +#define MATCH_TH_VLXSEG7WUV 0xcc006007 +#define MASK_TH_VLXSEG7WUV 0xfc00707f +#define MATCH_TH_VLXSEG7EV 0xcc007007 +#define MASK_TH_VLXSEG7EV 0xfc00707f +#define MATCH_TH_VSXSEG7BV 0xcc000027 +#define MASK_TH_VSXSEG7BV 0xfc00707f +#define MATCH_TH_VSXSEG7HV 0xcc005027 +#define MASK_TH_VSXSEG7HV 0xfc00707f +#define MATCH_TH_VSXSEG7WV 0xcc006027 +#define MASK_TH_VSXSEG7WV 0xfc00707f +#define MATCH_TH_VSXSEG7EV 0xcc007027 +#define MASK_TH_VSXSEG7EV 0xfc00707f +#define MATCH_TH_VLXSEG8BV 0xfc000007 +#define MASK_TH_VLXSEG8BV 0xfc00707f +#define MATCH_TH_VLXSEG8HV 0xfc005007 +#define MASK_TH_VLXSEG8HV 0xfc00707f +#define MATCH_TH_VLXSEG8WV 0xfc006007 +#define MASK_TH_VLXSEG8WV 0xfc00707f +#define MATCH_TH_VLXSEG8BUV 0xec000007 +#define MASK_TH_VLXSEG8BUV 0xfc00707f +#define MATCH_TH_VLXSEG8HUV 0xec005007 +#define MASK_TH_VLXSEG8HUV 0xfc00707f +#define MATCH_TH_VLXSEG8WUV 0xec006007 +#define MASK_TH_VLXSEG8WUV 0xfc00707f +#define MATCH_TH_VLXSEG8EV 0xec007007 +#define MASK_TH_VLXSEG8EV 0xfc00707f +#define MATCH_TH_VSXSEG8BV 0xec000027 +#define MASK_TH_VSXSEG8BV 0xfc00707f +#define MATCH_TH_VSXSEG8HV 0xec005027 +#define MASK_TH_VSXSEG8HV 0xfc00707f +#define MATCH_TH_VSXSEG8WV 0xec006027 +#define MASK_TH_VSXSEG8WV 0xfc00707f +#define MATCH_TH_VSXSEG8EV 0xec007027 +#define MASK_TH_VSXSEG8EV 0xfc00707f +#define MATCH_TH_VLSEG2BFFV 0x31000007 +#define MASK_TH_VLSEG2BFFV 0xfdf0707f +#define MATCH_TH_VLSEG2HFFV 0x31005007 +#define MASK_TH_VLSEG2HFFV 0xfdf0707f +#define MATCH_TH_VLSEG2WFFV 0x31006007 +#define MASK_TH_VLSEG2WFFV 0xfdf0707f +#define MATCH_TH_VLSEG2BUFFV 0x21000007 +#define MASK_TH_VLSEG2BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG2HUFFV 0x21005007 +#define MASK_TH_VLSEG2HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG2WUFFV 0x21006007 +#define MASK_TH_VLSEG2WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG2EFFV 0x21007007 +#define MASK_TH_VLSEG2EFFV 0xfdf0707f +#define MATCH_TH_VLSEG3BFFV 0x51000007 +#define MASK_TH_VLSEG3BFFV 0xfdf0707f +#define MATCH_TH_VLSEG3HFFV 0x51005007 +#define MASK_TH_VLSEG3HFFV 0xfdf0707f +#define MATCH_TH_VLSEG3WFFV 0x51006007 +#define MASK_TH_VLSEG3WFFV 0xfdf0707f +#define MATCH_TH_VLSEG3BUFFV 0x41000007 +#define MASK_TH_VLSEG3BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG3HUFFV 0x41005007 +#define MASK_TH_VLSEG3HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG3WUFFV 0x41006007 +#define MASK_TH_VLSEG3WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG3EFFV 0x41007007 +#define MASK_TH_VLSEG3EFFV 0xfdf0707f +#define MATCH_TH_VLSEG4BFFV 0x71000007 +#define MASK_TH_VLSEG4BFFV 0xfdf0707f +#define MATCH_TH_VLSEG4HFFV 0x71005007 +#define MASK_TH_VLSEG4HFFV 0xfdf0707f +#define MATCH_TH_VLSEG4WFFV 0x71006007 +#define MASK_TH_VLSEG4WFFV 0xfdf0707f +#define MATCH_TH_VLSEG4BUFFV 0x61000007 +#define MASK_TH_VLSEG4BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG4HUFFV 0x61005007 +#define MASK_TH_VLSEG4HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG4WUFFV 0x61006007 +#define MASK_TH_VLSEG4WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG4EFFV 0x61007007 +#define MASK_TH_VLSEG4EFFV 0xfdf0707f +#define MATCH_TH_VLSEG5BFFV 0x91000007 +#define MASK_TH_VLSEG5BFFV 0xfdf0707f +#define MATCH_TH_VLSEG5HFFV 0x91005007 +#define MASK_TH_VLSEG5HFFV 0xfdf0707f +#define MATCH_TH_VLSEG5WFFV 0x91006007 +#define MASK_TH_VLSEG5WFFV 0xfdf0707f +#define MATCH_TH_VLSEG5BUFFV 0x81000007 +#define MASK_TH_VLSEG5BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG5HUFFV 0x81005007 +#define MASK_TH_VLSEG5HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG5WUFFV 0x81006007 +#define MASK_TH_VLSEG5WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG5EFFV 0x81007007 +#define MASK_TH_VLSEG5EFFV 0xfdf0707f +#define MATCH_TH_VLSEG6BFFV 0xb1000007 +#define MASK_TH_VLSEG6BFFV 0xfdf0707f +#define MATCH_TH_VLSEG6HFFV 0xb1005007 +#define MASK_TH_VLSEG6HFFV 0xfdf0707f +#define MATCH_TH_VLSEG6WFFV 0xb1006007 +#define MASK_TH_VLSEG6WFFV 0xfdf0707f +#define MATCH_TH_VLSEG6BUFFV 0xa1000007 +#define MASK_TH_VLSEG6BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG6HUFFV 0xa1005007 +#define MASK_TH_VLSEG6HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG6WUFFV 0xa1006007 +#define MASK_TH_VLSEG6WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG6EFFV 0xa1007007 +#define MASK_TH_VLSEG6EFFV 0xfdf0707f +#define MATCH_TH_VLSEG7BFFV 0xd1000007 +#define MASK_TH_VLSEG7BFFV 0xfdf0707f +#define MATCH_TH_VLSEG7HFFV 0xd1005007 +#define MASK_TH_VLSEG7HFFV 0xfdf0707f +#define MATCH_TH_VLSEG7WFFV 0xd1006007 +#define MASK_TH_VLSEG7WFFV 0xfdf0707f +#define MATCH_TH_VLSEG7BUFFV 0xc1000007 +#define MASK_TH_VLSEG7BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG7HUFFV 0xc1005007 +#define MASK_TH_VLSEG7HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG7WUFFV 0xc1006007 +#define MASK_TH_VLSEG7WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG7EFFV 0xc1007007 +#define MASK_TH_VLSEG7EFFV 0xfdf0707f +#define MATCH_TH_VLSEG8BFFV 0xf1000007 +#define MASK_TH_VLSEG8BFFV 0xfdf0707f +#define MATCH_TH_VLSEG8HFFV 0xf1005007 +#define MASK_TH_VLSEG8HFFV 0xfdf0707f +#define MATCH_TH_VLSEG8WFFV 0xf1006007 +#define MASK_TH_VLSEG8WFFV 0xfdf0707f +#define MATCH_TH_VLSEG8BUFFV 0xe1000007 +#define MASK_TH_VLSEG8BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG8HUFFV 0xe1005007 +#define MASK_TH_VLSEG8HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG8WUFFV 0xe1006007 +#define MASK_TH_VLSEG8WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG8EFFV 0xe1007007 +#define MASK_TH_VLSEG8EFFV 0xfdf0707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index a26ef8abf12..f9c3293b29b 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -468,6 +468,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADMEMPAIR, INSN_CLASS_XTHEADSYNC, INSN_CLASS_XTHEADVECTOR, + INSN_CLASS_XTHEADZVLSSEG, INSN_CLASS_XVENTANACONDOPS, }; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 05bdce449f4..d089aa4958d 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2281,6 +2281,286 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vlhuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLHUFFV, MASK_TH_VLHUFFV, match_opcode, INSN_DREF }, {"th.vlwuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLWUFFV, MASK_TH_VLWUFFV, match_opcode, INSN_DREF }, {"th.vleff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLEFFV, MASK_TH_VLEFFV, match_opcode, INSN_DREF }, +{"th.vlseg2b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2BV, MASK_TH_VLSEG2BV, match_opcode, INSN_DREF }, +{"th.vlseg2h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2HV, MASK_TH_VLSEG2HV, match_opcode, INSN_DREF }, +{"th.vlseg2w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2WV, MASK_TH_VLSEG2WV, match_opcode, INSN_DREF }, +{"th.vlseg2bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2BUV, MASK_TH_VLSEG2BUV, match_opcode, INSN_DREF }, +{"th.vlseg2hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2HUV, MASK_TH_VLSEG2HUV, match_opcode, INSN_DREF }, +{"th.vlseg2wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2WUV, MASK_TH_VLSEG2WUV, match_opcode, INSN_DREF }, +{"th.vlseg2e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2EV, MASK_TH_VLSEG2EV, match_opcode, INSN_DREF }, +{"th.vsseg2b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG2BV, MASK_TH_VSSEG2BV, match_opcode, INSN_DREF }, +{"th.vsseg2h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG2HV, MASK_TH_VSSEG2HV, match_opcode, INSN_DREF }, +{"th.vsseg2w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG2WV, MASK_TH_VSSEG2WV, match_opcode, INSN_DREF }, +{"th.vsseg2e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG2EV, MASK_TH_VSSEG2EV, match_opcode, INSN_DREF }, +{"th.vlseg3b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3BV, MASK_TH_VLSEG3BV, match_opcode, INSN_DREF }, +{"th.vlseg3h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3HV, MASK_TH_VLSEG3HV, match_opcode, INSN_DREF }, +{"th.vlseg3w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3WV, MASK_TH_VLSEG3WV, match_opcode, INSN_DREF }, +{"th.vlseg3bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3BUV, MASK_TH_VLSEG3BUV, match_opcode, INSN_DREF }, +{"th.vlseg3hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3HUV, MASK_TH_VLSEG3HUV, match_opcode, INSN_DREF }, +{"th.vlseg3wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3WUV, MASK_TH_VLSEG3WUV, match_opcode, INSN_DREF }, +{"th.vlseg3e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3EV, MASK_TH_VLSEG3EV, match_opcode, INSN_DREF }, +{"th.vsseg3b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG3BV, MASK_TH_VSSEG3BV, match_opcode, INSN_DREF }, +{"th.vsseg3h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG3HV, MASK_TH_VSSEG3HV, match_opcode, INSN_DREF }, +{"th.vsseg3w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG3WV, MASK_TH_VSSEG3WV, match_opcode, INSN_DREF }, +{"th.vsseg3e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG3EV, MASK_TH_VSSEG3EV, match_opcode, INSN_DREF }, +{"th.vlseg4b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4BV, MASK_TH_VLSEG4BV, match_opcode, INSN_DREF }, +{"th.vlseg4h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4HV, MASK_TH_VLSEG4HV, match_opcode, INSN_DREF }, +{"th.vlseg4w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4WV, MASK_TH_VLSEG4WV, match_opcode, INSN_DREF }, +{"th.vlseg4bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4BUV, MASK_TH_VLSEG4BUV, match_opcode, INSN_DREF }, +{"th.vlseg4hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4HUV, MASK_TH_VLSEG4HUV, match_opcode, INSN_DREF }, +{"th.vlseg4wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4WUV, MASK_TH_VLSEG4WUV, match_opcode, INSN_DREF }, +{"th.vlseg4e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4EV, MASK_TH_VLSEG4EV, match_opcode, INSN_DREF }, +{"th.vsseg4b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG4BV, MASK_TH_VSSEG4BV, match_opcode, INSN_DREF }, +{"th.vsseg4h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG4HV, MASK_TH_VSSEG4HV, match_opcode, INSN_DREF }, +{"th.vsseg4w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG4WV, MASK_TH_VSSEG4WV, match_opcode, INSN_DREF }, +{"th.vsseg4e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG4EV, MASK_TH_VSSEG4EV, match_opcode, INSN_DREF }, +{"th.vlseg5b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5BV, MASK_TH_VLSEG5BV, match_opcode, INSN_DREF }, +{"th.vlseg5h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5HV, MASK_TH_VLSEG5HV, match_opcode, INSN_DREF }, +{"th.vlseg5w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5WV, MASK_TH_VLSEG5WV, match_opcode, INSN_DREF }, +{"th.vlseg5bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5BUV, MASK_TH_VLSEG5BUV, match_opcode, INSN_DREF }, +{"th.vlseg5hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5HUV, MASK_TH_VLSEG5HUV, match_opcode, INSN_DREF }, +{"th.vlseg5wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5WUV, MASK_TH_VLSEG5WUV, match_opcode, INSN_DREF }, +{"th.vlseg5e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5EV, MASK_TH_VLSEG5EV, match_opcode, INSN_DREF }, +{"th.vsseg5b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG5BV, MASK_TH_VSSEG5BV, match_opcode, INSN_DREF }, +{"th.vsseg5h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG5HV, MASK_TH_VSSEG5HV, match_opcode, INSN_DREF }, +{"th.vsseg5w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG5WV, MASK_TH_VSSEG5WV, match_opcode, INSN_DREF }, +{"th.vsseg5e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG5EV, MASK_TH_VSSEG5EV, match_opcode, INSN_DREF }, +{"th.vlseg6b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6BV, MASK_TH_VLSEG6BV, match_opcode, INSN_DREF }, +{"th.vlseg6h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6HV, MASK_TH_VLSEG6HV, match_opcode, INSN_DREF }, +{"th.vlseg6w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6WV, MASK_TH_VLSEG6WV, match_opcode, INSN_DREF }, +{"th.vlseg6bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6BUV, MASK_TH_VLSEG6BUV, match_opcode, INSN_DREF }, +{"th.vlseg6hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6HUV, MASK_TH_VLSEG6HUV, match_opcode, INSN_DREF }, +{"th.vlseg6wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6WUV, MASK_TH_VLSEG6WUV, match_opcode, INSN_DREF }, +{"th.vlseg6e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6EV, MASK_TH_VLSEG6EV, match_opcode, INSN_DREF }, +{"th.vsseg6b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG6BV, MASK_TH_VSSEG6BV, match_opcode, INSN_DREF }, +{"th.vsseg6h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG6HV, MASK_TH_VSSEG6HV, match_opcode, INSN_DREF }, +{"th.vsseg6w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG6WV, MASK_TH_VSSEG6WV, match_opcode, INSN_DREF }, +{"th.vsseg6e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG6EV, MASK_TH_VSSEG6EV, match_opcode, INSN_DREF }, +{"th.vlseg7b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7BV, MASK_TH_VLSEG7BV, match_opcode, INSN_DREF }, +{"th.vlseg7h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7HV, MASK_TH_VLSEG7HV, match_opcode, INSN_DREF }, +{"th.vlseg7w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7WV, MASK_TH_VLSEG7WV, match_opcode, INSN_DREF }, +{"th.vlseg7bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7BUV, MASK_TH_VLSEG7BUV, match_opcode, INSN_DREF }, +{"th.vlseg7hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7HUV, MASK_TH_VLSEG7HUV, match_opcode, INSN_DREF }, +{"th.vlseg7wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7WUV, MASK_TH_VLSEG7WUV, match_opcode, INSN_DREF }, +{"th.vlseg7e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7EV, MASK_TH_VLSEG7EV, match_opcode, INSN_DREF }, +{"th.vsseg7b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG7BV, MASK_TH_VSSEG7BV, match_opcode, INSN_DREF }, +{"th.vsseg7h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG7HV, MASK_TH_VSSEG7HV, match_opcode, INSN_DREF }, +{"th.vsseg7w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG7WV, MASK_TH_VSSEG7WV, match_opcode, INSN_DREF }, +{"th.vsseg7e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG7EV, MASK_TH_VSSEG7EV, match_opcode, INSN_DREF }, +{"th.vlseg8b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8BV, MASK_TH_VLSEG8BV, match_opcode, INSN_DREF }, +{"th.vlseg8h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8HV, MASK_TH_VLSEG8HV, match_opcode, INSN_DREF }, +{"th.vlseg8w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8WV, MASK_TH_VLSEG8WV, match_opcode, INSN_DREF }, +{"th.vlseg8bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8BUV, MASK_TH_VLSEG8BUV, match_opcode, INSN_DREF }, +{"th.vlseg8hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8HUV, MASK_TH_VLSEG8HUV, match_opcode, INSN_DREF }, +{"th.vlseg8wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8WUV, MASK_TH_VLSEG8WUV, match_opcode, INSN_DREF }, +{"th.vlseg8e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8EV, MASK_TH_VLSEG8EV, match_opcode, INSN_DREF }, +{"th.vsseg8b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG8BV, MASK_TH_VSSEG8BV, match_opcode, INSN_DREF }, +{"th.vsseg8h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG8HV, MASK_TH_VSSEG8HV, match_opcode, INSN_DREF }, +{"th.vsseg8w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG8WV, MASK_TH_VSSEG8WV, match_opcode, INSN_DREF }, +{"th.vsseg8e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG8EV, MASK_TH_VSSEG8EV, match_opcode, INSN_DREF }, +{"th.vlsseg2b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s),tVm", MATCH_TH_VLSSEG2BV, MASK_TH_VLSSEG2BV, match_opcode, INSN_DREF }, +{"th.vlsseg2h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s),tVm", MATCH_TH_VLSSEG2HV, MASK_TH_VLSSEG2HV, match_opcode, INSN_DREF }, +{"th.vlsseg2w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s),tVm", MATCH_TH_VLSSEG2WV, MASK_TH_VLSSEG2WV, match_opcode, INSN_DREF }, +{"th.vlsseg2bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, 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}, +{"th.vlseg6huff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6HUFFV, MASK_TH_VLSEG6HUFFV, match_opcode, INSN_DREF }, +{"th.vlseg6wuff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6WUFFV, MASK_TH_VLSEG6WUFFV, match_opcode, INSN_DREF }, +{"th.vlseg6eff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6EFFV, MASK_TH_VLSEG6EFFV, match_opcode, INSN_DREF }, +{"th.vlseg7bff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7BFFV, MASK_TH_VLSEG7BFFV, match_opcode, INSN_DREF }, +{"th.vlseg7hff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7HFFV, MASK_TH_VLSEG7HFFV, match_opcode, INSN_DREF }, +{"th.vlseg7wff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7WFFV, MASK_TH_VLSEG7WFFV, match_opcode, INSN_DREF }, +{"th.vlseg7buff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7BUFFV, MASK_TH_VLSEG7BUFFV, match_opcode, INSN_DREF }, +{"th.vlseg7huff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7HUFFV, MASK_TH_VLSEG7HUFFV, match_opcode, INSN_DREF }, +{"th.vlseg7wuff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7WUFFV, MASK_TH_VLSEG7WUFFV, match_opcode, INSN_DREF }, +{"th.vlseg7eff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7EFFV, MASK_TH_VLSEG7EFFV, match_opcode, INSN_DREF }, +{"th.vlseg8bff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8BFFV, MASK_TH_VLSEG8BFFV, match_opcode, INSN_DREF }, +{"th.vlseg8hff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8HFFV, MASK_TH_VLSEG8HFFV, match_opcode, INSN_DREF }, +{"th.vlseg8wff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8WFFV, MASK_TH_VLSEG8WFFV, match_opcode, INSN_DREF }, +{"th.vlseg8buff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8BUFFV, MASK_TH_VLSEG8BUFFV, match_opcode, INSN_DREF }, +{"th.vlseg8huff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8HUFFV, MASK_TH_VLSEG8HUFFV, match_opcode, INSN_DREF }, +{"th.vlseg8wuff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8WUFFV, MASK_TH_VLSEG8WUFFV, match_opcode, INSN_DREF }, +{"th.vlseg8eff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8EFFV, MASK_TH_VLSEG8EFFV, match_opcode, INSN_DREF }, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, From patchwork Fri Nov 10 07:25:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 79537 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CAE31385700D for ; Fri, 10 Nov 2023 07:26:34 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from 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h=From:To:Subject:Date:Message-Id:MIME-Version; b=Os2UI3FbGypuBEZKQzOk7C3h4pvfJ8H8LcIAUHcrsORDzCDJLqrbWTfOm6g1QQGsEgbeV37eJXncOjNoWuLlbcakakLPhWiTe9ChetCF9TECXw6gmJ3Ua5TaDRJhnCnJ71EMIyIBQDtn45o/74xjhj62UUfOUizfowPItqY0Sz8= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R131e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045192; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=6; SR=0; TI=SMTPD_---0Vw3jYqK_1699601169; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw3jYqK_1699601169) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:26:10 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 06/12] RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:25:49 +0800 Message-Id: <20231110072549.1873-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.3 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the sub-extension "XTheadZvamo" for the "XTheadVector" extension, and it provides AMO instructions for T-Head VECTOR vendor extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add support for "XTheadZvamo" extension. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: * testsuite/gas/riscv/x-thead-vector-zvamo.d: New test. * testsuite/gas/riscv/x-thead-vector-zvamo.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VAMOADDWV): New. * opcode/riscv.h (enum riscv_insn_class): Add insn class. opcodes/ChangeLog: * riscv-opc.c: Likewise. --- bfd/elfxx-riscv.c | 5 ++ gas/doc/c-riscv.texi | 6 ++ .../gas/riscv/x-thead-vector-zvamo.d | 81 +++++++++++++++++++ .../gas/riscv/x-thead-vector-zvamo.s | 74 +++++++++++++++++ include/opcode/riscv-opc.h | 36 +++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 18 +++++ 7 files changed, 221 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.d create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 2d2ab040674..a2d6725bc36 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1376,6 +1376,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadvector", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadzvlsseg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadzvamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2594,6 +2595,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadvector"); case INSN_CLASS_XTHEADZVLSSEG: return riscv_subset_supports (rps, "xtheadzvlsseg"); + case INSN_CLASS_XTHEADZVAMO: + return riscv_subset_supports (rps, "xtheadzvamo"); case INSN_CLASS_XVENTANACONDOPS: return riscv_subset_supports (rps, "xventanacondops"); default: @@ -2842,6 +2845,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadvector"; case INSN_CLASS_XTHEADZVLSSEG: return "xtheadzvlsseg"; + case INSN_CLASS_XTHEADZVAMO: + return "xtheadzvamo"; default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index e47200faaf6..adf5756d553 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -825,6 +825,12 @@ and it provides load/store segment instructions for thead vector. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}. +@item XTheadZvamo +The XTheadZvamo extension is a subextension of the XTheadVector extension, +and it provides AMO instructions for the T-Head VECTOR vendor extension. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}. + @item XVentanaCondOps XVentanaCondOps extension provides instructions for branchless sequences that perform conditional arithmetic, conditional diff --git a/gas/testsuite/gas/riscv/x-thead-vector-zvamo.d b/gas/testsuite/gas/riscv/x-thead-vector-zvamo.d new file mode 100644 index 00000000000..6b507ad66d3 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-zvamo.d @@ -0,0 +1,81 @@ +#as: -march=rv32if_xtheadvector_xtheadzvamo +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+0685e22f[ ]+th.vamoaddw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0285e22f[ ]+th.vamoaddw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0685f22f[ ]+th.vamoaddd.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0285f22f[ ]+th.vamoaddd.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0485e22f[ ]+th.vamoaddw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0085e22f[ ]+th.vamoaddw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0485f22f[ ]+th.vamoaddd.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0085f22f[ ]+th.vamoaddd.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0e85e22f[ ]+th.vamoswapw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0a85e22f[ ]+th.vamoswapw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0e85f22f[ ]+th.vamoswapd.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0a85f22f[ ]+th.vamoswapd.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0c85e22f[ ]+th.vamoswapw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0885e22f[ ]+th.vamoswapw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0c85f22f[ ]+th.vamoswapd.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0885f22f[ ]+th.vamoswapd.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+2685e22f[ ]+th.vamoxorw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+2285e22f[ ]+th.vamoxorw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+2685f22f[ ]+th.vamoxord.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+2285f22f[ ]+th.vamoxord.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+2485e22f[ ]+th.vamoxorw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+2085e22f[ ]+th.vamoxorw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+2485f22f[ ]+th.vamoxord.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+2085f22f[ ]+th.vamoxord.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+6685e22f[ ]+th.vamoandw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+6285e22f[ ]+th.vamoandw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+6685f22f[ ]+th.vamoandd.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+6285f22f[ ]+th.vamoandd.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+6485e22f[ ]+th.vamoandw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+6085e22f[ ]+th.vamoandw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+6485f22f[ ]+th.vamoandd.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+6085f22f[ ]+th.vamoandd.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+4685e22f[ ]+th.vamoorw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+4285e22f[ ]+th.vamoorw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+4685f22f[ ]+th.vamoord.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+4285f22f[ ]+th.vamoord.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+4485e22f[ ]+th.vamoorw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+4085e22f[ ]+th.vamoorw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+4485f22f[ ]+th.vamoord.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+4085f22f[ ]+th.vamoord.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+8685e22f[ ]+th.vamominw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+8285e22f[ ]+th.vamominw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+8685f22f[ ]+th.vamomind.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+8285f22f[ ]+th.vamomind.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+8485e22f[ ]+th.vamominw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+8085e22f[ ]+th.vamominw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+8485f22f[ ]+th.vamomind.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+8085f22f[ ]+th.vamomind.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+a685e22f[ ]+th.vamomaxw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+a285e22f[ ]+th.vamomaxw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+a685f22f[ ]+th.vamomaxd.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+a285f22f[ ]+th.vamomaxd.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+a485e22f[ ]+th.vamomaxw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+a085e22f[ ]+th.vamomaxw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+a485f22f[ ]+th.vamomaxd.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+a085f22f[ ]+th.vamomaxd.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+c685e22f[ ]+th.vamominuw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+c285e22f[ ]+th.vamominuw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+c685f22f[ ]+th.vamominud.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+c285f22f[ ]+th.vamominud.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+c485e22f[ ]+th.vamominuw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+c085e22f[ ]+th.vamominuw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+c485f22f[ ]+th.vamominud.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+c085f22f[ ]+th.vamominud.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+e685e22f[ ]+th.vamomaxuw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+e285e22f[ ]+th.vamomaxuw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+e685f22f[ ]+th.vamomaxud.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+e285f22f[ ]+th.vamomaxud.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+e485e22f[ ]+th.vamomaxuw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+e085e22f[ ]+th.vamomaxuw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+e485f22f[ ]+th.vamomaxud.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+e085f22f[ ]+th.vamomaxud.v[ ]+zero,v8,\(a1\),v4,v0.t diff --git a/gas/testsuite/gas/riscv/x-thead-vector-zvamo.s b/gas/testsuite/gas/riscv/x-thead-vector-zvamo.s new file mode 100644 index 00000000000..9d55a1f0076 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-zvamo.s @@ -0,0 +1,74 @@ + th.vamoaddw.v v4, v8, (a1), v4 + th.vamoaddw.v x0, v8, (a1), v4 + th.vamoaddd.v v4, v8, (a1), v4 + th.vamoaddd.v x0, v8, (a1), v4 + th.vamoaddw.v v4, v8, (a1), v4, v0.t + th.vamoaddw.v x0, v8, (a1), v4, v0.t + th.vamoaddd.v v4, v8, (a1), v4, v0.t + th.vamoaddd.v x0, v8, (a1), v4, v0.t + th.vamoswapw.v v4, v8, (a1), v4 + th.vamoswapw.v x0, v8, (a1), v4 + th.vamoswapd.v v4, v8, (a1), v4 + th.vamoswapd.v x0, v8, (a1), v4 + th.vamoswapw.v v4, v8, (a1), v4, v0.t + th.vamoswapw.v x0, v8, (a1), v4, v0.t + th.vamoswapd.v v4, v8, (a1), v4, v0.t + th.vamoswapd.v x0, v8, (a1), v4, v0.t + + th.vamoxorw.v v4, v8, (a1), v4 + th.vamoxorw.v x0, v8, (a1), v4 + th.vamoxord.v v4, v8, (a1), v4 + th.vamoxord.v x0, v8, (a1), v4 + th.vamoxorw.v v4, v8, (a1), v4, v0.t + th.vamoxorw.v x0, v8, (a1), v4, v0.t + th.vamoxord.v v4, v8, (a1), v4, v0.t + th.vamoxord.v x0, v8, (a1), v4, v0.t + th.vamoandw.v v4, v8, (a1), v4 + th.vamoandw.v x0, v8, (a1), v4 + th.vamoandd.v v4, v8, (a1), v4 + th.vamoandd.v x0, v8, (a1), v4 + th.vamoandw.v v4, v8, (a1), v4, v0.t + th.vamoandw.v x0, v8, (a1), v4, v0.t + th.vamoandd.v v4, v8, (a1), v4, v0.t + th.vamoandd.v x0, v8, (a1), v4, v0.t + th.vamoorw.v v4, v8, (a1), v4 + th.vamoorw.v x0, v8, (a1), v4 + th.vamoord.v v4, v8, (a1), v4 + th.vamoord.v x0, v8, (a1), v4 + th.vamoorw.v v4, v8, (a1), v4, v0.t + th.vamoorw.v x0, v8, (a1), v4, v0.t + th.vamoord.v v4, v8, (a1), v4, v0.t + th.vamoord.v x0, v8, (a1), v4, v0.t + + th.vamominw.v v4, v8, (a1), v4 + th.vamominw.v x0, v8, (a1), v4 + th.vamomind.v v4, v8, (a1), v4 + th.vamomind.v x0, v8, (a1), v4 + th.vamominw.v v4, v8, (a1), v4, v0.t + th.vamominw.v x0, v8, (a1), v4, v0.t + th.vamomind.v v4, v8, (a1), v4, v0.t + th.vamomind.v x0, v8, (a1), v4, v0.t + th.vamomaxw.v v4, v8, (a1), v4 + th.vamomaxw.v x0, v8, (a1), v4 + th.vamomaxd.v v4, v8, (a1), v4 + th.vamomaxd.v x0, v8, (a1), v4 + th.vamomaxw.v v4, v8, (a1), v4, v0.t + th.vamomaxw.v x0, v8, (a1), v4, v0.t + th.vamomaxd.v v4, v8, (a1), v4, v0.t + th.vamomaxd.v x0, v8, (a1), v4, v0.t + th.vamominuw.v v4, v8, (a1), v4 + th.vamominuw.v x0, v8, (a1), v4 + th.vamominud.v v4, v8, (a1), v4 + th.vamominud.v x0, v8, (a1), v4 + th.vamominuw.v v4, v8, (a1), v4, v0.t + th.vamominuw.v x0, v8, (a1), v4, v0.t + th.vamominud.v v4, v8, (a1), v4, v0.t + th.vamominud.v x0, v8, (a1), v4, v0.t + th.vamomaxuw.v v4, v8, (a1), v4 + th.vamomaxuw.v x0, v8, (a1), v4 + th.vamomaxud.v v4, v8, (a1), v4 + th.vamomaxud.v x0, v8, (a1), v4 + th.vamomaxuw.v v4, v8, (a1), v4, v0.t + th.vamomaxuw.v x0, v8, (a1), v4, v0.t + th.vamomaxud.v v4, v8, (a1), v4, v0.t + th.vamomaxud.v x0, v8, (a1), v4, v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index c1f94f484d8..832092aee60 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3301,6 +3301,42 @@ #define MASK_TH_VLSEG8WUFFV 0xfdf0707f #define MATCH_TH_VLSEG8EFFV 0xe1007007 #define MASK_TH_VLSEG8EFFV 0xfdf0707f +#define MATCH_TH_VAMOADDWV 0x0000602f +#define MASK_TH_VAMOADDWV 0xf800707f +#define MATCH_TH_VAMOADDDV 0x0000702f +#define MASK_TH_VAMOADDDV 0xf800707f +#define MATCH_TH_VAMOSWAPWV 0x0800602f +#define MASK_TH_VAMOSWAPWV 0xf800707f +#define MATCH_TH_VAMOSWAPDV 0x0800702f +#define MASK_TH_VAMOSWAPDV 0xf800707f +#define MATCH_TH_VAMOXORWV 0x2000602f +#define MASK_TH_VAMOXORWV 0xf800707f +#define MATCH_TH_VAMOXORDV 0x2000702f +#define MASK_TH_VAMOXORDV 0xf800707f +#define MATCH_TH_VAMOANDWV 0x6000602f +#define MASK_TH_VAMOANDWV 0xf800707f +#define MATCH_TH_VAMOANDDV 0x6000702f +#define MASK_TH_VAMOANDDV 0xf800707f +#define MATCH_TH_VAMOORWV 0x4000602f +#define MASK_TH_VAMOORWV 0xf800707f +#define MATCH_TH_VAMOORDV 0x4000702f +#define MASK_TH_VAMOORDV 0xf800707f +#define MATCH_TH_VAMOMINWV 0x8000602f +#define MASK_TH_VAMOMINWV 0xf800707f +#define MATCH_TH_VAMOMINDV 0x8000702f +#define MASK_TH_VAMOMINDV 0xf800707f +#define MATCH_TH_VAMOMAXWV 0xa000602f +#define MASK_TH_VAMOMAXWV 0xf800707f +#define MATCH_TH_VAMOMAXDV 0xa000702f +#define MASK_TH_VAMOMAXDV 0xf800707f +#define MATCH_TH_VAMOMINUWV 0xc000602f +#define MASK_TH_VAMOMINUWV 0xf800707f +#define MATCH_TH_VAMOMINUDV 0xc000702f +#define MASK_TH_VAMOMINUDV 0xf800707f +#define MATCH_TH_VAMOMAXUWV 0xe000602f +#define MASK_TH_VAMOMAXUWV 0xf800707f +#define MATCH_TH_VAMOMAXUDV 0xe000702f +#define MASK_TH_VAMOMAXUDV 0xf800707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f9c3293b29b..f484b259497 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -469,6 +469,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADSYNC, INSN_CLASS_XTHEADVECTOR, INSN_CLASS_XTHEADZVLSSEG, + INSN_CLASS_XTHEADZVAMO, INSN_CLASS_XVENTANACONDOPS, }; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index d089aa4958d..6c3057aa67a 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2561,6 +2561,24 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vlseg8huff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8HUFFV, MASK_TH_VLSEG8HUFFV, match_opcode, INSN_DREF }, {"th.vlseg8wuff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8WUFFV, MASK_TH_VLSEG8WUFFV, match_opcode, INSN_DREF }, {"th.vlseg8eff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8EFFV, MASK_TH_VLSEG8EFFV, match_opcode, INSN_DREF }, +{"th.vamoaddw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOADDWV, MASK_TH_VAMOADDWV, match_opcode, INSN_DREF}, +{"th.vamoaddd.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOADDDV, MASK_TH_VAMOADDDV, match_opcode, INSN_DREF}, +{"th.vamoswapw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOSWAPWV, MASK_TH_VAMOSWAPWV, match_opcode, INSN_DREF}, +{"th.vamoswapd.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOSWAPDV, MASK_TH_VAMOSWAPDV, match_opcode, INSN_DREF}, +{"th.vamoxorw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOXORWV, MASK_TH_VAMOXORWV, match_opcode, INSN_DREF}, +{"th.vamoxord.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOXORDV, MASK_TH_VAMOXORDV, match_opcode, INSN_DREF}, +{"th.vamoandw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOANDWV, MASK_TH_VAMOANDWV, match_opcode, INSN_DREF}, +{"th.vamoandd.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOANDDV, MASK_TH_VAMOANDDV, match_opcode, INSN_DREF}, +{"th.vamoorw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOORWV, MASK_TH_VAMOORWV, match_opcode, INSN_DREF}, +{"th.vamoord.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOORDV, MASK_TH_VAMOORDV, match_opcode, INSN_DREF}, +{"th.vamominw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINWV, MASK_TH_VAMOMINWV, match_opcode, INSN_DREF}, +{"th.vamomind.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINDV, MASK_TH_VAMOMINDV, match_opcode, INSN_DREF}, +{"th.vamomaxw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXWV, MASK_TH_VAMOMAXWV, match_opcode, INSN_DREF}, +{"th.vamomaxd.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXDV, MASK_TH_VAMOMAXDV, match_opcode, INSN_DREF}, +{"th.vamominuw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUWV, MASK_TH_VAMOMINUWV, match_opcode, INSN_DREF}, +{"th.vamominud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUDV, MASK_TH_VAMOMINUDV, match_opcode, INSN_DREF}, +{"th.vamomaxuw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUWV, MASK_TH_VAMOMAXUWV, match_opcode, INSN_DREF}, +{"th.vamomaxud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUDV, MASK_TH_VAMOMAXUDV, match_opcode, INSN_DREF}, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, From patchwork Fri Nov 10 07:31:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 79538 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D77AA3858421 for ; Fri, 10 Nov 2023 07:31:56 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from out30-124.freemail.mail.aliyun.com (out30-124.freemail.mail.aliyun.com [115.124.30.124]) by sourceware.org (Postfix) with ESMTPS id 960893858D38 for ; Fri, 10 Nov 2023 07:31:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 960893858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 960893858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.124 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699601501; cv=none; b=H434/WrZ5V5+Rizxsaf2m9JuwG++nmgnvCVmzfq7YjKIS5sbIavyhkZ4MBeHTiH9oc1OPy8rsrDAbWf0Og5AWON4TnrvsJRgRA5hU/ZSVM6kuEua6LgwnSN9ZYODjgO5/tB9qcimnfRscHAHCN09EfQ3lnbgzMUw56V1uoX5P50= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699601501; c=relaxed/simple; bh=VopDC+5OcEEhInzuUIlo9g9SRs45U54viU+EV0Axays=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=BZh4+1GcPzZWGjlTOoMfGGo3cV0tL7XUkj8g/aW6YBoyoxlYexUyXGRaQk82VXrWDTl6/aRB9BQTGusKLMTUXvflC+gLOTOFGbexDODUlo/vu4E8wT44Uj+wGDKF0hqCFx/mD7kazO7yDr5Xgi/aJU1LcPtzKEwkXk1TSPr9ifI= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R171e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046056; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=6; SR=0; TI=SMTPD_---0Vw3dMMk_1699601486; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw3dMMk_1699601486) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:31:28 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 07/12] RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:31:18 +0800 Message-Id: <20231110073118.1917-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-18.8 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds integer arithmetic instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for integer arithmetic instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VADDVV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise. --- gas/testsuite/gas/riscv/x-thead-vector.d | 322 ++++++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 335 +++++++++++++++++++++++ include/opcode/riscv-opc.h | 262 ++++++++++++++++++ opcodes/riscv-opc.c | 143 ++++++++++ 4 files changed, 1062 insertions(+) diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index d7cb1e1a457..e3a1579300b 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -142,3 +142,325 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+03057207[ ]+th.vleff.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+03057207[ ]+th.vleff.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+01057207[ ]+th.vleff.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+02860257[ ]+th.vadd.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+0285c257[ ]+th.vadd.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+0287b257[ ]+th.vadd.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+02883257[ ]+th.vadd.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+00860257[ ]+th.vadd.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+0085c257[ ]+th.vadd.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+0087b257[ ]+th.vadd.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+00883257[ ]+th.vadd.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+0a860257[ ]+th.vsub.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+0a85c257[ ]+th.vsub.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+0e85c257[ ]+th.vrsub.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+0e87b257[ ]+th.vrsub.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+0e883257[ ]+th.vrsub.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+08860257[ ]+th.vsub.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+0885c257[ ]+th.vsub.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+0c85c257[ ]+th.vrsub.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+0c87b257[ ]+th.vrsub.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+0c883257[ ]+th.vrsub.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+c6806257[ ]+th.vwcvt.x.x.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+c2806257[ ]+th.vwcvtu.x.x.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+c4806257[ ]+th.vwcvt.x.x.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+c0806257[ ]+th.vwcvtu.x.x.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+c2862257[ ]+th.vwaddu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+c285e257[ ]+th.vwaddu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+c0862257[ ]+th.vwaddu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+c085e257[ ]+th.vwaddu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+ca862257[ ]+th.vwsubu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+ca85e257[ ]+th.vwsubu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+c8862257[ ]+th.vwsubu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+c885e257[ ]+th.vwsubu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+c6862257[ ]+th.vwadd.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+c685e257[ ]+th.vwadd.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+c4862257[ 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]+2e860257[ ]+th.vxor.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+2e85c257[ ]+th.vxor.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+2e87b257[ ]+th.vxor.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+2e883257[ ]+th.vxor.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+2c860257[ ]+th.vxor.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+2c85c257[ ]+th.vxor.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+2c87b257[ ]+th.vxor.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+2c883257[ ]+th.vxor.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+96860257[ ]+th.vsll.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+9685c257[ ]+th.vsll.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+9680b257[ ]+th.vsll.vi[ ]+v4,v8,1 +[ ]+[0-9a-f]+:[ ]+968fb257[ ]+th.vsll.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+94860257[ ]+th.vsll.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+9485c257[ ]+th.vsll.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+9480b257[ ]+th.vsll.vi[ ]+v4,v8,1,v0.t +[ ]+[0-9a-f]+:[ ]+948fb257[ ]+th.vsll.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+a2860257[ ]+th.vsrl.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+a285c257[ ]+th.vsrl.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+a280b257[ ]+th.vsrl.vi[ ]+v4,v8,1 +[ ]+[0-9a-f]+:[ ]+a28fb257[ ]+th.vsrl.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+a0860257[ ]+th.vsrl.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+a085c257[ ]+th.vsrl.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+a080b257[ ]+th.vsrl.vi[ ]+v4,v8,1,v0.t +[ ]+[0-9a-f]+:[ ]+a08fb257[ ]+th.vsrl.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+a6860257[ ]+th.vsra.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+a685c257[ ]+th.vsra.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+a680b257[ ]+th.vsra.vi[ ]+v4,v8,1 +[ ]+[0-9a-f]+:[ ]+a68fb257[ ]+th.vsra.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+a4860257[ ]+th.vsra.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+a485c257[ ]+th.vsra.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+a480b257[ ]+th.vsra.vi[ ]+v4,v8,1,v0.t +[ ]+[0-9a-f]+:[ ]+a48fb257[ ]+th.vsra.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+b2860257[ ]+th.vnsrl.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+b285c257[ ]+th.vnsrl.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+b280b257[ ]+th.vnsrl.vi[ ]+v4,v8,1 +[ ]+[0-9a-f]+:[ ]+b28fb257[ ]+th.vnsrl.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+b0860257[ ]+th.vnsrl.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+b085c257[ ]+th.vnsrl.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+b080b257[ ]+th.vnsrl.vi[ ]+v4,v8,1,v0.t +[ ]+[0-9a-f]+:[ ]+b08fb257[ ]+th.vnsrl.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+b6860257[ ]+th.vnsra.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+b685c257[ ]+th.vnsra.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+b680b257[ ]+th.vnsra.vi[ ]+v4,v8,1 +[ ]+[0-9a-f]+:[ ]+b68fb257[ ]+th.vnsra.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+b4860257[ ]+th.vnsra.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+b485c257[ ]+th.vnsra.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+b480b257[ ]+th.vnsra.vi[ ]+v4,v8,1,v0.t +[ ]+[0-9a-f]+:[ ]+b48fb257[ ]+th.vnsra.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+6ec40257[ ]+th.vmslt.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+6ac40257[ ]+th.vmsltu.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+76c40257[ ]+th.vmsle.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+72c40257[ ]+th.vmsleu.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+6cc40257[ ]+th.vmslt.vv[ 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]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+7887b257[ ]+th.vmsgtu.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+78883257[ ]+th.vmsgtu.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+6e85c257[ ]+th.vmslt.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+76422257[ ]+th.vmnot.m[ ]+v4,v4 +[ ]+[0-9a-f]+:[ ]+6a85c257[ ]+th.vmsltu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+76422257[ ]+th.vmnot.m[ ]+v4,v4 +[ ]+[0-9a-f]+:[ ]+6cc64457[ ]+th.vmslt.vx[ ]+v8,v12,a2,v0.t +[ ]+[0-9a-f]+:[ ]+6e802457[ ]+th.vmxor.mm[ ]+v8,v8,v0 +[ ]+[0-9a-f]+:[ ]+68c64457[ ]+th.vmsltu.vx[ ]+v8,v12,a2,v0.t +[ ]+[0-9a-f]+:[ ]+6e802457[ ]+th.vmxor.mm[ ]+v8,v8,v0 +[ ]+[0-9a-f]+:[ ]+6e85c657[ ]+th.vmslt.vx[ ]+v12,v8,a1 +[ ]+[0-9a-f]+:[ ]+62062657[ ]+th.vmandnot.mm[ ]+v12,v0,v12 +[ ]+[0-9a-f]+:[ ]+62402257[ ]+th.vmandnot.mm[ ]+v4,v4,v0 +[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+th.vmor.mm[ ]+v4,v12,v4 +[ ]+[0-9a-f]+:[ ]+6a85c657[ ]+th.vmsltu.vx[ ]+v12,v8,a1 +[ ]+[0-9a-f]+:[ ]+62062657[ ]+th.vmandnot.mm[ ]+v12,v0,v12 +[ ]+[0-9a-f]+:[ ]+62402257[ ]+th.vmandnot.mm[ ]+v4,v4,v0 +[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+th.vmor.mm[ ]+v4,v12,v4 +[ ]+[0-9a-f]+:[ ]+62860257[ ]+th.vmseq.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+6285c257[ ]+th.vmseq.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+6287b257[ ]+th.vmseq.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+62883257[ ]+th.vmseq.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+60860257[ ]+th.vmseq.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+6085c257[ ]+th.vmseq.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+6087b257[ ]+th.vmseq.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+60883257[ ]+th.vmseq.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+66860257[ ]+th.vmsne.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+6685c257[ ]+th.vmsne.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+6687b257[ ]+th.vmsne.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+66883257[ ]+th.vmsne.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+64860257[ ]+th.vmsne.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+6485c257[ ]+th.vmsne.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+6487b257[ ]+th.vmsne.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+64883257[ ]+th.vmsne.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+6a860257[ ]+th.vmsltu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+6a85c257[ ]+th.vmsltu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+68860257[ ]+th.vmsltu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+6885c257[ ]+th.vmsltu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+6e860257[ ]+th.vmslt.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+6e85c257[ ]+th.vmslt.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+6c860257[ ]+th.vmslt.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+6c85c257[ ]+th.vmslt.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+72860257[ ]+th.vmsleu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+7285c257[ ]+th.vmsleu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+7287b257[ ]+th.vmsleu.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+72883257[ ]+th.vmsleu.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+70860257[ ]+th.vmsleu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+7085c257[ ]+th.vmsleu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+7087b257[ ]+th.vmsleu.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+70883257[ ]+th.vmsleu.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+76860257[ ]+th.vmsle.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+7685c257[ ]+th.vmsle.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+7687b257[ ]+th.vmsle.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+76883257[ ]+th.vmsle.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+74860257[ ]+th.vmsle.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+7485c257[ ]+th.vmsle.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+7487b257[ ]+th.vmsle.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+74883257[ ]+th.vmsle.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+7a85c257[ ]+th.vmsgtu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+7a87b257[ ]+th.vmsgtu.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+7a883257[ ]+th.vmsgtu.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+7885c257[ ]+th.vmsgtu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+7887b257[ ]+th.vmsgtu.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+78883257[ ]+th.vmsgtu.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+7e85c257[ ]+th.vmsgt.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+7e87b257[ ]+th.vmsgt.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+7e883257[ ]+th.vmsgt.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+7c85c257[ ]+th.vmsgt.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+7c87b257[ ]+th.vmsgt.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+7c883257[ ]+th.vmsgt.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+12860257[ ]+th.vminu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+1285c257[ ]+th.vminu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+10860257[ ]+th.vminu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+1085c257[ ]+th.vminu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+16860257[ ]+th.vmin.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+1685c257[ ]+th.vmin.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+14860257[ ]+th.vmin.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+1485c257[ ]+th.vmin.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+1a860257[ ]+th.vmaxu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+1a85c257[ ]+th.vmaxu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+18860257[ ]+th.vmaxu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+1885c257[ ]+th.vmaxu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+1e860257[ ]+th.vmax.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+1e85c257[ ]+th.vmax.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+1c860257[ ]+th.vmax.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+1c85c257[ ]+th.vmax.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+96862257[ ]+th.vmul.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+9685e257[ ]+th.vmul.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+94862257[ ]+th.vmul.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+9485e257[ ]+th.vmul.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+9e862257[ ]+th.vmulh.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+9e85e257[ ]+th.vmulh.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+9c862257[ ]+th.vmulh.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+9c85e257[ ]+th.vmulh.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+92862257[ ]+th.vmulhu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+9285e257[ ]+th.vmulhu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+90862257[ ]+th.vmulhu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+9085e257[ ]+th.vmulhu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+9a862257[ ]+th.vmulhsu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+9a85e257[ ]+th.vmulhsu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+98862257[ ]+th.vmulhsu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+9885e257[ ]+th.vmulhsu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+ee862257[ ]+th.vwmul.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+ee85e257[ ]+th.vwmul.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+ec862257[ ]+th.vwmul.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+ec85e257[ ]+th.vwmul.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+e2862257[ ]+th.vwmulu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+e285e257[ ]+th.vwmulu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+e0862257[ ]+th.vwmulu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+e085e257[ ]+th.vwmulu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+ea862257[ ]+th.vwmulsu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+ea85e257[ ]+th.vwmulsu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+e8862257[ ]+th.vwmulsu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+e885e257[ ]+th.vwmulsu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+b6862257[ ]+th.vmacc.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+b685e257[ ]+th.vmacc.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+b4862257[ ]+th.vmacc.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+b485e257[ ]+th.vmacc.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+be862257[ ]+th.vnmsac.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+be85e257[ ]+th.vnmsac.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+bc862257[ ]+th.vnmsac.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+bc85e257[ ]+th.vnmsac.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+a6862257[ ]+th.vmadd.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+a685e257[ ]+th.vmadd.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+a4862257[ ]+th.vmadd.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+a485e257[ ]+th.vmadd.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+ae862257[ ]+th.vnmsub.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+ae85e257[ ]+th.vnmsub.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+ac862257[ ]+th.vnmsub.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+ac85e257[ ]+th.vnmsub.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f2862257[ ]+th.vwmaccu.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+f285e257[ ]+th.vwmaccu.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+f0862257[ ]+th.vwmaccu.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f085e257[ ]+th.vwmaccu.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f6862257[ ]+th.vwmacc.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+f685e257[ ]+th.vwmacc.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+f4862257[ ]+th.vwmacc.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f485e257[ ]+th.vwmacc.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+fa862257[ ]+th.vwmaccsu.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+fa85e257[ ]+th.vwmaccsu.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+f8862257[ ]+th.vwmaccsu.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f885e257[ ]+th.vwmaccsu.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+fe85e257[ ]+th.vwmaccus.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+fc85e257[ ]+th.vwmaccus.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+82862257[ ]+th.vdivu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+8285e257[ ]+th.vdivu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+80862257[ ]+th.vdivu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+8085e257[ ]+th.vdivu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+86862257[ ]+th.vdiv.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+8685e257[ ]+th.vdiv.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+84862257[ ]+th.vdiv.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+8485e257[ ]+th.vdiv.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+8a862257[ ]+th.vremu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+8a85e257[ ]+th.vremu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+88862257[ ]+th.vremu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+8885e257[ ]+th.vremu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+8e862257[ ]+th.vrem.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+8e85e257[ ]+th.vrem.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+8c862257[ ]+th.vrem.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+8c85e257[ ]+th.vrem.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+5c860257[ ]+th.vmerge.vvm[ ]+v4,v8,v12,v0 +[ ]+[0-9a-f]+:[ ]+5c85c257[ ]+th.vmerge.vxm[ ]+v4,v8,a1,v0 +[ ]+[0-9a-f]+:[ ]+5c87b257[ ]+th.vmerge.vim[ ]+v4,v8,15,v0 +[ ]+[0-9a-f]+:[ ]+5c883257[ ]+th.vmerge.vim[ ]+v4,v8,-16,v0 +[ ]+[0-9a-f]+:[ ]+5e060457[ ]+th.vmv.v.v[ ]+v8,v12 +[ ]+[0-9a-f]+:[ ]+5e05c457[ ]+th.vmv.v.x[ ]+v8,a1 +[ ]+[0-9a-f]+:[ ]+5e07b457[ ]+th.vmv.v.i[ ]+v8,15 +[ ]+[0-9a-f]+:[ ]+5e083457[ ]+th.vmv.v.i[ ]+v8,-16 diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index c65e9e8790c..55887e0ce41 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -137,3 +137,338 @@ th.vleff.v v4, (a0) th.vleff.v v4, 0(a0) th.vleff.v v4, (a0), v0.t + + th.vadd.vv v4, v8, v12 + th.vadd.vx v4, v8, a1 + th.vadd.vi v4, v8, 15 + th.vadd.vi v4, v8, -16 + th.vadd.vv v4, v8, v12, v0.t + th.vadd.vx v4, v8, a1, v0.t + th.vadd.vi v4, v8, 15, v0.t + th.vadd.vi v4, v8, -16, v0.t + th.vsub.vv v4, v8, v12 + th.vsub.vx v4, v8, a1 + th.vrsub.vx v4, v8, a1 + th.vrsub.vi v4, v8, 15 + th.vrsub.vi v4, v8, -16 + th.vsub.vv v4, v8, v12, v0.t + th.vsub.vx v4, v8, a1, v0.t + th.vrsub.vx v4, v8, a1, v0.t + th.vrsub.vi v4, v8, 15, v0.t + th.vrsub.vi v4, v8, -16, v0.t + + # Aliases + th.vwcvt.x.x.v v4, v8 + th.vwcvtu.x.x.v v4, v8 + th.vwcvt.x.x.v v4, v8, v0.t + th.vwcvtu.x.x.v v4, v8, v0.t + + th.vwaddu.vv v4, v8, v12 + th.vwaddu.vx v4, v8, a1 + th.vwaddu.vv v4, v8, v12, v0.t + th.vwaddu.vx v4, v8, a1, v0.t + th.vwsubu.vv v4, v8, v12 + th.vwsubu.vx v4, v8, a1 + th.vwsubu.vv v4, v8, v12, v0.t + th.vwsubu.vx v4, v8, a1, v0.t + th.vwadd.vv v4, v8, v12 + th.vwadd.vx v4, v8, a1 + th.vwadd.vv v4, v8, v12, v0.t + th.vwadd.vx v4, v8, a1, v0.t + th.vwsub.vv v4, v8, v12 + th.vwsub.vx v4, v8, a1 + th.vwsub.vv v4, v8, v12, v0.t + th.vwsub.vx v4, v8, a1, v0.t + th.vwaddu.wv v4, v8, v12 + th.vwaddu.wx v4, v8, a1 + th.vwaddu.wv v4, v8, v12, v0.t + th.vwaddu.wx v4, v8, a1, v0.t + th.vwsubu.wv v4, v8, v12 + th.vwsubu.wx v4, v8, a1 + th.vwsubu.wv v4, v8, v12, v0.t + th.vwsubu.wx v4, v8, a1, v0.t + th.vwadd.wv v4, v8, v12 + th.vwadd.wx v4, v8, a1 + th.vwadd.wv v4, v8, v12, v0.t + th.vwadd.wx v4, v8, a1, v0.t + th.vwsub.wv v4, v8, v12 + th.vwsub.wx v4, v8, a1 + th.vwsub.wv v4, v8, v12, v0.t + th.vwsub.wx v4, v8, a1, v0.t + + th.vadc.vvm v4, v8, v12, v0 + th.vadc.vxm v4, v8, a1, v0 + th.vadc.vim v4, v8, 15, v0 + th.vadc.vim v4, v8, -16, v0 + th.vmadc.vvm v4, v8, v12, v0 + th.vmadc.vxm v4, v8, a1, v0 + th.vmadc.vim v4, v8, 15, v0 + th.vmadc.vim v4, v8, -16, v0 + th.vsbc.vvm v4, v8, v12, v0 + th.vsbc.vxm v4, v8, a1, v0 + th.vmsbc.vvm v4, v8, v12, v0 + th.vmsbc.vxm v4, v8, a1, v0 + + # Aliases + th.vnot.v v4, v8 + th.vnot.v v4, v8, v0.t + + th.vand.vv v4, v8, v12 + th.vand.vx v4, v8, a1 + th.vand.vi v4, v8, 15 + th.vand.vi v4, v8, -16 + th.vand.vv v4, v8, v12, v0.t + th.vand.vx v4, v8, a1, v0.t + th.vand.vi v4, v8, 15, v0.t + th.vand.vi v4, v8, -16, v0.t + th.vor.vv v4, v8, v12 + th.vor.vx v4, v8, a1 + th.vor.vi v4, v8, 15 + th.vor.vi v4, v8, -16 + th.vor.vv v4, v8, v12, v0.t + th.vor.vx v4, v8, a1, v0.t + th.vor.vi v4, v8, 15, v0.t + th.vor.vi v4, v8, -16, v0.t + th.vxor.vv v4, v8, v12 + th.vxor.vx v4, v8, a1 + th.vxor.vi v4, v8, 15 + th.vxor.vi v4, v8, -16 + th.vxor.vv v4, v8, v12, v0.t + th.vxor.vx v4, v8, a1, v0.t + th.vxor.vi v4, v8, 15, v0.t + th.vxor.vi v4, v8, -16, v0.t + + th.vsll.vv v4, v8, v12 + th.vsll.vx v4, v8, a1 + th.vsll.vi v4, v8, 1 + th.vsll.vi v4, v8, 31 + th.vsll.vv v4, v8, v12, v0.t + th.vsll.vx v4, v8, a1, v0.t + th.vsll.vi v4, v8, 1, v0.t + th.vsll.vi v4, v8, 31, v0.t + th.vsrl.vv v4, v8, v12 + th.vsrl.vx v4, v8, a1 + th.vsrl.vi v4, v8, 1 + th.vsrl.vi v4, v8, 31 + th.vsrl.vv v4, v8, v12, v0.t + th.vsrl.vx v4, v8, a1, v0.t + th.vsrl.vi v4, v8, 1, v0.t + th.vsrl.vi v4, v8, 31, v0.t + th.vsra.vv v4, v8, v12 + th.vsra.vx v4, v8, a1 + th.vsra.vi v4, v8, 1 + th.vsra.vi v4, v8, 31 + th.vsra.vv v4, v8, v12, v0.t + th.vsra.vx v4, v8, a1, v0.t + th.vsra.vi v4, v8, 1, v0.t + th.vsra.vi v4, v8, 31, v0.t + + th.vnsrl.vv v4, v8, v12 + th.vnsrl.vx v4, v8, a1 + th.vnsrl.vi v4, v8, 1 + th.vnsrl.vi v4, v8, 31 + th.vnsrl.vv v4, v8, v12, v0.t + th.vnsrl.vx v4, v8, a1, v0.t + th.vnsrl.vi v4, v8, 1, v0.t + th.vnsrl.vi v4, v8, 31, v0.t + th.vnsra.vv v4, v8, v12 + th.vnsra.vx v4, v8, a1 + th.vnsra.vi v4, v8, 1 + th.vnsra.vi v4, v8, 31 + th.vnsra.vv v4, v8, v12, v0.t + th.vnsra.vx v4, v8, a1, v0.t + th.vnsra.vi v4, v8, 1, v0.t + th.vnsra.vi v4, v8, 31, v0.t + + # Aliases + th.vmsgt.vv v4, v8, v12 + th.vmsgtu.vv v4, v8, v12 + th.vmsge.vv v4, v8, v12 + th.vmsgeu.vv v4, v8, v12 + th.vmsgt.vv v4, v8, v12, v0.t + th.vmsgtu.vv v4, v8, v12, v0.t + th.vmsge.vv v4, v8, v12, v0.t + th.vmsgeu.vv v4, v8, v12, v0.t + th.vmslt.vi v4, v8, 16 + th.vmslt.vi v4, v8, -15 + th.vmsltu.vi v4, v8, 16 + th.vmsltu.vi v4, v8, -15 + th.vmsge.vi v4, v8, 16 + th.vmsge.vi v4, v8, -15 + th.vmsgeu.vi v4, v8, 16 + th.vmsgeu.vi v4, v8, -15 + th.vmslt.vi v4, v8, 16, v0.t + th.vmslt.vi v4, v8, -15, v0.t + th.vmsltu.vi v4, v8, 16, v0.t + th.vmsltu.vi v4, v8, -15, v0.t + th.vmsge.vi v4, v8, 16, v0.t + th.vmsge.vi v4, v8, -15, v0.t + th.vmsgeu.vi v4, v8, 16, v0.t + th.vmsgeu.vi v4, v8, -15, v0.t + + # Macros + th.vmsge.vx v4, v8, a1 + th.vmsgeu.vx v4, v8, a1 + th.vmsge.vx v8, v12, a2, v0.t + th.vmsgeu.vx v8, v12, a2, v0.t + th.vmsge.vx v4, v8, a1, v0.t, v12 + th.vmsgeu.vx v4, v8, a1, v0.t, v12 + + th.vmseq.vv v4, v8, v12 + th.vmseq.vx v4, v8, a1 + th.vmseq.vi v4, v8, 15 + th.vmseq.vi v4, v8, -16 + th.vmseq.vv v4, v8, v12, v0.t + th.vmseq.vx v4, v8, a1, v0.t + th.vmseq.vi v4, v8, 15, v0.t + th.vmseq.vi v4, v8, -16, v0.t + th.vmsne.vv v4, v8, v12 + th.vmsne.vx v4, v8, a1 + th.vmsne.vi v4, v8, 15 + th.vmsne.vi v4, v8, -16 + th.vmsne.vv v4, v8, v12, v0.t + th.vmsne.vx v4, v8, a1, v0.t + th.vmsne.vi v4, v8, 15, v0.t + th.vmsne.vi v4, v8, -16, v0.t + th.vmsltu.vv v4, v8, v12 + th.vmsltu.vx v4, v8, a1 + th.vmsltu.vv v4, v8, v12, v0.t + th.vmsltu.vx v4, v8, a1, v0.t + th.vmslt.vv v4, v8, v12 + th.vmslt.vx v4, v8, a1 + th.vmslt.vv v4, v8, v12, v0.t + th.vmslt.vx v4, v8, a1, v0.t + th.vmsleu.vv v4, v8, v12 + th.vmsleu.vx v4, v8, a1 + th.vmsleu.vi v4, v8, 15 + th.vmsleu.vi v4, v8, -16 + th.vmsleu.vv v4, v8, v12, v0.t + th.vmsleu.vx v4, v8, a1, v0.t + th.vmsleu.vi v4, v8, 15, v0.t + th.vmsleu.vi v4, v8, -16, v0.t + th.vmsle.vv v4, v8, v12 + th.vmsle.vx v4, v8, a1 + th.vmsle.vi v4, v8, 15 + th.vmsle.vi v4, v8, -16 + th.vmsle.vv v4, v8, v12, v0.t + th.vmsle.vx v4, v8, a1, v0.t + th.vmsle.vi v4, v8, 15, v0.t + th.vmsle.vi v4, v8, -16, v0.t + th.vmsgtu.vx v4, v8, a1 + th.vmsgtu.vi v4, v8, 15 + th.vmsgtu.vi v4, v8, -16 + th.vmsgtu.vx v4, v8, a1, v0.t + th.vmsgtu.vi v4, v8, 15, v0.t + th.vmsgtu.vi v4, v8, -16, v0.t + th.vmsgt.vx v4, v8, a1 + th.vmsgt.vi v4, v8, 15 + th.vmsgt.vi v4, v8, -16 + th.vmsgt.vx v4, v8, a1, v0.t + th.vmsgt.vi v4, v8, 15, v0.t + th.vmsgt.vi v4, v8, -16, v0.t + + th.vminu.vv v4, v8, v12 + th.vminu.vx v4, v8, a1 + th.vminu.vv v4, v8, v12, v0.t + th.vminu.vx v4, v8, a1, v0.t + th.vmin.vv v4, v8, v12 + th.vmin.vx v4, v8, a1 + th.vmin.vv v4, v8, v12, v0.t + th.vmin.vx v4, v8, a1, v0.t + th.vmaxu.vv v4, v8, v12 + th.vmaxu.vx v4, v8, a1 + th.vmaxu.vv v4, v8, v12, v0.t + th.vmaxu.vx v4, v8, a1, v0.t + th.vmax.vv v4, v8, v12 + th.vmax.vx v4, v8, a1 + th.vmax.vv v4, v8, v12, v0.t + th.vmax.vx v4, v8, a1, v0.t + + th.vmul.vv v4, v8, v12 + th.vmul.vx v4, v8, a1 + th.vmul.vv v4, v8, v12, v0.t + th.vmul.vx v4, v8, a1, v0.t + th.vmulh.vv v4, v8, v12 + th.vmulh.vx v4, v8, a1 + th.vmulh.vv v4, v8, v12, v0.t + th.vmulh.vx v4, v8, a1, v0.t + th.vmulhu.vv v4, v8, v12 + th.vmulhu.vx v4, v8, a1 + th.vmulhu.vv v4, v8, v12, v0.t + th.vmulhu.vx v4, v8, a1, v0.t + th.vmulhsu.vv v4, v8, v12 + th.vmulhsu.vx v4, v8, a1 + th.vmulhsu.vv v4, v8, v12, v0.t + th.vmulhsu.vx v4, v8, a1, v0.t + + th.vwmul.vv v4, v8, v12 + th.vwmul.vx v4, v8, a1 + th.vwmul.vv v4, v8, v12, v0.t + th.vwmul.vx v4, v8, a1, v0.t + th.vwmulu.vv v4, v8, v12 + th.vwmulu.vx v4, v8, a1 + th.vwmulu.vv v4, v8, v12, v0.t + th.vwmulu.vx v4, v8, a1, v0.t + th.vwmulsu.vv v4, v8, v12 + th.vwmulsu.vx v4, v8, a1 + th.vwmulsu.vv v4, v8, v12, v0.t + th.vwmulsu.vx v4, v8, a1, v0.t + + th.vmacc.vv v4, v12, v8 + th.vmacc.vx v4, a1, v8 + th.vmacc.vv v4, v12, v8, v0.t + th.vmacc.vx v4, a1, v8, v0.t + th.vnmsac.vv v4, v12, v8 + th.vnmsac.vx v4, a1, v8 + th.vnmsac.vv v4, v12, v8, v0.t + th.vnmsac.vx v4, a1, v8, v0.t + th.vmadd.vv v4, v12, v8 + th.vmadd.vx v4, a1, v8 + th.vmadd.vv v4, v12, v8, v0.t + th.vmadd.vx v4, a1, v8, v0.t + th.vnmsub.vv v4, v12, v8 + th.vnmsub.vx v4, a1, v8 + th.vnmsub.vv v4, v12, v8, v0.t + th.vnmsub.vx v4, a1, v8, v0.t + + th.vwmaccu.vv v4, v12, v8 + th.vwmaccu.vx v4, a1, v8 + th.vwmaccu.vv v4, v12, v8, v0.t + th.vwmaccu.vx v4, a1, v8, v0.t + th.vwmacc.vv v4, v12, v8 + th.vwmacc.vx v4, a1, v8 + th.vwmacc.vv v4, v12, v8, v0.t + th.vwmacc.vx v4, a1, v8, v0.t + th.vwmaccsu.vv v4, v12, v8 + th.vwmaccsu.vx v4, a1, v8 + th.vwmaccsu.vv v4, v12, v8, v0.t + th.vwmaccsu.vx v4, a1, v8, v0.t + th.vwmaccus.vx v4, a1, v8 + th.vwmaccus.vx v4, a1, v8, v0.t + + th.vdivu.vv v4, v8, v12 + th.vdivu.vx v4, v8, a1 + th.vdivu.vv v4, v8, v12, v0.t + th.vdivu.vx v4, v8, a1, v0.t + th.vdiv.vv v4, v8, v12 + th.vdiv.vx v4, v8, a1 + th.vdiv.vv v4, v8, v12, v0.t + th.vdiv.vx v4, v8, a1, v0.t + th.vremu.vv v4, v8, v12 + th.vremu.vx v4, v8, a1 + th.vremu.vv v4, v8, v12, v0.t + th.vremu.vx v4, v8, a1, v0.t + th.vrem.vv v4, v8, v12 + th.vrem.vx v4, v8, a1 + th.vrem.vv v4, v8, v12, v0.t + th.vrem.vx v4, v8, a1, v0.t + + th.vmerge.vvm v4, v8, v12, v0 + th.vmerge.vxm v4, v8, a1, v0 + th.vmerge.vim v4, v8, 15, v0 + th.vmerge.vim v4, v8, -16, v0 + + th.vmv.v.v v8, v12 + th.vmv.v.x v8, a1 + th.vmv.v.i v8, 15 + th.vmv.v.i v8, -16 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 832092aee60..553f3142ed8 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3337,6 +3337,268 @@ #define MASK_TH_VAMOMAXUWV 0xf800707f #define MATCH_TH_VAMOMAXUDV 0xe000702f #define MASK_TH_VAMOMAXUDV 0xf800707f +#define MATCH_TH_VADDVV 0x00000057 +#define MASK_TH_VADDVV 0xfc00707f +#define MATCH_TH_VADDVX 0x00004057 +#define MASK_TH_VADDVX 0xfc00707f +#define MATCH_TH_VADDVI 0x00003057 +#define MASK_TH_VADDVI 0xfc00707f +#define MATCH_TH_VSUBVV 0x08000057 +#define MASK_TH_VSUBVV 0xfc00707f +#define MATCH_TH_VSUBVX 0x08004057 +#define MASK_TH_VSUBVX 0xfc00707f +#define MATCH_TH_VRSUBVX 0x0c004057 +#define MASK_TH_VRSUBVX 0xfc00707f +#define MATCH_TH_VRSUBVI 0x0c003057 +#define MASK_TH_VRSUBVI 0xfc00707f +#define MATCH_TH_VWCVTXXV 0xc4006057 +#define MASK_TH_VWCVTXXV 0xfc0ff07f +#define MATCH_TH_VWCVTUXXV 0xc0006057 +#define MASK_TH_VWCVTUXXV 0xfc0ff07f +#define MATCH_TH_VWADDVV 0xc4002057 +#define MASK_TH_VWADDVV 0xfc00707f +#define MATCH_TH_VWADDVX 0xc4006057 +#define MASK_TH_VWADDVX 0xfc00707f +#define MATCH_TH_VWSUBVV 0xcc002057 +#define MASK_TH_VWSUBVV 0xfc00707f +#define MATCH_TH_VWSUBVX 0xcc006057 +#define MASK_TH_VWSUBVX 0xfc00707f +#define MATCH_TH_VWADDWV 0xd4002057 +#define MASK_TH_VWADDWV 0xfc00707f +#define MATCH_TH_VWADDWX 0xd4006057 +#define MASK_TH_VWADDWX 0xfc00707f +#define MATCH_TH_VWSUBWV 0xdc002057 +#define MASK_TH_VWSUBWV 0xfc00707f +#define MATCH_TH_VWSUBWX 0xdc006057 +#define MASK_TH_VWSUBWX 0xfc00707f +#define MATCH_TH_VWADDUVV 0xc0002057 +#define MASK_TH_VWADDUVV 0xfc00707f +#define MATCH_TH_VWADDUVX 0xc0006057 +#define MASK_TH_VWADDUVX 0xfc00707f +#define MATCH_TH_VWSUBUVV 0xc8002057 +#define MASK_TH_VWSUBUVV 0xfc00707f +#define MATCH_TH_VWSUBUVX 0xc8006057 +#define MASK_TH_VWSUBUVX 0xfc00707f +#define MATCH_TH_VWADDUWV 0xd0002057 +#define MASK_TH_VWADDUWV 0xfc00707f +#define MATCH_TH_VWADDUWX 0xd0006057 +#define MASK_TH_VWADDUWX 0xfc00707f +#define MATCH_TH_VWSUBUWV 0xd8002057 +#define MASK_TH_VWSUBUWV 0xfc00707f +#define MATCH_TH_VWSUBUWX 0xd8006057 +#define MASK_TH_VWSUBUWX 0xfc00707f +#define MATCH_TH_VADCVVM 0x42000057 +#define MASK_TH_VADCVVM 0xfe00707f +#define MATCH_TH_VADCVXM 0x42004057 +#define MASK_TH_VADCVXM 0xfe00707f +#define MATCH_TH_VADCVIM 0x42003057 +#define MASK_TH_VADCVIM 0xfe00707f +#define MATCH_TH_VMADCVVM 0x46000057 +#define MASK_TH_VMADCVVM 0xfe00707f +#define MATCH_TH_VMADCVXM 0x46004057 +#define MASK_TH_VMADCVXM 0xfe00707f +#define MATCH_TH_VMADCVIM 0x46003057 +#define MASK_TH_VMADCVIM 0xfe00707f +#define MATCH_TH_VSBCVVM 0x4a000057 +#define MASK_TH_VSBCVVM 0xfe00707f +#define MATCH_TH_VSBCVXM 0x4a004057 +#define MASK_TH_VSBCVXM 0xfe00707f +#define MATCH_TH_VMSBCVVM 0x4e000057 +#define MASK_TH_VMSBCVVM 0xfe00707f +#define MATCH_TH_VMSBCVXM 0x4e004057 +#define MASK_TH_VMSBCVXM 0xfe00707f +#define MATCH_TH_VNOTV 0x2c0fb057 +#define MASK_TH_VNOTV 0xfc0ff07f +#define MATCH_TH_VANDVV 0x24000057 +#define MASK_TH_VANDVV 0xfc00707f +#define MATCH_TH_VANDVX 0x24004057 +#define MASK_TH_VANDVX 0xfc00707f +#define MATCH_TH_VANDVI 0x24003057 +#define MASK_TH_VANDVI 0xfc00707f +#define MATCH_TH_VORVV 0x28000057 +#define MASK_TH_VORVV 0xfc00707f +#define MATCH_TH_VORVX 0x28004057 +#define MASK_TH_VORVX 0xfc00707f +#define MATCH_TH_VORVI 0x28003057 +#define MASK_TH_VORVI 0xfc00707f +#define MATCH_TH_VXORVV 0x2c000057 +#define MASK_TH_VXORVV 0xfc00707f +#define MATCH_TH_VXORVX 0x2c004057 +#define MASK_TH_VXORVX 0xfc00707f +#define MATCH_TH_VXORVI 0x2c003057 +#define MASK_TH_VXORVI 0xfc00707f +#define MATCH_TH_VSLLVV 0x94000057 +#define MASK_TH_VSLLVV 0xfc00707f +#define MATCH_TH_VSLLVX 0x94004057 +#define MASK_TH_VSLLVX 0xfc00707f +#define MATCH_TH_VSLLVI 0x94003057 +#define MASK_TH_VSLLVI 0xfc00707f +#define MATCH_TH_VSRLVV 0xa0000057 +#define MASK_TH_VSRLVV 0xfc00707f +#define MATCH_TH_VSRLVX 0xa0004057 +#define MASK_TH_VSRLVX 0xfc00707f +#define MATCH_TH_VSRLVI 0xa0003057 +#define MASK_TH_VSRLVI 0xfc00707f +#define MATCH_TH_VSRAVV 0xa4000057 +#define MASK_TH_VSRAVV 0xfc00707f +#define MATCH_TH_VSRAVX 0xa4004057 +#define MASK_TH_VSRAVX 0xfc00707f +#define MATCH_TH_VSRAVI 0xa4003057 +#define MASK_TH_VSRAVI 0xfc00707f +#define MATCH_TH_VNSRLVV 0xb0000057 +#define MASK_TH_VNSRLVV 0xfc00707f +#define MATCH_TH_VNSRLVX 0xb0004057 +#define MASK_TH_VNSRLVX 0xfc00707f +#define MATCH_TH_VNSRLVI 0xb0003057 +#define MASK_TH_VNSRLVI 0xfc00707f +#define MATCH_TH_VNSRAVV 0xb4000057 +#define MASK_TH_VNSRAVV 0xfc00707f +#define MATCH_TH_VNSRAVX 0xb4004057 +#define MASK_TH_VNSRAVX 0xfc00707f +#define MATCH_TH_VNSRAVI 0xb4003057 +#define MASK_TH_VNSRAVI 0xfc00707f +#define MATCH_TH_VMSEQVV 0x60000057 +#define MASK_TH_VMSEQVV 0xfc00707f +#define MATCH_TH_VMSEQVX 0x60004057 +#define MASK_TH_VMSEQVX 0xfc00707f +#define MATCH_TH_VMSEQVI 0x60003057 +#define MASK_TH_VMSEQVI 0xfc00707f +#define MATCH_TH_VMSNEVV 0x64000057 +#define MASK_TH_VMSNEVV 0xfc00707f +#define MATCH_TH_VMSNEVX 0x64004057 +#define MASK_TH_VMSNEVX 0xfc00707f +#define MATCH_TH_VMSNEVI 0x64003057 +#define MASK_TH_VMSNEVI 0xfc00707f +#define MATCH_TH_VMSLTVV 0x6c000057 +#define MASK_TH_VMSLTVV 0xfc00707f +#define MATCH_TH_VMSLTVX 0x6c004057 +#define MASK_TH_VMSLTVX 0xfc00707f +#define MATCH_TH_VMSLTUVV 0x68000057 +#define MASK_TH_VMSLTUVV 0xfc00707f +#define MATCH_TH_VMSLTUVX 0x68004057 +#define MASK_TH_VMSLTUVX 0xfc00707f +#define MATCH_TH_VMSLEVV 0x74000057 +#define MASK_TH_VMSLEVV 0xfc00707f +#define MATCH_TH_VMSLEVX 0x74004057 +#define MASK_TH_VMSLEVX 0xfc00707f +#define MATCH_TH_VMSLEVI 0x74003057 +#define MASK_TH_VMSLEVI 0xfc00707f +#define MATCH_TH_VMSLEUVV 0x70000057 +#define MASK_TH_VMSLEUVV 0xfc00707f +#define MATCH_TH_VMSLEUVX 0x70004057 +#define MASK_TH_VMSLEUVX 0xfc00707f +#define MATCH_TH_VMSLEUVI 0x70003057 +#define MASK_TH_VMSLEUVI 0xfc00707f +#define MATCH_TH_VMSGTVX 0x7c004057 +#define MASK_TH_VMSGTVX 0xfc00707f +#define MATCH_TH_VMSGTVI 0x7c003057 +#define MASK_TH_VMSGTVI 0xfc00707f +#define MATCH_TH_VMSGTUVX 0x78004057 +#define MASK_TH_VMSGTUVX 0xfc00707f +#define MATCH_TH_VMSGTUVI 0x78003057 +#define MASK_TH_VMSGTUVI 0xfc00707f +#define MATCH_TH_VMINVV 0x14000057 +#define MASK_TH_VMINVV 0xfc00707f +#define MATCH_TH_VMINVX 0x14004057 +#define MASK_TH_VMINVX 0xfc00707f +#define MATCH_TH_VMAXVV 0x1c000057 +#define MASK_TH_VMAXVV 0xfc00707f +#define MATCH_TH_VMAXVX 0x1c004057 +#define MASK_TH_VMAXVX 0xfc00707f +#define MATCH_TH_VMINUVV 0x10000057 +#define MASK_TH_VMINUVV 0xfc00707f +#define MATCH_TH_VMINUVX 0x10004057 +#define MASK_TH_VMINUVX 0xfc00707f +#define MATCH_TH_VMAXUVV 0x18000057 +#define MASK_TH_VMAXUVV 0xfc00707f +#define MATCH_TH_VMAXUVX 0x18004057 +#define MASK_TH_VMAXUVX 0xfc00707f +#define MATCH_TH_VMULVV 0x94002057 +#define MASK_TH_VMULVV 0xfc00707f +#define MATCH_TH_VMULVX 0x94006057 +#define MASK_TH_VMULVX 0xfc00707f +#define MATCH_TH_VMULHVV 0x9c002057 +#define MASK_TH_VMULHVV 0xfc00707f +#define MATCH_TH_VMULHVX 0x9c006057 +#define MASK_TH_VMULHVX 0xfc00707f +#define MATCH_TH_VMULHUVV 0x90002057 +#define MASK_TH_VMULHUVV 0xfc00707f +#define MATCH_TH_VMULHUVX 0x90006057 +#define MASK_TH_VMULHUVX 0xfc00707f +#define MATCH_TH_VMULHSUVV 0x98002057 +#define MASK_TH_VMULHSUVV 0xfc00707f +#define MATCH_TH_VMULHSUVX 0x98006057 +#define MASK_TH_VMULHSUVX 0xfc00707f +#define MATCH_TH_VWMULVV 0xec002057 +#define MASK_TH_VWMULVV 0xfc00707f +#define MATCH_TH_VWMULVX 0xec006057 +#define MASK_TH_VWMULVX 0xfc00707f +#define MATCH_TH_VWMULUVV 0xe0002057 +#define MASK_TH_VWMULUVV 0xfc00707f +#define MATCH_TH_VWMULUVX 0xe0006057 +#define MASK_TH_VWMULUVX 0xfc00707f +#define MATCH_TH_VWMULSUVV 0xe8002057 +#define MASK_TH_VWMULSUVV 0xfc00707f +#define MATCH_TH_VWMULSUVX 0xe8006057 +#define MASK_TH_VWMULSUVX 0xfc00707f +#define MATCH_TH_VMACCVV 0xb4002057 +#define MASK_TH_VMACCVV 0xfc00707f +#define MATCH_TH_VMACCVX 0xb4006057 +#define MASK_TH_VMACCVX 0xfc00707f +#define MATCH_TH_VNMSACVV 0xbc002057 +#define MASK_TH_VNMSACVV 0xfc00707f +#define MATCH_TH_VNMSACVX 0xbc006057 +#define MASK_TH_VNMSACVX 0xfc00707f +#define MATCH_TH_VMADDVV 0xa4002057 +#define MASK_TH_VMADDVV 0xfc00707f +#define MATCH_TH_VMADDVX 0xa4006057 +#define MASK_TH_VMADDVX 0xfc00707f +#define MATCH_TH_VNMSUBVV 0xac002057 +#define MASK_TH_VNMSUBVV 0xfc00707f +#define MATCH_TH_VNMSUBVX 0xac006057 +#define MASK_TH_VNMSUBVX 0xfc00707f +#define MATCH_TH_VWMACCUVV 0xf0002057 +#define MASK_TH_VWMACCUVV 0xfc00707f +#define MATCH_TH_VWMACCUVX 0xf0006057 +#define MASK_TH_VWMACCUVX 0xfc00707f +#define MATCH_TH_VWMACCVV 0xf4002057 +#define MASK_TH_VWMACCVV 0xfc00707f +#define MATCH_TH_VWMACCVX 0xf4006057 +#define MASK_TH_VWMACCVX 0xfc00707f +#define MATCH_TH_VWMACCSUVV 0xf8002057 +#define MASK_TH_VWMACCSUVV 0xfc00707f +#define MATCH_TH_VWMACCSUVX 0xf8006057 +#define MASK_TH_VWMACCSUVX 0xfc00707f +#define MATCH_TH_VWMACCUSVX 0xfc006057 +#define MASK_TH_VWMACCUSVX 0xfc00707f +#define MATCH_TH_VDIVVV 0x84002057 +#define MASK_TH_VDIVVV 0xfc00707f +#define MATCH_TH_VDIVVX 0x84006057 +#define MASK_TH_VDIVVX 0xfc00707f +#define MATCH_TH_VDIVUVV 0x80002057 +#define MASK_TH_VDIVUVV 0xfc00707f +#define MATCH_TH_VDIVUVX 0x80006057 +#define MASK_TH_VDIVUVX 0xfc00707f +#define MATCH_TH_VREMVV 0x8c002057 +#define MASK_TH_VREMVV 0xfc00707f +#define MATCH_TH_VREMVX 0x8c006057 +#define MASK_TH_VREMVX 0xfc00707f +#define MATCH_TH_VREMUVV 0x88002057 +#define MASK_TH_VREMUVV 0xfc00707f +#define MATCH_TH_VREMUVX 0x88006057 +#define MASK_TH_VREMUVX 0xfc00707f +#define MATCH_TH_VMERGEVVM 0x5c000057 +#define MASK_TH_VMERGEVVM 0xfe00707f +#define MATCH_TH_VMERGEVXM 0x5c004057 +#define MASK_TH_VMERGEVXM 0xfe00707f +#define MATCH_TH_VMERGEVIM 0x5c003057 +#define MASK_TH_VMERGEVIM 0xfe00707f +#define MATCH_TH_VMVVV 0x5e000057 +#define MASK_TH_VMVVV 0xfff0707f +#define MATCH_TH_VMVVX 0x5e004057 +#define MASK_TH_VMVVX 0xfff0707f +#define MATCH_TH_VMVVI 0x5e003057 +#define MASK_TH_VMVVI 0xfff0707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6c3057aa67a..bd7b866358f 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2579,6 +2579,149 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vamominud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUDV, MASK_TH_VAMOMINUDV, match_opcode, INSN_DREF}, {"th.vamomaxuw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUWV, MASK_TH_VAMOMAXUWV, match_opcode, INSN_DREF}, {"th.vamomaxud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUDV, MASK_TH_VAMOMAXUDV, match_opcode, INSN_DREF}, +{"th.vadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VADDVV, MASK_TH_VADDVV, match_opcode, 0 }, +{"th.vadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VADDVX, MASK_TH_VADDVX, match_opcode, 0 }, +{"th.vadd.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VADDVI, MASK_TH_VADDVI, match_opcode, 0 }, +{"th.vsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSUBVV, MASK_TH_VSUBVV, match_opcode, 0 }, +{"th.vsub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSUBVX, MASK_TH_VSUBVX, match_opcode, 0 }, +{"th.vrsub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VRSUBVX, MASK_TH_VRSUBVX, match_opcode, 0 }, +{"th.vrsub.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VRSUBVI, MASK_TH_VRSUBVI, match_opcode, 0 }, +{"th.vwcvt.x.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VWCVTXXV, MASK_TH_VWCVTXXV, match_opcode, INSN_ALIAS }, +{"th.vwcvtu.x.x.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VWCVTUXXV, MASK_TH_VWCVTUXXV, match_opcode, INSN_ALIAS }, +{"th.vwaddu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWADDUVV, MASK_TH_VWADDUVV, match_opcode, 0 }, +{"th.vwaddu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWADDUVX, MASK_TH_VWADDUVX, match_opcode, 0 }, +{"th.vwsubu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWSUBUVV, MASK_TH_VWSUBUVV, match_opcode, 0 }, +{"th.vwsubu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWSUBUVX, MASK_TH_VWSUBUVX, match_opcode, 0 }, +{"th.vwadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWADDVV, MASK_TH_VWADDVV, match_opcode, 0 }, +{"th.vwadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWADDVX, MASK_TH_VWADDVX, match_opcode, 0 }, +{"th.vwsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWSUBVV, MASK_TH_VWSUBVV, match_opcode, 0 }, +{"th.vwsub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWSUBVX, MASK_TH_VWSUBVX, match_opcode, 0 }, +{"th.vwaddu.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWADDUWV, MASK_TH_VWADDUWV, match_opcode, 0 }, +{"th.vwaddu.wx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWADDUWX, MASK_TH_VWADDUWX, match_opcode, 0 }, +{"th.vwsubu.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWSUBUWV, MASK_TH_VWSUBUWV, match_opcode, 0 }, +{"th.vwsubu.wx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWSUBUWX, MASK_TH_VWSUBUWX, match_opcode, 0 }, +{"th.vwadd.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWADDWV, MASK_TH_VWADDWV, match_opcode, 0 }, +{"th.vwadd.wx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWADDWX, MASK_TH_VWADDWX, match_opcode, 0 }, +{"th.vwsub.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWSUBWV, MASK_TH_VWSUBWV, match_opcode, 0 }, +{"th.vwsub.wx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWSUBWX, MASK_TH_VWSUBWX, match_opcode, 0 }, +{"th.vadc.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_TH_VADCVVM, MASK_TH_VADCVVM, match_opcode, 0 }, +{"th.vadc.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_TH_VADCVXM, MASK_TH_VADCVXM, match_opcode, 0 }, +{"th.vadc.vim", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vi,V0", MATCH_TH_VADCVIM, MASK_TH_VADCVIM, match_opcode, 0 }, +{"th.vmadc.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_TH_VMADCVVM, MASK_TH_VMADCVVM, match_opcode, 0 }, +{"th.vmadc.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_TH_VMADCVXM, MASK_TH_VMADCVXM, match_opcode, 0 }, +{"th.vmadc.vim", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vi,V0", MATCH_TH_VMADCVIM, MASK_TH_VMADCVIM, match_opcode, 0 }, +{"th.vsbc.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_TH_VSBCVVM, MASK_TH_VSBCVVM, match_opcode, 0 }, +{"th.vsbc.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_TH_VSBCVXM, MASK_TH_VSBCVXM, match_opcode, 0 }, +{"th.vmsbc.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_TH_VMSBCVVM, MASK_TH_VMSBCVVM, match_opcode, 0 }, +{"th.vmsbc.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_TH_VMSBCVXM, MASK_TH_VMSBCVXM, match_opcode, 0 }, +{"th.vnot.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VNOTV, MASK_TH_VNOTV, match_opcode, INSN_ALIAS }, +{"th.vand.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VANDVV, MASK_TH_VANDVV, match_opcode, 0 }, +{"th.vand.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VANDVX, MASK_TH_VANDVX, match_opcode, 0 }, +{"th.vand.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VANDVI, MASK_TH_VANDVI, match_opcode, 0 }, +{"th.vor.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VORVV, MASK_TH_VORVV, match_opcode, 0 }, +{"th.vor.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VORVX, MASK_TH_VORVX, match_opcode, 0 }, +{"th.vor.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VORVI, MASK_TH_VORVI, match_opcode, 0 }, +{"th.vxor.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VXORVV, MASK_TH_VXORVV, match_opcode, 0 }, +{"th.vxor.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VXORVX, MASK_TH_VXORVX, match_opcode, 0 }, +{"th.vxor.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VXORVI, MASK_TH_VXORVI, match_opcode, 0 }, +{"th.vsll.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSLLVV, MASK_TH_VSLLVV, match_opcode, 0 }, +{"th.vsll.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSLLVX, MASK_TH_VSLLVX, match_opcode, 0 }, +{"th.vsll.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSLLVI, MASK_TH_VSLLVI, match_opcode, 0 }, +{"th.vsrl.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSRLVV, MASK_TH_VSRLVV, match_opcode, 0 }, +{"th.vsrl.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSRLVX, MASK_TH_VSRLVX, match_opcode, 0 }, +{"th.vsrl.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSRLVI, MASK_TH_VSRLVI, match_opcode, 0 }, +{"th.vsra.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSRAVV, MASK_TH_VSRAVV, match_opcode, 0 }, +{"th.vsra.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSRAVX, MASK_TH_VSRAVX, match_opcode, 0 }, +{"th.vsra.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSRAVI, MASK_TH_VSRAVI, match_opcode, 0 }, +{"th.vnsrl.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VNSRLVV, MASK_TH_VNSRLVV, match_opcode, 0 }, +{"th.vnsrl.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VNSRLVX, MASK_TH_VNSRLVX, match_opcode, 0 }, +{"th.vnsrl.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VNSRLVI, MASK_TH_VNSRLVI, match_opcode, 0 }, +{"th.vnsra.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VNSRAVV, MASK_TH_VNSRAVV, match_opcode, 0 }, +{"th.vnsra.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VNSRAVX, MASK_TH_VNSRAVX, match_opcode, 0 }, +{"th.vnsra.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VNSRAVI, MASK_TH_VNSRAVI, match_opcode, 0 }, +{"th.vmseq.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMSEQVV, MASK_TH_VMSEQVV, match_opcode, 0 }, +{"th.vmseq.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSEQVX, MASK_TH_VMSEQVX, match_opcode, 0 }, +{"th.vmseq.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VMSEQVI, MASK_TH_VMSEQVI, match_opcode, 0 }, +{"th.vmsne.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMSNEVV, MASK_TH_VMSNEVV, match_opcode, 0 }, +{"th.vmsne.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSNEVX, MASK_TH_VMSNEVX, match_opcode, 0 }, +{"th.vmsne.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VMSNEVI, MASK_TH_VMSNEVI, match_opcode, 0 }, +{"th.vmsltu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMSLTUVV, MASK_TH_VMSLTUVV, match_opcode, 0 }, +{"th.vmsltu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSLTUVX, MASK_TH_VMSLTUVX, match_opcode, 0 }, +{"th.vmslt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMSLTVV, MASK_TH_VMSLTVV, match_opcode, 0 }, +{"th.vmslt.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSLTVX, MASK_TH_VMSLTVX, match_opcode, 0 }, +{"th.vmsleu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMSLEUVV, MASK_TH_VMSLEUVV, match_opcode, 0 }, +{"th.vmsleu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSLEUVX, MASK_TH_VMSLEUVX, match_opcode, 0 }, +{"th.vmsleu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VMSLEUVI, MASK_TH_VMSLEUVI, match_opcode, 0 }, +{"th.vmsle.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMSLEVV, MASK_TH_VMSLEVV, match_opcode, 0 }, +{"th.vmsle.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSLEVX, MASK_TH_VMSLEVX, match_opcode, 0 }, +{"th.vmsle.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VMSLEVI, MASK_TH_VMSLEVI, match_opcode, 0 }, +{"th.vmsgtu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSGTUVX, MASK_TH_VMSGTUVX, match_opcode, 0 }, +{"th.vmsgtu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VMSGTUVI, MASK_TH_VMSGTUVI, match_opcode, 0 }, +{"th.vmsgt.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSGTVX, MASK_TH_VMSGTVX, match_opcode, 0 }, +{"th.vmsgt.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VMSGTVI, MASK_TH_VMSGTVI, match_opcode, 0 }, +{"th.vmsgt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMSLTVV, MASK_TH_VMSLTVV, match_opcode, INSN_ALIAS }, +{"th.vmsgtu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMSLTUVV, MASK_TH_VMSLTUVV, match_opcode, INSN_ALIAS }, +{"th.vmsge.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMSLEVV, MASK_TH_VMSLEVV, match_opcode, INSN_ALIAS }, +{"th.vmsgeu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMSLEUVV, MASK_TH_VMSLEUVV, match_opcode, INSN_ALIAS }, +{"th.vmslt.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_TH_VMSLEVI, MASK_TH_VMSLEVI, match_opcode, INSN_ALIAS }, +{"th.vmsltu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_TH_VMSLEUVI, MASK_TH_VMSLEUVI, match_opcode, INSN_ALIAS }, +{"th.vmsge.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_TH_VMSGTVI, MASK_TH_VMSGTVI, match_opcode, INSN_ALIAS }, +{"th.vmsgeu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_TH_VMSGTUVI, MASK_TH_VMSGTUVI, match_opcode, INSN_ALIAS }, +{"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO }, +{"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO }, +{"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 1, (int) M_VMSGE, match_never, INSN_MACRO }, +{"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 1, (int) M_VMSGE, match_never, INSN_MACRO }, +{"th.vminu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMINUVV, MASK_TH_VMINUVV, match_opcode, 0}, +{"th.vminu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMINUVX, MASK_TH_VMINUVX, match_opcode, 0}, +{"th.vmin.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMINVV, MASK_TH_VMINVV, match_opcode, 0}, +{"th.vmin.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMINVX, MASK_TH_VMINVX, match_opcode, 0}, +{"th.vmaxu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMAXUVV, MASK_TH_VMAXUVV, match_opcode, 0}, +{"th.vmaxu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMAXUVX, MASK_TH_VMAXUVX, match_opcode, 0}, +{"th.vmax.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMAXVV, MASK_TH_VMAXVV, match_opcode, 0}, +{"th.vmax.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMAXVX, MASK_TH_VMAXVX, match_opcode, 0}, +{"th.vmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMULVV, MASK_TH_VMULVV, match_opcode, 0 }, +{"th.vmul.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMULVX, MASK_TH_VMULVX, match_opcode, 0 }, +{"th.vmulh.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMULHVV, MASK_TH_VMULHVV, match_opcode, 0 }, +{"th.vmulh.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMULHVX, MASK_TH_VMULHVX, match_opcode, 0 }, +{"th.vmulhu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMULHUVV, MASK_TH_VMULHUVV, match_opcode, 0 }, +{"th.vmulhu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMULHUVX, MASK_TH_VMULHUVX, match_opcode, 0 }, +{"th.vmulhsu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMULHSUVV, MASK_TH_VMULHSUVV, match_opcode, 0 }, +{"th.vmulhsu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMULHSUVX, MASK_TH_VMULHSUVX, match_opcode, 0 }, +{"th.vwmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWMULVV, MASK_TH_VWMULVV, match_opcode, 0 }, +{"th.vwmul.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWMULVX, MASK_TH_VWMULVX, match_opcode, 0 }, +{"th.vwmulu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWMULUVV, MASK_TH_VWMULUVV, match_opcode, 0 }, +{"th.vwmulu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWMULUVX, MASK_TH_VWMULUVX, match_opcode, 0 }, +{"th.vwmulsu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWMULSUVV, MASK_TH_VWMULSUVV, match_opcode, 0 }, +{"th.vwmulsu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWMULSUVX, MASK_TH_VWMULSUVX, match_opcode, 0 }, +{"th.vmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMACCVV, MASK_TH_VMACCVV, match_opcode, 0}, +{"th.vmacc.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VMACCVX, MASK_TH_VMACCVX, match_opcode, 0}, +{"th.vnmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VNMSACVV, MASK_TH_VNMSACVV, match_opcode, 0}, +{"th.vnmsac.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VNMSACVX, MASK_TH_VNMSACVX, match_opcode, 0}, +{"th.vmadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMADDVV, MASK_TH_VMADDVV, match_opcode, 0}, +{"th.vmadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VMADDVX, MASK_TH_VMADDVX, match_opcode, 0}, +{"th.vnmsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VNMSUBVV, MASK_TH_VNMSUBVV, match_opcode, 0}, +{"th.vnmsub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VNMSUBVX, MASK_TH_VNMSUBVX, match_opcode, 0}, +{"th.vwmaccu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWMACCUVV, MASK_TH_VWMACCUVV, match_opcode, 0}, +{"th.vwmaccu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWMACCUVX, MASK_TH_VWMACCUVX, match_opcode, 0}, +{"th.vwmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWMACCVV, MASK_TH_VWMACCVV, match_opcode, 0}, +{"th.vwmacc.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWMACCVX, MASK_TH_VWMACCVX, match_opcode, 0}, +{"th.vwmaccsu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWMACCSUVV, MASK_TH_VWMACCSUVV, match_opcode, 0}, +{"th.vwmaccsu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWMACCSUVX, MASK_TH_VWMACCSUVX, match_opcode, 0}, +{"th.vwmaccus.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWMACCUSVX, MASK_TH_VWMACCUSVX, match_opcode, 0}, +{"th.vdivu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VDIVUVV, MASK_TH_VDIVUVV, match_opcode, 0 }, +{"th.vdivu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VDIVUVX, MASK_TH_VDIVUVX, match_opcode, 0 }, +{"th.vdiv.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VDIVVV, MASK_TH_VDIVVV, match_opcode, 0 }, +{"th.vdiv.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VDIVVX, MASK_TH_VDIVVX, match_opcode, 0 }, +{"th.vremu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREMUVV, MASK_TH_VREMUVV, match_opcode, 0 }, +{"th.vremu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VREMUVX, MASK_TH_VREMUVX, match_opcode, 0 }, +{"th.vrem.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREMVV, MASK_TH_VREMVV, match_opcode, 0 }, +{"th.vrem.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VREMVX, MASK_TH_VREMVX, match_opcode, 0 }, +{"th.vmerge.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_TH_VMERGEVVM, MASK_TH_VMERGEVVM, match_opcode, 0 }, +{"th.vmerge.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_TH_VMERGEVXM, MASK_TH_VMERGEVXM, match_opcode, 0 }, +{"th.vmerge.vim", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vi,V0", MATCH_TH_VMERGEVIM, MASK_TH_VMERGEVIM, match_opcode, 0 }, +{"th.vmv.v.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs", MATCH_TH_VMVVV, MASK_TH_VMVVV, match_opcode, 0 }, +{"th.vmv.v.x", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s", MATCH_TH_VMVVX, MASK_TH_VMVVX, match_opcode, 0 }, +{"th.vmv.v.i", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vi", MATCH_TH_VMVVI, MASK_TH_VMVVI, match_opcode, 0 }, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, From patchwork Fri Nov 10 07:31:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 79539 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0E8AB38582A9 for ; Fri, 10 Nov 2023 07:32:30 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from out30-97.freemail.mail.aliyun.com (out30-97.freemail.mail.aliyun.com [115.124.30.97]) by sourceware.org (Postfix) with ESMTPS id 33A063856DE6 for ; Fri, 10 Nov 2023 07:32:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 33A063856DE6 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 33A063856DE6 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.97 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699601536; cv=none; b=GTHtCOx7lycVRXx4/D0GM0znjPZo8Jbre7Pp2ADQcZprs2XO+lvhfIF+wM9bEVRuXNhJhRZ6+slRud+/IyklS9kCmcOp/hVDO6zpu5feklTaRIhA7cbk4/13kmq0GmYTjg0tXZuFgsdavE7+bN8DhDXLizznfLQ7dXWzpYQU6ms= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699601536; c=relaxed/simple; bh=UOfMBuJwOI3TN67wkdBzPMMM+cGEqVDLLYw/6bE39aM=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=W7IRfJfhUT79se8aW/0diaAGTOkvYM2HiOEZH0oH6ddMSleq3HgL+Fd4G5TbkRojCrMAgfdlQbJEwYu2jvRM2y/OOyapaCBWDX1ETmzGHFehqB/4eMBS1Q1769wBxl9OBjXRnMTbAc17QqVHae2ZY3dTE+CGiAfdeuxJp2t6oF8= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R211e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046056; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=6; SR=0; TI=SMTPD_---0Vw3dMcS_1699601526; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw3dMcS_1699601526) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:32:07 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 08/12] RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:31:56 +0800 Message-Id: <20231110073156.1961-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.4 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds fixed-point arithmetic instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for fixed-point arithmetic instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VSADDUVV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise. --- gas/testsuite/gas/riscv/x-thead-vector.d | 86 ++++++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 92 ++++++++++++++++++++++++ include/opcode/riscv-opc.h | 72 +++++++++++++++++++ opcodes/riscv-opc.c | 36 ++++++++++ 4 files changed, 286 insertions(+) diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index e3a1579300b..9a199177f37 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -464,3 +464,89 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+5e05c457[ ]+th.vmv.v.x[ ]+v8,a1 [ ]+[0-9a-f]+:[ ]+5e07b457[ ]+th.vmv.v.i[ ]+v8,15 [ ]+[0-9a-f]+:[ ]+5e083457[ ]+th.vmv.v.i[ ]+v8,-16 +[ ]+[0-9a-f]+:[ ]+82860257[ ]+th.vsaddu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+8285c257[ ]+th.vsaddu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+8287b257[ ]+th.vsaddu.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+82883257[ ]+th.vsaddu.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+80860257[ ]+th.vsaddu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+8085c257[ ]+th.vsaddu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+8087b257[ ]+th.vsaddu.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+80883257[ ]+th.vsaddu.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+86860257[ ]+th.vsadd.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+8685c257[ ]+th.vsadd.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+8687b257[ ]+th.vsadd.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+86883257[ ]+th.vsadd.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+84860257[ ]+th.vsadd.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+8485c257[ ]+th.vsadd.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+8487b257[ ]+th.vsadd.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+84883257[ ]+th.vsadd.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+8a860257[ ]+th.vssubu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+8a85c257[ ]+th.vssubu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+88860257[ ]+th.vssubu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+8885c257[ ]+th.vssubu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+8e860257[ ]+th.vssub.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+8e85c257[ ]+th.vssub.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+8c860257[ ]+th.vssub.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+8c85c257[ ]+th.vssub.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+92860257[ ]+th.vaadd.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+9285c257[ ]+th.vaadd.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+9287b257[ ]+th.vaadd.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+92883257[ ]+th.vaadd.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+90860257[ ]+th.vaadd.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+9085c257[ ]+th.vaadd.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+9087b257[ ]+th.vaadd.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+90883257[ ]+th.vaadd.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+9a860257[ ]+th.vasub.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+9a85c257[ ]+th.vasub.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+98860257[ ]+th.vasub.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+9885c257[ ]+th.vasub.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+9e860257[ ]+th.vsmul.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+9e85c257[ ]+th.vsmul.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+9c860257[ ]+th.vsmul.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+9c85c257[ ]+th.vsmul.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+f2860257[ ]+th.vwsmaccu.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+f285c257[ ]+th.vwsmaccu.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+f6860257[ ]+th.vwsmacc.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+f685c257[ ]+th.vwsmacc.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+fa860257[ ]+th.vwsmaccsu.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+fa85c257[ ]+th.vwsmaccsu.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+fe85c257[ ]+th.vwsmaccus.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+f0860257[ ]+th.vwsmaccu.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f085c257[ ]+th.vwsmaccu.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f4860257[ ]+th.vwsmacc.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f485c257[ ]+th.vwsmacc.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f8860257[ ]+th.vwsmaccsu.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f885c257[ ]+th.vwsmaccsu.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+fc85c257[ ]+th.vwsmaccus.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+aa860257[ ]+th.vssrl.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+aa85c257[ ]+th.vssrl.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+aa80b257[ ]+th.vssrl.vi[ ]+v4,v8,1 +[ ]+[0-9a-f]+:[ ]+aa8fb257[ ]+th.vssrl.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+a8860257[ ]+th.vssrl.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+a885c257[ ]+th.vssrl.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+a880b257[ ]+th.vssrl.vi[ ]+v4,v8,1,v0.t +[ ]+[0-9a-f]+:[ ]+a88fb257[ ]+th.vssrl.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+ae860257[ ]+th.vssra.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+ae85c257[ ]+th.vssra.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+ae80b257[ ]+th.vssra.vi[ ]+v4,v8,1 +[ ]+[0-9a-f]+:[ ]+ae8fb257[ ]+th.vssra.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+ac860257[ ]+th.vssra.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+ac85c257[ ]+th.vssra.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+ac80b257[ ]+th.vssra.vi[ ]+v4,v8,1,v0.t +[ ]+[0-9a-f]+:[ ]+ac8fb257[ ]+th.vssra.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+ba860257[ ]+th.vnclipu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+ba85c257[ ]+th.vnclipu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+ba80b257[ ]+th.vnclipu.vi[ ]+v4,v8,1 +[ ]+[0-9a-f]+:[ ]+ba8fb257[ ]+th.vnclipu.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+b8860257[ ]+th.vnclipu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+b885c257[ ]+th.vnclipu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+b880b257[ ]+th.vnclipu.vi[ ]+v4,v8,1,v0.t +[ ]+[0-9a-f]+:[ ]+b88fb257[ ]+th.vnclipu.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+be860257[ ]+th.vnclip.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+be85c257[ ]+th.vnclip.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+be80b257[ ]+th.vnclip.vi[ ]+v4,v8,1 +[ ]+[0-9a-f]+:[ ]+be8fb257[ ]+th.vnclip.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+bc860257[ ]+th.vnclip.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+bc85c257[ ]+th.vnclip.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+bc80b257[ ]+th.vnclip.vi[ ]+v4,v8,1,v0.t +[ ]+[0-9a-f]+:[ ]+bc8fb257[ ]+th.vnclip.vi[ ]+v4,v8,31,v0.t diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index 55887e0ce41..b2fbb0c343f 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -472,3 +472,95 @@ th.vmv.v.x v8, a1 th.vmv.v.i v8, 15 th.vmv.v.i v8, -16 + + th.vsaddu.vv v4, v8, v12 + th.vsaddu.vx v4, v8, a1 + th.vsaddu.vi v4, v8, 15 + th.vsaddu.vi v4, v8, -16 + th.vsaddu.vv v4, v8, v12, v0.t + th.vsaddu.vx v4, v8, a1, v0.t + th.vsaddu.vi v4, v8, 15, v0.t + th.vsaddu.vi v4, v8, -16, v0.t + th.vsadd.vv v4, v8, v12 + th.vsadd.vx v4, v8, a1 + th.vsadd.vi v4, v8, 15 + th.vsadd.vi v4, v8, -16 + th.vsadd.vv v4, v8, v12, v0.t + th.vsadd.vx v4, v8, a1, v0.t + th.vsadd.vi v4, v8, 15, v0.t + th.vsadd.vi v4, v8, -16, v0.t + th.vssubu.vv v4, v8, v12 + th.vssubu.vx v4, v8, a1 + th.vssubu.vv v4, v8, v12, v0.t + th.vssubu.vx v4, v8, a1, v0.t + th.vssub.vv v4, v8, v12 + th.vssub.vx v4, v8, a1 + th.vssub.vv v4, v8, v12, v0.t + th.vssub.vx v4, v8, a1, v0.t + + th.vaadd.vv v4, v8, v12 + th.vaadd.vx v4, v8, a1 + th.vaadd.vi v4, v8, 15 + th.vaadd.vi v4, v8, -16 + th.vaadd.vv v4, v8, v12, v0.t + th.vaadd.vx v4, v8, a1, v0.t + th.vaadd.vi v4, v8, 15, v0.t + th.vaadd.vi v4, v8, -16, v0.t + th.vasub.vv v4, v8, v12 + th.vasub.vx v4, v8, a1 + th.vasub.vv v4, v8, v12, v0.t + th.vasub.vx v4, v8, a1, v0.t + + th.vsmul.vv v4, v8, v12 + th.vsmul.vx v4, v8, a1 + th.vsmul.vv v4, v8, v12, v0.t + th.vsmul.vx v4, v8, a1, v0.t + + th.vwsmaccu.vv v4, v12, v8 + th.vwsmaccu.vx v4, a1, v8 + th.vwsmacc.vv v4, v12, v8 + th.vwsmacc.vx v4, a1, v8 + th.vwsmaccsu.vv v4, v12, v8 + th.vwsmaccsu.vx v4, a1, v8 + th.vwsmaccus.vx v4, a1, v8 + th.vwsmaccu.vv v4, v12, v8, v0.t + th.vwsmaccu.vx v4, a1, v8, v0.t + th.vwsmacc.vv v4, v12, v8, v0.t + th.vwsmacc.vx v4, a1, v8, v0.t + th.vwsmaccsu.vv v4, v12, v8, v0.t + th.vwsmaccsu.vx v4, a1, v8, v0.t + th.vwsmaccus.vx v4, a1, v8, v0.t + + th.vssrl.vv v4, v8, v12 + th.vssrl.vx v4, v8, a1 + th.vssrl.vi v4, v8, 1 + th.vssrl.vi v4, v8, 31 + th.vssrl.vv v4, v8, v12, v0.t + th.vssrl.vx v4, v8, a1, v0.t + th.vssrl.vi v4, v8, 1, v0.t + th.vssrl.vi v4, v8, 31, v0.t + th.vssra.vv v4, v8, v12 + th.vssra.vx v4, v8, a1 + th.vssra.vi v4, v8, 1 + th.vssra.vi v4, v8, 31 + th.vssra.vv v4, v8, v12, v0.t + th.vssra.vx v4, v8, a1, v0.t + th.vssra.vi v4, v8, 1, v0.t + th.vssra.vi v4, v8, 31, v0.t + + th.vnclipu.vv v4, v8, v12 + th.vnclipu.vx v4, v8, a1 + th.vnclipu.vi v4, v8, 1 + th.vnclipu.vi v4, v8, 31 + th.vnclipu.vv v4, v8, v12, v0.t + th.vnclipu.vx v4, v8, a1, v0.t + th.vnclipu.vi v4, v8, 1, v0.t + th.vnclipu.vi v4, v8, 31, v0.t + th.vnclip.vv v4, v8, v12 + th.vnclip.vx v4, v8, a1 + th.vnclip.vi v4, v8, 1 + th.vnclip.vi v4, v8, 31 + th.vnclip.vv v4, v8, v12, v0.t + th.vnclip.vx v4, v8, a1, v0.t + th.vnclip.vi v4, v8, 1, v0.t + th.vnclip.vi v4, v8, 31, v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 553f3142ed8..059b2fa68bb 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3599,6 +3599,78 @@ #define MASK_TH_VMVVX 0xfff0707f #define MATCH_TH_VMVVI 0x5e003057 #define MASK_TH_VMVVI 0xfff0707f +#define MATCH_TH_VSADDUVV 0x80000057 +#define MASK_TH_VSADDUVV 0xfc00707f +#define MATCH_TH_VSADDUVX 0x80004057 +#define MASK_TH_VSADDUVX 0xfc00707f +#define MATCH_TH_VSADDUVI 0x80003057 +#define MASK_TH_VSADDUVI 0xfc00707f +#define MATCH_TH_VSADDVV 0x84000057 +#define MASK_TH_VSADDVV 0xfc00707f +#define MATCH_TH_VSADDVX 0x84004057 +#define MASK_TH_VSADDVX 0xfc00707f +#define MATCH_TH_VSADDVI 0x84003057 +#define MASK_TH_VSADDVI 0xfc00707f +#define MATCH_TH_VSSUBUVV 0x88000057 +#define MASK_TH_VSSUBUVV 0xfc00707f +#define MATCH_TH_VSSUBUVX 0x88004057 +#define MASK_TH_VSSUBUVX 0xfc00707f +#define MATCH_TH_VSSUBVV 0x8c000057 +#define MASK_TH_VSSUBVV 0xfc00707f +#define MATCH_TH_VSSUBVX 0x8c004057 +#define MASK_TH_VSSUBVX 0xfc00707f +#define MATCH_TH_VAADDVV 0x90000057 +#define MASK_TH_VAADDVV 0xfc00707f +#define MATCH_TH_VAADDVX 0x90004057 +#define MASK_TH_VAADDVX 0xfc00707f +#define MATCH_TH_VAADDVI 0x90003057 +#define MASK_TH_VAADDVI 0xfc00707f +#define MATCH_TH_VASUBVV 0x98000057 +#define MASK_TH_VASUBVV 0xfc00707f +#define MATCH_TH_VASUBVX 0x98004057 +#define MASK_TH_VASUBVX 0xfc00707f +#define MATCH_TH_VSMULVV 0x9c000057 +#define MASK_TH_VSMULVV 0xfc00707f +#define MATCH_TH_VSMULVX 0x9c004057 +#define MASK_TH_VSMULVX 0xfc00707f +#define MATCH_TH_VWSMACCUVV 0xf0000057 +#define MASK_TH_VWSMACCUVV 0xfc00707f +#define MATCH_TH_VWSMACCUVX 0xf0004057 +#define MASK_TH_VWSMACCUVX 0xfc00707f +#define MATCH_TH_VWSMACCVV 0xf4000057 +#define MASK_TH_VWSMACCVV 0xfc00707f +#define MATCH_TH_VWSMACCVX 0xf4004057 +#define MASK_TH_VWSMACCVX 0xfc00707f +#define MATCH_TH_VWSMACCSUVV 0xf8000057 +#define MASK_TH_VWSMACCSUVV 0xfc00707f +#define MATCH_TH_VWSMACCSUVX 0xf8004057 +#define MASK_TH_VWSMACCSUVX 0xfc00707f +#define MATCH_TH_VWSMACCUSVX 0xfc004057 +#define MASK_TH_VWSMACCUSVX 0xfc00707f +#define MATCH_TH_VSSRLVV 0xa8000057 +#define MASK_TH_VSSRLVV 0xfc00707f +#define MATCH_TH_VSSRLVX 0xa8004057 +#define MASK_TH_VSSRLVX 0xfc00707f +#define MATCH_TH_VSSRLVI 0xa8003057 +#define MASK_TH_VSSRLVI 0xfc00707f +#define MATCH_TH_VSSRAVV 0xac000057 +#define MASK_TH_VSSRAVV 0xfc00707f +#define MATCH_TH_VSSRAVX 0xac004057 +#define MASK_TH_VSSRAVX 0xfc00707f +#define MATCH_TH_VSSRAVI 0xac003057 +#define MASK_TH_VSSRAVI 0xfc00707f +#define MATCH_TH_VNCLIPUVV 0xb8000057 +#define MASK_TH_VNCLIPUVV 0xfc00707f +#define MATCH_TH_VNCLIPUVX 0xb8004057 +#define MASK_TH_VNCLIPUVX 0xfc00707f +#define MATCH_TH_VNCLIPUVI 0xb8003057 +#define MASK_TH_VNCLIPUVI 0xfc00707f +#define MATCH_TH_VNCLIPVV 0xbc000057 +#define MASK_TH_VNCLIPVV 0xfc00707f +#define MATCH_TH_VNCLIPVX 0xbc004057 +#define MASK_TH_VNCLIPVX 0xfc00707f +#define MATCH_TH_VNCLIPVI 0xbc003057 +#define MASK_TH_VNCLIPVI 0xfc00707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index bd7b866358f..c7d6d171902 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2722,6 +2722,42 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vmv.v.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs", MATCH_TH_VMVVV, MASK_TH_VMVVV, match_opcode, 0 }, {"th.vmv.v.x", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s", MATCH_TH_VMVVX, MASK_TH_VMVVX, match_opcode, 0 }, {"th.vmv.v.i", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vi", MATCH_TH_VMVVI, MASK_TH_VMVVI, match_opcode, 0 }, +{"th.vsaddu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSADDUVV, MASK_TH_VSADDUVV, match_opcode, 0 }, +{"th.vsaddu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSADDUVX, MASK_TH_VSADDUVX, match_opcode, 0 }, +{"th.vsaddu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VSADDUVI, MASK_TH_VSADDUVI, match_opcode, 0 }, +{"th.vsadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSADDVV, MASK_TH_VSADDVV, match_opcode, 0 }, +{"th.vsadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSADDVX, MASK_TH_VSADDVX, match_opcode, 0 }, +{"th.vsadd.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VSADDVI, MASK_TH_VSADDVI, match_opcode, 0 }, +{"th.vssubu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSSUBUVV, MASK_TH_VSSUBUVV, match_opcode, 0 }, +{"th.vssubu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSSUBUVX, MASK_TH_VSSUBUVX, match_opcode, 0 }, +{"th.vssub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSSUBVV, MASK_TH_VSSUBVV, match_opcode, 0 }, +{"th.vssub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSSUBVX, MASK_TH_VSSUBVX, match_opcode, 0 }, +{"th.vaadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VAADDVV, MASK_TH_VAADDVV, match_opcode, 0 }, +{"th.vaadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VAADDVX, MASK_TH_VAADDVX, match_opcode, 0 }, +{"th.vaadd.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VAADDVI, MASK_TH_VAADDVI, match_opcode, 0 }, +{"th.vasub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VASUBVV, MASK_TH_VASUBVV, match_opcode, 0 }, +{"th.vasub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VASUBVX, MASK_TH_VASUBVX, match_opcode, 0 }, +{"th.vsmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSMULVV, MASK_TH_VSMULVV, match_opcode, 0 }, +{"th.vsmul.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSMULVX, MASK_TH_VSMULVX, match_opcode, 0 }, +{"th.vwsmaccu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWSMACCUVV, MASK_TH_VWSMACCUVV, match_opcode, 0 }, +{"th.vwsmaccu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWSMACCUVX, MASK_TH_VWSMACCUVX, match_opcode, 0 }, +{"th.vwsmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWSMACCVV, MASK_TH_VWSMACCVV, match_opcode, 0 }, +{"th.vwsmacc.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWSMACCVX, MASK_TH_VWSMACCVX, match_opcode, 0 }, +{"th.vwsmaccsu.vv",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWSMACCSUVV, MASK_TH_VWSMACCSUVV, match_opcode, 0 }, +{"th.vwsmaccsu.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWSMACCSUVX, MASK_TH_VWSMACCSUVX, match_opcode, 0 }, +{"th.vwsmaccus.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWSMACCUSVX, MASK_TH_VWSMACCUSVX, match_opcode, 0 }, +{"th.vssrl.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSSRLVV, MASK_TH_VSSRLVV, match_opcode, 0 }, +{"th.vssrl.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSSRLVX, MASK_TH_VSSRLVX, match_opcode, 0 }, +{"th.vssrl.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSSRLVI, MASK_TH_VSSRLVI, match_opcode, 0 }, +{"th.vssra.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSSRAVV, MASK_TH_VSSRAVV, match_opcode, 0 }, +{"th.vssra.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSSRAVX, MASK_TH_VSSRAVX, match_opcode, 0 }, +{"th.vssra.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSSRAVI, MASK_TH_VSSRAVI, match_opcode, 0 }, +{"th.vnclipu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VNCLIPUVV, MASK_TH_VNCLIPUVV, match_opcode, 0 }, +{"th.vnclipu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VNCLIPUVX, MASK_TH_VNCLIPUVX, match_opcode, 0 }, +{"th.vnclipu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VNCLIPUVI, MASK_TH_VNCLIPUVI, match_opcode, 0 }, +{"th.vnclip.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VNCLIPVV, MASK_TH_VNCLIPVV, match_opcode, 0 }, +{"th.vnclip.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VNCLIPVX, MASK_TH_VNCLIPVX, match_opcode, 0 }, +{"th.vnclip.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VNCLIPVI, MASK_TH_VNCLIPVI, match_opcode, 0 }, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, From patchwork Fri Nov 10 07:32:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 79540 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 53AF83857004 for ; Fri, 10 Nov 2023 07:33:34 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from out30-110.freemail.mail.aliyun.com (out30-110.freemail.mail.aliyun.com [115.124.30.110]) by sourceware.org (Postfix) with ESMTPS id 304A73858D38 for ; Fri, 10 Nov 2023 07:33:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 304A73858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 304A73858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.110 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699601598; cv=none; b=Vsfch/1/tNM80P2n5RRV1nWI0RdKgfIMly7DCATwaOyUQ+5V8qDQBXHK7xBG5tbK3TpYXIWshRtKkoCk0tlBkmTWcAjIzTEZ0/c9IX5VnXy+8S+yJmznSLh6beALm30JY/MSghYt7VVLIdfSDTdjK7P/TRUfv0To2ovYdQKt2r4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699601598; c=relaxed/simple; bh=Z61uQT3TjNocd3WoPBhJYGKeI/pjBuKVWrdKwITemyQ=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=JJtrJ9KKe/civlV7QrMGw7+TIM736DXdYWr6CPqHhXA9c9b1x+OBgBmXgO/26iGRCwC5NMzGhoNsyM8KRt768Olmaq6cBKQ/ETdvbUIH8s7kVnbdKk+QrWxZgSeycK0Dx/4AcMPaSu22pzHAeYM1fkuqj5cX+v4/mulNvxTlX5U= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R161e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046060; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=6; SR=0; TI=SMTPD_---0Vw3kl07_1699601575; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw3kl07_1699601575) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:32:56 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 09/12] RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:32:47 +0800 Message-Id: <20231110073247.2005-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.6 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds floating-point arithmetic instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for floating-point arithmetic instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VFADDVV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise. --- gas/testsuite/gas/riscv/x-thead-vector.d | 170 ++++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 188 +++++++++++++++++++++++ include/opcode/riscv-opc.h | 168 ++++++++++++++++++++ opcodes/riscv-opc.c | 86 +++++++++++ 4 files changed, 612 insertions(+) diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index 9a199177f37..09e4a9c2f73 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -550,3 +550,173 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+bc85c257[ ]+th.vnclip.vx[ ]+v4,v8,a1,v0.t [ ]+[0-9a-f]+:[ ]+bc80b257[ ]+th.vnclip.vi[ ]+v4,v8,1,v0.t [ ]+[0-9a-f]+:[ ]+bc8fb257[ ]+th.vnclip.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+02861257[ ]+th.vfadd.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+02865257[ ]+th.vfadd.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+00861257[ ]+th.vfadd.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+00865257[ ]+th.vfadd.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+0a861257[ ]+th.vfsub.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+0a865257[ ]+th.vfsub.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+08861257[ ]+th.vfsub.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+08865257[ ]+th.vfsub.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+9e865257[ ]+th.vfrsub.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+9c865257[ ]+th.vfrsub.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+c2861257[ ]+th.vfwadd.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+c2865257[ ]+th.vfwadd.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+c0861257[ ]+th.vfwadd.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+c0865257[ ]+th.vfwadd.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+ca861257[ ]+th.vfwsub.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+ca865257[ ]+th.vfwsub.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+c8861257[ ]+th.vfwsub.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+c8865257[ ]+th.vfwsub.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+d2861257[ ]+th.vfwadd.wv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+d2865257[ ]+th.vfwadd.wf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+d0861257[ ]+th.vfwadd.wv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+d0865257[ ]+th.vfwadd.wf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+da861257[ ]+th.vfwsub.wv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+da865257[ ]+th.vfwsub.wf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+d8861257[ ]+th.vfwsub.wv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+d8865257[ ]+th.vfwsub.wf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+92861257[ ]+th.vfmul.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+92865257[ ]+th.vfmul.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+90861257[ ]+th.vfmul.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+90865257[ ]+th.vfmul.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+82861257[ ]+th.vfdiv.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+82865257[ ]+th.vfdiv.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+80861257[ ]+th.vfdiv.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+80865257[ ]+th.vfdiv.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+86865257[ ]+th.vfrdiv.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+84865257[ ]+th.vfrdiv.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+e2861257[ ]+th.vfwmul.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+e2865257[ ]+th.vfwmul.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+e0861257[ ]+th.vfwmul.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+e0865257[ ]+th.vfwmul.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+a2861257[ ]+th.vfmadd.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+a2865257[ ]+th.vfmadd.vf[ ]+v4,fa2,v8 +[ ]+[0-9a-f]+:[ ]+a6861257[ ]+th.vfnmadd.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+a6865257[ ]+th.vfnmadd.vf[ ]+v4,fa2,v8 +[ ]+[0-9a-f]+:[ ]+aa861257[ ]+th.vfmsub.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+aa865257[ ]+th.vfmsub.vf[ ]+v4,fa2,v8 +[ ]+[0-9a-f]+:[ ]+ae861257[ ]+th.vfnmsub.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+ae865257[ ]+th.vfnmsub.vf[ ]+v4,fa2,v8 +[ ]+[0-9a-f]+:[ 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]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+b0865257[ ]+th.vfmacc.vf[ ]+v4,fa2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+b4861257[ ]+th.vfnmacc.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+b4865257[ ]+th.vfnmacc.vf[ ]+v4,fa2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+b8861257[ ]+th.vfmsac.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+b8865257[ ]+th.vfmsac.vf[ ]+v4,fa2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+bc861257[ ]+th.vfnmsac.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+bc865257[ ]+th.vfnmsac.vf[ ]+v4,fa2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f2861257[ ]+th.vfwmacc.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+f2865257[ ]+th.vfwmacc.vf[ ]+v4,fa2,v8 +[ ]+[0-9a-f]+:[ ]+f6861257[ ]+th.vfwnmacc.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+f6865257[ ]+th.vfwnmacc.vf[ ]+v4,fa2,v8 +[ ]+[0-9a-f]+:[ ]+fa861257[ ]+th.vfwmsac.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+fa865257[ ]+th.vfwmsac.vf[ ]+v4,fa2,v8 +[ ]+[0-9a-f]+:[ ]+fe861257[ ]+th.vfwnmsac.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+fe865257[ ]+th.vfwnmsac.vf[ ]+v4,fa2,v8 +[ ]+[0-9a-f]+:[ ]+f0861257[ ]+th.vfwmacc.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f0865257[ ]+th.vfwmacc.vf[ ]+v4,fa2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f4861257[ ]+th.vfwnmacc.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f4865257[ ]+th.vfwnmacc.vf[ ]+v4,fa2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f8861257[ ]+th.vfwmsac.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f8865257[ ]+th.vfwmsac.vf[ ]+v4,fa2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+fc861257[ ]+th.vfwnmsac.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+fc865257[ ]+th.vfwnmsac.vf[ ]+v4,fa2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+8e801257[ ]+th.vfsqrt.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8c801257[ ]+th.vfsqrt.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+12861257[ ]+th.vfmin.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+12865257[ ]+th.vfmin.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+1a861257[ ]+th.vfmax.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+1a865257[ ]+th.vfmax.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+10861257[ ]+th.vfmin.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+10865257[ ]+th.vfmin.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+18861257[ ]+th.vfmax.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+18865257[ ]+th.vfmax.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+22861257[ ]+th.vfsgnj.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+22865257[ ]+th.vfsgnj.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+26861257[ ]+th.vfsgnjn.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+26865257[ ]+th.vfsgnjn.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+2a861257[ ]+th.vfsgnjx.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+2a865257[ ]+th.vfsgnjx.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+20861257[ ]+th.vfsgnj.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+20865257[ ]+th.vfsgnj.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+24861257[ ]+th.vfsgnjn.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+24865257[ ]+th.vfsgnjn.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+28861257[ ]+th.vfsgnjx.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+28865257[ ]+th.vfsgnjx.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+6ec41257[ ]+th.vmflt.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+66c41257[ ]+th.vmfle.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+6cc41257[ ]+th.vmflt.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+64c41257[ ]+th.vmfle.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+62861257[ ]+th.vmfeq.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+62865257[ ]+th.vmfeq.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+72861257[ ]+th.vmfne.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+72865257[ ]+th.vmfne.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+6e861257[ ]+th.vmflt.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+6e865257[ ]+th.vmflt.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+66861257[ ]+th.vmfle.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+66865257[ ]+th.vmfle.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+76865257[ ]+th.vmfgt.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+7e865257[ ]+th.vmfge.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+60861257[ ]+th.vmfeq.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+60865257[ ]+th.vmfeq.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+70861257[ ]+th.vmfne.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+70865257[ ]+th.vmfne.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+6c861257[ ]+th.vmflt.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+6c865257[ ]+th.vmflt.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+64861257[ ]+th.vmfle.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+64865257[ ]+th.vmfle.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+74865257[ ]+th.vmfgt.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+7c865257[ ]+th.vmfge.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+6a861257[ ]+th.vmford.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+6a865257[ ]+th.vmford.vf[ ]+v4,v8,fa2 +[ ]+[0-9a-f]+:[ ]+68861257[ ]+th.vmford.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+68865257[ ]+th.vmford.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+8e881257[ ]+th.vfclass.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8c881257[ ]+th.vfclass.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+5c865257[ ]+th.vfmerge.vfm[ ]+v4,v8,fa2,v0 +[ ]+[0-9a-f]+:[ ]+5e05d257[ ]+th.vfmv.v.f[ ]+v4,fa1 +[ ]+[0-9a-f]+:[ ]+8a801257[ ]+th.vfcvt.xu.f.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8a809257[ ]+th.vfcvt.x.f.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8a811257[ ]+th.vfcvt.f.xu.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8a819257[ ]+th.vfcvt.f.x.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+88801257[ ]+th.vfcvt.xu.f.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+88809257[ ]+th.vfcvt.x.f.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+88811257[ ]+th.vfcvt.f.xu.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+88819257[ ]+th.vfcvt.f.x.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+8a841257[ ]+th.vfwcvt.xu.f.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8a849257[ ]+th.vfwcvt.x.f.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8a851257[ ]+th.vfwcvt.f.xu.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8a859257[ ]+th.vfwcvt.f.x.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8a861257[ ]+th.vfwcvt.f.f.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+88841257[ ]+th.vfwcvt.xu.f.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+88849257[ ]+th.vfwcvt.x.f.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+88851257[ ]+th.vfwcvt.f.xu.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+88859257[ ]+th.vfwcvt.f.x.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+88861257[ ]+th.vfwcvt.f.f.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+8a881257[ ]+th.vfncvt.xu.f.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8a889257[ ]+th.vfncvt.x.f.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8a891257[ ]+th.vfncvt.f.xu.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8a899257[ ]+th.vfncvt.f.x.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8a8a1257[ ]+th.vfncvt.f.f.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+88881257[ ]+th.vfncvt.xu.f.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+88889257[ ]+th.vfncvt.x.f.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+88891257[ ]+th.vfncvt.f.xu.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+88899257[ ]+th.vfncvt.f.x.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+888a1257[ ]+th.vfncvt.f.f.v[ ]+v4,v8,v0.t diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index b2fbb0c343f..f7de24fdd63 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -564,3 +564,191 @@ th.vnclip.vx v4, v8, a1, v0.t th.vnclip.vi v4, v8, 1, v0.t th.vnclip.vi v4, v8, 31, v0.t + + th.vfadd.vv v4, v8, v12 + th.vfadd.vf v4, v8, fa2 + th.vfadd.vv v4, v8, v12, v0.t + th.vfadd.vf v4, v8, fa2, v0.t + th.vfsub.vv v4, v8, v12 + th.vfsub.vf v4, v8, fa2 + th.vfsub.vv v4, v8, v12, v0.t + th.vfsub.vf v4, v8, fa2, v0.t + th.vfrsub.vf v4, v8, fa2 + th.vfrsub.vf v4, v8, fa2, v0.t + + th.vfwadd.vv v4, v8, v12 + th.vfwadd.vf v4, v8, fa2 + th.vfwadd.vv v4, v8, v12, v0.t + th.vfwadd.vf v4, v8, fa2, v0.t + th.vfwsub.vv v4, v8, v12 + th.vfwsub.vf v4, v8, fa2 + th.vfwsub.vv v4, v8, v12, v0.t + th.vfwsub.vf v4, v8, fa2, v0.t + th.vfwadd.wv v4, v8, v12 + th.vfwadd.wf v4, v8, fa2 + th.vfwadd.wv v4, v8, v12, v0.t + th.vfwadd.wf v4, v8, fa2, v0.t + th.vfwsub.wv v4, v8, v12 + th.vfwsub.wf v4, v8, fa2 + th.vfwsub.wv v4, v8, v12, v0.t + th.vfwsub.wf v4, v8, fa2, v0.t + + th.vfmul.vv v4, v8, v12 + th.vfmul.vf v4, v8, fa2 + th.vfmul.vv v4, v8, v12, v0.t + th.vfmul.vf v4, v8, fa2, v0.t + th.vfdiv.vv v4, v8, v12 + th.vfdiv.vf v4, v8, fa2 + th.vfdiv.vv v4, v8, v12, v0.t + th.vfdiv.vf v4, v8, fa2, v0.t + th.vfrdiv.vf v4, v8, fa2 + th.vfrdiv.vf v4, v8, fa2, v0.t + + th.vfwmul.vv v4, v8, v12 + th.vfwmul.vf v4, v8, fa2 + th.vfwmul.vv v4, v8, v12, v0.t + th.vfwmul.vf v4, v8, fa2, v0.t + + th.vfmadd.vv v4, v12, v8 + th.vfmadd.vf v4, fa2, v8 + th.vfnmadd.vv v4, v12, v8 + th.vfnmadd.vf v4, fa2, v8 + th.vfmsub.vv v4, v12, v8 + th.vfmsub.vf v4, fa2, v8 + th.vfnmsub.vv v4, v12, v8 + th.vfnmsub.vf v4, fa2, v8 + th.vfmadd.vv v4, v12, v8, v0.t + th.vfmadd.vf v4, fa2, v8, v0.t + th.vfnmadd.vv v4, v12, v8, v0.t + th.vfnmadd.vf v4, fa2, v8, v0.t + th.vfmsub.vv v4, v12, v8, v0.t + th.vfmsub.vf v4, fa2, v8, v0.t + th.vfnmsub.vv v4, v12, v8, v0.t + th.vfnmsub.vf v4, fa2, v8, v0.t + th.vfmacc.vv v4, v12, v8 + th.vfmacc.vf v4, fa2, v8 + th.vfnmacc.vv v4, v12, v8 + th.vfnmacc.vf v4, fa2, v8 + th.vfmsac.vv v4, v12, v8 + th.vfmsac.vf v4, fa2, v8 + th.vfnmsac.vv v4, v12, v8 + th.vfnmsac.vf v4, fa2, v8 + th.vfmacc.vv v4, v12, v8, v0.t + th.vfmacc.vf v4, fa2, v8, v0.t + th.vfnmacc.vv v4, v12, v8, v0.t + th.vfnmacc.vf v4, fa2, v8, v0.t + th.vfmsac.vv v4, v12, v8, v0.t + th.vfmsac.vf v4, fa2, v8, v0.t + th.vfnmsac.vv v4, v12, v8, v0.t + th.vfnmsac.vf v4, fa2, v8, v0.t + + th.vfwmacc.vv v4, v12, v8 + th.vfwmacc.vf v4, fa2, v8 + th.vfwnmacc.vv v4, v12, v8 + th.vfwnmacc.vf v4, fa2, v8 + th.vfwmsac.vv v4, v12, v8 + th.vfwmsac.vf v4, fa2, v8 + th.vfwnmsac.vv v4, v12, v8 + th.vfwnmsac.vf v4, fa2, v8 + th.vfwmacc.vv v4, v12, v8, v0.t + th.vfwmacc.vf v4, fa2, v8, v0.t + th.vfwnmacc.vv v4, v12, v8, v0.t + th.vfwnmacc.vf v4, fa2, v8, v0.t + th.vfwmsac.vv v4, v12, v8, v0.t + th.vfwmsac.vf v4, fa2, v8, v0.t + th.vfwnmsac.vv v4, v12, v8, v0.t + th.vfwnmsac.vf v4, fa2, v8, v0.t + + th.vfsqrt.v v4, v8 + th.vfsqrt.v v4, v8, v0.t + + th.vfmin.vv v4, v8, v12 + th.vfmin.vf v4, v8, fa2 + th.vfmax.vv v4, v8, v12 + th.vfmax.vf v4, v8, fa2 + th.vfmin.vv v4, v8, v12, v0.t + th.vfmin.vf v4, v8, fa2, v0.t + th.vfmax.vv v4, v8, v12, v0.t + th.vfmax.vf v4, v8, fa2, v0.t + + th.vfsgnj.vv v4, v8, v12 + th.vfsgnj.vf v4, v8, fa2 + th.vfsgnjn.vv v4, v8, v12 + th.vfsgnjn.vf v4, v8, fa2 + th.vfsgnjx.vv v4, v8, v12 + th.vfsgnjx.vf v4, v8, fa2 + th.vfsgnj.vv v4, v8, v12, v0.t + th.vfsgnj.vf v4, v8, fa2, v0.t + th.vfsgnjn.vv v4, v8, v12, v0.t + th.vfsgnjn.vf v4, v8, fa2, v0.t + th.vfsgnjx.vv v4, v8, v12, v0.t + th.vfsgnjx.vf v4, v8, fa2, v0.t + + # Aliases + th.vmfgt.vv v4, v8, v12 + th.vmfge.vv v4, v8, v12 + th.vmfgt.vv v4, v8, v12, v0.t + th.vmfge.vv v4, v8, v12, v0.t + + th.vmfeq.vv v4, v8, v12 + th.vmfeq.vf v4, v8, fa2 + th.vmfne.vv v4, v8, v12 + th.vmfne.vf v4, v8, fa2 + th.vmflt.vv v4, v8, v12 + th.vmflt.vf v4, v8, fa2 + th.vmfle.vv v4, v8, v12 + th.vmfle.vf v4, v8, fa2 + th.vmfgt.vf v4, v8, fa2 + th.vmfge.vf v4, v8, fa2 + th.vmfeq.vv v4, v8, v12, v0.t + th.vmfeq.vf v4, v8, fa2, v0.t + th.vmfne.vv v4, v8, v12, v0.t + th.vmfne.vf v4, v8, fa2, v0.t + th.vmflt.vv v4, v8, v12, v0.t + th.vmflt.vf v4, v8, fa2, v0.t + th.vmfle.vv v4, v8, v12, v0.t + th.vmfle.vf v4, v8, fa2, v0.t + th.vmfgt.vf v4, v8, fa2, v0.t + th.vmfge.vf v4, v8, fa2, v0.t + + th.vmford.vv v4, v8, v12 + th.vmford.vf v4, v8, fa2 + th.vmford.vv v4, v8, v12, v0.t + th.vmford.vf v4, v8, fa2, v0.t + + th.vfclass.v v4, v8 + th.vfclass.v v4, v8, v0.t + + th.vfmerge.vfm v4, v8, fa2, v0 + th.vfmv.v.f v4, fa1 + + th.vfcvt.xu.f.v v4, v8 + th.vfcvt.x.f.v v4, v8 + th.vfcvt.f.xu.v v4, v8 + th.vfcvt.f.x.v v4, v8 + th.vfcvt.xu.f.v v4, v8, v0.t + th.vfcvt.x.f.v v4, v8, v0.t + th.vfcvt.f.xu.v v4, v8, v0.t + th.vfcvt.f.x.v v4, v8, v0.t + + th.vfwcvt.xu.f.v v4, v8 + th.vfwcvt.x.f.v v4, v8 + th.vfwcvt.f.xu.v v4, v8 + th.vfwcvt.f.x.v v4, v8 + th.vfwcvt.f.f.v v4, v8 + th.vfwcvt.xu.f.v v4, v8, v0.t + th.vfwcvt.x.f.v v4, v8, v0.t + th.vfwcvt.f.xu.v v4, v8, v0.t + th.vfwcvt.f.x.v v4, v8, v0.t + th.vfwcvt.f.f.v v4, v8, v0.t + + th.vfncvt.xu.f.v v4, v8 + th.vfncvt.x.f.v v4, v8 + th.vfncvt.f.xu.v v4, v8 + th.vfncvt.f.x.v v4, v8 + th.vfncvt.f.f.v v4, v8 + th.vfncvt.xu.f.v v4, v8, v0.t + th.vfncvt.x.f.v v4, v8, v0.t + th.vfncvt.f.xu.v v4, v8, v0.t + th.vfncvt.f.x.v v4, v8, v0.t + th.vfncvt.f.f.v v4, v8, v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 059b2fa68bb..2ec07a0b2a5 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3671,6 +3671,174 @@ #define MASK_TH_VNCLIPVX 0xfc00707f #define MATCH_TH_VNCLIPVI 0xbc003057 #define MASK_TH_VNCLIPVI 0xfc00707f +#define MATCH_TH_VFADDVV 0x00001057 +#define MASK_TH_VFADDVV 0xfc00707f +#define MATCH_TH_VFADDVF 0x00005057 +#define MASK_TH_VFADDVF 0xfc00707f +#define MATCH_TH_VFSUBVV 0x08001057 +#define MASK_TH_VFSUBVV 0xfc00707f +#define MATCH_TH_VFSUBVF 0x08005057 +#define MASK_TH_VFSUBVF 0xfc00707f +#define MATCH_TH_VFRSUBVF 0x9c005057 +#define MASK_TH_VFRSUBVF 0xfc00707f +#define MATCH_TH_VFWADDVV 0xc0001057 +#define MASK_TH_VFWADDVV 0xfc00707f +#define MATCH_TH_VFWADDVF 0xc0005057 +#define MASK_TH_VFWADDVF 0xfc00707f +#define MATCH_TH_VFWSUBVV 0xc8001057 +#define MASK_TH_VFWSUBVV 0xfc00707f +#define MATCH_TH_VFWSUBVF 0xc8005057 +#define MASK_TH_VFWSUBVF 0xfc00707f +#define MATCH_TH_VFWADDWV 0xd0001057 +#define MASK_TH_VFWADDWV 0xfc00707f +#define MATCH_TH_VFWADDWF 0xd0005057 +#define MASK_TH_VFWADDWF 0xfc00707f +#define MATCH_TH_VFWSUBWV 0xd8001057 +#define MASK_TH_VFWSUBWV 0xfc00707f +#define MATCH_TH_VFWSUBWF 0xd8005057 +#define MASK_TH_VFWSUBWF 0xfc00707f +#define MATCH_TH_VFMULVV 0x90001057 +#define MASK_TH_VFMULVV 0xfc00707f +#define MATCH_TH_VFMULVF 0x90005057 +#define MASK_TH_VFMULVF 0xfc00707f +#define MATCH_TH_VFDIVVV 0x80001057 +#define MASK_TH_VFDIVVV 0xfc00707f +#define MATCH_TH_VFDIVVF 0x80005057 +#define MASK_TH_VFDIVVF 0xfc00707f +#define MATCH_TH_VFRDIVVF 0x84005057 +#define MASK_TH_VFRDIVVF 0xfc00707f +#define MATCH_TH_VFWMULVV 0xe0001057 +#define MASK_TH_VFWMULVV 0xfc00707f +#define MATCH_TH_VFWMULVF 0xe0005057 +#define MASK_TH_VFWMULVF 0xfc00707f +#define MATCH_TH_VFMADDVV 0xa0001057 +#define MASK_TH_VFMADDVV 0xfc00707f +#define MATCH_TH_VFMADDVF 0xa0005057 +#define MASK_TH_VFMADDVF 0xfc00707f +#define MATCH_TH_VFNMADDVV 0xa4001057 +#define MASK_TH_VFNMADDVV 0xfc00707f +#define MATCH_TH_VFNMADDVF 0xa4005057 +#define MASK_TH_VFNMADDVF 0xfc00707f +#define MATCH_TH_VFMSUBVV 0xa8001057 +#define MASK_TH_VFMSUBVV 0xfc00707f +#define MATCH_TH_VFMSUBVF 0xa8005057 +#define MASK_TH_VFMSUBVF 0xfc00707f +#define MATCH_TH_VFNMSUBVV 0xac001057 +#define MASK_TH_VFNMSUBVV 0xfc00707f +#define MATCH_TH_VFNMSUBVF 0xac005057 +#define MASK_TH_VFNMSUBVF 0xfc00707f +#define MATCH_TH_VFMACCVV 0xb0001057 +#define MASK_TH_VFMACCVV 0xfc00707f +#define MATCH_TH_VFMACCVF 0xb0005057 +#define MASK_TH_VFMACCVF 0xfc00707f +#define MATCH_TH_VFNMACCVV 0xb4001057 +#define MASK_TH_VFNMACCVV 0xfc00707f +#define MATCH_TH_VFNMACCVF 0xb4005057 +#define MASK_TH_VFNMACCVF 0xfc00707f +#define MATCH_TH_VFMSACVV 0xb8001057 +#define MASK_TH_VFMSACVV 0xfc00707f +#define MATCH_TH_VFMSACVF 0xb8005057 +#define MASK_TH_VFMSACVF 0xfc00707f +#define MATCH_TH_VFNMSACVV 0xbc001057 +#define MASK_TH_VFNMSACVV 0xfc00707f +#define MATCH_TH_VFNMSACVF 0xbc005057 +#define MASK_TH_VFNMSACVF 0xfc00707f +#define MATCH_TH_VFWMACCVV 0xf0001057 +#define MASK_TH_VFWMACCVV 0xfc00707f +#define MATCH_TH_VFWMACCVF 0xf0005057 +#define MASK_TH_VFWMACCVF 0xfc00707f +#define MATCH_TH_VFWNMACCVV 0xf4001057 +#define MASK_TH_VFWNMACCVV 0xfc00707f +#define MATCH_TH_VFWNMACCVF 0xf4005057 +#define MASK_TH_VFWNMACCVF 0xfc00707f +#define MATCH_TH_VFWMSACVV 0xf8001057 +#define MASK_TH_VFWMSACVV 0xfc00707f +#define MATCH_TH_VFWMSACVF 0xf8005057 +#define MASK_TH_VFWMSACVF 0xfc00707f +#define MATCH_TH_VFWNMSACVV 0xfc001057 +#define MASK_TH_VFWNMSACVV 0xfc00707f +#define MATCH_TH_VFWNMSACVF 0xfc005057 +#define MASK_TH_VFWNMSACVF 0xfc00707f +#define MATCH_TH_VFSQRTV 0x8c001057 +#define MASK_TH_VFSQRTV 0xfc0ff07f +#define MATCH_TH_VFMINVV 0x10001057 +#define MASK_TH_VFMINVV 0xfc00707f +#define MATCH_TH_VFMINVF 0x10005057 +#define MASK_TH_VFMINVF 0xfc00707f +#define MATCH_TH_VFMAXVV 0x18001057 +#define MASK_TH_VFMAXVV 0xfc00707f +#define MATCH_TH_VFMAXVF 0x18005057 +#define MASK_TH_VFMAXVF 0xfc00707f +#define MATCH_TH_VFSGNJVV 0x20001057 +#define MASK_TH_VFSGNJVV 0xfc00707f +#define MATCH_TH_VFSGNJVF 0x20005057 +#define MASK_TH_VFSGNJVF 0xfc00707f +#define MATCH_TH_VFSGNJNVV 0x24001057 +#define MASK_TH_VFSGNJNVV 0xfc00707f +#define MATCH_TH_VFSGNJNVF 0x24005057 +#define MASK_TH_VFSGNJNVF 0xfc00707f +#define MATCH_TH_VFSGNJXVV 0x28001057 +#define MASK_TH_VFSGNJXVV 0xfc00707f +#define MATCH_TH_VFSGNJXVF 0x28005057 +#define MASK_TH_VFSGNJXVF 0xfc00707f +#define MATCH_TH_VMFEQVV 0x60001057 +#define MASK_TH_VMFEQVV 0xfc00707f +#define MATCH_TH_VMFEQVF 0x60005057 +#define MASK_TH_VMFEQVF 0xfc00707f +#define MATCH_TH_VMFNEVV 0x70001057 +#define MASK_TH_VMFNEVV 0xfc00707f +#define MATCH_TH_VMFNEVF 0x70005057 +#define MASK_TH_VMFNEVF 0xfc00707f +#define MATCH_TH_VMFLTVV 0x6c001057 +#define MASK_TH_VMFLTVV 0xfc00707f +#define MATCH_TH_VMFLTVF 0x6c005057 +#define MASK_TH_VMFLTVF 0xfc00707f +#define MATCH_TH_VMFLEVV 0x64001057 +#define MASK_TH_VMFLEVV 0xfc00707f +#define MATCH_TH_VMFLEVF 0x64005057 +#define MASK_TH_VMFLEVF 0xfc00707f +#define MATCH_TH_VMFGTVF 0x74005057 +#define MASK_TH_VMFGTVF 0xfc00707f +#define MATCH_TH_VMFGEVF 0x7c005057 +#define MASK_TH_VMFGEVF 0xfc00707f +#define MATCH_TH_VMFORDVV 0x68001057 +#define MASK_TH_VMFORDVV 0xfc00707f +#define MATCH_TH_VMFORDVF 0x68005057 +#define MASK_TH_VMFORDVF 0xfc00707f +#define MATCH_TH_VFCLASSV 0x8c081057 +#define MASK_TH_VFCLASSV 0xfc0ff07f +#define MATCH_TH_VFMERGEVFM 0x5c005057 +#define MASK_TH_VFMERGEVFM 0xfe00707f +#define MATCH_TH_VFMVVF 0x5e005057 +#define MASK_TH_VFMVVF 0xfff0707f +#define MATCH_TH_VFCVTXUFV 0x88001057 +#define MASK_TH_VFCVTXUFV 0xfc0ff07f +#define MATCH_TH_VFCVTXFV 0x88009057 +#define MASK_TH_VFCVTXFV 0xfc0ff07f +#define MATCH_TH_VFCVTFXUV 0x88011057 +#define MASK_TH_VFCVTFXUV 0xfc0ff07f +#define MATCH_TH_VFCVTFXV 0x88019057 +#define MASK_TH_VFCVTFXV 0xfc0ff07f +#define MATCH_TH_VFWCVTXUFV 0x88041057 +#define MASK_TH_VFWCVTXUFV 0xfc0ff07f +#define MATCH_TH_VFWCVTXFV 0x88049057 +#define MASK_TH_VFWCVTXFV 0xfc0ff07f +#define MATCH_TH_VFWCVTFXUV 0x88051057 +#define MASK_TH_VFWCVTFXUV 0xfc0ff07f +#define MATCH_TH_VFWCVTFXV 0x88059057 +#define MASK_TH_VFWCVTFXV 0xfc0ff07f +#define MATCH_TH_VFWCVTFFV 0x88061057 +#define MASK_TH_VFWCVTFFV 0xfc0ff07f +#define MATCH_TH_VFNCVTXUFV 0x88081057 +#define MASK_TH_VFNCVTXUFV 0xfc0ff07f +#define MATCH_TH_VFNCVTXFV 0x88089057 +#define MASK_TH_VFNCVTXFV 0xfc0ff07f +#define MATCH_TH_VFNCVTFXUV 0x88091057 +#define MASK_TH_VFNCVTFXUV 0xfc0ff07f +#define MATCH_TH_VFNCVTFXV 0x88099057 +#define MASK_TH_VFNCVTFXV 0xfc0ff07f +#define MATCH_TH_VFNCVTFFV 0x880a1057 +#define MASK_TH_VFNCVTFFV 0xfc0ff07f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index c7d6d171902..a556f44d99d 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2758,6 +2758,92 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vnclip.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VNCLIPVV, MASK_TH_VNCLIPVV, match_opcode, 0 }, {"th.vnclip.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VNCLIPVX, MASK_TH_VNCLIPVX, match_opcode, 0 }, {"th.vnclip.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VNCLIPVI, MASK_TH_VNCLIPVI, match_opcode, 0 }, +{"th.vfadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFADDVV, MASK_TH_VFADDVV, match_opcode, 0}, +{"th.vfadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFADDVF, MASK_TH_VFADDVF, match_opcode, 0}, +{"th.vfsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFSUBVV, MASK_TH_VFSUBVV, match_opcode, 0}, +{"th.vfsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFSUBVF, MASK_TH_VFSUBVF, match_opcode, 0}, +{"th.vfrsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFRSUBVF, MASK_TH_VFRSUBVF, match_opcode, 0}, +{"th.vfwadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWADDVV, MASK_TH_VFWADDVV, match_opcode, 0}, +{"th.vfwadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFWADDVF, MASK_TH_VFWADDVF, match_opcode, 0}, +{"th.vfwsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWSUBVV, MASK_TH_VFWSUBVV, match_opcode, 0}, +{"th.vfwsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFWSUBVF, MASK_TH_VFWSUBVF, match_opcode, 0}, +{"th.vfwadd.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWADDWV, MASK_TH_VFWADDWV, match_opcode, 0}, +{"th.vfwsub.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWSUBWV, MASK_TH_VFWSUBWV, match_opcode, 0}, +{"th.vfwadd.wf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFWADDWF, MASK_TH_VFWADDWF, match_opcode, 0}, +{"th.vfwsub.wf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFWSUBWF, MASK_TH_VFWSUBWF, match_opcode, 0}, +{"th.vfmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFMULVV, MASK_TH_VFMULVV, match_opcode, 0}, +{"th.vfmul.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFMULVF, MASK_TH_VFMULVF, match_opcode, 0}, +{"th.vfdiv.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFDIVVV, MASK_TH_VFDIVVV, match_opcode, 0}, +{"th.vfdiv.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFDIVVF, MASK_TH_VFDIVVF, match_opcode, 0}, +{"th.vfrdiv.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFRDIVVF, MASK_TH_VFRDIVVF, match_opcode, 0}, +{"th.vfwmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWMULVV, MASK_TH_VFWMULVV, match_opcode, 0}, +{"th.vfwmul.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFWMULVF, MASK_TH_VFWMULVF, match_opcode, 0}, +{"th.vfmadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFMADDVV, MASK_TH_VFMADDVV, match_opcode, 0}, +{"th.vfmadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFMADDVF, MASK_TH_VFMADDVF, match_opcode, 0}, +{"th.vfnmadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFNMADDVV, MASK_TH_VFNMADDVV, match_opcode, 0}, +{"th.vfnmadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFNMADDVF, MASK_TH_VFNMADDVF, match_opcode, 0}, +{"th.vfmsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFMSUBVV, MASK_TH_VFMSUBVV, match_opcode, 0}, +{"th.vfmsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFMSUBVF, MASK_TH_VFMSUBVF, match_opcode, 0}, +{"th.vfnmsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFNMSUBVV, MASK_TH_VFNMSUBVV, match_opcode, 0}, +{"th.vfnmsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFNMSUBVF, MASK_TH_VFNMSUBVF, match_opcode, 0}, +{"th.vfmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFMACCVV, MASK_TH_VFMACCVV, match_opcode, 0}, +{"th.vfmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFMACCVF, MASK_TH_VFMACCVF, match_opcode, 0}, +{"th.vfnmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFNMACCVV, MASK_TH_VFNMACCVV, match_opcode, 0}, +{"th.vfnmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFNMACCVF, MASK_TH_VFNMACCVF, match_opcode, 0}, +{"th.vfmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFMSACVV, MASK_TH_VFMSACVV, match_opcode, 0}, +{"th.vfmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFMSACVF, MASK_TH_VFMSACVF, match_opcode, 0}, +{"th.vfnmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFNMSACVV, MASK_TH_VFNMSACVV, match_opcode, 0}, +{"th.vfnmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFNMSACVF, MASK_TH_VFNMSACVF, match_opcode, 0}, +{"th.vfwmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFWMACCVV, MASK_TH_VFWMACCVV, match_opcode, 0}, +{"th.vfwmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFWMACCVF, MASK_TH_VFWMACCVF, match_opcode, 0}, +{"th.vfwnmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFWNMACCVV, MASK_TH_VFWNMACCVV, match_opcode, 0}, +{"th.vfwnmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFWNMACCVF, MASK_TH_VFWNMACCVF, match_opcode, 0}, +{"th.vfwmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFWMSACVV, MASK_TH_VFWMSACVV, match_opcode, 0}, +{"th.vfwmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFWMSACVF, MASK_TH_VFWMSACVF, match_opcode, 0}, +{"th.vfwnmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFWNMSACVV, MASK_TH_VFWNMSACVV, match_opcode, 0}, +{"th.vfwnmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFWNMSACVF, MASK_TH_VFWNMSACVF, match_opcode, 0}, +{"th.vfsqrt.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFSQRTV, MASK_TH_VFSQRTV, match_opcode, 0}, +{"th.vfmin.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFMINVV, MASK_TH_VFMINVV, match_opcode, 0}, +{"th.vfmin.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFMINVF, MASK_TH_VFMINVF, match_opcode, 0}, +{"th.vfmax.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFMAXVV, MASK_TH_VFMAXVV, match_opcode, 0}, +{"th.vfmax.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFMAXVF, MASK_TH_VFMAXVF, match_opcode, 0}, +{"th.vfsgnj.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFSGNJVV, MASK_TH_VFSGNJVV, match_opcode, 0}, +{"th.vfsgnj.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFSGNJVF, MASK_TH_VFSGNJVF, match_opcode, 0}, +{"th.vfsgnjn.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFSGNJNVV, MASK_TH_VFSGNJNVV, match_opcode, 0}, +{"th.vfsgnjn.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFSGNJNVF, MASK_TH_VFSGNJNVF, match_opcode, 0}, +{"th.vfsgnjx.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFSGNJXVV, MASK_TH_VFSGNJXVV, match_opcode, 0}, +{"th.vfsgnjx.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFSGNJXVF, MASK_TH_VFSGNJXVF, match_opcode, 0}, +{"th.vmfeq.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMFEQVV, MASK_TH_VMFEQVV, match_opcode, 0}, +{"th.vmfeq.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFEQVF, MASK_TH_VMFEQVF, match_opcode, 0}, +{"th.vmfne.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMFNEVV, MASK_TH_VMFNEVV, match_opcode, 0}, +{"th.vmfne.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFNEVF, MASK_TH_VMFNEVF, match_opcode, 0}, +{"th.vmflt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMFLTVV, MASK_TH_VMFLTVV, match_opcode, 0}, +{"th.vmflt.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFLTVF, MASK_TH_VMFLTVF, match_opcode, 0}, +{"th.vmfle.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMFLEVV, MASK_TH_VMFLEVV, match_opcode, 0}, +{"th.vmfle.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFLEVF, MASK_TH_VMFLEVF, match_opcode, 0}, +{"th.vmfgt.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFGTVF, MASK_TH_VMFGTVF, match_opcode, 0}, +{"th.vmfge.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFGEVF, MASK_TH_VMFGEVF, match_opcode, 0}, +{"th.vmfgt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMFLTVV, MASK_TH_VMFLTVV, match_opcode, INSN_ALIAS}, +{"th.vmfge.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMFLEVV, MASK_TH_VMFLEVV, match_opcode, INSN_ALIAS}, +{"th.vmford.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMFORDVV, MASK_TH_VMFORDVV, match_opcode, 0}, +{"th.vmford.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFORDVF, MASK_TH_VMFORDVF, match_opcode, 0}, +{"th.vfclass.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCLASSV, MASK_TH_VFCLASSV, match_opcode, 0}, +{"th.vfmerge.vfm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,S,V0", MATCH_TH_VFMERGEVFM, MASK_TH_VFMERGEVFM, match_opcode, 0}, +{"th.vfmv.v.f", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S", MATCH_TH_VFMVVF, MASK_TH_VFMVVF, match_opcode, 0 }, +{"th.vfcvt.xu.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTXUFV, MASK_TH_VFCVTXUFV, match_opcode, 0}, +{"th.vfcvt.x.f.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTXFV, MASK_TH_VFCVTXFV, match_opcode, 0}, +{"th.vfcvt.f.xu.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTFXUV, MASK_TH_VFCVTFXUV, match_opcode, 0}, +{"th.vfcvt.f.x.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTFXV, MASK_TH_VFCVTFXV, match_opcode, 0}, +{"th.vfwcvt.xu.f.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTXUFV, MASK_TH_VFWCVTXUFV, match_opcode, 0}, +{"th.vfwcvt.x.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTXFV, MASK_TH_VFWCVTXFV, match_opcode, 0}, +{"th.vfwcvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFXUV, MASK_TH_VFWCVTFXUV, match_opcode, 0}, +{"th.vfwcvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFXV, MASK_TH_VFWCVTFXV, match_opcode, 0}, +{"th.vfwcvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFFV, MASK_TH_VFWCVTFFV, match_opcode, 0}, +{"th.vfncvt.xu.f.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTXUFV, MASK_TH_VFNCVTXUFV, match_opcode, 0}, +{"th.vfncvt.x.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTXFV, MASK_TH_VFNCVTXFV, match_opcode, 0}, +{"th.vfncvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXUV, MASK_TH_VFNCVTFXUV, match_opcode, 0}, +{"th.vfncvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXV, MASK_TH_VFNCVTFXV, match_opcode, 0}, +{"th.vfncvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFFV, MASK_TH_VFNCVTFFV, match_opcode, 0}, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, From patchwork Fri Nov 10 07:33:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 79541 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E5C9D3857359 for ; Fri, 10 Nov 2023 07:34:08 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from out30-110.freemail.mail.aliyun.com (out30-110.freemail.mail.aliyun.com [115.124.30.110]) by sourceware.org (Postfix) with ESMTPS id C38FD385C6F7 for ; Fri, 10 Nov 2023 07:33:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C38FD385C6F7 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C38FD385C6F7 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.110 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699601634; cv=none; b=tpBZnPev2ZKIUpwo3/m46N2jAC4DI3iaT6gTBUbFY0ql7yAfPwfnh0iVwjysRMeXctRtZnqPHowVC+DBmjr4bFi7WssvEfj3AhCYTFtwJSzqdXdTjtuvkXNhcjpf3DHDcWBLYqyQSxUTMzfVFqcYinCBDO9vV3xwpiuJWIQ9bXw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699601634; c=relaxed/simple; bh=FeVzcR2qtNB3j/jGHuYbNlH1o0DWkeJ4inea1eQUA7U=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=VLt04yu1kl1Mocw6GF0Y3ECew5k6kA2jK04B8G+KHG4iyn1Rpn2bSAO6KSmxH2SHBsmcssADTnPxZWXI1WhBSyh7U8zySSryuNfmlnNsB8Q4j65Kt9nuHjQUtMpLP5xGSSNc0eHIUpkqJiSLBwcIh5dnXuSkQjLNutIuvuv4y2o= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R431e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046059; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=6; SR=0; TI=SMTPD_---0Vw3fBOC_1699601625; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw3fBOC_1699601625) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:33:46 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 10/12] RISC-V: Add reductions instructions for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:33:37 +0800 Message-Id: <20231110073337.2049-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.6 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds reductions instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for reductions instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VREDSUMVV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise. --- gas/testsuite/gas/riscv/x-thead-vector.d | 32 +++++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 36 ++++++++++++++++++++++++ include/opcode/riscv-opc.h | 32 +++++++++++++++++++++ opcodes/riscv-opc.c | 16 +++++++++++ 4 files changed, 116 insertions(+) diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index 09e4a9c2f73..50061606298 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -720,3 +720,35 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+88891257[ ]+th.vfncvt.f.xu.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+88899257[ ]+th.vfncvt.f.x.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+888a1257[ ]+th.vfncvt.f.f.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+02862257[ ]+th.vredsum.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+1a842257[ ]+th.vredmaxu.vs[ ]+v4,v8,v8 +[ ]+[0-9a-f]+:[ ]+1e842257[ ]+th.vredmax.vs[ ]+v4,v8,v8 +[ ]+[0-9a-f]+:[ ]+12842257[ ]+th.vredminu.vs[ ]+v4,v8,v8 +[ ]+[0-9a-f]+:[ ]+16842257[ ]+th.vredmin.vs[ ]+v4,v8,v8 +[ ]+[0-9a-f]+:[ ]+06862257[ ]+th.vredand.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+0a862257[ ]+th.vredor.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+0e862257[ ]+th.vredxor.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+00862257[ ]+th.vredsum.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+18842257[ ]+th.vredmaxu.vs[ ]+v4,v8,v8,v0.t +[ ]+[0-9a-f]+:[ ]+1c842257[ ]+th.vredmax.vs[ ]+v4,v8,v8,v0.t +[ ]+[0-9a-f]+:[ ]+10842257[ ]+th.vredminu.vs[ ]+v4,v8,v8,v0.t +[ ]+[0-9a-f]+:[ ]+14842257[ ]+th.vredmin.vs[ ]+v4,v8,v8,v0.t +[ ]+[0-9a-f]+:[ ]+04862257[ ]+th.vredand.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+08862257[ ]+th.vredor.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+0c862257[ ]+th.vredxor.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+c2860257[ ]+th.vwredsumu.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+c6860257[ ]+th.vwredsum.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+c0860257[ ]+th.vwredsumu.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+c4860257[ ]+th.vwredsum.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+0e861257[ ]+th.vfredosum.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+06861257[ ]+th.vfredsum.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+1e861257[ ]+th.vfredmax.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+16861257[ ]+th.vfredmin.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+0c861257[ ]+th.vfredosum.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+04861257[ ]+th.vfredsum.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+1c861257[ ]+th.vfredmax.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+14861257[ ]+th.vfredmin.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+ce861257[ ]+th.vfwredosum.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+c6861257[ ]+th.vfwredsum.vs[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+cc861257[ ]+th.vfwredosum.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+c4861257[ ]+th.vfwredsum.vs[ ]+v4,v8,v12,v0.t diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index f7de24fdd63..eb1eccc5abc 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -752,3 +752,39 @@ th.vfncvt.f.xu.v v4, v8, v0.t th.vfncvt.f.x.v v4, v8, v0.t th.vfncvt.f.f.v v4, v8, v0.t + + th.vredsum.vs v4, v8, v12 + th.vredmaxu.vs v4, v8, v8 + th.vredmax.vs v4, v8, v8 + th.vredminu.vs v4, v8, v8 + th.vredmin.vs v4, v8, v8 + th.vredand.vs v4, v8, v12 + th.vredor.vs v4, v8, v12 + th.vredxor.vs v4, v8, v12 + th.vredsum.vs v4, v8, v12, v0.t + th.vredmaxu.vs v4, v8, v8, v0.t + th.vredmax.vs v4, v8, v8, v0.t + th.vredminu.vs v4, v8, v8, v0.t + th.vredmin.vs v4, v8, v8, v0.t + th.vredand.vs v4, v8, v12, v0.t + th.vredor.vs v4, v8, v12, v0.t + th.vredxor.vs v4, v8, v12, v0.t + + th.vwredsumu.vs v4, v8, v12 + th.vwredsum.vs v4, v8, v12 + th.vwredsumu.vs v4, v8, v12, v0.t + th.vwredsum.vs v4, v8, v12, v0.t + + th.vfredosum.vs v4, v8, v12 + th.vfredsum.vs v4, v8, v12 + th.vfredmax.vs v4, v8, v12 + th.vfredmin.vs v4, v8, v12 + th.vfredosum.vs v4, v8, v12, v0.t + th.vfredsum.vs v4, v8, v12, v0.t + th.vfredmax.vs v4, v8, v12, v0.t + th.vfredmin.vs v4, v8, v12, v0.t + + th.vfwredosum.vs v4, v8, v12 + th.vfwredsum.vs v4, v8, v12 + th.vfwredosum.vs v4, v8, v12, v0.t + th.vfwredsum.vs v4, v8, v12, v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 2ec07a0b2a5..233172d7c5f 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3839,6 +3839,38 @@ #define MASK_TH_VFNCVTFXV 0xfc0ff07f #define MATCH_TH_VFNCVTFFV 0x880a1057 #define MASK_TH_VFNCVTFFV 0xfc0ff07f +#define MATCH_TH_VREDSUMVV 0x00002057 +#define MASK_TH_VREDSUMVV 0xfc00707f +#define MATCH_TH_VREDMAXVV 0x1c002057 +#define MASK_TH_VREDMAXVV 0xfc00707f +#define MATCH_TH_VREDMAXUVV 0x18002057 +#define MASK_TH_VREDMAXUVV 0xfc00707f +#define MATCH_TH_VREDMINVV 0x14002057 +#define MASK_TH_VREDMINVV 0xfc00707f +#define MATCH_TH_VREDMINUVV 0x10002057 +#define MASK_TH_VREDMINUVV 0xfc00707f +#define MATCH_TH_VREDANDVV 0x04002057 +#define MASK_TH_VREDANDVV 0xfc00707f +#define MATCH_TH_VREDORVV 0x08002057 +#define MASK_TH_VREDORVV 0xfc00707f +#define MATCH_TH_VREDXORVV 0x0c002057 +#define MASK_TH_VREDXORVV 0xfc00707f +#define MATCH_TH_VWREDSUMUVV 0xc0000057 +#define MASK_TH_VWREDSUMUVV 0xfc00707f +#define MATCH_TH_VWREDSUMVV 0xc4000057 +#define MASK_TH_VWREDSUMVV 0xfc00707f +#define MATCH_TH_VFREDOSUMV 0x0c001057 +#define MASK_TH_VFREDOSUMV 0xfc00707f +#define MATCH_TH_VFREDSUMV 0x04001057 +#define MASK_TH_VFREDSUMV 0xfc00707f +#define MATCH_TH_VFREDMAXV 0x1c001057 +#define MASK_TH_VFREDMAXV 0xfc00707f +#define MATCH_TH_VFREDMINV 0x14001057 +#define MASK_TH_VFREDMINV 0xfc00707f +#define MATCH_TH_VFWREDOSUMV 0xcc001057 +#define MASK_TH_VFWREDOSUMV 0xfc00707f +#define MATCH_TH_VFWREDSUMV 0xc4001057 +#define MASK_TH_VFWREDSUMV 0xfc00707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index a556f44d99d..39be63f2ee6 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2844,6 +2844,22 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vfncvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXUV, MASK_TH_VFNCVTFXUV, match_opcode, 0}, {"th.vfncvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXV, MASK_TH_VFNCVTFXV, match_opcode, 0}, {"th.vfncvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFFV, MASK_TH_VFNCVTFFV, match_opcode, 0}, +{"th.vredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDSUMVV, MASK_TH_VREDSUMVV, match_opcode, 0}, +{"th.vredmaxu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDMAXUVV, MASK_TH_VREDMAXUVV, match_opcode, 0}, +{"th.vredmax.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDMAXVV, MASK_TH_VREDMAXVV, match_opcode, 0}, +{"th.vredminu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDMINUVV, MASK_TH_VREDMINUVV, match_opcode, 0}, +{"th.vredmin.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDMINVV, MASK_TH_VREDMINVV, match_opcode, 0}, +{"th.vredand.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDANDVV, MASK_TH_VREDANDVV, match_opcode, 0}, +{"th.vredor.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDORVV, MASK_TH_VREDORVV, match_opcode, 0}, +{"th.vredxor.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDXORVV, MASK_TH_VREDXORVV, match_opcode, 0}, +{"th.vwredsumu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWREDSUMUVV, MASK_TH_VWREDSUMUVV, match_opcode, 0}, +{"th.vwredsum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWREDSUMVV, MASK_TH_VWREDSUMVV, match_opcode, 0}, +{"th.vfredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFREDOSUMV, MASK_TH_VFREDOSUMV, match_opcode, 0}, +{"th.vfredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFREDSUMV, MASK_TH_VFREDSUMV, match_opcode, 0}, +{"th.vfredmax.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFREDMAXV, MASK_TH_VFREDMAXV, match_opcode, 0}, +{"th.vfredmin.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFREDMINV, MASK_TH_VFREDMINV, match_opcode, 0}, +{"th.vfwredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWREDOSUMV, MASK_TH_VFWREDOSUMV, match_opcode, 0}, +{"th.vfwredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWREDSUMV, MASK_TH_VFWREDSUMV, match_opcode, 0}, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, From patchwork Fri Nov 10 07:34:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jin 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15:34:44 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 11/12] RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:34:35 +0800 Message-Id: <20231110073435.2098-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.4 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds mask instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for mask instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMANDMM): New. opcodes/ChangeLog: * riscv-opc.c: Likewise. --- gas/testsuite/gas/riscv/x-thead-vector.d | 26 ++++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 30 ++++++++++++++++++++++++ include/opcode/riscv-opc.h | 30 ++++++++++++++++++++++++ opcodes/riscv-opc.c | 19 +++++++++++++++ 4 files changed, 105 insertions(+) diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index 50061606298..8a43fe38b8b 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -752,3 +752,29 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+c6861257[ ]+th.vfwredsum.vs[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+cc861257[ ]+th.vfwredosum.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+c4861257[ ]+th.vfwredsum.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+66842257[ ]+th.vmcpy.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+6e422257[ ]+th.vmclr.m[ ]+v4 +[ ]+[0-9a-f]+:[ ]+7e422257[ ]+th.vmset.m[ ]+v4 +[ ]+[0-9a-f]+:[ ]+76842257[ ]+th.vmnot.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+66862257[ ]+th.vmand.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+76862257[ ]+th.vmnand.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+62862257[ ]+th.vmandnot.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+6e862257[ ]+th.vmxor.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+6a862257[ ]+th.vmor.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+7a862257[ ]+th.vmnor.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+72862257[ ]+th.vmornot.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+7e862257[ ]+th.vmxnor.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+52c02557[ ]+th.vmpopc.m[ ]+a0,v12 +[ ]+[0-9a-f]+:[ ]+56c02557[ ]+th.vmfirst.m[ ]+a0,v12 +[ ]+[0-9a-f]+:[ ]+5a80a257[ ]+th.vmsbf.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+5a81a257[ ]+th.vmsif.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+5a812257[ ]+th.vmsof.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+5a882257[ ]+th.viota.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+5a08a257[ ]+th.vid.v[ ]+v4 +[ ]+[0-9a-f]+:[ ]+50c02557[ ]+th.vmpopc.m[ ]+a0,v12,v0.t +[ ]+[0-9a-f]+:[ ]+54c02557[ ]+th.vmfirst.m[ ]+a0,v12,v0.t +[ ]+[0-9a-f]+:[ ]+5880a257[ ]+th.vmsbf.m[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+5881a257[ ]+th.vmsif.m[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+58812257[ ]+th.vmsof.m[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+58882257[ ]+th.viota.m[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+5808a257[ ]+th.vid.v[ ]+v4,v0.t diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index eb1eccc5abc..f23de9f7154 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -788,3 +788,33 @@ th.vfwredsum.vs v4, v8, v12 th.vfwredosum.vs v4, v8, v12, v0.t th.vfwredsum.vs v4, v8, v12, v0.t + + # Aliases + th.vmcpy.m v4, v8 + th.vmclr.m v4 + th.vmset.m v4 + th.vmnot.m v4, v8 + + th.vmand.mm v4, v8, v12 + th.vmnand.mm v4, v8, v12 + th.vmandnot.mm v4, v8, v12 + th.vmxor.mm v4, v8, v12 + th.vmor.mm v4, v8, v12 + th.vmnor.mm v4, v8, v12 + th.vmornot.mm v4, v8, v12 + th.vmxnor.mm v4, v8, v12 + + th.vmpopc.m a0, v12 + th.vmfirst.m a0, v12 + th.vmsbf.m v4, v8 + th.vmsif.m v4, v8 + th.vmsof.m v4, v8 + th.viota.m v4, v8 + th.vid.v v4 + th.vmpopc.m a0, v12, v0.t + th.vmfirst.m a0, v12, v0.t + th.vmsbf.m v4, v8, v0.t + th.vmsif.m v4, v8, v0.t + th.vmsof.m v4, v8, v0.t + th.viota.m v4, v8, v0.t + th.vid.v v4, v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 233172d7c5f..9da64bf1a74 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3871,6 +3871,36 @@ #define MASK_TH_VFWREDOSUMV 0xfc00707f #define MATCH_TH_VFWREDSUMV 0xc4001057 #define MASK_TH_VFWREDSUMV 0xfc00707f +#define MATCH_TH_VMANDMM 0x66002057 +#define MASK_TH_VMANDMM 0xfe00707f +#define MATCH_TH_VMNANDMM 0x76002057 +#define MASK_TH_VMNANDMM 0xfe00707f +#define MATCH_TH_VMANDNOTMM 0x62002057 +#define MASK_TH_VMANDNOTMM 0xfe00707f +#define MATCH_TH_VMXORMM 0x6e002057 +#define MASK_TH_VMXORMM 0xfe00707f +#define MATCH_TH_VMORMM 0x6a002057 +#define MASK_TH_VMORMM 0xfe00707f +#define MATCH_TH_VMNORMM 0x7a002057 +#define MASK_TH_VMNORMM 0xfe00707f +#define MATCH_TH_VMORNOTMM 0x72002057 +#define MASK_TH_VMORNOTMM 0xfe00707f +#define MATCH_TH_VMXNORMM 0x7e002057 +#define MASK_TH_VMXNORMM 0xfe00707f +#define MATCH_TH_VMPOPCM 0x50002057 +#define MASK_TH_VMPOPCM 0xfc0ff07f +#define MATCH_TH_VMFIRSTM 0x54002057 +#define MASK_TH_VMFIRSTM 0xfc0ff07f +#define MATCH_TH_VMSBFM 0x5800a057 +#define MASK_TH_VMSBFM 0xfc0ff07f +#define MATCH_TH_VMSIFM 0x5801a057 +#define MASK_TH_VMSIFM 0xfc0ff07f +#define MATCH_TH_VMSOFM 0x58012057 +#define MASK_TH_VMSOFM 0xfc0ff07f +#define MATCH_TH_VIOTAM 0x58082057 +#define MASK_TH_VIOTAM 0xfc0ff07f +#define MATCH_TH_VIDV 0x5808a057 +#define MASK_TH_VIDV 0xfdfff07f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 39be63f2ee6..fab3f7c6c39 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2860,6 +2860,25 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vfredmin.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFREDMINV, MASK_TH_VFREDMINV, match_opcode, 0}, {"th.vfwredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWREDOSUMV, MASK_TH_VFWREDOSUMV, match_opcode, 0}, {"th.vfwredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWREDSUMV, MASK_TH_VFWREDSUMV, match_opcode, 0}, +{"th.vmcpy.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_TH_VMANDMM, MASK_TH_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS}, +{"th.vmclr.m", 0, INSN_CLASS_XTHEADVECTOR, "Vv", MATCH_TH_VMXORMM, MASK_TH_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS}, +{"th.vmset.m", 0, INSN_CLASS_XTHEADVECTOR, "Vv", MATCH_TH_VMXNORMM, MASK_TH_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS}, +{"th.vmnot.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_TH_VMNANDMM, MASK_TH_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS}, +{"th.vmand.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_TH_VMANDMM, MASK_TH_VMANDMM, match_opcode, 0}, +{"th.vmnand.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_TH_VMNANDMM, MASK_TH_VMNANDMM, match_opcode, 0}, +{"th.vmandnot.mm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_TH_VMANDNOTMM, MASK_TH_VMANDNOTMM, match_opcode, 0}, +{"th.vmxor.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_TH_VMXORMM, MASK_TH_VMXORMM, match_opcode, 0}, +{"th.vmor.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_TH_VMORMM, MASK_TH_VMORMM, match_opcode, 0}, +{"th.vmnor.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_TH_VMNORMM, MASK_TH_VMNORMM, match_opcode, 0}, +{"th.vmornot.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_TH_VMORNOTMM, MASK_TH_VMORNOTMM, match_opcode, 0}, +{"th.vmxnor.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_TH_VMXNORMM, MASK_TH_VMXNORMM, match_opcode, 0}, +{"th.vmpopc.m", 0, INSN_CLASS_XTHEADVECTOR, "d,VtVm", MATCH_TH_VMPOPCM, MASK_TH_VMPOPCM, match_opcode, 0}, +{"th.vmfirst.m", 0, INSN_CLASS_XTHEADVECTOR, "d,VtVm", MATCH_TH_VMFIRSTM, MASK_TH_VMFIRSTM, match_opcode, 0}, +{"th.vmsbf.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSBFM, MASK_TH_VMSBFM, match_opcode, 0}, +{"th.vmsif.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSIFM, MASK_TH_VMSIFM, match_opcode, 0}, +{"th.vmsof.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSOFM, MASK_TH_VMSOFM, match_opcode, 0}, +{"th.viota.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VIOTAM, MASK_TH_VIOTAM, match_opcode, 0}, +{"th.vid.v", 0, INSN_CLASS_XTHEADVECTOR, "VdVm", MATCH_TH_VIDV, MASK_TH_VIDV, match_opcode, 0}, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, From patchwork Fri Nov 10 07:35:14 2023 Content-Type: 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localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw3kmHB_1699601754) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:35:56 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 12/12] RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:35:14 +0800 Message-Id: <20231110073514.2142-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.3 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds permutation instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for permutation instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMVXS): New. opcodes/ChangeLog: * riscv-opc.c: Likewise. --- gas/testsuite/gas/riscv/x-thead-vector.d | 30 +++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 38 ++++++++++++++++++++++++ include/opcode/riscv-opc.h | 30 +++++++++++++++++++ opcodes/riscv-opc.c | 15 ++++++++++ 4 files changed, 113 insertions(+) diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index 8a43fe38b8b..885baf73490 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -778,3 +778,33 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+58812257[ ]+th.vmsof.m[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+58882257[ ]+th.viota.m[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+5808a257[ ]+th.vid.v[ ]+v4,v0.t +[ ]+[0-9a-f]+:[ ]+32c02557[ ]+th.vmv.x.s[ ]+a0,v12 +[ ]+[0-9a-f]+:[ ]+32c62557[ ]+th.vext.x.v[ ]+a0,v12,a2 +[ ]+[0-9a-f]+:[ ]+36056257[ ]+th.vmv.s.x[ ]+v4,a0 +[ ]+[0-9a-f]+:[ ]+32801557[ ]+th.vfmv.f.s[ ]+fa0,v8 +[ ]+[0-9a-f]+:[ ]+3605d257[ ]+th.vfmv.s.f[ ]+v4,fa1 +[ ]+[0-9a-f]+:[ ]+3a85c257[ ]+th.vslideup.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3a803257[ ]+th.vslideup.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+3a8fb257[ ]+th.vslideup.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+3e85c257[ ]+th.vslidedown.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3e803257[ ]+th.vslidedown.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+3e8fb257[ ]+th.vslidedown.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+3885c257[ ]+th.vslideup.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+38803257[ ]+th.vslideup.vi[ ]+v4,v8,0,v0.t +[ ]+[0-9a-f]+:[ ]+388fb257[ ]+th.vslideup.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+3c85c257[ ]+th.vslidedown.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+3c803257[ ]+th.vslidedown.vi[ ]+v4,v8,0,v0.t +[ ]+[0-9a-f]+:[ ]+3c8fb257[ ]+th.vslidedown.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+3a85e257[ ]+th.vslide1up.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3e85e257[ ]+th.vslide1down.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3885e257[ ]+th.vslide1up.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+3c85e257[ ]+th.vslide1down.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+32860257[ ]+th.vrgather.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+3285c257[ ]+th.vrgather.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+32803257[ ]+th.vrgather.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+328fb257[ ]+th.vrgather.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+30860257[ ]+th.vrgather.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+3085c257[ ]+th.vrgather.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+30803257[ ]+th.vrgather.vi[ ]+v4,v8,0,v0.t +[ ]+[0-9a-f]+:[ ]+308fb257[ ]+th.vrgather.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+5e862257[ ]+th.vcompress.vm[ ]+v4,v8,v12 diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index f23de9f7154..d7171057388 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -818,3 +818,41 @@ th.vmsof.m v4, v8, v0.t th.viota.m v4, v8, v0.t th.vid.v v4, v0.t + + # Alias + th.vmv.x.s a0, v12 + + th.vext.x.v a0, v12, a2 + th.vmv.s.x v4, a0 + + th.vfmv.f.s fa0, v8 + th.vfmv.s.f v4, fa1 + + th.vslideup.vx v4, v8, a1 + th.vslideup.vi v4, v8, 0 + th.vslideup.vi v4, v8, 31 + th.vslidedown.vx v4, v8, a1 + th.vslidedown.vi v4, v8, 0 + th.vslidedown.vi v4, v8, 31 + th.vslideup.vx v4, v8, a1, v0.t + th.vslideup.vi v4, v8, 0, v0.t + th.vslideup.vi v4, v8, 31, v0.t + th.vslidedown.vx v4, v8, a1, v0.t + th.vslidedown.vi v4, v8, 0, v0.t + th.vslidedown.vi v4, v8, 31, v0.t + + th.vslide1up.vx v4, v8, a1 + th.vslide1down.vx v4, v8, a1 + th.vslide1up.vx v4, v8, a1, v0.t + th.vslide1down.vx v4, v8, a1, v0.t + + th.vrgather.vv v4, v8, v12 + th.vrgather.vx v4, v8, a1 + th.vrgather.vi v4, v8, 0 + th.vrgather.vi v4, v8, 31 + th.vrgather.vv v4, v8, v12, v0.t + th.vrgather.vx v4, v8, a1, v0.t + th.vrgather.vi v4, v8, 0, v0.t + th.vrgather.vi v4, v8, 31, v0.t + + th.vcompress.vm v4, v8, v12 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 9da64bf1a74..3b7f01a145c 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3901,6 +3901,36 @@ #define MASK_TH_VIOTAM 0xfc0ff07f #define MATCH_TH_VIDV 0x5808a057 #define MASK_TH_VIDV 0xfdfff07f +#define MATCH_TH_VMVXS 0x32002057 +#define MASK_TH_VMVXS 0xfe0ff07f +#define MATCH_TH_VEXTXV 0x32002057 +#define MASK_TH_VEXTXV 0xfe00707f +#define MATCH_TH_VMVSX 0x36006057 +#define MASK_TH_VMVSX 0xfff0707f +#define MATCH_TH_VFMVFS 0x32001057 +#define MASK_TH_VFMVFS 0xfe0ff07f +#define MATCH_TH_VFMVSF 0x36005057 +#define MASK_TH_VFMVSF 0xfff0707f +#define MATCH_TH_VSLIDEUPVX 0x38004057 +#define MASK_TH_VSLIDEUPVX 0xfc00707f +#define MATCH_TH_VSLIDEUPVI 0x38003057 +#define MASK_TH_VSLIDEUPVI 0xfc00707f +#define MATCH_TH_VSLIDEDOWNVX 0x3c004057 +#define MASK_TH_VSLIDEDOWNVX 0xfc00707f +#define MATCH_TH_VSLIDEDOWNVI 0x3c003057 +#define MASK_TH_VSLIDEDOWNVI 0xfc00707f +#define MATCH_TH_VSLIDE1UPVX 0x38006057 +#define MASK_TH_VSLIDE1UPVX 0xfc00707f +#define MATCH_TH_VSLIDE1DOWNVX 0x3c006057 +#define MASK_TH_VSLIDE1DOWNVX 0xfc00707f +#define MATCH_TH_VRGATHERVV 0x30000057 +#define MASK_TH_VRGATHERVV 0xfc00707f +#define MATCH_TH_VRGATHERVX 0x30004057 +#define MASK_TH_VRGATHERVX 0xfc00707f +#define MATCH_TH_VRGATHERVI 0x30003057 +#define MASK_TH_VRGATHERVI 0xfc00707f +#define MATCH_TH_VCOMPRESSV 0x5e002057 +#define MASK_TH_VCOMPRESSV 0xfe00707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index fab3f7c6c39..933018842e1 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2879,6 +2879,21 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vmsof.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSOFM, MASK_TH_VMSOFM, match_opcode, 0}, {"th.viota.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VIOTAM, MASK_TH_VIOTAM, match_opcode, 0}, {"th.vid.v", 0, INSN_CLASS_XTHEADVECTOR, "VdVm", MATCH_TH_VIDV, MASK_TH_VIDV, match_opcode, 0}, +{"th.vmv.x.s", 0, INSN_CLASS_XTHEADVECTOR, "d,Vt", MATCH_TH_VMVXS, MASK_TH_VMVXS, match_opcode, INSN_ALIAS}, +{"th.vext.x.v", 0, INSN_CLASS_XTHEADVECTOR, "d,Vt,s", MATCH_TH_VEXTXV, MASK_TH_VEXTXV, match_opcode, 0}, +{"th.vmv.s.x", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s", MATCH_TH_VMVSX, MASK_TH_VMVSX, match_opcode, 0}, +{"th.vfmv.f.s", 0, INSN_CLASS_XTHEADVECTOR, "D,Vt", MATCH_TH_VFMVFS, MASK_TH_VFMVFS, match_opcode, 0}, +{"th.vfmv.s.f", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S", MATCH_TH_VFMVSF, MASK_TH_VFMVSF, match_opcode, 0}, +{"th.vslideup.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSLIDEUPVX, MASK_TH_VSLIDEUPVX, match_opcode, 0}, +{"th.vslideup.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSLIDEUPVI, MASK_TH_VSLIDEUPVI, match_opcode, 0}, +{"th.vslidedown.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSLIDEDOWNVX, MASK_TH_VSLIDEDOWNVX, match_opcode, 0}, +{"th.vslidedown.vi",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSLIDEDOWNVI, MASK_TH_VSLIDEDOWNVI, match_opcode, 0}, +{"th.vslide1up.vx",0 ,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSLIDE1UPVX, MASK_TH_VSLIDE1UPVX, match_opcode, 0}, +{"th.vslide1down.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSLIDE1DOWNVX, MASK_TH_VSLIDE1DOWNVX, match_opcode, 0}, +{"th.vrgather.vv",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VRGATHERVV, MASK_TH_VRGATHERVV, match_opcode, 0}, +{"th.vrgather.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VRGATHERVX, MASK_TH_VRGATHERVX, match_opcode, 0}, +{"th.vrgather.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VRGATHERVI, MASK_TH_VRGATHERVI, match_opcode, 0}, +{"th.vcompress.vm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_TH_VCOMPRESSV, MASK_TH_VCOMPRESSV, match_opcode, 0}, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },