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Mon, 6 Nov 2023 13:13:08 +0000 From: Victor Do Nascimento To: CC: , , Victor Do Nascimento Subject: [PATCH 1/3] aarch64: Add LSE128 instruction operand support Date: Mon, 6 Nov 2023 13:12:46 +0000 Message-ID: <20231106131301.2576862-2-victor.donascimento@arm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106131301.2576862-1-victor.donascimento@arm.com> References: <20231106131301.2576862-1-victor.donascimento@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AMS0EPF000001B1:EE_|VI0PR08MB10582:EE_|AMS0EPF00000195:EE_|AM8PR08MB5699:EE_ X-MS-Office365-Filtering-Correlation-Id: 0959ce14-9a07-44b6-ea82-08dbdeca26e7 X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 4rURpBiKUSVyH7AzMUB5tRjQJeIJVw3PBg7nbz+KVsY3pR4PMTL/vKxCKw3wFfUJMYzG7U6AjJsHh9e/d3OIb5+PIyuZMame8rAp6j2R9fOvmgtFV9NBgKDnyVYEsYVsNQQrDf+l5rTA6qWbVQYg0mQ8SVoO4n6GTijdEhYHmb1xdx0n4A5ivCjDguHlg0BelRHfjNueuGzujwx78bACR5urGz5rzOp7KjGw5t3e5tDggSbTZjTVF/TEo0mHTWnHgWjNtWSuqpqrtaP3A7nYf8kZQ86wKjuLz9+Siod9BH3MriV3jKvdSSFVFFij70hK21HPlHq5Eo/pwCzDhw5HL4xbNhUljvgohEsBAz0a7tq9AD//Bv2MYMSDBXYUlmqPoQSmeWCsroLmRIsh1p8gY9I4cJRcNPqoHLJbcQ0fE86eQmiEBf+BAmr9aT19s2+9jj4caWFG5/9v2/Jdabtp50z1/GsoMm8USRNjf5pHiTmZ3XgulW0xIrhHg5/S27RZgBM5ojZTdKUL2PTJmv1HeKLzKQY5r+JhYa0stHwGWNEtx+hn0xxZMUAk62gV2G+8lDq4gky2qclVaFit1XWOOusxnrI+Q3ENFWg3AWQ6XCPZZY7xcRdGpOnsYQ1Xx39vIlVSuF7GL2QHfptVP/2KEHMFZWMhYRmAhyYaxPBt+g7wy21FYGUAUECAbM0UOJxSXFEuMmtEyoCUebrlauHlmSf0X07WLGvZUMlMU2ebgLaaJdFvu8YFOjGP9VF94SXCWW7NRSTEgWF3crXfCr6NCA== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF00000195.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR08MB5699 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Given the particular encoding of the LSE128 instructions, create the necessary shared input+output operand register description and handling in the code to allow for the encoding of the LSE128 128-bit atomic operations. gas/ChangeLog: * config/tc-aarch64.c (parse_operands): include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): opcodes/ChangeLog: * aarch64-opc.c (fields): (aarch64_print_operand): * aarch64-opc.h (enum aarch64_field_kind): * aarch64-tbl.h (AARCH64_OPERANDS): --- gas/config/tc-aarch64.c | 5 +++++ include/opcode/aarch64.h | 2 ++ opcodes/aarch64-opc.c | 4 ++++ opcodes/aarch64-opc.h | 2 ++ opcodes/aarch64-tbl.h | 2 ++ 5 files changed, 15 insertions(+) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 1f687fe1ca0..7e76c1b0733 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -7863,6 +7863,11 @@ parse_operands (char *str, const aarch64_opcode *opcode) po_char_or_fail ('!'); break; + case AARCH64_OPND_LSE128_Rt: + case AARCH64_OPND_LSE128_Rt2: + po_int_fp_reg_or_fail (REG_TYPE_R_64); + break; + default: as_fatal (_("unhandled operand code %d"), operands[i]); } diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 72d8ec2ce27..2b7e633fae2 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -519,6 +519,8 @@ enum aarch64_opnd AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ AARCH64_OPND_BARRIER_GCSB, /* Barrier operand for GCSB. */ AARCH64_OPND_BTI_TARGET, /* BTI {}. */ + AARCH64_OPND_LSE128_Rt, /* LSE128 . */ + AARCH64_OPND_LSE128_Rt2, /* LSE128 . */ AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [, #*16]. */ AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [, #*32]. */ AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [, #, MUL VL]. */ diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 6d9f3a06def..70e29579e66 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -226,6 +226,8 @@ const aarch64_field fields[] = { 10, 8 }, /* CSSC_imm8. */ { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */ { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */ + { 0, 5 }, /* LSE128_Rt: Shared input+output operand register. */ + { 16, 5 }, /* LSE128_Rt2: Shared input+output operand register 2. */ { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */ { 22, 1 }, /* N: in logical (immediate) instructions. */ { 30, 1 }, /* Q: in most AdvSIMD instructions. */ @@ -3770,6 +3772,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_Rt_SYS: case AARCH64_OPND_PAIRREG: case AARCH64_OPND_SVE_Rm: + case AARCH64_OPND_LSE128_Rt: + case AARCH64_OPND_LSE128_Rt2: /* The optional-ness of in e.g. IC {, } is determined by the , therefore we use opnd->present to override the generic optional-ness information. */ diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index fe1f882c20e..f07ab2c56f1 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -36,6 +36,8 @@ enum aarch64_field_kind FLD_CSSC_imm8, FLD_H, FLD_L, + FLD_LSE128_Rt, + FLD_LSE128_Rt2, FLD_M, FLD_N, FLD_Q, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 463939d24ca..150b042d7ee 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -6305,6 +6305,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "the GCSB option name DSYNC") \ Y(SYSTEM, hint, "BTI_TARGET", 0, F (), \ "BTI targets j/c/jc") \ + Y(INT_REG, regno, "LSE128_Rt", 0, F(FLD_LSE128_Rt), "an integer register") \ + Y(INT_REG, regno, "LSE128_Rt2", 0, F(FLD_LSE128_Rt2), "an integer register") \ Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \ 4 << OPD_F_OD_LSB, F(FLD_Rn), \ "an address with a 4-bit signed offset, multiplied by 16") \ From patchwork Mon Nov 6 13:12:47 2023 Content-Type: text/plain; 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Mon, 6 Nov 2023 13:13:08 +0000 From: Victor Do Nascimento To: CC: , , Victor Do Nascimento Subject: [PATCH 2/3] aarch64: Add arch support for LSE128 extension Date: Mon, 6 Nov 2023 13:12:47 +0000 Message-ID: <20231106131301.2576862-3-victor.donascimento@arm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106131301.2576862-1-victor.donascimento@arm.com> References: <20231106131301.2576862-1-victor.donascimento@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AMS0EPF000001B1:EE_|PAVPR08MB9436:EE_|DU6PEPF0000A7E1:EE_|DB9PR08MB8625:EE_ X-MS-Office365-Filtering-Correlation-Id: 61c301d9-8798-439e-8214-08dbdeca25d5 X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: nvZQYGlt5kF/1pfAn7TRkrklAKS2Yn7krqtvqFXKFSmxJUl9pW2SyJc6iQMPljtooD1hXiAcVsgm1ABOn/DcKo/KgHL4CId+UgLEkpGHx6Xh5oV2BEIADXqeA5g7kDtU16Qvhwb9j+1wO5VhWzOEmgOa5Lr8WNtWj2/9BLg5sW10jbxk3ybDmyfEaw8RYKyK8Qfdhkg/d6Eg0YVPFwJVbt99xBvyYvrOxqKUc9DbmFHFYtd63bh9pE97J7I/YaUCxwVLblF7r5JLMEWA9CMESf7QK9R0g+dSBINqYU/Zm0JdGnwpPiCm+Xoa3Vqf14odZfZzC61jm4Kc9r944a9bG4h2f3fgpd0MSdQOUGmn0Kh+gKFGDS8zm+JnKc3f2EsEfGasWAEDbX06RHq1yNAxA5QG4JT6PPDCWiNNRgejgY6EhI7b5Gk1+vU26MV7LYpcZygbNBnVPrwbLSKzSnxpAOFa2vzzr1VbqkLn6g8W06dcZPK4SkP3edzBoOnFPkUDKw7REQS1sGdxkgG0cRZ1i8ixxJSDdVkPsC8upP1ayjDp3qgB9d89FMv3oP3nUuD1umdjPvn4OGkQT775bSzdXlO3PwMoRaWmQHbMMdrwaMIRZG9gC6BpRu5cru0lI5Q1QOGu/NGRd/Jz6j3B6RosUAYhQGLhK+sNWQHy9iG6IyXxvu08uO646i5bRxOaune6xkSY/hWVZoQb2ZJ7q/lvp3D651BI76K29Jwyw6+yQbxlTNph0k1Mvfdu3Bizf3Jy8b8mvqe5YhXZsY5HY1gSlw== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF0000A7E1.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB8625 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Enable the `+lse128' feature modifier which, together with new internal feature flags, enables LSE128 instructions, which are represented via the new `_LSE128_INSN' macro. gas/ChangeLog: * config/tc-aarch64.c (aarch64_features): Add new "lse128" entry. include/ChangeLog: * include/opcode/aarch64.h (enum aarch64_feature_bit): New AARCH64_FEATURE_LSE128 feature bit. (enum aarch64_insn_class): New lse128_atomic instruction class. opcodes/ChangeLog: * opcodes/aarch64-tbl.h (aarch64_feature_lse128): New. (LSE128): Likewise. (_LSE128_INSN): Likewise. --- gas/config/tc-aarch64.c | 1 + gas/doc/c-aarch64.texi | 2 ++ include/opcode/aarch64.h | 3 +++ opcodes/aarch64-tbl.h | 5 +++++ 4 files changed, 11 insertions(+) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 7e76c1b0733..325ea2f99d8 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10239,6 +10239,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_FEATURE (SIMD)}, {"fp", AARCH64_FEATURE (FP), AARCH64_NO_FEATURES}, {"lse", AARCH64_FEATURE (LSE), AARCH64_NO_FEATURES}, + {"lse128", AARCH64_FEATURES (2, LSE, LSE128), AARCH64_NO_FEATURES}, {"simd", AARCH64_FEATURE (SIMD), AARCH64_FEATURE (FP)}, {"pan", AARCH64_FEATURE (PAN), AARCH64_NO_FEATURES}, {"lor", AARCH64_FEATURE (LOR), AARCH64_NO_FEATURES}, diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index a3ca714c299..b9fddd6a7f9 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -263,6 +263,8 @@ automatically cause those extensions to be disabled. @tab Enable Check Feature Status Extension. @item @code{gcs} @tab N/A @tab No @tab Enable Guarded Control Stack Extension. +@item @code{lse128} @Armv9.4-A @tab No + @tab Enable the 128-bit Atomic Instructions extension. This implies @code{lse}. @end multitable @node AArch64 Syntax diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 2b7e633fae2..3dd55f1438e 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -165,6 +165,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_GCS, /* SME2. */ AARCH64_FEATURE_SME2, + /* LSE128. */ + AARCH64_FEATURE_LSE128, AARCH64_NUM_FEATURES }; @@ -855,6 +857,7 @@ enum aarch64_insn_class log_imm, log_shift, lse_atomic, + lse128_atomic, movewide, pcreladdr, ic_system, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 150b042d7ee..58787fbc4a9 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2470,6 +2470,8 @@ static const aarch64_feature_set aarch64_feature_crc = AARCH64_FEATURE (CRC); static const aarch64_feature_set aarch64_feature_lse = AARCH64_FEATURE (LSE); +static const aarch64_feature_set aarch64_feature_lse128 = + AARCH64_FEATURES (2, LSE, LSE128); static const aarch64_feature_set aarch64_feature_lor = AARCH64_FEATURE (LOR); static const aarch64_feature_set aarch64_feature_rdma = @@ -2582,6 +2584,7 @@ static const aarch64_feature_set aarch64_feature_gcs = #define SIMD &aarch64_feature_simd #define CRC &aarch64_feature_crc #define LSE &aarch64_feature_lse +#define LSE128 &aarch64_feature_lse128 #define LOR &aarch64_feature_lor #define RDMA &aarch64_feature_rdma #define FP_F16 &aarch64_feature_fp_f16 @@ -2649,6 +2652,8 @@ static const aarch64_feature_set aarch64_feature_gcs = { NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, 0, 0, NULL } #define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LSE, OPS, QUALS, FLAGS, 0, 0, NULL } +#define _LSE128_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, LSE128, OPS, QUALS, FLAGS, 0, 0, NULL } #define _LOR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LOR, OPS, QUALS, FLAGS, 0, 0, NULL } #define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ From patchwork Mon Nov 6 13:12:48 2023 Content-Type: text/plain; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF00009523.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB9708 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Implement, together with the necessary tests, the following new LSE128 atomic instructions: * Atomic bit clear on quadword in memory (ldclrp{a|l|al}); * Atomic bit set on quadword in memory (ldsetp{a|l|al}); * Swap quadword in memory (swpp{a|l|al}); gas/ChangeLog: * testsuite/gas/aarch64/lse128-atomic.d: New. * testsuite/gas/aarch64/lse128-atomic.s: Likewise. opcodes/ChangeLog: * aarch64-tbl.h (ldclrp): new _LSE128_INSN entry. (ldclrpa): Likewise. (ldclrpal): Likewise. (ldclrpl): Likewise. (ldsetp): Likewise. (ldsetpa): Likewise. (ldsetpal): Likewise. (ldsetpl): Likewise. (swpp): Likewise. (swppa): Likewise. (swppal): Likewise. (swppl): Likewise. --- gas/testsuite/gas/aarch64/lse128-atomic.d | 32 ++++++++++++++++++++++ gas/testsuite/gas/aarch64/lse128-atomic.s | 33 +++++++++++++++++++++++ opcodes/aarch64-tbl.h | 13 +++++++++ 3 files changed, 78 insertions(+) create mode 100644 gas/testsuite/gas/aarch64/lse128-atomic.d create mode 100644 gas/testsuite/gas/aarch64/lse128-atomic.s diff --git a/gas/testsuite/gas/aarch64/lse128-atomic.d b/gas/testsuite/gas/aarch64/lse128-atomic.d new file mode 100644 index 00000000000..bea83fe3642 --- /dev/null +++ b/gas/testsuite/gas/aarch64/lse128-atomic.d @@ -0,0 +1,32 @@ +#objdump: -dr +#as:-march=armv9-a+lse128 + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: 19211040 ldclrp x0, x1, \[x2\] + 4: 192313e2 ldclrp x2, x3, \[sp\] + 8: 19a11040 ldclrpa x0, x1, \[x2\] + c: 19a313e2 ldclrpa x2, x3, \[sp\] + 10: 19e11040 ldclrpal x0, x1, \[x2\] + 14: 19e313e2 ldclrpal x2, x3, \[sp\] + 18: 19611040 ldclrpl x0, x1, \[x2\] + 1c: 196313e2 ldclrpl x2, x3, \[sp\] + 20: 19213040 ldsetp x0, x1, \[x2\] + 24: 192333e2 ldsetp x2, x3, \[sp\] + 28: 19a13040 ldsetpa x0, x1, \[x2\] + 2c: 19a333e2 ldsetpa x2, x3, \[sp\] + 30: 19e13040 ldsetpal x0, x1, \[x2\] + 34: 19e333e2 ldsetpal x2, x3, \[sp\] + 38: 19613040 ldsetpl x0, x1, \[x2\] + 3c: 196333e2 ldsetpl x2, x3, \[sp\] + 40: 19218040 swpp x0, x1, \[x2\] + 44: 192383e2 swpp x2, x3, \[sp\] + 48: 19a18040 swppa x0, x1, \[x2\] + 4c: 19a383e2 swppa x2, x3, \[sp\] + 50: 19e18040 swppal x0, x1, \[x2\] + 54: 19e383e2 swppal x2, x3, \[sp\] + 58: 19618040 swppl x0, x1, \[x2\] + 5c: 196383e2 swppl x2, x3, \[sp\] \ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/lse128-atomic.s b/gas/testsuite/gas/aarch64/lse128-atomic.s new file mode 100644 index 00000000000..802f1b76fc7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/lse128-atomic.s @@ -0,0 +1,33 @@ +/* lse128-atomic.s Test file For AArch64 LSE128 atomic instructions + encoding. + + Copyright (C) 2014-2023 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GAS. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the license, or + (at your option) any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + + .macro format_0 op + .irp suffix, , a, al, l + \op\suffix x0, x1, [x2] + \op\suffix x2, x3, [sp] + .endr + .endm + +func: + format_0 ldclrp + format_0 ldsetp + format_0 swpp diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 58787fbc4a9..74fd6695d81 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4101,6 +4101,19 @@ const struct aarch64_opcode aarch64_opcode_table[] = _LSE_INSN ("stuminlb", 0x3860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), _LSE_INSN ("stuminlh", 0x7860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), _LSE_INSN ("stuminl", 0xb860701f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), + /* LSE128 extension (atomic). */ + _LSE128_INSN ("ldclrp", 0x19201000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldclrpa", 0x19a01000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldclrpal", 0x19e01000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldclrpl", 0x19601000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldsetp", 0x19203000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldsetpa", 0x19a03000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldsetpal", 0x19e03000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("ldsetpl", 0x19603000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("swpp", 0x19208000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("swppa", 0x19a08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("swppal", 0x19e08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + _LSE128_INSN ("swppl", 0x19608000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), /* Move wide (immediate). */ CORE_INSN ("movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS), CORE_INSN ("mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV),