From patchwork Thu Sep 28 08:01:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cai X-Patchwork-Id: 76821 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AC38E3865C15 for ; Thu, 28 Sep 2023 08:02:26 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 355043858D20 for ; Thu, 28 Sep 2023 08:01:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 355043858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.6.5]) by gateway (Coremail) with SMTP id _____8Dxg_DzMhVlK7otAA--.22441S3; Thu, 28 Sep 2023 16:01:55 +0800 (CST) Received: from 5.5.5 (unknown [10.2.6.5]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bxni_zMhVl3CUVAA--.43623S4; Thu, 28 Sep 2023 16:01:55 +0800 (CST) From: Lulu Cai To: binutils@sourceware.org Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn, liuzhensong@loongson.cn, mengqinggang@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name, maskray@google.com, cailulu Subject: [PATCH 1/2] as: add option for generate R_LARCH_32/64_PCREL. Date: Thu, 28 Sep 2023 16:01:52 +0800 Message-Id: <20230928080153.3626326-1-cailulu@loongson.cn> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bxni_zMhVl3CUVAA--.43623S4 X-CM-SenderInfo: xfdlz3tox6z05rqj20fqof0/1tbiAQAIB2UU4qQG3QAFsn X-Coremail-Antispam: 1Uk129KBj93XoWxCFWfXr4fuw4kJFyUGFy3GFX_yoWrZFWUpa 47Z3ZIyF48AFZ3uF9IqasYga43Za4xG3y2vryaq3WxCwsxJ34Ygw42yr93XF1qvw4vkF42 vFyFqw15GFyDAFgCm3ZEXasCq-sJn29KB7ZKAUJUUUUr529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUU90b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVWxJr0_GcWln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12 xvs2x26I8E6xACxx1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r12 6r1DMcIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64 vIr41l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1l4IxYO2xFxVAFwI0_ Jrv_JF1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1V AY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAI cVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42 IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVj vjDU0xZFpf9x07j5xhLUUUUU= X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" From: cailulu Some older kernels cannot handle the newly generated R_LARCH_32/64_PCREL, so the assembler generates R_LARCH_ADD32/64+R_LARCH_SUB32/64 by default, and use the assembler option mthin-add-sub to generate R_LARCH_32/64_PCREL as much as possible. The Option of mthin-add-sub does not affect the generation of R_LARCH_32_PCREL relocation in .eh_frame. --- gas/config/tc-loongarch.c | 29 +++++++++++++++++++++++++++++ gas/config/tc-loongarch.h | 13 +++++++------ include/opcode/loongarch.h | 1 + 3 files changed, 37 insertions(+), 6 deletions(-) diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c index 57faffeb14d..d1d21fadb77 100644 --- a/gas/config/tc-loongarch.c +++ b/gas/config/tc-loongarch.c @@ -120,6 +120,7 @@ enum options OPTION_LA_GLOBAL_WITH_ABS, OPTION_RELAX, OPTION_NO_RELAX, + OPTION_THIN_ADD_SUB, OPTION_END_OF_ENUM, }; @@ -136,6 +137,7 @@ struct option md_longopts[] = { "mrelax", no_argument, NULL, OPTION_RELAX }, { "mno-relax", no_argument, NULL, OPTION_NO_RELAX }, + { "mthin-add-sub", no_argument, NULL, OPTION_THIN_ADD_SUB}, { NULL, no_argument, NULL, 0 } }; @@ -214,6 +216,10 @@ md_parse_option (int c, const char *arg) LARCH_opts.relax = 0; break; + case OPTION_THIN_ADD_SUB: + LARCH_opts.thin_add_sub = 1; + break; + case OPTION_IGNORE: break; @@ -1195,6 +1201,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) static int64_t stack_top; static int last_reloc_is_sop_push_pcrel_1 = 0; int last_reloc_is_sop_push_pcrel = last_reloc_is_sop_push_pcrel_1; + segT sub_segment; last_reloc_is_sop_push_pcrel_1 = 0; char *buf = fixP->fx_frag->fr_literal + fixP->fx_where; @@ -1287,6 +1294,23 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) } } + /* If symbol in .eh_frame the address may be adjusted, and contents of + .eh_frame will be adjusted, so use pc-relative relocation for FDE + initial location. + The Option of mthin-add-sub does not affect the generation of + R_LARCH_32_PCREL relocation in .eh_frame. */ + if (fixP->fx_r_type == BFD_RELOC_32 + && fixP->fx_addsy && fixP->fx_subsy + && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy)) + && strcmp (sub_segment->name, ".eh_frame") == 0 + && S_GET_VALUE (fixP->fx_subsy) + == fixP->fx_frag->fr_address + fixP->fx_where) + { + fixP->fx_r_type = BFD_RELOC_LARCH_32_PCREL; + fixP->fx_subsy = NULL; + break; + } + if (fixP->fx_addsy && fixP->fx_subsy) { fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); @@ -1589,6 +1613,11 @@ md_show_usage (FILE *stream) { fprintf (stream, _("LARCH options:\n")); /* FIXME */ + fprintf (stream, _("\ + -mthin-add-sub Convert a pair of R_LARCH_ADD32/64 and R_LARCH_SUB32/64 to\n\ + R_LARCH_32/64_PCREL as much as possible\n\ + The option does not affect the generation of R_LARCH_32_PCREL\n\ + relocations in .eh_frame\n")); } static void diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h index fd09435640b..4afa38422d6 100644 --- a/gas/config/tc-loongarch.h +++ b/gas/config/tc-loongarch.h @@ -75,12 +75,13 @@ extern bool loongarch_frag_align_code (int); or PC at start of subsy or with relax but sub_symbol_segment not in SEC_CODE, we generate 32/64_PCREL. */ #define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \ - (!((BFD_RELOC_32 || BFD_RELOC_64) \ - &&(!LARCH_opts.relax \ - || S_GET_VALUE (FIX->fx_subsy) \ - == FIX->fx_frag->fr_address + FIX->fx_where \ - || (LARCH_opts.relax \ - && ((S_GET_SEGMENT (FIX->fx_subsy)->flags & SEC_CODE) == 0))))) + (!(LARCH_opts.thin_add_sub \ + && (BFD_RELOC_32 || BFD_RELOC_64) \ + && (!LARCH_opts.relax \ + || S_GET_VALUE (FIX->fx_subsy) \ + == FIX->fx_frag->fr_address + FIX->fx_where \ + || (LARCH_opts.relax \ + && ((S_GET_SEGMENT (FIX->fx_subsy)->flags & SEC_CODE) == 0))))) #define TC_VALIDATE_FIX_SUB(FIX, SEG) 1 #define DIFF_EXPR_OK 1 diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h index e145db5e8a6..2ed4082cf43 100644 --- a/include/opcode/loongarch.h +++ b/include/opcode/loongarch.h @@ -236,6 +236,7 @@ dec2 : [1-9][0-9]? #define ase_gabs isa.use_la_global_with_abs int relax; + int thin_add_sub; } LARCH_opts; extern size_t loongarch_insn_length (insn_t insn); From patchwork Thu Sep 28 08:01:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cai X-Patchwork-Id: 76822 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 752BF3861912 for ; Thu, 28 Sep 2023 08:02:31 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 573163858CD1 for ; Thu, 28 Sep 2023 08:02:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 573163858CD1 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.6.5]) by gateway (Coremail) with SMTP id _____8DxVuj2MhVlM7otAA--.52200S3; Thu, 28 Sep 2023 16:01:58 +0800 (CST) Received: from 5.5.5 (unknown [10.2.6.5]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bxni_zMhVl3CUVAA--.43623S5; Thu, 28 Sep 2023 16:01:56 +0800 (CST) From: Lulu Cai To: binutils@sourceware.org Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn, liuzhensong@loongson.cn, mengqinggang@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name, maskray@google.com, cailulu Subject: [PATCH 2/2] Add testsuits for new assembler option of mthin-add-sub. Date: Thu, 28 Sep 2023 16:01:53 +0800 Message-Id: <20230928080153.3626326-2-cailulu@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230928080153.3626326-1-cailulu@loongson.cn> References: <20230928080153.3626326-1-cailulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bxni_zMhVl3CUVAA--.43623S5 X-CM-SenderInfo: xfdlz3tox6z05rqj20fqof0/1tbiAQAIB2UU4qQHKwAAsV X-Coremail-Antispam: 1Uk129KBj93XoW3Ar1UJryDCry8JryxXF15ZFc_yoWfXw1rpr 9rZrnakFW0kan7WF4UCry5Cw17Xw40v3Wjva4fGFyIkr1xGryxJw4xJw4aqayDtryUKw1a vr1kXrW2qFyvkwcCm3ZEXasCq-sJn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUv2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK 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List-Subscribe: , Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" From: cailulu --- gas/testsuite/gas/loongarch/no_thin_add_sub.d | 66 +++++++++++++++++++ gas/testsuite/gas/loongarch/no_thin_add_sub.s | 44 +++++++++++++ ...pcrel_norelax.d => thin_add_sub_norelax.d} | 25 ++++--- ...pcrel_norelax.s => thin_add_sub_norelax.s} | 8 +-- .../{pcrel_relax.d => thin_add_sub_relax.d} | 12 ++-- .../{pcrel_relax.s => thin_add_sub_relax.s} | 0 6 files changed, 131 insertions(+), 24 deletions(-) create mode 100644 gas/testsuite/gas/loongarch/no_thin_add_sub.d create mode 100644 gas/testsuite/gas/loongarch/no_thin_add_sub.s rename gas/testsuite/gas/loongarch/{pcrel_norelax.d => thin_add_sub_norelax.d} (75%) rename gas/testsuite/gas/loongarch/{pcrel_norelax.s => thin_add_sub_norelax.s} (87%) rename gas/testsuite/gas/loongarch/{pcrel_relax.d => thin_add_sub_relax.d} (91%) rename gas/testsuite/gas/loongarch/{pcrel_relax.s => thin_add_sub_relax.s} (100%) diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub.d b/gas/testsuite/gas/loongarch/no_thin_add_sub.d new file mode 100644 index 00000000000..614aca71d66 --- /dev/null +++ b/gas/testsuite/gas/loongarch/no_thin_add_sub.d @@ -0,0 +1,66 @@ +#as: +#objdump: -Dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +00000000.* <.L1>: +[ ]+... +[ ]+0:[ ]+R_LARCH_ADD32[ ]+.L3 +[ ]+0:[ ]+R_LARCH_SUB32[ ]+.L1 +[ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3 +[ ]+4:[ ]+R_LARCH_SUB32[ ]+.L1 + +0*00000008[ ]+<.L2>: +[ ]+... +[ ]+8:[ ]+R_LARCH_ADD64[ ]+.L3 +[ ]+8:[ ]+R_LARCH_SUB64[ ]+.L2 +[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3 +[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L2 + +Disassembly[ ]+of[ ]+section[ ]+sx: + +0*00000000[ ]+<.L3>: +[ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 +[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 +[ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff + +0*0000000c[ ]+<.L4>: +[ ]+... +[ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4 +[ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5 +[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L4 +[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L5 + +Disassembly[ ]+of[ ]+section[ ]+sy: + +0*00000000[ ]+<.L5>: +[ ]+... +[ ]+0:[ ]+R_LARCH_ADD32[ ]+.L1 +[ ]+0:[ ]+R_LARCH_SUB32[ ]+.L5 +[ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3 +[ ]+4:[ ]+R_LARCH_SUB32[ ]+.L5 +[ ]+8:[ ]+R_LARCH_ADD64[ ]+.L1 +[ ]+8:[ ]+R_LARCH_SUB64[ ]+.L5 +[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3 +[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L5 + +Disassembly[ ]+of[ ]+section[ ]+sz: + +0*00000000[ ]+: +[ ]+0:[ ]+00000000[ ]+.word[ ]+0x00000000 +[ ]+0:[ ]+R_LARCH_ADD32[ ]+.L1 +[ ]+0:[ ]+R_LARCH_SUB32[ ]+.L2 +[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 +[ ]+... +[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L3 +[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L5 +[ ]+c:[ ]+R_LARCH_ADD64[ ]+.L1 +[ ]+c:[ ]+R_LARCH_SUB64[ ]+.L2 +[ ]+14:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 +[ ]+18:[ ]+ffffffff[ ]+.word[ ]+0xffffffff +[ ]+... +[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L3 +[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L5 diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub.s b/gas/testsuite/gas/loongarch/no_thin_add_sub.s new file mode 100644 index 00000000000..c680168956f --- /dev/null +++ b/gas/testsuite/gas/loongarch/no_thin_add_sub.s @@ -0,0 +1,44 @@ + .section .text +.L1: + # add32+sub32 + .4byte .L3-.L1 + .4byte .L3-.L1 +.L2: + # add64+sub64 + .8byte .L3-.L2 + .8byte .L3-.L2 + + .section sx +.L3: + # no relocation + .4byte .L3-.L4 + .8byte .L3-.L4 +.L4: + # add32+sub32 + .4byte .L4-.L5 + # add64+sub64 + .8byte .L4-.L5 + + .section sy +.L5: + # add32+sub32 + .4byte .L1-.L5 + .4byte .L3-.L5 + # add64+sub64 + .8byte .L1-.L5 + .8byte .L3-.L5 + + .section sz + # add32+sub32 + .4byte .L1-.L2 + # no relocation + .4byte .L3-.L4 + # add32+sub32 + .4byte .L3-.L5 + + # add64+sub64 + .8byte .L1-.L2 + # no relocation + .8byte .L3-.L4 + # add64+sub64 + .8byte .L3-.L5 diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.d b/gas/testsuite/gas/loongarch/thin_add_sub_norelax.d similarity index 75% rename from gas/testsuite/gas/loongarch/pcrel_norelax.d rename to gas/testsuite/gas/loongarch/thin_add_sub_norelax.d index 842c8d48e0e..702093b6997 100644 --- a/gas/testsuite/gas/loongarch/pcrel_norelax.d +++ b/gas/testsuite/gas/loongarch/thin_add_sub_norelax.d @@ -1,4 +1,4 @@ -#as: -mno-relax +#as: -mthin-add-sub -mno-relax #objdump: -Dr .*:[ ]+file format .* @@ -10,20 +10,17 @@ Disassembly of section .text: [ ]+... [ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L3 [ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4 - -0*00000008[ ]+<.L2>: -[ ]+... [ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3 [ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L3\+0x8 Disassembly[ ]+of[ ]+section[ ]+sx: -0*00000000[ ]+<.L3>: +0*00000000[ ]+<.L3>: [ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 [ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 [ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff -0*0000000c[ ]+<.L4>: +0*0000000c[ ]+<.L4>: [ ]+... [ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4 [ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5 @@ -32,25 +29,25 @@ Disassembly[ ]+of[ ]+section[ ]+sx: Disassembly[ ]+of[ ]+section[ ]+sy: -0*00000000[ ]+<.L5>: +0*00000000[ ]+<.L5>: [ ]+... [ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L1 -[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L2\+0x4 +[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4 [ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L1\+0x8 -[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L2\+0x10 +[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L3\+0x10 Disassembly[ ]+of[ ]+section[ ]+sz: -0*00000000[ ]+: +0*00000000[ ]+: [ ]+0:[ ]+fffffff8[ ]+.word[ ]+0xfffffff8 [ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 [ ]+8:[ ]+00000000[ ]+.word[ ]+0x00000000 -[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L2 -[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L3 +[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L3 +[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L5 [ ]+c:[ ]+fffffff8[ ]+.word[ ]+0xfffffff8 [ ]+10:[ ]+ffffffff[ ]+.word[ ]+0xffffffff [ ]+14:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 [ ]+18:[ ]+ffffffff[ ]+.word[ ]+0xffffffff [ ]+... -[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L2 -[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L3 +[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L3 +[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L5 diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.s b/gas/testsuite/gas/loongarch/thin_add_sub_norelax.s similarity index 87% rename from gas/testsuite/gas/loongarch/pcrel_norelax.s rename to gas/testsuite/gas/loongarch/thin_add_sub_norelax.s index 09527f146a9..94cfd90870c 100644 --- a/gas/testsuite/gas/loongarch/pcrel_norelax.s +++ b/gas/testsuite/gas/loongarch/thin_add_sub_norelax.s @@ -23,20 +23,20 @@ .L5: # 32_pcrel .4byte .L1-.L5 - .4byte .L2-.L5 + .4byte .L3-.L5 # 64_pcrel .8byte .L1-.L5 - .8byte .L2-.L5 + .8byte .L3-.L5 .section sz # no relocation .4byte .L1-.L2 .4byte .L3-.L4 # add32+sub32 - .4byte .L2-.L3 + .4byte .L3-.L5 # no relocation .8byte .L1-.L2 .8byte .L3-.L4 # add64+sub64 - .8byte .L2-.L3 + .8byte .L3-.L5 diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.d b/gas/testsuite/gas/loongarch/thin_add_sub_relax.d similarity index 91% rename from gas/testsuite/gas/loongarch/pcrel_relax.d rename to gas/testsuite/gas/loongarch/thin_add_sub_relax.d index d6f875259be..9455c3e66bf 100644 --- a/gas/testsuite/gas/loongarch/pcrel_relax.d +++ b/gas/testsuite/gas/loongarch/thin_add_sub_relax.d @@ -1,4 +1,4 @@ -#as: +#as: -mthin-add-sub #objdump: -Dr .*:[ ]+file format .* @@ -12,7 +12,7 @@ Disassembly of section .text: [ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3 [ ]+4:[ ]+R_LARCH_SUB32[ ]+.L1 -0*00000008[ ]+<.L2>: +0*00000008[ ]+<.L2>: [ ]+... [ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3 [ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3 @@ -20,12 +20,12 @@ Disassembly of section .text: Disassembly[ ]+of[ ]+section[ ]+sx: -0*00000000[ ]+<.L3>: +0*00000000[ ]+<.L3>: [ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 [ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 [ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff -0*0000000c[ ]+<.L4>: +0*0000000c[ ]+<.L4>: [ ]+... [ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4 [ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5 @@ -34,7 +34,7 @@ Disassembly[ ]+of[ ]+section[ ]+sx: Disassembly[ ]+of[ ]+section[ ]+sy: -0*00000000[ ]+<.L5>: +0*00000000[ ]+<.L5>: [ ]+... [ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L1 [ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4 @@ -43,7 +43,7 @@ Disassembly[ ]+of[ ]+section[ ]+sy: Disassembly[ ]+of[ ]+section[ ]+sz: -0*00000000[ ]+: +0*00000000[ ]+: [ ]+0:[ ]+00000000[ ]+.word[ ]+0x00000000 [ ]+0:[ ]+R_LARCH_ADD32[ ]+.L1 [ ]+0:[ ]+R_LARCH_SUB32[ ]+.L2 diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.s b/gas/testsuite/gas/loongarch/thin_add_sub_relax.s similarity index 100% rename from gas/testsuite/gas/loongarch/pcrel_relax.s rename to gas/testsuite/gas/loongarch/thin_add_sub_relax.s