From patchwork Tue Sep 19 15:25:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Frager, Neal via Binutils" X-Patchwork-Id: 76388 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A17CE3854830 for ; Tue, 19 Sep 2023 15:27:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A17CE3854830 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1695137265; bh=XcpwT8qeeKX8VM/z+eIQm+CPkPmj8tSyv93yTJa9G+I=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=PH282URmGA9+17nWj8H2v7rFakkuZsRF9xdB7vD3gvpB9AMDwlqo1N7qqpbcxfRDp t6gVsx2kszU54npEDOfCEhVivZtB2LZkBpC8Z3Ez8nkK96BQe+2kNqLgNzoAw/mY54 q0XxoN9WUcv+oXUNRtmIVm1WYHGvIgBmQrW0ePms= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 3262A3858C31 for ; Tue, 19 Sep 2023 15:25:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3262A3858C31 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="370285662" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="370285662" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 08:25:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="739758912" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="739758912" Received: from scymds03.sc.intel.com ([10.148.94.166]) by orsmga007.jf.intel.com with ESMTP; 19 Sep 2023 08:25:31 -0700 Received: from shgcc101.sh.intel.com (shgcc101.sh.intel.com [10.239.85.97]) by scymds03.sc.intel.com (Postfix) with ESMTP id CBC8E6A; Tue, 19 Sep 2023 08:25:29 -0700 (PDT) To: binutils@sourceware.org Cc: jbeulich@suse.com, hongjiu.lu@intel.com, konglin1 Subject: [PATCH 1/8] Support APX GPR32 with rex2 prefix Date: Tue, 19 Sep 2023 15:25:20 +0000 Message-Id: <20230919152527.497773-2-lili.cui@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230919152527.497773-1-lili.cui@intel.com> References: <20230919152527.497773-1-lili.cui@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Cui, Lili via Binutils" From: "Frager, Neal via Binutils" Reply-To: "Cui, Lili" Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" From: konglin1 gas/ChangeLog: * gas/NEWS: Support Intel APX. * gas/config/tc-i386.c (struct _i386_insn): Add rex2 rex-byte for gpr32 r16-r31. Add has_nf, has_zero_upper. (cpu_arch): Add apx. (register_number): Handle RegRex2 for gpr32. (is_any_apx_encoding): New func. Test apx encoding. (is_any_apx_rex2_encoding): New func. Test rex2 prefix encoding. (build_rex2_prefix): New func. Build legacy insn in opcode 0/1 use gpr32 with rex2 prefix. (optimize_encoding): Handel add r16-r31 for registers. (md_assemble): Handle apx encoding. (check_EgprOperands): New func. Check if Egprs operands are valid for the instruction (match_template): Handle Egpr operands check. (set_rex_rex2): New func. set i.rex and i.rex2. (process_operands): Handle i.rex2. (set_rex_vrex): Ditto. (build_modrm_byte): Ditto. (output_insn): Handle rex2 2-byte prefix output. (check_register): Handle check egpr illegal without target apx, 64-bit mode and with rex_prefix.. (enum i386_error): Add invalid_pseudo_prefix. (struct _i386_insn): Add rex2_encoding. (md_assemble): Handle invalid_pseudo_prefix. (parse_insn): Handle Prefix_REX2. * gas/doc/c-i386.texi: Document .apx. * gas/testsuite/gas/i386/x86-64.exp: Run APX tests. * gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test. * gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-rex2. * testsuite/gas/i386/x86-64-opcode-inval-intel.d: D5 valid in 64-bit mode. * testsuite/gas/i386/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-rex2.d: New test. * testsuite/gas/i386/x86-64-apx-rex2.s: Ditto. * testsuite/gas/i386/x86-64-apx-rex2-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-rex2-inval.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Ditto. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-inval-pseudo.l: Add rex2 invalid testcase. * testsuite/gas/i386/x86-64-inval-pseudo.s: Ditto. opcode/ChangeLog: * opcodes/i386-gen.c: Add APX. * opcodes/i386-init.h (CPU_MWAITX_FLAGS): Regenerated. * opcodes/i386-opc.h (CpuAPX): New. (i386_cpu_flags): Add cpuapx. (No_egpr): New define for egprs (r16-r31) on instruction illegal. (i386_opcode_modifier): Add no_egpr. (RegRex2): New define. (Prefix_REX2): New. (Prefix_NoOptimize): Adjust the value. * opcodes/i386-opc.tbl: Handle legacy insn in opcode map0/1 illegal with egprs and add rex2 prefix. * opcodes/i386-reg.tbl: Add egprs (r16-r31). * opcodes/i386-tbl.h: Regenerated. * opcodes/i386-dis.c (struct instr_info): Add erex for gpr32. Add last_erex_prefix for rex2 prefix. (att_names64[][8]): Extend for gpr32. (att_names32[][8]): Ditto. (att_names16[][8]): Ditto. (att_names8rex[][8]): Ditto. (ckprefix): Handle REX2 (0xd5) prefix. (print_insn): Handle rex2 M0 for opcode map. (print_register): Handle erex for gpr32. (OP_E_memory): Ditto. (OP_REG): Ditto. (OP_EM): Ditto. (OP_EX): Ditto. --- gas/NEWS | 3 + gas/config/tc-i386.c | 174 +++++++++++++++-- gas/doc/c-i386.texi | 3 +- .../i386/ilp32/x86-64-opcode-inval-intel.d | 4 +- .../gas/i386/ilp32/x86-64-opcode-inval.d | 4 +- .../gas/i386/x86-64-apx-egpr-inval.l | 24 +++ .../gas/i386/x86-64-apx-egpr-inval.s | 18 ++ .../gas/i386/x86-64-apx-rex2-inval.d | 29 +++ .../gas/i386/x86-64-apx-rex2-inval.s | 25 +++ gas/testsuite/gas/i386/x86-64-apx-rex2.d | 148 +++++++++++++++ gas/testsuite/gas/i386/x86-64-apx-rex2.s | 175 ++++++++++++++++++ gas/testsuite/gas/i386/x86-64-inval-pseudo.l | 12 ++ gas/testsuite/gas/i386/x86-64-inval-pseudo.s | 8 + .../gas/i386/x86-64-opcode-inval-intel.d | 4 +- gas/testsuite/gas/i386/x86-64-opcode-inval.d | 4 +- gas/testsuite/gas/i386/x86-64-pseudos.d | 20 ++ gas/testsuite/gas/i386/x86-64-pseudos.s | 21 +++ gas/testsuite/gas/i386/x86-64.exp | 3 + include/opcode/i386.h | 2 + opcodes/i386-dis.c | 126 +++++++++++-- opcodes/i386-gen.c | 2 + opcodes/i386-opc.h | 14 +- opcodes/i386-opc.tbl | 26 +-- opcodes/i386-reg.tbl | 64 +++++++ 24 files changed, 852 insertions(+), 61 deletions(-) create mode 100644 gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-rex2-inval.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-rex2-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-rex2.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-rex2.s diff --git a/gas/NEWS b/gas/NEWS index 730ffad9bc9..7203ebb1a0b 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,8 @@ -*- text -*- + +* Add support for Intel APX instructions. + * Add support for Intel AVX10.1. * Add support for Intel PBNDKB instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index cec9a02be52..51486985919 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -247,6 +247,7 @@ enum i386_error invalid_vector_register_set, invalid_tmm_register_set, invalid_dest_and_src_register_set, + invalid_pseudo_prefix, unsupported_vector_index_register, unsupported_broadcast, broadcast_needed, @@ -353,6 +354,7 @@ struct _i386_insn modrm_byte rm; rex_byte rex; rex_byte vrex; + rex_byte rex2; // for extends gpr32 r16-r31 sib_byte sib; vex_prefix vex; @@ -405,6 +407,11 @@ struct _i386_insn /* Compressed disp8*N attribute. */ unsigned int memshift; + /* No CSPAZO flags update.*/ + bool has_nf; + + bool has_zero_upper; + /* Prefer load or store in encoding. */ enum { @@ -426,6 +433,9 @@ struct _i386_insn /* Prefer the REX byte in encoding. */ bool rex_encoding; + /* Prefer the REX2 byte in encoding. */ + bool rex2_encoding; + /* Disable instruction size optimization. */ bool no_optimize; @@ -1165,6 +1175,7 @@ static const arch_entry cpu_arch[] = VECARCH (sm4, SM4, ANY_SM4, reset), SUBARCH (pbndkb, PBNDKB, PBNDKB, false), VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set), + SUBARCH (apx_f, APX_F, APX_F, false), }; #undef SUBARCH @@ -1694,6 +1705,7 @@ is_cpu (const insn_template *t, enum i386_cpu cpu) case CpuHLE: return t->cpu.bitfield.cpuhle; case CpuAVX512F: return t->cpu.bitfield.cpuavx512f; case CpuAVX512VL: return t->cpu.bitfield.cpuavx512vl; + case CpuAPX_F: return t->cpu.bitfield.cpuapx_f; case Cpu64: return t->cpu.bitfield.cpu64; case CpuNo64: return t->cpu.bitfield.cpuno64; default: @@ -2332,6 +2344,9 @@ register_number (const reg_entry *r) if (r->reg_flags & RegRex) nr += 8; + if (r->reg_flags & RegRex2) + nr += 16; + if (r->reg_flags & RegVRex) nr += 16; @@ -3832,6 +3847,18 @@ is_any_vex_encoding (const insn_template *t) return t->opcode_modifier.vex || is_evex_encoding (t); } +static INLINE bool +is_any_apx_encoding (void) +{ + return i.rex2 || i.rex2_encoding; +} + +static INLINE bool +is_any_apx_rex2_encoding (void) +{ + return (i.rex2 && i.vex.length == 2) || i.rex2_encoding; +} + static unsigned int get_broadcast_bytes (const insn_template *t, bool diag) { @@ -4089,6 +4116,19 @@ build_evex_prefix (void) i.vex.bytes[3] |= i.mask.reg->reg_num; } +/* Build (2 bytes) rex2 prefix. + | D5h | + | m | R4 X4 B4 | W R X B | +*/ +static void +build_rex2_prefix (void) +{ + i.vex.length = 2; + i.vex.bytes[0] = 0xd5; + i.vex.bytes[1] = ((i.tm.opcode_space << 7) + | (i.rex2 << 4) | i.rex); +} + static void process_immext (void) { @@ -4354,12 +4394,12 @@ optimize_encoding (void) i.suffix = 0; /* Convert to byte registers. */ if (i.types[1].bitfield.word) - j = 16; + j = 16 + 16; // new 16 apx additional gprs. else if (i.types[1].bitfield.dword) - j = 32; + j = 32 + 16 * 2; // new 16 apx additional gprs else - j = 48; - if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) + j = 48 + 16 * 3; // new 16 apx additional gprs + if (!(i.op[1].regs->reg_flags & (RegRex | RegRex2)) && base_regnum < 4) j += 8; i.op[1].regs -= j; } @@ -5269,6 +5309,9 @@ md_assemble (char *line) case invalid_dest_and_src_register_set: err_msg = _("destination and source registers must be distinct"); break; + case invalid_pseudo_prefix: + err_msg = _("unsupport rex2 pseudo prefix"); + break; case unsupported_vector_index_register: err_msg = _("unsupported vector index register"); break; @@ -5498,7 +5541,17 @@ md_assemble (char *line) as_warn (_("translating to `%sp'"), insn_name (&i.tm)); } - if (is_any_vex_encoding (&i.tm)) + if (is_any_apx_encoding ()) + { + if (!is_any_vex_encoding (&i.tm) + && i.tm.opcode_space <= SPACE_0F + && !i.vex.register_specifier && !i.has_nf && !i.has_zero_upper) + build_rex2_prefix (); + + /* The individual REX.RXBW bits got consumed. */ + i.rex &= REX_OPCODE; + } + else if (is_any_vex_encoding (&i.tm)) { if (!cpu_arch_flags.bitfield.cpui286) { @@ -5514,6 +5567,13 @@ md_assemble (char *line) return; } + /* Check for explicit REX2 prefix. */ + if (i.rex2 || i.rex2_encoding) + { + as_bad (_("REX2 prefix invalid with `%s'"), insn_name (&i.tm)); + return; + } + if (i.tm.opcode_modifier.vex) build_vex_prefix (t); else @@ -5553,11 +5613,11 @@ md_assemble (char *line) && (i.op[1].regs->reg_flags & RegRex64) != 0) || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) - && i.rex != 0)) + && (i.rex != 0 || i.rex2!=0))) { int x; - - i.rex |= REX_OPCODE; + if (!i.rex2) + i.rex |= REX_OPCODE; for (x = 0; x < 2; x++) { /* Look for 8 bit operand that uses old registers. */ @@ -5567,9 +5627,16 @@ md_assemble (char *line) gas_assert (!(i.op[x].regs->reg_flags & RegRex)); /* In case it is "hi" register, give up. */ if (i.op[x].regs->reg_num > 3) - as_bad (_("can't encode register '%s%s' in an " - "instruction requiring REX prefix."), - register_prefix, i.op[x].regs->reg_name); + { + if (i.rex) + as_bad (_("can't encode register '%s%s' in an " + "instruction requiring REX prefix."), + register_prefix, i.op[x].regs->reg_name); + else + as_bad (_("can't encode register '%s%s' in an " + "instruction requiring REX2 prefix."), + register_prefix, i.op[x].regs->reg_name); + } /* Otherwise it is equivalent to the extended register. Since the encoding doesn't change this is merely @@ -5580,7 +5647,7 @@ md_assemble (char *line) } } - if (i.rex == 0 && i.rex_encoding) + if ((i.rex == 0 && i.rex_encoding) || (i.rex2 == 0 && i.rex2_encoding)) { /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand that uses legacy register. If it is "hi" register, don't add @@ -5594,6 +5661,7 @@ md_assemble (char *line) { gas_assert (!(i.op[x].regs->reg_flags & RegRex)); i.rex_encoding = false; + i.rex2_encoding = false; break; } @@ -5772,6 +5840,10 @@ parse_insn (const char *line, char *mnemonic, bool prefix_only) /* {rex} */ i.rex_encoding = true; break; + case Prefix_REX2: + /* {rex2} */ + i.rex2_encoding = true; + break; case Prefix_NoOptimize: /* {nooptimize} */ i.no_optimize = true; @@ -6899,6 +6971,42 @@ VEX_check_encoding (const insn_template *t) return 0; } +/* Check if Egprs operands are valid for the instruction. */ + +static int +check_EgprOperands (const insn_template *t) +{ + if (t->opcode_modifier.no_egpr) + { + for (unsigned int op = 0; op < i.operands; op++) + { + if (i.types[op].bitfield.class != Reg) + continue; + + if (i.op[op].regs->reg_flags & RegRex2) + { + i.error = register_type_mismatch; + return 1; + } + } + + if ((i.index_reg && (i.index_reg->reg_flags & RegRex2)) + || (i.base_reg && (i.base_reg->reg_flags & RegRex2))) + { + i.error = register_type_mismatch; + return 1; + } + + /* Check pseudo prefix {rex2} are valid. */ + if (i.rex2_encoding) + { + i.error = invalid_pseudo_prefix; + return 1; + } + } + return 0; +} + /* Helper function for the progress() macro in match_template(). */ static INLINE enum i386_error progress (enum i386_error new, enum i386_error last, @@ -7371,6 +7479,13 @@ match_template (char mnem_suffix) continue; } + /* Check if EGRPS operands(r16-r31) are valid. */ + if (check_EgprOperands (t)) + { + specific_error = progress (i.error); + continue; + } + /* We've found a match; break out of loop. */ break; } @@ -8245,6 +8360,18 @@ static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit, if (r->reg_flags & RegVRex) i.vrex |= rex_bit; + + if (r->reg_flags & RegRex2) + i.rex2 |= rex_bit; +} + +static INLINE void +set_rex_rex2 (const reg_entry *r, unsigned int rex_bit) +{ + if ((r->reg_flags & RegRex) != 0) + i.rex |= rex_bit; + if ((r->reg_flags & RegRex2) != 0) + i.rex2 |= rex_bit; } static int @@ -8728,8 +8855,7 @@ build_modrm_byte (void) i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; i.types[op] = operand_type_and_not (i.types[op], anydisp); i.types[op].bitfield.disp32 = 1; - if ((i.index_reg->reg_flags & RegRex) != 0) - i.rex |= REX_X; + set_rex_rex2 (i.index_reg, REX_X); } } /* RIP addressing for 64bit mode. */ @@ -8800,8 +8926,7 @@ build_modrm_byte (void) if (!i.tm.opcode_modifier.sib) i.rm.regmem = i.base_reg->reg_num; - if ((i.base_reg->reg_flags & RegRex) != 0) - i.rex |= REX_B; + set_rex_rex2 (i.base_reg, REX_B); i.sib.base = i.base_reg->reg_num; /* x86-64 ignores REX prefix bit here to avoid decoder complications. */ @@ -8839,8 +8964,7 @@ build_modrm_byte (void) else i.sib.index = i.index_reg->reg_num; i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; - if ((i.index_reg->reg_flags & RegRex) != 0) - i.rex |= REX_X; + set_rex_rex2 (i.index_reg, REX_X); } if (i.disp_operands @@ -9987,6 +10111,12 @@ output_insn (void) for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) if (*q) frag_opcode_byte (*q); + + if (is_any_apx_rex2_encoding ()) + { + frag_opcode_byte (i.vex.bytes[0]); + frag_opcode_byte (i.vex.bytes[1]); + } } else { @@ -13985,6 +14115,14 @@ static bool check_register (const reg_entry *r) i.vec_encoding = vex_encoding_error; } + if (r->reg_flags & RegRex2) + { + if (!cpu_arch_flags.bitfield.cpuapx_f + || flag_code != CODE_64BIT + || i.rex_encoding) + return false; + } + if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) && (!cpu_arch_flags.bitfield.cpu64 || r->reg_type.bitfield.class != RegCR diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index b04e1b00b4b..5d79a332f53 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -216,6 +216,7 @@ accept various extension mnemonics. For example, @code{avx10.1/512}, @code{avx10.1/256}, @code{avx10.1/128}, +@code{apx}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1662,7 +1663,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru} @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb} -@item @samp{.tlbsync} +@item @samp{.tlbsync} @tab @samp{.apx} @end multitable Apart from the warning, there are only two other effects on diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d b/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d index a2b09d2e74f..605548285f2 100644 --- a/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d @@ -11,11 +11,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 37 \(bad\) 0+1 : -[ ]*[a-f0-9]+: d5 \(bad\) +[ ]*[a-f0-9]+: d5 rex2 [ ]*[a-f0-9]+: 0a .byte 0xa 0+3 : -[ ]*[a-f0-9]+: d5 \(bad\) +[ ]*[a-f0-9]+: d5 rex2 [ ]*[a-f0-9]+: 02 .byte 0x2 0+5 : diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval.d b/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval.d index 5a17b0b412e..c9d3f2fdbb6 100644 --- a/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval.d +++ b/gas/testsuite/gas/i386/ilp32/x86-64-opcode-inval.d @@ -11,11 +11,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 37 \(bad\) 0+1 : -[ ]*[a-f0-9]+: d5 \(bad\) +[ ]*[a-f0-9]+: d5 rex2 [ ]*[a-f0-9]+: 0a .byte 0xa 0+3 : -[ ]*[a-f0-9]+: d5 \(bad\) +[ ]*[a-f0-9]+: d5 rex2 [ ]*[a-f0-9]+: 02 .byte 0x2 0+5 : diff --git a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l new file mode 100644 index 00000000000..c419f449f27 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l @@ -0,0 +1,24 @@ +.*: Assembler messages: +.*:4: Error: bad register name `%r17d' +.*:7: Error: register type mismatch for `xsave' +.*:8: Error: register type mismatch for `xsave64' +.*:9: Error: register type mismatch for `xrstor' +.*:10: Error: register type mismatch for `xrstor64' +.*:11: Error: register type mismatch for `xsaves' +.*:12: Error: register type mismatch for `xsaves64' +.*:13: Error: register type mismatch for `xrstors' +.*:14: Error: register type mismatch for `xrstors64' +.*:15: Error: register type mismatch for `xsaveopt' +.*:16: Error: register type mismatch for `xsaveopt64' +.*:17: Error: register type mismatch for `xsavec' +.*:18: Error: register type mismatch for `xsavec64' +GAS LISTING .* +#... +[ ]*1[ ]+\# Check Illegal 64bit APX instructions +[ ]*2[ ]+\.text +[ ]*3[ ]+\.arch \.noapx_f +[ ]*4[ ]+test \$0x7, %r17d +[ ]*5[ ]+\.arch \.apx_f +[ ]*6[ ]+\?\?\?\? D510F7C1 test \$0x7, %r17d +[ ]*6[ ]+07000000 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s new file mode 100644 index 00000000000..5249b888046 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s @@ -0,0 +1,18 @@ +# Check Illegal 64bit APX instructions + .text + .arch .noapx_f + test $0x7, %r17d + .arch .apx_f + test $0x7, %r17d + xsave (%r16, %rbx) + xsave64 (%r16, %rbx) + xrstor (%r16, %rbx) + xrstor64 (%r16, %rbx) + xsaves (%r16, %rbx) + xsaves64 (%r16, %rbx) + xrstors (%r16, %rbx) + xrstors64 (%r16, %rbx) + xsaveopt (%r16, %rbx) + xsaveopt64 (%r16, %rbx) + xsavec (%r16, %rbx) + xsavec64 (%r16, %rbx) diff --git a/gas/testsuite/gas/i386/x86-64-apx-rex2-inval.d b/gas/testsuite/gas/i386/x86-64-apx-rex2-inval.d new file mode 100644 index 00000000000..655792818cc --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-rex2-inval.d @@ -0,0 +1,29 @@ +#as: +#objdump: -dw +#name: x86-64 APX use gpr32 with rex2 prefix illegal check +#source: x86-64-apx-rex2-inval.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +\s*[a-f0-9]+:\s*d5 f0 d5 f0\s+{rex2} pmullw %mm0,%mm6 +\s*[a-f0-9]+:\s*d5 f9 d5 f9\s+{rex2} pmullw %mm1,%mm7 +\s*[a-f0-9]+:\s*d5 88 d5 f9\s+{rex2} pmullw %mm1,%mm7 +\s*[a-f0-9]+:\s*d5 f7 d5 f9\s+{rex2} pmullw %mm1,%mm7 +\s*[a-f0-9]+:\s*d5 80 d5 f9\s+{rex2} pmullw %mm1,%mm7 +\s*[a-f0-9]+:\s*66 d5 f9 d5 f9\s+{rex2} pmullw %xmm9,%xmm7 +\s*[a-f0-9]+:\s*66 41\s+data16 rex.B +\s*[a-f0-9]+:\s*d5 f9 d5 f9\s+{rex2} pmullw %mm1,%mm7 +\s*[a-f0-9]+:\s*d5 ff 21 f8\s+{rex2} mov %db15,%r24 +\s*[a-f0-9]+:\s*d5 01 21 00\s+{rex2} and %eax,\(%r8\) +\s*[a-f0-9]+:\s*d5 00 00 f7\s+{rex2} add %sil,%dil +\s*[a-f0-9]+:\s*d5 ff 20 f8\s+{rex2} mov %cr15,%r24 +\s*[a-f0-9]+:\s*d5 81 ae\s+\(bad\) +\s*[a-f0-9]+:\s*27\s+\(bad\) +\s*[a-f0-9]+:\s*d5 c1 38\s+\(bad\) +\s*[a-f0-9]+:\s*f6\s+.byte 0xf6 +\s*[a-f0-9]+:\s*07\s+\(bad\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-apx-rex2-inval.s b/gas/testsuite/gas/i386/x86-64-apx-rex2-inval.s new file mode 100644 index 00000000000..51dd8df79d6 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-rex2-inval.s @@ -0,0 +1,25 @@ +# Check 64bit instructions with rex2 prefix bad encoding + + .allow_index_reg + .text +_start: +# check {rex2} pseudo prefix to force REX2 encoding. +.byte 0xd5, 0xf0, 0xd5, 0xf0 +.byte 0xd5, 0xf9, 0xd5, 0xf9 +.byte 0xd5, 0x88, 0xd5, 0xf9 +.byte 0xd5, 0xf7, 0xd5, 0xf9 +.byte 0xd5, 0x80, 0xd5, 0xf9 + +.byte 0x66 +.byte 0xd5, 0xf9, 0xd5, 0xf9 +.byte 0x66, 0x41 +.byte 0xd5, 0xf9, 0xd5, 0xf9 +.byte 0xd5, 0xff, 0x21, 0xf8 +.byte 0xd5, 0x01, 0x21, 0x00 +.byte 0xd5, 0x00, 0x00, 0xf7 +.byte 0xd5, 0xff, 0x20, 0xf8 +# check xsave/xstore are not allowed to use rex2. +.byte 0xd5, 0x81, 0xae, 0x27 +# check rex2 only use for map0/1 +.byte 0xd5, 0xc1, 0x38, 0xf6, 0x07 + diff --git a/gas/testsuite/gas/i386/x86-64-apx-rex2.d b/gas/testsuite/gas/i386/x86-64-apx-rex2.d new file mode 100644 index 00000000000..d64b615ff4d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-rex2.d @@ -0,0 +1,148 @@ +#as: +#objdump: -dw +#name: x86-64 APX use gpr32 with rex2 prefix +#source: x86-64-apx-rex2.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +\s*[a-f0-9]+:\s*d5 11 f6 c0 07\s+test \$0x7,%r24b +\s*[a-f0-9]+:\s*d5 11 f7 c0 07 00 00 00 test \$0x7,%r24d +\s*[a-f0-9]+:\s*d5 19 f7 c0 07 00 00 00 test \$0x7,%r24 +\s*[a-f0-9]+:\s*66 d5 11 f7 c0 07 00 test \$0x7,%r24w +\s*[a-f0-9]+:\s*d5 40 8d 00\s+lea \(%rax\),%r16d +\s*[a-f0-9]+:\s*d5 40 8d 08\s+lea \(%rax\),%r17d +\s*[a-f0-9]+:\s*d5 40 8d 10\s+lea \(%rax\),%r18d +\s*[a-f0-9]+:\s*d5 40 8d 18\s+lea \(%rax\),%r19d +\s*[a-f0-9]+:\s*d5 40 8d 20\s+lea \(%rax\),%r20d +\s*[a-f0-9]+:\s*d5 40 8d 28\s+lea \(%rax\),%r21d +\s*[a-f0-9]+:\s*d5 40 8d 30\s+lea \(%rax\),%r22d +\s*[a-f0-9]+:\s*d5 40 8d 38\s+lea \(%rax\),%r23d +\s*[a-f0-9]+:\s*d5 44 8d 00\s+lea \(%rax\),%r24d +\s*[a-f0-9]+:\s*d5 44 8d 08\s+lea \(%rax\),%r25d +\s*[a-f0-9]+:\s*d5 44 8d 10\s+lea \(%rax\),%r26d +\s*[a-f0-9]+:\s*d5 44 8d 18\s+lea \(%rax\),%r27d +\s*[a-f0-9]+:\s*d5 44 8d 20\s+lea \(%rax\),%r28d +\s*[a-f0-9]+:\s*d5 44 8d 28\s+lea \(%rax\),%r29d +\s*[a-f0-9]+:\s*d5 44 8d 30\s+lea \(%rax\),%r30d +\s*[a-f0-9]+:\s*d5 44 8d 38\s+lea \(%rax\),%r31d +\s*[a-f0-9]+:\s*d5 20 8d 04 05 00 00 00 00\s+lea 0x0\(,%r16,1\),%eax +\s*[a-f0-9]+:\s*d5 20 8d 04 0d 00 00 00 00\s+lea 0x0\(,%r17,1\),%eax +\s*[a-f0-9]+:\s*d5 20 8d 04 15 00 00 00 00\s+lea 0x0\(,%r18,1\),%eax +\s*[a-f0-9]+:\s*d5 20 8d 04 1d 00 00 00 00\s+lea 0x0\(,%r19,1\),%eax +\s*[a-f0-9]+:\s*d5 20 8d 04 25 00 00 00 00\s+lea 0x0\(,%r20,1\),%eax +\s*[a-f0-9]+:\s*d5 20 8d 04 2d 00 00 00 00\s+lea 0x0\(,%r21,1\),%eax +\s*[a-f0-9]+:\s*d5 20 8d 04 35 00 00 00 00\s+lea 0x0\(,%r22,1\),%eax +\s*[a-f0-9]+:\s*d5 20 8d 04 3d 00 00 00 00\s+lea 0x0\(,%r23,1\),%eax +\s*[a-f0-9]+:\s*d5 22 8d 04 05 00 00 00 00\s+lea 0x0\(,%r24,1\),%eax +\s*[a-f0-9]+:\s*d5 22 8d 04 0d 00 00 00 00\s+lea 0x0\(,%r25,1\),%eax +\s*[a-f0-9]+:\s*d5 22 8d 04 15 00 00 00 00\s+lea 0x0\(,%r26,1\),%eax +\s*[a-f0-9]+:\s*d5 22 8d 04 1d 00 00 00 00\s+lea 0x0\(,%r27,1\),%eax +\s*[a-f0-9]+:\s*d5 22 8d 04 25 00 00 00 00\s+lea 0x0\(,%r28,1\),%eax +\s*[a-f0-9]+:\s*d5 22 8d 04 2d 00 00 00 00\s+lea 0x0\(,%r29,1\),%eax +\s*[a-f0-9]+:\s*d5 22 8d 04 35 00 00 00 00\s+lea 0x0\(,%r30,1\),%eax +\s*[a-f0-9]+:\s*d5 22 8d 04 3d 00 00 00 00\s+lea 0x0\(,%r31,1\),%eax +\s*[a-f0-9]+:\s*d5 10 8d 00\s+lea \(%r16\),%eax +\s*[a-f0-9]+:\s*d5 10 8d 01\s+lea \(%r17\),%eax +\s*[a-f0-9]+:\s*d5 10 8d 02\s+lea \(%r18\),%eax +\s*[a-f0-9]+:\s*d5 10 8d 03\s+lea \(%r19\),%eax +\s*[a-f0-9]+:\s*d5 10 8d 04 24 lea \(%r20\),%eax +\s*[a-f0-9]+:\s*d5 10 8d 45 00 lea 0x0\(%r21\),%eax +\s*[a-f0-9]+:\s*d5 10 8d 06\s+lea \(%r22\),%eax +\s*[a-f0-9]+:\s*d5 10 8d 07\s+lea \(%r23\),%eax +\s*[a-f0-9]+:\s*d5 11 8d 00\s+lea \(%r24\),%eax +\s*[a-f0-9]+:\s*d5 11 8d 01\s+lea \(%r25\),%eax +\s*[a-f0-9]+:\s*d5 11 8d 02\s+lea \(%r26\),%eax +\s*[a-f0-9]+:\s*d5 11 8d 03\s+lea \(%r27\),%eax +\s*[a-f0-9]+:\s*d5 11 8d 04 24 lea \(%r28\),%eax +\s*[a-f0-9]+:\s*d5 11 8d 45 00 lea 0x0\(%r29\),%eax +\s*[a-f0-9]+:\s*d5 11 8d 06 lea \(%r30\),%eax +\s*[a-f0-9]+:\s*d5 11 8d 07 lea \(%r31\),%eax +\s*[a-f0-9]+:\s*d5 10 8d 44 24 01 lea 0x1\(%r20\),%eax +\s*[a-f0-9]+:\s*d5 11 8d 44 24 01 lea 0x1\(%r28\),%eax +\s*[a-f0-9]+:\s*d5 10 8d 84 24 81 00 00 00 lea 0x81\(%r20\),%eax +\s*[a-f0-9]+:\s*d5 11 8d 84 24 81 00 00 00 lea 0x81\(%r28\),%eax +\s*[a-f0-9]+:\s*4c 8d 38 lea \(%rax\),%r15 +\s*[a-f0-9]+:\s*d5 48 8d 00 lea \(%rax\),%r16 +\s*[a-f0-9]+:\s*49 8d 07 lea \(%r15\),%rax +\s*[a-f0-9]+:\s*d5 18 8d 00 lea \(%r16\),%rax +\s*[a-f0-9]+:\s*4a 8d 04 3d 00 00 00 00 lea 0x0\(,%r15,1\),%rax +\s*[a-f0-9]+:\s*d5 28 8d 04 05 00 00 00 00 lea 0x0\(,%r16,1\),%rax +\s*[a-f0-9]+:\s*44 0f af f8 imul %eax,%r15d +\s*[a-f0-9]+:\s*d5 c0 af c0 imul %eax,%r16d +\s*[a-f0-9]+:\s*d5 90 62 12 punpckldq %mm2,\(%r18\) +\s*[a-f0-9]+:\s*d5 10 b8 01 00 00 00 mov \$0x1,%r16d +\s*[a-f0-9]+:\s*d5 18 63 c0\s+movslq %r16d,%rax +\s*[a-f0-9]+:\s*d5 48 63 c0\s+movslq %eax,%r16 +\s*[a-f0-9]+:\s*d5 58 63 c8\s+movslq %r16d,%r17 +\s*[a-f0-9]+:\s*d5 90 4c c0\s+cmovl %r16d,%eax +\s*[a-f0-9]+:\s*d5 c0 4c c0\s+cmovl %eax,%r16d +\s*[a-f0-9]+:\s*d5 d0 4c c8\s+cmovl %r16d,%r17d +\s*[a-f0-9]+:\s*d5 90 af 1c 00\s+imul \(%r16,%rax,1\),%ebx +\s*[a-f0-9]+:\s*d5 a0 af 1c 00\s+imul \(%rax,%r16,1\),%ebx +\s*[a-f0-9]+:\s*d5 c0 af 04 18\s+imul \(%rax,%rbx,1\),%r16d +\s*[a-f0-9]+:\s*d5 b0 af 04 08\s+imul \(%r16,%r17,1\),%eax +\s*[a-f0-9]+:\s*d5 e0 af 0c 00\s+imul \(%rax,%r16,1\),%r17d +\s*[a-f0-9]+:\s*d5 d0 af 0c 00\s+imul \(%r16,%rax,1\),%r17d +\s*[a-f0-9]+:\s*d5 f0 af 14 08\s+imul \(%r16,%r17,1\),%r18d +\s*[a-f0-9]+:\s*d5 90 4c 1c 00\s+cmovl \(%r16,%rax,1\),%ebx +\s*[a-f0-9]+:\s*d5 a0 4c 1c 00\s+cmovl \(%rax,%r16,1\),%ebx +\s*[a-f0-9]+:\s*d5 c0 4c 04 18\s+cmovl \(%rax,%rbx,1\),%r16d +\s*[a-f0-9]+:\s*d5 b0 4c 04 08\s+cmovl \(%r16,%r17,1\),%eax +\s*[a-f0-9]+:\s*d5 e0 4c 0c 00\s+cmovl \(%rax,%r16,1\),%r17d +\s*[a-f0-9]+:\s*d5 d0 4c 0c 00\s+cmovl \(%r16,%rax,1\),%r17d +\s*[a-f0-9]+:\s*d5 f0 4c 14 08\s+cmovl \(%r16,%r17,1\),%r18d +\s*[a-f0-9]+:\s*d5 10 89 c0 \s+mov %eax,%r16d +\s*[a-f0-9]+:\s*d5 40 89 c0 \s+mov %r16d,%eax +\s*[a-f0-9]+:\s*d5 50 89 c1 \s+mov %r16d,%r17d +\s*[a-f0-9]+:\s*d5 10 8b 1c 00\s+mov \(%r16,%rax,1\),%ebx +\s*[a-f0-9]+:\s*d5 20 8b 1c 00\s+mov \(%rax,%r16,1\),%ebx +\s*[a-f0-9]+:\s*d5 40 8b 04 18\s+mov \(%rax,%rbx,1\),%r16d +\s*[a-f0-9]+:\s*d5 30 8b 04 08\s+mov \(%r16,%r17,1\),%eax +\s*[a-f0-9]+:\s*d5 60 8b 0c 00\s+mov \(%rax,%r16,1\),%r17d +\s*[a-f0-9]+:\s*d5 50 8b 0c 00\s+mov \(%r16,%rax,1\),%r17d +\s*[a-f0-9]+:\s*d5 70 8b 14 08\s+mov \(%r16,%r17,1\),%r18d +\s*[a-f0-9]+:\s*d5 a0 94 04 00\s+sete \(%rax,%r16,1\) +\s*[a-f0-9]+:\s*d5 90 94 04 00\s+sete \(%r16,%rax,1\) +\s*[a-f0-9]+:\s*d5 b0 94 04 08\s+sete \(%r16,%r17,1\) +\s*[a-f0-9]+:\s*d5 a0 1f 04 00\s+nopl \(%rax,%r16,1\) +\s*[a-f0-9]+:\s*d5 90 1f 04 00\s+nopl \(%r16,%rax,1\) +\s*[a-f0-9]+:\s*d5 b0 1f 04 08\s+nopl \(%r16,%r17,1\) +\s*[a-f0-9]+:\s*d5 20 ff 04 00\s+incl \(%rax,%r16,1\) +\s*[a-f0-9]+:\s*d5 10 ff 04 00\s+incl \(%r16,%rax,1\) +\s*[a-f0-9]+:\s*d5 30 ff 04 08\s+incl \(%r16,%r17,1\) +\s*[a-f0-9]+:\s*d5 20 ff 0c 00\s+decl \(%rax,%r16,1\) +\s*[a-f0-9]+:\s*d5 10 ff 0c 00\s+decl \(%r16,%rax,1\) +\s*[a-f0-9]+:\s*d5 30 ff 0c 08\s+decl \(%r16,%r17,1\) +\s*[a-f0-9]+:\s*d5 20 f7 14 00\s+notl \(%rax,%r16,1\) +\s*[a-f0-9]+:\s*d5 10 f7 14 00\s+notl \(%r16,%rax,1\) +\s*[a-f0-9]+:\s*d5 30 f7 14 08\s+notl \(%r16,%r17,1\) +\s*[a-f0-9]+:\s*d5 20 f7 1c 00\s+negl \(%rax,%r16,1\) +\s*[a-f0-9]+:\s*d5 10 f7 1c 00\s+negl \(%r16,%rax,1\) +\s*[a-f0-9]+:\s*d5 30 f7 1c 08\s+negl \(%r16,%r17,1\) +\s*[a-f0-9]+:\s*d5 20 f7 24 00\s+mull \(%rax,%r16,1\) +\s*[a-f0-9]+:\s*d5 10 f7 24 00\s+mull \(%r16,%rax,1\) +\s*[a-f0-9]+:\s*d5 30 f7 24 08\s+mull \(%r16,%r17,1\) +\s*[a-f0-9]+:\s*d5 20 f7 2c 00\s+imull \(%rax,%r16,1\) +\s*[a-f0-9]+:\s*d5 10 f7 2c 00\s+imull \(%r16,%rax,1\) +\s*[a-f0-9]+:\s*d5 30 f7 2c 08\s+imull \(%r16,%r17,1\) +\s*[a-f0-9]+:\s*d5 20 f7 34 00\s+divl \(%rax,%r16,1\) +\s*[a-f0-9]+:\s*d5 10 f7 34 00\s+divl \(%r16,%rax,1\) +\s*[a-f0-9]+:\s*d5 30 f7 34 08\s+divl \(%r16,%r17,1\) +\s*[a-f0-9]+:\s*d5 20 f7 3c 00\s+idivl \(%rax,%r16,1\) +\s*[a-f0-9]+:\s*d5 10 f7 3c 00\s+idivl \(%r16,%rax,1\) +\s*[a-f0-9]+:\s*d5 30 f7 3c 08\s+idivl \(%r16,%r17,1\) +\s*[a-f0-9]+:\s*d5 90 94 c0 \s+sete %r16b +\s*[a-f0-9]+:\s*d5 90 1f c0 \s+nop %r16d +\s*[a-f0-9]+:\s*d5 10 ff c0 \s+inc %r16d +\s*[a-f0-9]+:\s*d5 10 ff c8 \s+dec %r16d +\s*[a-f0-9]+:\s*d5 10 f7 d0 \s+not %r16d +\s*[a-f0-9]+:\s*d5 10 f7 d8 \s+neg %r16d +\s*[a-f0-9]+:\s*d5 10 f7 e0 \s+mul %r16d +\s*[a-f0-9]+:\s*d5 10 f7 e8 \s+imul %r16d +\s*[a-f0-9]+:\s*d5 10 f7 f0 \s+div %r16d +\s*[a-f0-9]+:\s*d5 10 f7 f8 \s+idiv %r16d +#pass diff --git a/gas/testsuite/gas/i386/x86-64-apx-rex2.s b/gas/testsuite/gas/i386/x86-64-apx-rex2.s new file mode 100644 index 00000000000..62bf817aae6 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-rex2.s @@ -0,0 +1,175 @@ +# Check 64bit instructions with rex2 prefix encoding + + .allow_index_reg + .text +_start: + test $0x7, %r24b + test $0x7, %r24d + test $0x7, %r24 + test $0x7, %r24w +## R bit + leal (%rax), %r16d + leal (%rax), %r17d + leal (%rax), %r18d + leal (%rax), %r19d + leal (%rax), %r20d + leal (%rax), %r21d + leal (%rax), %r22d + leal (%rax), %r23d + leal (%rax), %r24d + leal (%rax), %r25d + leal (%rax), %r26d + leal (%rax), %r27d + leal (%rax), %r28d + leal (%rax), %r29d + leal (%rax), %r30d + leal (%rax), %r31d +## X bit + leal (,%r16), %eax + leal (,%r17), %eax + leal (,%r18), %eax + leal (,%r19), %eax + leal (,%r20), %eax + leal (,%r21), %eax + leal (,%r22), %eax + leal (,%r23), %eax + leal (,%r24), %eax + leal (,%r25), %eax + leal (,%r26), %eax + leal (,%r27), %eax + leal (,%r28), %eax + leal (,%r29), %eax + leal (,%r30), %eax + leal (,%r31), %eax +## B bit + leal (%r16), %eax + leal (%r17), %eax + leal (%r18), %eax + leal (%r19), %eax + leal (%r20), %eax + leal (%r21), %eax + leal (%r22), %eax + leal (%r23), %eax + leal (%r24), %eax + leal (%r25), %eax + leal (%r26), %eax + leal (%r27), %eax + leal (%r28), %eax + leal (%r29), %eax + leal (%r30), %eax + leal (%r31), %eax +## SIB + leal 1(%r20), %eax + leal 1(%r28), %eax + leal 129(%r20), %eax + leal 129(%r28), %eax +## W bit + leaq (%rax), %r15 + leaq (%rax), %r16 + leaq (%r15), %rax + leaq (%r16), %rax + leaq (,%r15), %rax + leaq (,%r16), %rax +## M bit + imull %eax, %r15d + imull %eax, %r16d + punpckldq (%r18), %mm2 #D5906212 + +## AddRegFrm + movl $1, %r16d +## MRMSrcReg + movslq %r16d, %rax + movslq %eax, %r16 + movslq %r16d, %r17 +## MRMSrcRegCC + cmovll %r16d, %eax + cmovll %eax, %r16d + cmovll %r16d, %r17d +## MRMSrcMem + imull (%r16,%rax), %ebx + imull (%rax,%r16), %ebx + imull (%rax,%rbx), %r16d + imull (%r16,%r17), %eax + imull (%rax,%r16), %r17d + imull (%r16,%rax), %r17d + imull (%r16,%r17), %r18d +## MRMSrcMemCC + cmovll (%r16,%rax), %ebx + cmovll (%rax,%r16), %ebx + cmovll (%rax,%rbx), %r16d + cmovll (%r16,%r17), %eax + cmovll (%rax,%r16), %r17d + cmovll (%r16,%rax), %r17d + cmovll (%r16,%r17), %r18d +## MRMDestReg + movl %eax, %r16d + movl %r16d, %eax + movl %r16d, %r17d +## MRMDestMem + movl (%r16,%rax), %ebx + movl (%rax,%r16), %ebx + movl (%rax,%rbx), %r16d + movl (%r16,%r17), %eax + movl (%rax,%r16), %r17d + movl (%r16,%rax), %r17d + movl (%r16,%r17), %r18d +## MRMXmCC + sete (%rax,%r16) + sete (%r16,%rax) + sete (%r16,%r17) +## MRMXm + nopl (%rax,%r16) + nopl (%r16,%rax) + nopl (%r16,%r17) +## MRM0m + incl (%rax,%r16) + incl (%r16,%rax) + incl (%r16,%r17) +## MRM1m + decl (%rax,%r16) + decl (%r16,%rax) + decl (%r16,%r17) +## MRM2m + notl (%rax,%r16) + notl (%r16,%rax) + notl (%r16,%r17) +## MRM3m + negl (%rax,%r16) + negl (%r16,%rax) + negl (%r16,%r17) +## MRM4m + mull (%rax,%r16) + mull (%r16,%rax) + mull (%r16,%r17) +## MRM5m + imull (%rax,%r16) + imull (%r16,%rax) + imull (%r16,%r17) +## MRM6m + divl (%rax,%r16) + divl (%r16,%rax) + divl (%r16,%r17) +## MRM7m + idivl (%rax,%r16) + idivl (%r16,%rax) + idivl (%r16,%r17) +## MRMXrCC + sete %r16b +## MRMXr + nopl %r16d +## MRM0r + incl %r16d +## MRM1r + decl %r16d +## MRM2r + notl %r16d +## MRM3r + negl %r16d +## MRM4r + mull %r16d +## MRM5r + imull %r16d +## MRM6r + divl %r16d +## MRM7r + idivl %r16d diff --git a/gas/testsuite/gas/i386/x86-64-inval-pseudo.l b/gas/testsuite/gas/i386/x86-64-inval-pseudo.l index 13ad0fb768f..9f5488d8218 100644 --- a/gas/testsuite/gas/i386/x86-64-inval-pseudo.l +++ b/gas/testsuite/gas/i386/x86-64-inval-pseudo.l @@ -1,10 +1,22 @@ .*: Assembler messages: .*:2: Error: .* .*:3: Error: .* +.*:6: Error: .* +.*:7: Error: .* +.*:10: Error: .* +.*:11: Error: .* GAS LISTING .* [ ]*1[ ]+\.text [ ]*2[ ]+\{disp16\} movb \(%ebp\),%al [ ]*3[ ]+\{disp16\} movb \(%rbp\),%al +[ ]*4[ ]+ +[ ]*5[ ]+.* +[ ]*6[ ]+\{rex2\} xsave \(%r15, %rbx\) +[ ]*7[ ]+\{rex2\} xsave64 \(%r15, %rbx\) +[ ]*8[ ]+ +[ ]*9[ ]+.* +[ ]*10[ ]+\{rex\} movl %eax,\(%r16\) +[ ]*11[ ]+\{rex\} movl %r16d,\(%r8\) #... diff --git a/gas/testsuite/gas/i386/x86-64-inval-pseudo.s b/gas/testsuite/gas/i386/x86-64-inval-pseudo.s index c10b14c2099..8b387de9319 100644 --- a/gas/testsuite/gas/i386/x86-64-inval-pseudo.s +++ b/gas/testsuite/gas/i386/x86-64-inval-pseudo.s @@ -1,4 +1,12 @@ .text {disp16} movb (%ebp),%al {disp16} movb (%rbp),%al + + /* Instruction not support APX. */ + {rex2} xsave (%r15, %rbx) + {rex2} xsave64 (%r15, %rbx) + + /* Add pseudo prefix {rex} for GPR32 register. */ + {rex} movl %eax,(%r16) + {rex} movl %r16d,(%r8) .p2align 4,0 diff --git a/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d b/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d index 6ee5b2f95ce..03126541f24 100644 --- a/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d +++ b/gas/testsuite/gas/i386/x86-64-opcode-inval-intel.d @@ -11,11 +11,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 37 \(bad\) 0+1 : -[ ]*[a-f0-9]+: d5 \(bad\) +[ ]*[a-f0-9]+: d5 rex2 [ ]*[a-f0-9]+: 0a .byte 0xa 0+3 : -[ ]*[a-f0-9]+: d5 \(bad\) +[ ]*[a-f0-9]+: d5 rex2 [ ]*[a-f0-9]+: 02 .byte 0x2 0+5 : diff --git a/gas/testsuite/gas/i386/x86-64-opcode-inval.d b/gas/testsuite/gas/i386/x86-64-opcode-inval.d index 12f02c1766c..0200f3dfd92 100644 --- a/gas/testsuite/gas/i386/x86-64-opcode-inval.d +++ b/gas/testsuite/gas/i386/x86-64-opcode-inval.d @@ -10,11 +10,11 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 37 \(bad\) 0+1 : -[ ]*[a-f0-9]+: d5 \(bad\) +[ ]*[a-f0-9]+: d5 rex2 [ ]*[a-f0-9]+: 0a .byte 0xa 0+3 : -[ ]*[a-f0-9]+: d5 \(bad\) +[ ]*[a-f0-9]+: d5 rex2 [ ]*[a-f0-9]+: 02 .byte 0x2 0+5 : diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.d b/gas/testsuite/gas/i386/x86-64-pseudos.d index 0cc75ef2457..8cc4040cb77 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.d +++ b/gas/testsuite/gas/i386/x86-64-pseudos.d @@ -404,6 +404,18 @@ Disassembly of section .text: +[a-f0-9]+: 41 0f 28 10 movaps \(%r8\),%xmm2 +[a-f0-9]+: 40 0f 38 01 01 rex phaddw \(%rcx\),%mm0 +[a-f0-9]+: 41 0f 38 01 00 phaddw \(%r8\),%mm0 + +[a-f0-9]+: 88 c4 mov %al,%ah + +[a-f0-9]+: d5 00 d3 e0 {rex2} shl %cl,%eax + +[a-f0-9]+: d5 00 a0 01 00 00 00 00 00 00 00 {rex2} movabs 0x1,%al + +[a-f0-9]+: d5 00 38 ca {rex2} cmp %cl,%dl + +[a-f0-9]+: d5 00 b3 01 {rex2} mov \$(0x)?1,%bl + +[a-f0-9]+: d5 00 89 c3 {rex2} mov %eax,%ebx + +[a-f0-9]+: d5 01 89 c6 {rex2} mov %eax,%r14d + +[a-f0-9]+: d5 01 89 00 {rex2} mov %eax,\(%r8\) + +[a-f0-9]+: d5 80 28 d7 {rex2} movaps %xmm7,%xmm2 + +[a-f0-9]+: d5 84 28 e7 {rex2} movaps %xmm7,%xmm12 + +[a-f0-9]+: d5 80 28 11 {rex2} movaps \(%rcx\),%xmm2 + +[a-f0-9]+: d5 81 28 10 {rex2} movaps \(%r8\),%xmm2 +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%rbp\),%al @@ -458,6 +470,14 @@ Disassembly of section .text: +[a-f0-9]+: 41 0f 28 10 movaps \(%r8\),%xmm2 +[a-f0-9]+: 40 0f 38 01 01 rex phaddw \(%rcx\),%mm0 +[a-f0-9]+: 41 0f 38 01 00 phaddw \(%r8\),%mm0 + +[a-f0-9]+: 88 c4 mov %al,%ah + +[a-f0-9]+: d5 00 89 c3 {rex2} mov %eax,%ebx + +[a-f0-9]+: d5 01 89 c6 {rex2} mov %eax,%r14d + +[a-f0-9]+: d5 01 89 00 {rex2} mov %eax,\(%r8\) + +[a-f0-9]+: d5 80 28 d7 {rex2} movaps %xmm7,%xmm2 + +[a-f0-9]+: d5 84 28 e7 {rex2} movaps %xmm7,%xmm12 + +[a-f0-9]+: d5 80 28 11 {rex2} movaps \(%rcx\),%xmm2 + +[a-f0-9]+: d5 81 28 10 {rex2} movaps \(%r8\),%xmm2 +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al +[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al +[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%rbp\),%al diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.s b/gas/testsuite/gas/i386/x86-64-pseudos.s index 08fac8381c6..eb25f2a8fbf 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.s +++ b/gas/testsuite/gas/i386/x86-64-pseudos.s @@ -360,6 +360,19 @@ _start: {rex} movaps (%r8),%xmm2 {rex} phaddw (%rcx),%mm0 {rex} phaddw (%r8),%mm0 + {rex2} mov %al,%ah + {rex2} shl %cl, %eax + {rex2} movabs 1, %al + {rex2} cmp %cl, %dl + {rex2} mov $1, %bl + {rex2} movl %eax,%ebx + {rex2} movl %eax,%r14d + {rex2} movl %eax,(%r8) + {rex2} movaps %xmm7,%xmm2 + {rex2} movaps %xmm7,%xmm12 + {rex2} movaps (%rcx),%xmm2 + {rex2} movaps (%r8),%xmm2 + movb (%rbp),%al {disp8} movb (%rbp),%al @@ -422,6 +435,14 @@ _start: {rex} movaps xmm2,XMMWORD PTR [r8] {rex} phaddw mm0,QWORD PTR [rcx] {rex} phaddw mm0,QWORD PTR [r8] + {rex2} mov ah,al + {rex2} mov ebx,eax + {rex2} mov r14d,eax + {rex2} mov DWORD PTR [r8],eax + {rex2} movaps xmm2,xmm7 + {rex2} movaps xmm12,xmm7 + {rex2} movaps xmm2,XMMWORD PTR [rcx] + {rex2} movaps xmm2,XMMWORD PTR [r8] mov al, BYTE PTR [rbp] {disp8} mov al, BYTE PTR [rbp] diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 52711cdcf6f..07df89ba0cc 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -360,6 +360,9 @@ run_dump_test "x86-64-avx512f-rcigrne-intel" run_dump_test "x86-64-avx512f-rcigrne" run_dump_test "x86-64-avx512f-rcigru-intel" run_dump_test "x86-64-avx512f-rcigru" +run_list_test "x86-64-apx-egpr-inval" "-al" +run_dump_test "x86-64-apx-rex2" +run_dump_test "x86-64-apx-rex2-inval" run_dump_test "x86-64-avx512f-rcigrz-intel" run_dump_test "x86-64-avx512f-rcigrz" run_dump_test "x86-64-clwb" diff --git a/include/opcode/i386.h b/include/opcode/i386.h index dec7652c1cc..a6af3d54da0 100644 --- a/include/opcode/i386.h +++ b/include/opcode/i386.h @@ -112,6 +112,8 @@ /* x86-64 extension prefix. */ #define REX_OPCODE 0x40 +#define REX2_OPCODE 0xd5 + /* Non-zero if OPCODE is the rex prefix. */ #define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE) diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 87ecf0f5e23..65bdd6f65db 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -144,6 +144,12 @@ struct instr_info /* Bits of REX we've already used. */ uint8_t rex_used; + /* REX2 prefix for the current instruction use gpr32(r16-r31). */ + unsigned char rex2; + /* Bits of REX2 we've already used. */ + unsigned char rex2_used; + unsigned char rex2_payload; + bool need_modrm; unsigned char need_vex; bool has_sib; @@ -169,6 +175,7 @@ struct instr_info signed char last_data_prefix; signed char last_addr_prefix; signed char last_rex_prefix; + signed char last_rex2_prefix; signed char last_seg_prefix; signed char fwait_prefix; /* The active segment register prefix. */ @@ -269,6 +276,12 @@ struct dis_private { ins->rex_used |= REX_OPCODE; \ } +#define USED_REX2(value) \ + { \ + if ((ins->rex2 & value)) \ + ins->rex2_used |= value; \ + } + #define EVEX_b_used 1 #define EVEX_len_used 2 @@ -286,6 +299,7 @@ struct dis_private { #define PREFIX_DATA 0x200 #define PREFIX_ADDR 0x400 #define PREFIX_FWAIT 0x800 +#define PREFIX_REX2 0x1000 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) to ADDR (exclusive) are valid. Returns true for success, false @@ -367,6 +381,7 @@ fetch_error (const instr_info *ins) #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) +#define PREFIX_IGNORED_REX2 (PREFIX_REX2 << PREFIX_IGNORED_SHIFT) /* Opcode prefixes. */ #define PREFIX_OPCODE (PREFIX_REPZ \ @@ -2390,22 +2405,30 @@ static const char intel_index16[][6] = { static const char att_names64[][8] = { "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", - "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" + "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", + "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", + "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31" }; static const char att_names32[][8] = { "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", - "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" + "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d", + "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d", + "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d" }; static const char att_names16[][8] = { "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", - "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" + "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w", + "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w", + "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w" }; static const char att_names8[][8] = { "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", }; static const char att_names8rex[][8] = { "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", - "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" + "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b", + "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b", + "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b" }; static const char att_names_seg[][4] = { "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", @@ -2794,9 +2817,9 @@ static const struct dis386 reg_table[][8] = { { Bad_Opcode }, { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, { Bad_Opcode }, - { "xrstors", { FXSAVE }, 0 }, - { "xsavec", { FXSAVE }, 0 }, - { "xsaves", { FXSAVE }, 0 }, + { "xrstors", { FXSAVE }, PREFIX_IGNORED_REX2 }, + { "xsavec", { FXSAVE }, PREFIX_IGNORED_REX2 }, + { "xsaves", { FXSAVE }, PREFIX_IGNORED_REX2 }, { MOD_TABLE (MOD_0FC7_REG_6) }, { MOD_TABLE (MOD_0FC7_REG_7) }, }, @@ -3364,7 +3387,7 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0FAE_REG_4_MOD_0 */ { - { "xsave", { FXSAVE }, 0 }, + { "xsave", { FXSAVE }, PREFIX_IGNORED_REX2 }, { "ptwrite{%LQ|}", { Edq }, 0 }, }, @@ -3382,7 +3405,7 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0FAE_REG_6_MOD_0 */ { - { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, + { "xsaveopt", { FXSAVE }, PREFIX_OPCODE | PREFIX_IGNORED_REX2 }, { "clrssbsy", { Mq }, PREFIX_OPCODE }, { "clwb", { Mb }, PREFIX_OPCODE }, }, @@ -8125,7 +8148,7 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FAE_REG_5 */ - { "xrstor", { FXSAVE }, PREFIX_OPCODE }, + { "xrstor", { FXSAVE }, PREFIX_OPCODE | PREFIX_IGNORED_REX2 }, { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, }, { @@ -8323,6 +8346,24 @@ ckprefix (instr_info *ins) return ckp_okay; ins->last_rex_prefix = i; break; + /* REX2 must be the last prefix. */ + case 0xd5: + if (ins->address_mode == mode_64bit) + { + if (ins->last_rex_prefix >= 0) + return ckp_bogus; + + ins->codep++; + if (!fetch_code (ins->info, ins->codep + 1)) + return ckp_fetch_error; + ins->rex2_payload = *ins->codep; + ins->rex2 = ins->rex2_payload >> 4; + ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE; + ins->codep++; + ins->last_rex2_prefix = i; + ins->all_prefixes[i] = REX2_OPCODE; + } + return ckp_okay; case 0xf3: ins->prefixes |= PREFIX_REPZ; ins->last_repz_prefix = i; @@ -8490,6 +8531,8 @@ prefix_name (enum address_mode mode, uint8_t pref, int sizeflag) return "bnd"; case NOTRACK_PREFIX: return "notrack"; + case REX2_OPCODE: + return "rex2"; default: return NULL; } @@ -8628,6 +8671,8 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) break; case USE_3BYTE_TABLE: + if (ins->last_rex2_prefix >= 0) + return &bad_opcode; if (!fetch_code (ins->info, ins->codep + 2)) return &err_opcode; vindex = *ins->codep++; @@ -8751,6 +8796,8 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) break; case USE_VEX_C4_TABLE: + if (ins->last_rex2_prefix >= 0) + return &bad_opcode; /* VEX prefix. */ if (!fetch_code (ins->info, ins->codep + 3)) return &err_opcode; @@ -8812,6 +8859,8 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) break; case USE_VEX_C5_TABLE: + if (ins->last_rex2_prefix >= 0) + return &bad_opcode; /* VEX prefix. */ if (!fetch_code (ins->info, ins->codep + 2)) return &err_opcode; @@ -8853,6 +8902,8 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) break; case USE_EVEX_TABLE: + if (ins->last_rex2_prefix >= 0) + return &bad_opcode; ins->two_source_ops = false; /* EVEX prefix. */ ins->vex.evex = true; @@ -9128,6 +9179,7 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) .last_data_prefix = -1, .last_addr_prefix = -1, .last_rex_prefix = -1, + .last_rex2_prefix = -1, .last_seg_prefix = -1, .fwait_prefix = -1, }; @@ -9292,13 +9344,17 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) goto out; } - if (*ins.codep == 0x0f) + /* M0 in rex2 prefix represents map0 or map1. */ + if (*ins.codep == 0x0f || (ins.rex2 & 0x8)) { unsigned char threebyte; - ins.codep++; - if (!fetch_code (info, ins.codep + 1)) - goto fetch_error_out; + if (!ins.rex2) + { + ins.codep++; + if (!fetch_code (info, ins.codep + 1)) + goto fetch_error_out; + } threebyte = *ins.codep; dp = &dis386_twobyte[threebyte]; ins.need_modrm = twobyte_has_modrm[threebyte]; @@ -9454,6 +9510,14 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) goto out; } + if ((dp->prefix_requirement & PREFIX_IGNORED_REX2) + && ins.last_rex2_prefix >= 0) + { + i386_dis_printf (info, dis_style_text, "(bad)"); + ret = ins.end_codep - priv.the_buffer; + goto out; + } + switch (dp->prefix_requirement) { case PREFIX_DATA: @@ -9468,6 +9532,7 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) ins.used_prefixes |= PREFIX_DATA; /* Fall through. */ case PREFIX_OPCODE: + case PREFIX_OPCODE | PREFIX_IGNORED_REX2: /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is unused, opcode is invalid. Since the PREFIX_DATA prefix may be used by putop and MMX/SSE operand and may be overridden by the @@ -9510,9 +9575,17 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) /* Check if the REX prefix is used. */ if ((ins.rex ^ ins.rex_used) == 0 - && !ins.need_vex && ins.last_rex_prefix >= 0) + && !ins.need_vex && ins.last_rex_prefix >= 0 + && ins.last_rex2_prefix < 0) ins.all_prefixes[ins.last_rex_prefix] = 0; + /* Check if the REX2 prefix is used. */ + if (ins.last_rex2_prefix >= 0 + && ((((ins.rex2 & 0x7) ^ (ins.rex2_used & 0x7)) == 0 + && (ins.rex2 & 0x7)) + || dp == &bad_opcode)) + ins.all_prefixes[ins.last_rex2_prefix] = 0; + /* Check if the SEG prefix is used. */ if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES | PREFIX_FS | PREFIX_GS)) != 0 @@ -9541,7 +9614,10 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) if (name == NULL) abort (); prefix_length += strlen (name) + 1; - i386_dis_printf (info, dis_style_mnemonic, "%s ", name); + if (ins.all_prefixes[i] == REX2_OPCODE) + i386_dis_printf (info, dis_style_mnemonic, "{%s} ", name); + else + i386_dis_printf (info, dis_style_mnemonic, "%s ", name); } /* Check maximum code length. */ @@ -11086,8 +11162,11 @@ print_register (instr_info *ins, unsigned int reg, unsigned int rexmask, ins->illegal_masking = true; USED_REX (rexmask); + USED_REX2 (rexmask); if (ins->rex & rexmask) reg += 8; + if (ins->rex2 & rexmask) + reg += 16; switch (bytemode) { @@ -11307,6 +11386,7 @@ static bool OP_E_memory (instr_info *ins, int bytemode, int sizeflag) { int add = (ins->rex & REX_B) ? 8 : 0; + add += (ins->rex2 & REX_B) ? 16 : 0; int riprel = 0; int shift; @@ -11414,6 +11494,7 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag) shift = 0; USED_REX (REX_B); + USED_REX2 (REX_B); if (ins->intel_syntax) intel_operand_size (ins, bytemode, sizeflag); append_seg (ins); @@ -11444,8 +11525,11 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag) { vindex = ins->sib.index; USED_REX (REX_X); + USED_REX2 (REX_X); if (ins->rex & REX_X) vindex += 8; + if (ins->rex2 & REX_X) + vindex += 16; switch (bytemode) { case vex_vsib_d_w_dq_mode: @@ -11866,7 +11950,7 @@ static bool OP_REG (instr_info *ins, int code, int sizeflag) { const char *s; - int add; + int add = 0; switch (code) { @@ -11877,10 +11961,11 @@ OP_REG (instr_info *ins, int code, int sizeflag) } USED_REX (REX_B); + USED_REX2 (REX_B); if (ins->rex & REX_B) add = 8; - else - add = 0; + if (ins->rex2 & REX_B) + add += 16; switch (code) { @@ -12590,8 +12675,11 @@ OP_EX (instr_info *ins, int bytemode, int sizeflag) reg = ins->modrm.rm; USED_REX (REX_B); + USED_REX2 (REX_B); if (ins->rex & REX_B) reg += 8; + if (ins->rex2 & REX_B) + reg += 16; if (ins->vex.evex) { USED_REX (REX_X); diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index cfc5a7a6172..6b8eb729797 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -380,6 +380,7 @@ static bitfield cpu_flags[] = BITFIELD (RAO_INT), BITFIELD (FRED), BITFIELD (LKGS), + BITFIELD (APX_F), BITFIELD (MWAITX), BITFIELD (CLZERO), BITFIELD (OSPKE), @@ -469,6 +470,7 @@ static bitfield opcode_modifiers[] = BITFIELD (ATTSyntax), BITFIELD (IntelSyntax), BITFIELD (ISA64), + BITFIELD (No_egpr), }; #define CLASS(n) #n, n diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 149ae0e950c..a055db5ce42 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -317,6 +317,8 @@ enum i386_cpu CpuAVX512F, /* Intel AVX-512 VL Instructions support required. */ CpuAVX512VL, + /* Intel APX Instructions support required. */ + CpuAPX_F, /* Not supported in the 64bit mode */ CpuNo64, @@ -352,6 +354,7 @@ enum i386_cpu cpuhle:1, \ cpuavx512f:1, \ cpuavx512vl:1, \ + cpuapx_f:1, \ /* NOTE: This field needs to remain last. */ \ cpuno64:1 @@ -742,6 +745,10 @@ enum #define INTEL64 2 #define INTEL64ONLY 3 ISA64, + + /* egprs (r16-r31) on instruction illegal. */ + No_egpr, + /* The last bitfield in i386_opcode_modifier. */ Opcode_Modifier_Num }; @@ -789,6 +796,7 @@ typedef struct i386_opcode_modifier unsigned int attsyntax:1; unsigned int intelsyntax:1; unsigned int isa64:2; + unsigned int no_egpr:1; } i386_opcode_modifier; /* Operand classes. */ @@ -988,7 +996,7 @@ typedef struct insn_template AMD 3DNow! instructions. If this template has no extension opcode (the usual case) use None Instructions */ - signed int extension_opcode:9; + signed int extension_opcode:0xA; #define None (-1) /* If no extension_opcode is possible. */ /* Pseudo prefixes. */ @@ -1001,7 +1009,8 @@ typedef struct insn_template #define Prefix_VEX3 6 /* {vex3} */ #define Prefix_EVEX 7 /* {evex} */ #define Prefix_REX 8 /* {rex} */ -#define Prefix_NoOptimize 9 /* {nooptimize} */ +#define Prefix_REX2 9 /* {rex2} */ +#define Prefix_NoOptimize 0xA /* {nooptimize} */ /* the bits in opcode_modifier are used to generate the final opcode from the base_opcode. These bits also are used to detect alternate forms of @@ -1028,6 +1037,7 @@ typedef struct #define RegRex 0x1 /* Extended register. */ #define RegRex64 0x2 /* Extended 8 bit register. */ #define RegVRex 0x4 /* Extended vector register. */ +#define RegRex2 0x8 /* Extended rex2 interge register. */ unsigned char reg_num; #define RegIP ((unsigned char ) ~0) /* EIZ and RIZ are fake index registers. */ diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index a534c53ca17..80248e5b72c 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -889,7 +889,7 @@ rex.wrxb, 0x4f, x64, NoSuf|IsPrefix, {} + rex:REX:x64, rex2:REX2:x64, nooptimize:NoOptimize:0> {}, PSEUDO_PREFIX/Prefix_, , NoSuf|IsPrefix, {} @@ -1422,16 +1422,16 @@ crc32, 0xf20f38f0, SSE4_2|x64, W|Modrm|No_wSuf|No_lSuf|No_sSuf, { Reg8|Reg64|Uns // xsave/xrstor New Instructions. -xsave, 0xfae/4, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } -xsave64, 0xfae/4, Xsave|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } -xrstor, 0xfae/5, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } -xrstor64, 0xfae/5, Xsave|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xsave, 0xfae/4, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_egpr, { Unspecified|BaseIndex } +xsave64, 0xfae/4, Xsave|x64, Modrm|NoSuf|Size64|No_egpr, { Unspecified|BaseIndex } +xrstor, 0xfae/5, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_egpr, { Unspecified|BaseIndex } +xrstor64, 0xfae/5, Xsave|x64, Modrm|NoSuf|Size64|No_egpr, { Unspecified|BaseIndex } xgetbv, 0xf01d0, Xsave, NoSuf, {} xsetbv, 0xf01d1, Xsave, NoSuf, {} // xsaveopt -xsaveopt, 0xfae/6, Xsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex } -xsaveopt64, 0xfae/6, Xsaveopt|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xsaveopt, 0xfae/6, Xsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_egpr, { Unspecified|BaseIndex } +xsaveopt64, 0xfae/6, Xsaveopt|x64, Modrm|NoSuf|Size64|No_egpr, { Unspecified|BaseIndex } // AES instructions. @@ -2492,17 +2492,17 @@ clflushopt, 0x660fae/7, ClflushOpt, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex // XSAVES/XRSTORS instructions. -xrstors, 0xfc7/3, XSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } -xrstors64, 0xfc7/3, XSAVES|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } -xsaves, 0xfc7/5, XSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } -xsaves64, 0xfc7/5, XSAVES|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xrstors, 0xfc7/3, XSAVES, Modrm|NoSuf|No_egpr, { Unspecified|BaseIndex } +xrstors64, 0xfc7/3, XSAVES|x64, Modrm|NoSuf|Size64|No_egpr, { Unspecified|BaseIndex } +xsaves, 0xfc7/5, XSAVES, Modrm|NoSuf|No_egpr, { Unspecified|BaseIndex } +xsaves64, 0xfc7/5, XSAVES|x64, Modrm|NoSuf|Size64|No_egpr, { Unspecified|BaseIndex } // XSAVES instructions end. // XSAVEC instructions. -xsavec, 0xfc7/4, XSAVEC, Modrm|NoSuf, { Unspecified|BaseIndex } -xsavec64, 0xfc7/4, XSAVEC|x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } +xsavec, 0xfc7/4, XSAVEC, Modrm|NoSuf|No_egpr, { Unspecified|BaseIndex } +xsavec64, 0xfc7/4, XSAVEC|x64, Modrm|NoSuf|Size64|No_egpr, { Unspecified|BaseIndex } // XSAVEC instructions end. diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index 2ac56e3fd0b..8fead35e320 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -43,6 +43,22 @@ r12b, Class=Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval r13b, Class=Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval r14b, Class=Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval r15b, Class=Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval +r16b, Class=Reg|Byte, RegRex2|RegRex64, 0, Dw2Inval, Dw2Inval +r17b, Class=Reg|Byte, RegRex2|RegRex64, 1, Dw2Inval, Dw2Inval +r18b, Class=Reg|Byte, RegRex2|RegRex64, 2, Dw2Inval, Dw2Inval +r19b, Class=Reg|Byte, RegRex2|RegRex64, 3, Dw2Inval, Dw2Inval +r20b, Class=Reg|Byte, RegRex2|RegRex64, 4, Dw2Inval, Dw2Inval +r21b, Class=Reg|Byte, RegRex2|RegRex64, 5, Dw2Inval, Dw2Inval +r22b, Class=Reg|Byte, RegRex2|RegRex64, 6, Dw2Inval, Dw2Inval +r23b, Class=Reg|Byte, RegRex2|RegRex64, 7, Dw2Inval, Dw2Inval +r24b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 0, Dw2Inval, Dw2Inval +r25b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 1, Dw2Inval, Dw2Inval +r26b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 2, Dw2Inval, Dw2Inval +r27b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 3, Dw2Inval, Dw2Inval +r28b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 4, Dw2Inval, Dw2Inval +r29b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 5, Dw2Inval, Dw2Inval +r30b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 6, Dw2Inval, Dw2Inval +r31b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 7, Dw2Inval, Dw2Inval // 16 bit regs ax, Class=Reg|Instance=Accum|Word, 0, 0, Dw2Inval, Dw2Inval cx, Class=Reg|Word, 0, 1, Dw2Inval, Dw2Inval @@ -60,6 +76,22 @@ r12w, Class=Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval r13w, Class=Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval r14w, Class=Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval r15w, Class=Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval +r16w, Class=Reg|Word, RegRex2, 0, Dw2Inval, Dw2Inval +r17w, Class=Reg|Word, RegRex2, 1, Dw2Inval, Dw2Inval +r18w, Class=Reg|Word, RegRex2, 2, Dw2Inval, Dw2Inval +r19w, Class=Reg|Word, RegRex2, 3, Dw2Inval, Dw2Inval +r20w, Class=Reg|Word, RegRex2, 4, Dw2Inval, Dw2Inval +r21w, Class=Reg|Word, RegRex2, 5, Dw2Inval, Dw2Inval +r22w, Class=Reg|Word, RegRex2, 6, Dw2Inval, Dw2Inval +r23w, Class=Reg|Word, RegRex2, 7, Dw2Inval, Dw2Inval +r24w, Class=Reg|Word, RegRex2|RegRex, 0, Dw2Inval, Dw2Inval +r25w, Class=Reg|Word, RegRex2|RegRex, 1, Dw2Inval, Dw2Inval +r26w, Class=Reg|Word, RegRex2|RegRex, 2, Dw2Inval, Dw2Inval +r27w, Class=Reg|Word, RegRex2|RegRex, 3, Dw2Inval, Dw2Inval +r28w, Class=Reg|Word, RegRex2|RegRex, 4, Dw2Inval, Dw2Inval +r29w, Class=Reg|Word, RegRex2|RegRex, 5, Dw2Inval, Dw2Inval +r30w, Class=Reg|Word, RegRex2|RegRex, 6, Dw2Inval, Dw2Inval +r31w, Class=Reg|Word, RegRex2|RegRex, 7, Dw2Inval, Dw2Inval // 32 bit regs eax, Class=Reg|Instance=Accum|Dword|BaseIndex, 0, 0, 0, Dw2Inval ecx, Class=Reg|Instance=RegC|Dword|BaseIndex, 0, 1, 1, Dw2Inval @@ -77,6 +109,22 @@ r12d, Class=Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval r13d, Class=Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval r14d, Class=Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval r15d, Class=Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval +r16d, Class=Reg|Dword|BaseIndex, RegRex2, 0, Dw2Inval, Dw2Inval +r17d, Class=Reg|Dword|BaseIndex, RegRex2, 1, Dw2Inval, Dw2Inval +r18d, Class=Reg|Dword|BaseIndex, RegRex2, 2, Dw2Inval, Dw2Inval +r19d, Class=Reg|Dword|BaseIndex, RegRex2, 3, Dw2Inval, Dw2Inval +r20d, Class=Reg|Dword|BaseIndex, RegRex2, 4, Dw2Inval, Dw2Inval +r21d, Class=Reg|Dword|BaseIndex, RegRex2, 5, Dw2Inval, Dw2Inval +r22d, Class=Reg|Dword|BaseIndex, RegRex2, 6, Dw2Inval, Dw2Inval +r23d, Class=Reg|Dword|BaseIndex, RegRex2, 7, Dw2Inval, Dw2Inval +r24d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 0, Dw2Inval, Dw2Inval +r25d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 1, Dw2Inval, Dw2Inval +r26d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 2, Dw2Inval, Dw2Inval +r27d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 3, Dw2Inval, Dw2Inval +r28d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 4, Dw2Inval, Dw2Inval +r29d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 5, Dw2Inval, Dw2Inval +r30d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 6, Dw2Inval, Dw2Inval +r31d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 7, Dw2Inval, Dw2Inval rax, Class=Reg|Instance=Accum|Qword|BaseIndex, 0, 0, Dw2Inval, 0 rcx, Class=Reg|Instance=RegC|Qword|BaseIndex, 0, 1, Dw2Inval, 2 rdx, Class=Reg|Instance=RegD|Qword|BaseIndex, 0, 2, Dw2Inval, 1 @@ -93,6 +141,22 @@ r12, Class=Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12 r13, Class=Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13 r14, Class=Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14 r15, Class=Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15 +r16, Class=Reg|Qword|BaseIndex, RegRex2, 0, Dw2Inval, 130 +r17, Class=Reg|Qword|BaseIndex, RegRex2, 1, Dw2Inval, 131 +r18, Class=Reg|Qword|BaseIndex, RegRex2, 2, Dw2Inval, 132 +r19, Class=Reg|Qword|BaseIndex, RegRex2, 3, Dw2Inval, 133 +r20, Class=Reg|Qword|BaseIndex, RegRex2, 4, Dw2Inval, 134 +r21, Class=Reg|Qword|BaseIndex, RegRex2, 5, Dw2Inval, 135 +r22, Class=Reg|Qword|BaseIndex, RegRex2, 6, Dw2Inval, 136 +r23, Class=Reg|Qword|BaseIndex, RegRex2, 7, Dw2Inval, 137 +r24, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 0, Dw2Inval, 138 +r25, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 1, Dw2Inval, 139 +r26, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 2, Dw2Inval, 140 +r27, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 3, Dw2Inval, 141 +r28, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 4, Dw2Inval, 142 +r29, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 5, Dw2Inval, 143 +r30, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 6, Dw2Inval, 144 +r31, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 7, Dw2Inval, 145 // Vector mask registers. k0, Class=RegMask, 0, 0, 93, 118 k1, Class=RegMask, 0, 1, 94, 119 From patchwork Tue Sep 19 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To: binutils@sourceware.org Cc: jbeulich@suse.com, hongjiu.lu@intel.com Subject: [PATCH 2/8] Support APX GPR32 with extend evex prefix Date: Tue, 19 Sep 2023 15:25:21 +0000 Message-Id: <20230919152527.497773-3-lili.cui@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230919152527.497773-1-lili.cui@intel.com> References: <20230919152527.497773-1-lili.cui@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Cui, Lili via Binutils" From: "Frager, Neal via Binutils" Reply-To: "Cui, Lili" Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. gas/ChangeLog: * config/tc-i386.c (is_any_apx_evex_encoding): New func. Test apx evex encoding. (build_legacy_insns_with_apx_encoding): New func. (build_evex_insns_with_extend_evex_prefix): New func. Build evex insns with gpr32 use extend evex prefix. (md_assemble): Handle apx with rex2 or evex encoding. (output_insn): Handle apx evex encoding. opcode/ChangeLog: * i386-opc.h (SPACE_EVEXMAP4): New define for legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex. * i386-gen.c (process_i386_opcode_modifier): set no_egpr for VEX instructions. * i386-tbl.h: Regenerated. * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-mod.h: Handle MOD_EVEX_MAP4_65, MOD_EVEX_MAP4_66_PREFIX_0, MOD_EVEX_MAP4_8A_W_0, MOD_EVEX_MAP4_DA_PREFIX_1, MOD_EVEX_MAP4_DB_PREFIX_1, MOD_EVEX_MAP4_DC_PREFIX_1, MOD_EVEX_MAP4_DD_PREFIX_1, MOD_EVEX_MAP4_DE_PREFIX_1, MOD_EVEX_MAP4_DF_PREFIX_1, MOD_EVEX_MAP4_F8_PREFIX_1, MOD_EVEX_MAP4_F8_PREFIX_2, MOD_EVEX_MAP4_F8_PREFIX_3, MOD_EVEX_MAP4_F9, MOD_EVEX_MAP4_8B. * i386-dis-evex-w.h: Handle EVEX_W_MAP4_8A. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_60, PREFIX_EVEX_MAP4_61, PREFIX_EVEX_MAP4_66, PREFIX_EVEX_MAP4_8B_M_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8, PREFIX_EVEX_MAP4_FC. * i386-dis-evex-reg.h: Handle REG_EVEX_MAP4_D8_PREFIX_1, REG_EVEX_0F38F3_L_0. * i386-dis-evex-x86.h: Handle X86_64_EVEX_0F90, X86_64_EVEX_0F91, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_MAP7_F8. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32, and add vex use gpr32 promote to evex. Add EVEX_MAP7. * opcodes/i386-dis.c (REG enum): Add REG_EVEX_MAP4_D8_PREFIX_1. (MOD enum): Add MOD_EVEX_MAP4_65, MOD_EVEX_MAP4_66_PREFIX_0, MOD_EVEX_MAP4_8A_W_0, MOD_EVEX_MAP4_8B, MOD_EVEX_MAP4_DA_PREFIX_1, MOD_EVEX_MAP4_DB_PREFIX_1, MOD_EVEX_MAP4_DC_PREFIX_1, MOD_EVEX_MAP4_DD_PREFIX_1, MOD_EVEX_MAP4_DE_PREFIX_1, MOD_EVEX_MAP4_DF_PREFIX_1, MOD_EVEX_MAP4_F8_PREFIX_1, MOD_EVEX_MAP4_F8_PREFIX_2, MOD_EVEX_MAP4_F8_PREFIX_3, MOD_EVEX_MAP4_F9, REG_EVEX_0F38F3_L_0. (PREFIX enum): Add PREFIX_EVEX_MAP4_60, PREFIX_EVEX_MAP4_61, PREFIX_EVEX_MAP4_66, PREFIX_EVEX_MAP4_8B_M_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8, PREFIX_EVEX_MAP4_FC. (EVEX_LEN_enum): Add EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. (EVEX_X86_enum): Add X86_64_EVEX_0F90, X86_64_EVEX_0F91, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F3849, X86_64_EVEX_0F384B, X86_64_EVEX_0F38E0, X86_64_EVEX_0F38E1, X86_64_EVEX_0F38E2, X86_64_EVEX_0F38E3, X86_64_EVEX_0F38E4, X86_64_EVEX_0F38E5, X86_64_EVEX_0F38E6, X86_64_EVEX_0F38E7, X86_64_EVEX_0F38E8, X86_64_EVEX_0F38E9, X86_64_EVEX_0F38EA, X86_64_EVEX_0F38EB, X86_64_EVEX_0F38EC, X86_64_EVEX_0F38ED, X86_64_EVEX_0F38EE, X86_64_EVEX_0F38EF, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0. (EVEX_MAP4): New define. (EVEX_MAP7): New. (evex_type): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4, Handle EVEX_MAP7. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Ditto. --- gas/config/tc-i386.c | 93 +++- opcodes/i386-dis-evex-len.h | 10 + opcodes/i386-dis-evex-mod.h | 50 ++ opcodes/i386-dis-evex-prefix.h | 83 ++++ opcodes/i386-dis-evex-reg.h | 14 + opcodes/i386-dis-evex-x86.h | 140 ++++++ opcodes/i386-dis-evex.h | 838 ++++++++++++++++++++++++++++----- opcodes/i386-dis.c | 131 +++++- opcodes/i386-gen.c | 10 + opcodes/i386-opc.h | 2 + opcodes/i386-opc.tbl | 80 ++++ 11 files changed, 1299 insertions(+), 152 deletions(-) create mode 100644 opcodes/i386-dis-evex-x86.h diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 51486985919..48916bc3846 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1945,6 +1945,30 @@ cpu_flags_match (const insn_template *t) && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) match |= CPU_FLAGS_ARCH_MATCH; } + else if (x.bitfield.cpuapx_f) + { + if (cpu.bitfield.cpuapx_f + && (!x.bitfield.cpumovbe || cpu.bitfield.cpumovbe) + && (!x.bitfield.cpuept || cpu.bitfield.cpuept) + && (!x.bitfield.cpuinvpcid || cpu.bitfield.cpuinvpcid) + && (!x.bitfield.cpusse4_2 || cpu.bitfield.cpusse4_2) + && (!x.bitfield.cpubmi2 || cpu.bitfield.cpubmi2) + && (!x.bitfield.cpubmi || cpu.bitfield.cpubmi) + && (!x.bitfield.cpuadx || cpu.bitfield.cpuadx) + && (!x.bitfield.cpusha || cpu.bitfield.cpusha) + && (!x.bitfield.cpuavx512bw || cpu.bitfield.cpuavx512bw) + && (!x.bitfield.cpuavx512dq || cpu.bitfield.cpuavx512dq) + && (!x.bitfield.cpuavx512f || cpu.bitfield.cpuavx512f) + && (!x.bitfield.cpushstk || cpu.bitfield.cpushstk) + && (!x.bitfield.cpumovdir64b || cpu.bitfield.cpumovdir64b) + && (!x.bitfield.cpumovdiri || cpu.bitfield.cpumovdiri) + && (!x.bitfield.cpuenqcmd || cpu.bitfield.cpuenqcmd) + && (!x.bitfield.cpukl || cpu.bitfield.cpukl) + && (!x.bitfield.cpuwidekl || cpu.bitfield.cpuwidekl) + && (!x.bitfield.cpucmpccxadd || cpu.bitfield.cpucmpccxadd) + && (!x.bitfield.cpurao_int || cpu.bitfield.cpurao_int)) + match |= CPU_FLAGS_ARCH_MATCH; + } else match |= CPU_FLAGS_ARCH_MATCH; } @@ -3850,7 +3874,10 @@ is_any_vex_encoding (const insn_template *t) static INLINE bool is_any_apx_encoding (void) { - return i.rex2 || i.rex2_encoding; + return i.rex2 + || i.rex2_encoding + || (i.vex.register_specifier + && i.vex.register_specifier->reg_flags & RegRex2); } static INLINE bool @@ -3859,6 +3886,12 @@ is_any_apx_rex2_encoding (void) return (i.rex2 && i.vex.length == 2) || i.rex2_encoding; } +static INLINE bool +is_any_apx_evex_encoding (void) +{ + return i.rex2 && i.vex.length == 4; +} + static unsigned int get_broadcast_bytes (const insn_template *t, bool diag) { @@ -4129,6 +4162,50 @@ build_rex2_prefix (void) | (i.rex2 << 4) | i.rex); } +/* Build the EVEX prefix (4-byte) for evex insn + | 62h | + | `R`X`B`R' | B'mmm | + | W | v`v`v`v | `x' | pp | + | z| L'L | b | `v | aaa | +*/ +static void +build_evex_insns_with_extend_evex_prefix (void) +{ + build_evex_prefix (); + if (i.rex2 & REX_R) + i.vex.bytes[1] &= 0xef; + if (i.vex.register_specifier + && register_number (i.vex.register_specifier) > 0xf) + i.vex.bytes[3] &=0xf7; + if (i.rex2 & REX_B) + i.vex.bytes[1] |= 0x08; + if (i.rex2 & REX_X) + i.vex.bytes[2] &= 0xfb; +} + +/* Build the EVEX prefix (4-byte) for legacy insn + | 62h | + | `R`X`B`R' | B'100 | + | W | v`v`v`v | `x' | pp | + | 000 | ND | `v | NF | 00 | + For legacy insn without ndd nor nf, [vvvvv] must be all zero. */ +static void +build_legacy_insns_with_apx_encoding (void) +{ + /* map{0,1} of legacy space without ndd or nf could use rex2 prefix. */ + if (i.tm.opcode_space <= SPACE_0F + && !i.vex.register_specifier && !i.has_nf && !i.has_zero_upper) + return build_rex2_prefix (); + + if (i.prefix[DATA_PREFIX] != 0) + { + i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66; + i.prefix[DATA_PREFIX] = 0; + } + + build_evex_insns_with_extend_evex_prefix (); +} + static void process_immext (void) { @@ -5544,9 +5621,10 @@ md_assemble (char *line) if (is_any_apx_encoding ()) { if (!is_any_vex_encoding (&i.tm) - && i.tm.opcode_space <= SPACE_0F - && !i.vex.register_specifier && !i.has_nf && !i.has_zero_upper) - build_rex2_prefix (); + || i.tm.opcode_space == SPACE_EVEXMAP4) + build_legacy_insns_with_apx_encoding (); + else + build_evex_insns_with_extend_evex_prefix (); /* The individual REX.RXBW bits got consumed. */ i.rex &= REX_OPCODE; @@ -5616,7 +5694,7 @@ md_assemble (char *line) && (i.rex != 0 || i.rex2!=0))) { int x; - if (!i.rex2) + if (!is_any_apx_encoding ()) i.rex |= REX_OPCODE; for (x = 0; x < 2; x++) { @@ -7935,7 +8013,8 @@ process_suffix (void) if (i.suffix != QWORD_MNEM_SUFFIX && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE && !i.tm.opcode_modifier.floatmf - && !is_any_vex_encoding (&i.tm) + && (!is_any_vex_encoding (&i.tm) + || i.tm.opcode_space == SPACE_EVEXMAP4) && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) || (flag_code == CODE_64BIT && i.tm.opcode_modifier.jump == JUMP_BYTE))) @@ -10057,7 +10136,7 @@ output_insn (void) /* Since the VEX/EVEX prefix contains the implicit prefix, we don't need the explicit prefix. */ - if (!is_any_vex_encoding (&i.tm)) + if (!is_any_vex_encoding (&i.tm) && !is_any_apx_evex_encoding ()) { switch (i.tm.opcode_modifier.opcodeprefix) { diff --git a/opcodes/i386-dis-evex-len.h b/opcodes/i386-dis-evex-len.h index a02609c50f2..1933a045822 100644 --- a/opcodes/i386-dis-evex-len.h +++ b/opcodes/i386-dis-evex-len.h @@ -62,6 +62,16 @@ static const struct dis386 evex_len_table[][3] = { { REG_TABLE (REG_EVEX_0F38C7_L_2) }, }, + /* EVEX_LEN_0F38F2 */ + { + { "andnS", { Gdq, VexGdq, Edq }, 0 }, + }, + + /* EVEX_LEN_0F38F3 */ + { + { REG_TABLE(REG_EVEX_0F38F3_L_0) }, + }, + /* EVEX_LEN_0F3A00 */ { { Bad_Opcode }, diff --git a/opcodes/i386-dis-evex-mod.h b/opcodes/i386-dis-evex-mod.h index f9f912c5094..5a1326a1b73 100644 --- a/opcodes/i386-dis-evex-mod.h +++ b/opcodes/i386-dis-evex-mod.h @@ -1 +1,51 @@ /* Nothing at present. */ + /* MOD_EVEX_MAP4_65 */ + { + { "wrussK", { M, Gdq }, PREFIX_DATA }, + }, + /* MOD_EVEX_MAP4_66_PREFIX_0 */ + { + { "wrssK", { M, Gdq }, 0 }, + }, + /* MOD_EVEX_MAP4_DA_PREFIX_1 */ + { + { Bad_Opcode }, + { "encodekey128", { Gd, Ed }, 0 }, + }, + /* MOD_EVEX_MAP4_DB_PREFIX_1 */ + { + { Bad_Opcode }, + { "encodekey256", { Gd, Ed }, 0 }, + }, + /* MOD_EVEX_MAP4_DC_PREFIX_1 */ + { + { "aesenc128kl", { XM, M }, 0 }, + }, + /* MOD_EVEX_MAP4_DD_PREFIX_1 */ + { + { "aesdec128kl", { XM, M }, 0 }, + }, + /* MOD_EVEX_MAP4_DE_PREFIX_1 */ + { + { "aesenc256kl", { XM, M }, 0 }, + }, + /* MOD_EVEX_MAP4_DF_PREFIX_1 */ + { + { "aesdec256kl", { XM, M }, 0 }, + }, + /* MOD_EVEX_MAP4_F8_PREFIX_1 */ + { + { "enqcmds", { Gva, M }, 0 }, + }, + /* MOD_EVEX_MAP4_F8_PREFIX_2 */ + { + { "movdir64b", { Gva, M }, 0 }, + }, + /* MOD_EVEX_MAP4_F8_PREFIX_3 */ + { + { "enqcmd", { Gva, M }, 0 }, + }, + /* MOD_EVEX_MAP4_F9 */ + { + { "movdiri", { Edq, Gdq }, 0 }, + }, diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h index 28da54922c7..f6f02de6c47 100644 --- a/opcodes/i386-dis-evex-prefix.h +++ b/opcodes/i386-dis-evex-prefix.h @@ -338,6 +338,89 @@ { "vcmpp%XH", { MaskG, Vex, EXxh, EXxEVexS, CMP }, 0 }, { "vcmps%XH", { MaskG, VexScalar, EXw, EXxEVexS, CMP }, 0 }, }, + /* PREFIX_EVEX_MAP4_60 */ + { + { "movbeS", { Gv, Ev }, 0 }, + { Bad_Opcode }, + { "movbeS", { Gv, Ev }, 0 }, + }, + /* PREFIX_EVEX_MAP4_61 */ + { + { "movbeS", { Ev, Gv }, 0 }, + { Bad_Opcode }, + { "movbeS", { Ev, Gv }, 0 }, + }, + /* PREFIX_EVEX_MAP4_66 */ + { + { MOD_TABLE (MOD_EVEX_MAP4_66_PREFIX_0) }, + { "adoxS", { Gdq, Edq }, 0 }, + { "adcxS", { Gdq, Edq }, 0 }, + }, + /* PREFIX_EVEX_MAP4_D8 */ + { + { "sha1nexte", { XM, EXxmm }, 0 }, + { REG_TABLE (REG_EVEX_MAP4_D8_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_DA */ + { + { "sha1msg2", { XM, EXxmm }, 0 }, + { MOD_TABLE (MOD_EVEX_MAP4_DA_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_DB */ + { + { "sha256rnds2", { XM, EXxmm, XMM0 }, 0 }, + { MOD_TABLE (MOD_EVEX_MAP4_DB_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_DC */ + { + { "sha256msg1", { XM, EXxmm }, 0 }, + { MOD_TABLE (MOD_EVEX_MAP4_DC_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_DD */ + { + { "sha256msg2", { XM, EXxmm }, 0 }, + { MOD_TABLE (MOD_EVEX_MAP4_DD_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_DE */ + { + { Bad_Opcode }, + { MOD_TABLE (MOD_EVEX_MAP4_DE_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_DF */ + { + { Bad_Opcode }, + { MOD_TABLE (MOD_EVEX_MAP4_DF_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_F0 */ + { + { "crc32A", { Gdq, Eb }, 0 }, + { "invept", { Gm, Mo }, 0 }, + }, + /* PREFIX_EVEX_MAP4_F1 */ + { + { "crc32Q", { Gdq, Ev }, 0 }, + { "invvpid", { Gm, Mo }, 0 }, + { "crc32Q", { Gdq, Ev }, 0 }, + }, + /* PREFIX_EVEX_MAP4_F2 */ + { + { Bad_Opcode }, + { "invpcid", { Gm, M }, 0 }, + }, + /* PREFIX_EVEX_MAP4_F8 */ + { + { Bad_Opcode }, + { MOD_TABLE (MOD_EVEX_MAP4_F8_PREFIX_1) }, + { MOD_TABLE (MOD_EVEX_MAP4_F8_PREFIX_2) }, + { MOD_TABLE (MOD_EVEX_MAP4_F8_PREFIX_3) }, + }, + /* PREFIX_EVEX_MAP4_FC */ + { + { "aadd", { Mdq, Gdq }, 0 }, + { "axor", { Mdq, Gdq }, 0 }, + { "aand", { Mdq, Gdq }, 0 }, + { "aor", { Mdq, Gdq }, 0 }, + }, /* PREFIX_EVEX_MAP5_10 */ { { Bad_Opcode }, diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h index 2885063628b..c3b4f083346 100644 --- a/opcodes/i386-dis-evex-reg.h +++ b/opcodes/i386-dis-evex-reg.h @@ -49,3 +49,17 @@ { "vscatterpf0qp%XW", { MVexVSIBQWpX }, PREFIX_DATA }, { "vscatterpf1qp%XW", { MVexVSIBQWpX }, PREFIX_DATA }, }, + /* REG_EVEX_0F38F3_L_0 */ + { + { Bad_Opcode }, + { "blsrS", { VexGdq, Edq }, 0 }, + { "blsmskS", { VexGdq, Edq }, 0 }, + { "blsiS", { VexGdq, Edq }, 0 }, + }, + /* REG_EVEX_MAP4_D8_PREFIX_1 */ + { + { "aesencwide128kl", { M }, 0 }, + { "aesdecwide128kl", { M }, 0 }, + { "aesencwide256kl", { M }, 0 }, + { "aesdecwide256kl", { M }, 0 }, + }, diff --git a/opcodes/i386-dis-evex-x86.h b/opcodes/i386-dis-evex-x86.h new file mode 100644 index 00000000000..1121223d877 --- /dev/null +++ b/opcodes/i386-dis-evex-x86.h @@ -0,0 +1,140 @@ + /* X86_64_EVEX_0F90 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F90) }, + }, + /* X86_64_EVEX_0F91 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F91) }, + }, + /* X86_64_EVEX_0F92 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F92) }, + }, + /* X86_64_EVEX_0F93 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F93) }, + }, + /* X86_64_EVEX_0F3849 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) }, + }, + /* X86_64_EVEX_0F384B */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) }, + }, + /* X86_64_EVEX_0F38E0 */ + { + { Bad_Opcode }, + { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E1 */ + { + { Bad_Opcode }, + { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E2 */ + { + { Bad_Opcode }, + { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E3 */ + { + { Bad_Opcode }, + { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E4 */ + { + { Bad_Opcode }, + { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E5 */ + { + { Bad_Opcode }, + { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E6 */ + { + { Bad_Opcode }, + { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E7 */ + { + { Bad_Opcode }, + { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E8 */ + { + { Bad_Opcode }, + { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E9 */ + { + { Bad_Opcode }, + { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38EA */ + { + { Bad_Opcode }, + { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38EB */ + { + { Bad_Opcode }, + { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38EC */ + { + { Bad_Opcode }, + { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38ED */ + { + { Bad_Opcode }, + { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38EE */ + { + { Bad_Opcode }, + { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38EF */ + { + { Bad_Opcode }, + { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38F2 */ + { + { Bad_Opcode }, + { EVEX_LEN_TABLE (EVEX_LEN_0F38F2) }, + }, + /* X86_64_EVEX_0F38F3 */ + { + { Bad_Opcode }, + { EVEX_LEN_TABLE (EVEX_LEN_0F38F3) }, + }, + /* X86_64_EVEX_0F38F5 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F38F5) }, + }, + /* X86_64_EVEX_0F38F6 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F38F6) }, + }, + /* X86_64_EVEX_0F38F7 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F38F7) }, + }, + /* X86_64_EVEX_0F3AF0 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3AF0) }, + }, diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index e6295119d2b..2a8c80c5200 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -164,10 +164,10 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 90 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F90) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F91) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F92) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F93) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -375,9 +375,9 @@ static const struct dis386 evex_table[][256] = { { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, /* 48 */ { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F3849) }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F384B) }, { "vrcp14p%XW", { XM, EXx }, PREFIX_DATA }, { "vrcp14s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, { "vrsqrt14p%XW", { XM, EXx }, 0 }, @@ -545,32 +545,32 @@ static const struct dis386 evex_table[][256] = { { "%XEvaesdecY", { XM, Vex, EXx }, PREFIX_DATA }, { "%XEvaesdeclastY", { XM, Vex, EXx }, PREFIX_DATA }, /* E0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E0) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E1) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E2) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E3) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E4) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E5) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E6) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E7) }, /* E8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E8) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E9) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38EA) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38EB) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38EC) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38ED) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38EE) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38EF) }, /* F0 */ { Bad_Opcode }, { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38F2) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38F3) }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38F5) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38F6) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38F7) }, /* F8 */ { Bad_Opcode }, { Bad_Opcode }, @@ -854,7 +854,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* F0 */ - { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F3AF0) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -872,7 +872,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, }, - /* EVEX_MAP5_ */ + /* EVEX_MAP4_ */ { /* 00 */ { Bad_Opcode }, @@ -893,8 +893,8 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 10 */ - { PREFIX_TABLE (PREFIX_EVEX_MAP5_10) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_11) }, + { Bad_Opcode }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -907,7 +907,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_1D) }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 20 */ @@ -922,12 +922,12 @@ static const struct dis386 evex_table[][256] = { /* 28 */ { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_2A) }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_2C) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_2D) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_2E) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_2F) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, /* 30 */ { Bad_Opcode }, { Bad_Opcode }, @@ -966,7 +966,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, /* 50 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_51) }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -974,15 +974,6 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 58 */ - { PREFIX_TABLE (PREFIX_EVEX_MAP5_58) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_59) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5A) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5B) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5C) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5D) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5E) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5F) }, - /* 60 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -991,6 +982,15 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 60 */ + { PREFIX_TABLE (PREFIX_EVEX_MAP4_60) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_61) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_EVEX_MAP4_65) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_66) }, + { Bad_Opcode }, /* 68 */ { Bad_Opcode }, { Bad_Opcode }, @@ -998,7 +998,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vmovwY", { XMScalar, Edw }, PREFIX_DATA }, + { Bad_Opcode }, { Bad_Opcode }, /* 70 */ { Bad_Opcode }, @@ -1010,13 +1010,13 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 78 */ - { PREFIX_TABLE (PREFIX_EVEX_MAP5_78) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_79) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_7A) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_7B) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_7C) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_7D) }, - { "vmovw", { Edw, XMScalar }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, { Bad_Opcode }, /* 80 */ { Bad_Opcode }, @@ -1113,19 +1113,19 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { "sha1rnds4", { XM, EXxmm, Ib }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* D8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_D8) }, + { "sha1msg1", { XM, EXxmm }, 0 }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_DA) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_DB) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_DC) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_DD) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_DE) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_DF) }, /* E0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1145,25 +1145,25 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* F0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_F0) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_F1) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_F2) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* F8 */ + { PREFIX_TABLE (PREFIX_EVEX_MAP4_F8) }, + { MOD_TABLE (MOD_EVEX_MAP4_F9) }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_FC) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, }, - /* EVEX_MAP6_ */ + /* EVEX_MAP5_ */ { /* 00 */ { Bad_Opcode }, @@ -1184,11 +1184,11 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 10 */ + { PREFIX_TABLE (PREFIX_EVEX_MAP5_10) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_11) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP6_13) }, - { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -1198,7 +1198,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_1D) }, { Bad_Opcode }, { Bad_Opcode }, /* 20 */ @@ -1213,12 +1213,12 @@ static const struct dis386 evex_table[][256] = { /* 28 */ { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_2A) }, { Bad_Opcode }, - { Bad_Opcode }, - { "vscalefp%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vscalefs%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_2C) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_2D) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_2E) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_2F) }, /* 30 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1240,39 +1240,39 @@ static const struct dis386 evex_table[][256] = { /* 40 */ { Bad_Opcode }, { Bad_Opcode }, - { "vgetexpp%XH", { XM, EXxh, EXxEVexS }, PREFIX_DATA }, - { "vgetexps%XH", { XMScalar, VexScalar, EXw, EXxEVexS }, PREFIX_DATA }, - { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 48 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 48 */ { Bad_Opcode }, - { "vrcpp%XH", { XM, EXxh }, PREFIX_DATA }, - { "vrcps%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA }, - { "vrsqrtp%XH", { XM, EXxh }, PREFIX_DATA }, - { "vrsqrts%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA }, - /* 50 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP6_56) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP6_57) }, - /* 58 */ { Bad_Opcode }, + /* 50 */ { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_51) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 58 */ + { PREFIX_TABLE (PREFIX_EVEX_MAP5_58) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_59) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_5A) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_5B) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_5C) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_5D) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_5E) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_5F) }, /* 60 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1289,7 +1289,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { "vmovwY", { XMScalar, Edw }, PREFIX_DATA }, { Bad_Opcode }, /* 70 */ { Bad_Opcode }, @@ -1301,7 +1301,15 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 78 */ + { PREFIX_TABLE (PREFIX_EVEX_MAP5_78) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_79) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_7A) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_7B) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_7C) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_7D) }, + { "vmovw", { Edw, XMScalar }, PREFIX_DATA }, { Bad_Opcode }, + /* 80 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -1309,8 +1317,8 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 80 */ { Bad_Opcode }, + /* 88 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -1318,8 +1326,8 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 88 */ { Bad_Opcode }, + /* 90 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -1327,24 +1335,16 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 90 */ + { Bad_Opcode }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmsubadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - /* 98 */ - { "vfmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfnmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfnmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfnmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfnmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, /* A0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1352,17 +1352,17 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmsubadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, /* A8 */ - { "vfmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfnmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfnmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfnmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfnmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, /* B0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1370,17 +1370,17 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmsubadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, /* B8 */ - { "vfmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfnmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfnmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfnmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfnmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, /* C0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1406,8 +1406,590 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP6_D6) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP6_D7) }, + { Bad_Opcode }, + { Bad_Opcode }, + /* D8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* E0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* E8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* F0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* F8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + /* EVEX_MAP6_ */ + { + /* 00 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 08 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 10 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP6_13) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vscalefp%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vscalefs%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { Bad_Opcode }, + { Bad_Opcode }, + { "vgetexpp%XH", { XM, EXxh, EXxEVexS }, PREFIX_DATA }, + { "vgetexps%XH", { XMScalar, VexScalar, EXw, EXxEVexS }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vrcpp%XH", { XM, EXxh }, PREFIX_DATA }, + { "vrcps%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA }, + { "vrsqrtp%XH", { XM, EXxh }, PREFIX_DATA }, + { "vrsqrts%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP6_56) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP6_57) }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmaddsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmsubadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + /* 98 */ + { "vfmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfnmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfnmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfnmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfnmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + /* A0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmaddsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmsubadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + /* A8 */ + { "vfmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfnmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfnmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfnmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfnmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + /* B0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmaddsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmsubadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + /* B8 */ + { "vfmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfnmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfnmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfnmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfnmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + /* C0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* C8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* D0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP6_D6) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP6_D7) }, + /* D8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* E0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* E8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* F0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* F8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + /* EVEX_MAP7_ */ + { + /* 00 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 08 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 10 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* A0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* A8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* B0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* B8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* C0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* C8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* D0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, /* D8 */ { Bad_Opcode }, { Bad_Opcode }, diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 65bdd6f65db..c8f3cfb8149 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -132,6 +132,13 @@ enum x86_64_isa intel64 }; +enum evex_type +{ + evex_default = 0, + evex_from_legacy, + evex_from_vex, +}; + struct instr_info { enum address_mode address_mode; @@ -212,7 +219,6 @@ struct instr_info int ll; bool w; bool evex; - bool r; bool v; bool zeroing; bool b; @@ -220,6 +226,8 @@ struct instr_info } vex; + enum evex_type evex_type; + /* Remember if the current op is a jump instruction. */ bool op_is_jump; @@ -793,6 +801,7 @@ enum USE_RM_TABLE, USE_PREFIX_TABLE, USE_X86_64_TABLE, + USE_X86_64_EVEX_FROM_VEX_TABLE, USE_3BYTE_TABLE, USE_XOP_8F_TABLE, USE_VEX_C4_TABLE, @@ -811,6 +820,8 @@ enum #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) +#define X86_64_EVEX_FROM_VEX_TABLE(I) \ + DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I)) #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) #define XOP_8F_TABLE() DIS386 (USE_XOP_8F_TABLE, 0) #define VEX_C4_TABLE() DIS386 (USE_VEX_C4_TABLE, 0) @@ -870,7 +881,9 @@ enum REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6_L_2, - REG_EVEX_0F38C7_L_2 + REG_EVEX_0F38C7_L_2, + REG_EVEX_0F38F3_L_0, + REG_EVEX_MAP4_D8_PREFIX_1 }; enum @@ -910,6 +923,19 @@ enum MOD_0F38DC_PREFIX_1, MOD_VEX_0F3849_X86_64_L_0_W_0, + + MOD_EVEX_MAP4_65, + MOD_EVEX_MAP4_66_PREFIX_0, + MOD_EVEX_MAP4_DA_PREFIX_1, + MOD_EVEX_MAP4_DB_PREFIX_1, + MOD_EVEX_MAP4_DC_PREFIX_1, + MOD_EVEX_MAP4_DD_PREFIX_1, + MOD_EVEX_MAP4_DE_PREFIX_1, + MOD_EVEX_MAP4_DF_PREFIX_1, + MOD_EVEX_MAP4_F8_PREFIX_1, + MOD_EVEX_MAP4_F8_PREFIX_2, + MOD_EVEX_MAP4_F8_PREFIX_3, + MOD_EVEX_MAP4_F9, }; enum @@ -1145,6 +1171,22 @@ enum PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, + PREFIX_EVEX_MAP4_60, + PREFIX_EVEX_MAP4_61, + PREFIX_EVEX_MAP4_66, + PREFIX_EVEX_MAP4_D8, + PREFIX_EVEX_MAP4_DA, + PREFIX_EVEX_MAP4_DB, + PREFIX_EVEX_MAP4_DC, + PREFIX_EVEX_MAP4_DD, + PREFIX_EVEX_MAP4_DE, + PREFIX_EVEX_MAP4_DF, + PREFIX_EVEX_MAP4_F0, + PREFIX_EVEX_MAP4_F1, + PREFIX_EVEX_MAP4_F2, + PREFIX_EVEX_MAP4_F8, + PREFIX_EVEX_MAP4_FC, + PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, @@ -1255,6 +1297,35 @@ enum X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF, + + X86_64_EVEX_0F90, + X86_64_EVEX_0F91, + X86_64_EVEX_0F92, + X86_64_EVEX_0F93, + X86_64_EVEX_0F3849, + X86_64_EVEX_0F384B, + X86_64_EVEX_0F38E0, + X86_64_EVEX_0F38E1, + X86_64_EVEX_0F38E2, + X86_64_EVEX_0F38E3, + X86_64_EVEX_0F38E4, + X86_64_EVEX_0F38E5, + X86_64_EVEX_0F38E6, + X86_64_EVEX_0F38E7, + X86_64_EVEX_0F38E8, + X86_64_EVEX_0F38E9, + X86_64_EVEX_0F38EA, + X86_64_EVEX_0F38EB, + X86_64_EVEX_0F38EC, + X86_64_EVEX_0F38ED, + X86_64_EVEX_0F38EE, + X86_64_EVEX_0F38EF, + X86_64_EVEX_0F38F2, + X86_64_EVEX_0F38F3, + X86_64_EVEX_0F38F5, + X86_64_EVEX_0F38F6, + X86_64_EVEX_0F38F7, + X86_64_EVEX_0F3AF0, }; enum @@ -1282,8 +1353,10 @@ enum EVEX_0F = 0, EVEX_0F38, EVEX_0F3A, + EVEX_MAP4, EVEX_MAP5, EVEX_MAP6, + EVEX_MAP7, }; enum @@ -1436,6 +1509,8 @@ enum EVEX_LEN_0F385B, EVEX_LEN_0F38C6, EVEX_LEN_0F38C7, + EVEX_LEN_0F38F2, + EVEX_LEN_0F38F3, EVEX_LEN_0F3A00, EVEX_LEN_0F3A01, EVEX_LEN_0F3A18, @@ -4476,6 +4551,8 @@ static const struct dis386 x86_64_table[][2] = { { Bad_Opcode }, { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, }, + +#include "i386-dis-evex-x86.h" }; static const struct dis386 three_byte_table[][256] = { @@ -8665,6 +8742,9 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) dp = &prefix_table[dp->op[1].bytemode][vindex]; break; + case USE_X86_64_EVEX_FROM_VEX_TABLE: + ins->evex_type = evex_from_vex; + /* Fall through. */ case USE_X86_64_TABLE: vindex = ins->address_mode == mode_64bit ? 1 : 0; dp = &x86_64_table[dp->op[1].bytemode][vindex]; @@ -8910,9 +8990,13 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) if (!fetch_code (ins->info, ins->codep + 4)) return &err_opcode; /* The first byte after 0x62. */ + if (*ins->codep & 0x8) + ins->rex2 |= REX_B; + if (!(*ins->codep & 0x10)) + ins->rex2 |= REX_R; + ins->rex = ~(*ins->codep >> 5) & 0x7; - ins->vex.r = *ins->codep & 0x10; - switch ((*ins->codep & 0xf)) + switch ((*ins->codep & 0x7)) { default: return &bad_opcode; @@ -8925,12 +9009,19 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) case 0x3: vex_table_index = EVEX_0F3A; break; + case 0x4: + vex_table_index = EVEX_MAP4; + ins->evex_type = evex_from_legacy; + break; case 0x5: vex_table_index = EVEX_MAP5; break; case 0x6: vex_table_index = EVEX_MAP6; break; + case 0x7: + vex_table_index = EVEX_MAP7; + break; } /* The second byte after 0x62. */ @@ -8941,9 +9032,8 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; - /* The U bit. */ if (!(*ins->codep & 0x4)) - return &bad_opcode; + ins->rex2 |= REX_X; switch ((*ins->codep & 0x3)) { @@ -8973,9 +9063,12 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) if (ins->address_mode != mode_64bit) { + if (ins->evex_type != evex_default + || (ins->rex2 & (REX_B | REX_X))) + return &bad_opcode; /* In 16/32-bit mode silently ignore following bits. */ ins->rex &= ~REX_B; - ins->vex.r = true; + ins->rex2 &= ~REX_R; } ins->need_vex = 4; @@ -9391,6 +9484,13 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) dp = get_valid_dis386 (dp, &ins); if (dp == &err_opcode) goto fetch_error_out; + + /* For APX instructions promoted from legacy maps 0/1, prefix + 0x66 is interpreted as the operand size override. */ + if (ins.evex_type == evex_from_legacy + && ins.vex.prefix == DATA_PREFIX_OPCODE) + sizeflag ^= DFLAG; + if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0) { if (!get_sib (&ins, sizeflag)) @@ -10280,7 +10380,7 @@ putop (instr_info *ins, const char *in_template, int sizeflag) { case 'X': if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2 - || !ins->vex.r + || (ins->rex2 & REX_R) || (ins->modrm.mod == 3 && (ins->rex & REX_X)) || !ins->vex.v || ins->vex.mask_register_specifier) break; @@ -11174,7 +11274,7 @@ print_register (instr_info *ins, unsigned int reg, unsigned int rexmask, case b_swap_mode: if (reg & 4) USED_REX (0); - if (ins->rex) + if (ins->rex || ins->rex2) names = att_names8rex; else names = att_names8; @@ -11390,7 +11490,7 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag) int riprel = 0; int shift; - if (ins->vex.evex) + if (ins->vex.evex && ins->evex_type == evex_default) { /* Zeroing-masking is invalid for memory destinations. Set the flag @@ -11737,7 +11837,7 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag) if (ins->rex & REX_R) modrm_reg += 8; - if (!ins->vex.r) + if (ins->rex2 & REX_R) modrm_reg += 16; if (vindex == modrm_reg) oappend (ins, "/(bad)"); @@ -11939,10 +12039,7 @@ OP_indirE (instr_info *ins, int bytemode, int sizeflag) static bool OP_G (instr_info *ins, int bytemode, int sizeflag) { - if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit) - oappend (ins, "(bad)"); - else - print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag); + print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag); return true; } @@ -12572,7 +12669,7 @@ OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) reg += 8; if (ins->vex.evex) { - if (!ins->vex.r) + if (ins->rex2 & REX_R) reg += 16; } @@ -13579,7 +13676,7 @@ DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag) /* Calc destination register number. */ if (ins->rex & REX_R) modrm_reg += 8; - if (!ins->vex.r) + if (ins->rex2 & REX_R) modrm_reg += 16; /* Calc src1 register number. */ diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 6b8eb729797..f43cb1ecf7c 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -1023,6 +1023,7 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, SPACE(0F), SPACE(0F38), SPACE(0F3A), + SPACE(EVEXMAP4), SPACE(EVEXMAP5), SPACE(EVEXMAP6), SPACE(XOP08), @@ -1121,6 +1122,15 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, fprintf (stderr, "%s: %d: W modifier without Word/Dword/Qword operand(s)\n", filename, lineno); + if (modifiers[Vex].value + || (space > SPACE_0F + && !(space == SPACE_EVEXMAP4 + || modifiers[EVex].value + || modifiers[Disp8MemShift].value + || modifiers[Broadcast].value + || modifiers[Masking].value + || modifiers[SAE].value))) + modifiers[No_egpr].value = 1; } if (space >= ARRAY_SIZE (spaces) || !spaces[space]) diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index a055db5ce42..9dd5625f54d 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -972,6 +972,7 @@ typedef struct insn_template 1: 0F opcode prefix / space. 2: 0F38 opcode prefix / space. 3: 0F3A opcode prefix / space. + 4: EVEXMAP4 opcode prefix / space. 5: EVEXMAP5 opcode prefix / space. 6: EVEXMAP6 opcode prefix / space. 8: XOP 08 opcode space. @@ -982,6 +983,7 @@ typedef struct insn_template #define SPACE_0F 1 #define SPACE_0F38 2 #define SPACE_0F3A 3 +#define SPACE_EVEXMAP4 4 #define SPACE_EVEXMAP5 5 #define SPACE_EVEXMAP6 6 #define SPACE_XOP08 8 diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 80248e5b72c..791a9fe0177 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -109,6 +109,7 @@ #define SpaceXOP09 OpcodeSpace=SPACE_XOP09 #define SpaceXOP0A OpcodeSpace=SPACE_XOP0A +#define EVexMap4 OpcodeSpace=SPACE_EVEXMAP4 #define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 #define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6 @@ -187,6 +188,7 @@ mov, 0xf24, i386|No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Te // Move after swapping the bytes movbe, 0x0f38f0, Movbe, D|Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movbe, 0x60, Movbe|APX_F|x64, D|Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // Move with sign extend. movsb, 0xfbe, i386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } @@ -300,6 +302,9 @@ sbb, 0x18, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg sbb, 0x83/3, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } sbb, 0x1c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } sbb, 0x80/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sbb, 0x18, APX_F|x64, D|W|CheckOperandSize|Modrm|EVex128|EVexMap4|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sbb, 0x83/3, APX_F|x64, Modrm|EVex128|EVexMap4|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +sbb, 0x80/3, APX_F|x64, W|Modrm|EVex128|EVexMap4|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } cmp, 0x38, 0, D|W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } cmp, 0x83/7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } @@ -332,9 +337,14 @@ adc, 0x10, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg adc, 0x83/2, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } adc, 0x14, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } adc, 0x80/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +adc, 0x10, APX_F|x64, D|W|CheckOperandSize|Modrm|EVex128|EVexMap4|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +adc, 0x83/2, APX_F|x64, Modrm|EVex128|EVexMap4|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +adc, 0x80/2, APX_F|x64, W|Modrm|EVex128|EVexMap4|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } neg, 0xf6/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + not, 0xf6/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +not, 0xf6/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } aaa, 0x37, No64, NoSuf, {} aas, 0x3f, No64, NoSuf, {} @@ -395,11 +405,19 @@ rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword| rcl, 0xc0/2, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcl, 0xd2/2, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcl, 0xd0/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcl, 0xc0/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcl, 0xd2/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcl, 0xd0/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xc0/3, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xd2/3, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcr, 0xd0/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcr, 0xc0/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcr, 0xd2/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcr, 0xd0/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sal, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } @@ -1312,13 +1330,16 @@ getsec, 0xf37, SMX, NoSuf, {} invept, 0x660f3880, EPT|No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } invept, 0x660f3880, EPT|x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } +invept, 0xf3f0, APX_F|EPT|x64, Modrm|NoSuf|NoRex64|EVex128|EVexMap4, { Oword|Unspecified|BaseIndex, Reg64 } invvpid, 0x660f3881, EPT|No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } invvpid, 0x660f3881, EPT|x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } +invvpid, 0xf3f1, APX_F|EPT|x64, Modrm|NoSuf|NoRex64|EVex128|EVexMap4, { Oword|Unspecified|BaseIndex, Reg64 } // INVPCID instruction invpcid, 0x660f3882, INVPCID|No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } invpcid, 0x660f3882, INVPCID|x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } +invpcid, 0xf3f2, APX_F|INVPCID|x64, Modrm|NoSuf|NoRex64|EVex128|EVexMap4, { Oword|Unspecified|BaseIndex, Reg64 } // SSSE3 instructions. @@ -1418,7 +1439,9 @@ pcmpestrm, 0x660f3a60, SSE4_2|x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { I pcmpistri, 0x660f3a63, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } pcmpistrm, 0x660f3a62, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } crc32, 0xf20f38f0, SSE4_2, W|Modrm|No_sSuf|No_qSuf, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } +crc32, 0xf0, APX_F|x64, W|Modrm|No_sSuf|No_qSuf|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } crc32, 0xf20f38f0, SSE4_2|x64, W|Modrm|No_wSuf|No_lSuf|No_sSuf, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } +crc32, 0xf0, APX_F|x64, W|Modrm|No_wSuf|No_lSuf|No_sSuf|EVex128|EVexMap4, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } // xsave/xrstor New Instructions. @@ -1822,13 +1845,21 @@ xtest, 0xf01d6, HLE|RTM, NoSuf, {} // BMI2 instructions. bzhi, 0xf5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +bzhi, 0xf5, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } mulx, 0xf2f6, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +mulx, 0xf2f6, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } pdep, 0xf2f5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +pdep, 0xf2f5, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } pext, 0xf3f5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +pext, 0xf3f5, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } rorx, 0xf2f0, BMI2, Modrm|CheckOperandSize|Vex128|Space0F3A|No_bSuf|No_wSuf|No_sSuf, { Imm8|Imm8S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +rorx, 0xf2f0, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F3A|No_bSuf|No_wSuf|No_sSuf, { Imm8|Imm8S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } sarx, 0xf3f7, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +sarx, 0xf3f7, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } shlx, 0x66f7, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +shlx, 0x66f7, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } shrx, 0xf2f7, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +shrx, 0xf2f7, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } // FMA4 instructions @@ -1899,10 +1930,15 @@ lwpins, 0x12/0, LWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV|Vex, { Imm32|Imm32S, Reg32|U // BMI instructions andn, 0xf2, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +andn, 0xf2, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } bextr, 0xf7, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +bextr, 0xf7, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } blsi, 0xf3/3, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +blsi, 0xf3/3, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } blsmsk, 0xf3/2, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +blsmsk, 0xf3/2, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } blsr, 0xf3/1, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +blsr, 0xf3/1, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } tzcnt, 0xf30fbc, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // TBM instructions @@ -2007,7 +2043,9 @@ xstore, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {} // Multy-precision Add Carry, rdseed instructions. adcx, 0x660f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +adcx, 0x6666, ADX|APX_F|x64, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|EVex128|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } adox, 0xf30f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +adox, 0xf366, ADX|APX_F|x64, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|EVex128|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } rdseed, 0xfc7/7, RdSeed, Modrm|NoSuf, { Reg16|Reg32|Reg64 } // SMAP instructions. @@ -2031,13 +2069,20 @@ bndldx, 0x0f1a, MPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } // SHA instructions. sha1rnds4, 0xf3acc, SHA, Modrm|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } +sha1rnds4, 0xd4, SHA|APX_F, Modrm|NoSuf|EVex128|EVexMap4, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } sha1nexte, 0xf38c8, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha1nexte, 0xd8, SHA|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { RegXMM|Unspecified|BaseIndex, RegXMM } sha1msg1, 0xf38c9, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha1msg1, 0xd9, SHA|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { RegXMM|Unspecified|BaseIndex, RegXMM } sha1msg2, 0xf38ca, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha1msg2, 0xda, SHA|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { RegXMM|Unspecified|BaseIndex, RegXMM } sha256rnds2, 0xf38cb, SHA, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } sha256rnds2, 0xf38cb, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha256rnds2, 0xdb, SHA|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { RegXMM|Unspecified|BaseIndex, RegXMM } sha256msg1, 0xf38cc, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha256msg1, 0xdc, SHA|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { RegXMM|Unspecified|BaseIndex, RegXMM } sha256msg2, 0xf38cd, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha256msg2, 0xdd, SHA|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { RegXMM|Unspecified|BaseIndex, RegXMM } // SHA512 instructions. @@ -2104,8 +2149,11 @@ kxnor, 0x46, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { kxor, 0x47, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } kmov, 0x90, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } +kmov, 0x90, |APX_F, Modrm|EVex128|Space0F|VexW0|NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } kmov, 0x91, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, |Unspecified|BaseIndex } +kmov, 0x91, |APX_F, Modrm|EVex128|Space0F|VexW0|NoSuf, { RegMask, |Unspecified|BaseIndex } kmov, 0x92, , D|Modrm|Vex128|Space0F|VexW0|NoSuf, { Reg32, RegMask } +kmov, 0x92, |APX_F, D|Modrm|EVex128|Space0F|VexW0|NoSuf, { Reg32, RegMask } knot, 0x44, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } kortest, 0x98, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } @@ -2626,8 +2674,11 @@ kadd, 0x4a, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|| kand, 0x41, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf, { RegMask, RegMask, RegMask } kandn, 0x42, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf|Optimize, { RegMask, RegMask, RegMask } kmov, 0x90, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } +kmov, 0x90, AVX512BW|APX_F, Modrm|EVex128|Space0F|VexW1||NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } kmov, 0x91, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, |Unspecified|BaseIndex } +kmov, 0x91, AVX512BW|APX_F, Modrm|EVex128|Space0F|VexW1||NoSuf, { RegMask, |Unspecified|BaseIndex } kmov, 0xf292, AVX512BW, D|Modrm|Vex128|Space0F|||NoSuf, { , RegMask } +kmov, 0xf292, AVX512BW|APX_F, D|Modrm|EVex128|Space0F|||NoSuf, { , RegMask } knot, 0x44, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, RegMask } kor, 0x45, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf, { RegMask, RegMask, RegMask } kortest, 0x98, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, RegMask } @@ -3046,9 +3097,13 @@ rdsspq, 0xf30f1e/1, SHSTK|x64, Modrm|NoSuf, { Reg64 } saveprevssp, 0xf30f01ea, SHSTK, NoSuf, {} rstorssp, 0xf30f01/5, SHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } wrssd, 0x0f38f6, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } +wrssd, 0x66, SHSTK|APX_F|x64, Modrm|IgnoreSize|NoSuf|EVex128|EVexMap4, { Reg32, Dword|Unspecified|BaseIndex } wrssq, 0x0f38f6, SHSTK|x64, Modrm|NoSuf|Size64, { Reg64, Qword|Unspecified|BaseIndex } +wrssq, 0x66, APX_F|SHSTK|x64, Modrm|NoSuf|Size64|EVex128|EVexMap4, { Reg64, Qword|Unspecified|BaseIndex } wrussd, 0x660f38f5, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } +wrussd, 0x6665, SHSTK|APX_F|x64, Modrm|IgnoreSize|NoSuf|EVex128|EVexMap4, { Reg32, Dword|Unspecified|BaseIndex } wrussq, 0x660f38f5, SHSTK|x64, Modrm|NoSuf, { Reg64, Qword|Unspecified|BaseIndex } +wrussq, 0x6665, SHSTK|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Reg64, Qword|Unspecified|BaseIndex } setssbsy, 0xf30f01e8, SHSTK, NoSuf, {} clrssbsy, 0xf30fae/6, SHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } endbr64, 0xf30f1efa, IBT, NoSuf, {} @@ -3096,7 +3151,9 @@ cldemote, 0x0f1c/0, CLDEMOTE, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } // MOVDIR[I,64B] instructions. movdiri, 0xf38f9, MOVDIRI, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +movdiri, 0xf9, MOVDIRI|APX_F|x64, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|EVex128|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } movdir64b, 0x660f38f8, MOVDIR64B, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movdir64b, 0x66f8, MOVDIR64B|APX_F|x64, Modrm|AddrPrefixOpReg|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, Reg32|Reg64 } // MOVEDIR instructions end. @@ -3125,7 +3182,9 @@ vcvtneps2bf16, 0xf372, AVX_NE_CONVERT, Modrm||Space0F38|VexW0|NoSu // ENQCMD instructions. enqcmd, 0xf20f38f8, ENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +enqcmd, 0xf2f8, ENQCMD|APX_F|x64, Modrm|AddrPrefixOpReg|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, Reg32|Reg64 } enqcmds, 0xf30f38f8, ENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +enqcmds, 0xf3f8, ENQCMD|APX_F|x64, Modrm|AddrPrefixOpReg|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, Reg32|Reg64 } // ENQCMD instructions end. @@ -3187,7 +3246,9 @@ xresldtrk, 0xf20f01e9, TSXLDTRK, NoSuf, {} // AMX instructions. ldtilecfg, 0x49/0, AMX_TILE|x64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } +ldtilecfg, 0x49/0, AMX_TILE|APX_F|x64, Modrm|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } sttilecfg, 0x6649/0, AMX_TILE|x64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } +sttilecfg, 0x6649/0, AMX_TILE|APX_F|x64, Modrm|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } tcmmimfp16ps, 0x666c, AMX_COMPLEX|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } tcmmrlfp16ps, 0x6c, AMX_COMPLEX|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } @@ -3200,8 +3261,11 @@ tdpbusd, 0x665e, AMX_INT8|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources| tdpbsud, 0xf35e, AMX_INT8|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } tileloadd, 0xf24b, AMX_TILE|x64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } +tileloadd, 0xf24b, AMX_TILE|APX_F|x64, Sibmem|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } tileloaddt1, 0x664b, AMX_TILE|x64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } +tileloaddt1, 0x664b, AMX_TILE|APX_F|x64, Sibmem|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } tilestored, 0xf34b, AMX_TILE|x64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex } +tilestored, 0xf34b, AMX_TILE|APX_F|x64, Sibmem|EVex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex } tilerelease, 0x49c0, AMX_TILE|x64, Vex128|Space0F38|VexW0|NoSuf, {} @@ -3213,15 +3277,25 @@ tilezero, 0xf249, AMX_TILE|x64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM } loadiwkey, 0xf30f38dc, KL, Load|Modrm|NoSuf, { RegXMM, RegXMM } encodekey128, 0xf30f38fa, KL, Modrm|NoSuf, { Reg32, Reg32 } +encodekey128, 0xf3da, KL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Reg32, Reg32 } encodekey256, 0xf30f38fb, KL, Modrm|NoSuf, { Reg32, Reg32 } +encodekey256, 0xf3db, KL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Reg32, Reg32 } aesenc128kl, 0xf30f38dc, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesenc128kl, 0xf3dc, KL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, RegXMM } aesdec128kl, 0xf30f38dd, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesdec128kl, 0xf3dd, KL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, RegXMM } aesenc256kl, 0xf30f38de, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesenc256kl, 0xf3de, KL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, RegXMM } aesdec256kl, 0xf30f38df, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesdec256kl, 0xf3df, KL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, RegXMM } aesencwide128kl, 0xf30f38d8/0, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesencwide128kl, 0xf3d8/0, WideKL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex } aesdecwide128kl, 0xf30f38d8/1, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesdecwide128kl, 0xf3d8/1, WideKL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex } aesencwide256kl, 0xf30f38d8/2, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesencwide256kl, 0xf3d8/2, WideKL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex } aesdecwide256kl, 0xf30f38d8/3, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesdecwide256kl, 0xf3d8/3, WideKL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex } // KEYLOCKER instructions end. @@ -3370,6 +3444,7 @@ prefetchit1, 0xf18/6, PREFETCHI|x64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex // CMPCCXADD instructions. cmpxadd, 0x66e, CMPCCXADD|x64, Modrm|Vex|Space0F38|VexVVVV|SwapSources|CheckOperandSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +cmpxadd, 0x66e, CMPCCXADD|x64|APX_F, Modrm|EVex128|Space0F38|VexVVVV|SwapSources|CheckOperandSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } // CMPCCXADD instructions end. @@ -3389,9 +3464,13 @@ wrmsrlist, 0xf30f01c6, MSRLIST|x64, NoSuf, {} // RAO-INT instructions. aadd, 0xf38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +aadd, 0xfc, RAO_INT|APX_F|x64, Modrm|IgnoreSize|CheckOperandSize|NoSuf|EVex128|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aand, 0x660f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +aand, 0x66fc, RAO_INT|APX_F|x64, Modrm|IgnoreSize|CheckOperandSize|NoSuf|EVex128|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aor, 0xf20f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +aor, 0xf2fc, RAO_INT|APX_F|x64, Modrm|IgnoreSize|CheckOperandSize|NoSuf|EVex128|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } axor, 0xf30f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +axor, 0xf3fc, RAO_INT|APX_F|x64, Modrm|IgnoreSize|CheckOperandSize|NoSuf|EVex128|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } // RAO-INT instructions end. @@ -3408,3 +3487,4 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, 0xf30f01ca, FRED|x64, NoSuf, {} // FRED instructions end. + From patchwork Tue Sep 19 15:25:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Frager, Neal via Binutils" X-Patchwork-Id: 76387 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E2686386BFE8 for ; Tue, 19 Sep 2023 15:27:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E2686386BFE8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1695137252; bh=IBZA/N87Nef6Ds+j/35LoddOXD1Czf4Cqf7JOXI0OnY=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=D6eJE0iGTebZvI6iWjX2ndRIZVCkT/P0tbUkT3RlConB1ynt/aII7AK4sDfoe0ZUH BlFxyJL96HEhVf79ll7THwXH0cT7TOXJ/W9+pE1IW+4mQEAnQK30Ln6BIUSj1aTlYF wkOsmf9WcEGVBXBc7r4zjZY8tvXR0N7Xwt1ije/0= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 518963858418 for ; Tue, 19 Sep 2023 15:25:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 518963858418 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="370285678" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="370285678" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 08:25:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="781339024" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="781339024" Received: from scymds03.sc.intel.com ([10.148.94.166]) by orsmga001.jf.intel.com with ESMTP; 19 Sep 2023 08:25:34 -0700 Received: from shgcc101.sh.intel.com (shgcc101.sh.intel.com [10.239.85.97]) by scymds03.sc.intel.com (Postfix) with ESMTP id 3B0676A; Tue, 19 Sep 2023 08:25:33 -0700 (PDT) To: binutils@sourceware.org Cc: jbeulich@suse.com, hongjiu.lu@intel.com Subject: [PATCH 3/8] Add tests for APX GPR32 with extend evex prefix Date: Tue, 19 Sep 2023 15:25:22 +0000 Message-Id: <20230919152527.497773-4-lili.cui@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230919152527.497773-1-lili.cui@intel.com> References: <20230919152527.497773-1-lili.cui@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Cui, Lili via Binutils" From: "Frager, Neal via Binutils" Reply-To: "Cui, Lili" Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" gas/ChangeLog: * testsuite/gas/i386/x86-64-apx-egpr-inval.l: Add some insn don't support gpr32 * testsuite/gas/i386/x86-64-apx-egpr-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-evex-egpr, x86-64-apx-evex-legacy and x86-64-apx-evex-vex. * testsuite/gas/i386/x86-64-apx-evex-egpr.d: New test. * testsuite/gas/i386/x86-64-apx-evex-egpr.s: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted-intrel.d: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: New test. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: New test. --- .../gas/i386/x86-64-apx-egpr-inval.l | 190 ++- .../gas/i386/x86-64-apx-egpr-inval.s | 194 ++- .../gas/i386/x86-64-apx-egpr-promote-inval.l | 17 + .../gas/i386/x86-64-apx-egpr-promote-inval.s | 18 + gas/testsuite/gas/i386/x86-64-apx-evex-egpr.d | 22 + gas/testsuite/gas/i386/x86-64-apx-evex-egpr.s | 25 + .../gas/i386/x86-64-apx-evex-promoted-intel.d | 740 +++++++++ .../gas/i386/x86-64-apx-evex-promoted.d | 740 +++++++++ .../gas/i386/x86-64-apx-evex-promoted.s | 1464 +++++++++++++++++ gas/testsuite/gas/i386/x86-64-evex.d | 2 +- gas/testsuite/gas/i386/x86-64-inval-movbe.l | 31 +- gas/testsuite/gas/i386/x86-64-inval-movbe.s | 1 + gas/testsuite/gas/i386/x86-64.exp | 4 + 13 files changed, 3430 insertions(+), 18 deletions(-) create mode 100644 gas/testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-evex-egpr.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-evex-egpr.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s diff --git a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l index c419f449f27..2fc8a4cc5f0 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l +++ b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l @@ -12,9 +12,197 @@ .*:16: Error: register type mismatch for `xsaveopt64' .*:17: Error: register type mismatch for `xsavec' .*:18: Error: register type mismatch for `xsavec64' +.*:20: Error: register type mismatch for `phaddw' +.*:21: Error: register type mismatch for `phaddd' +.*:22: Error: register type mismatch for `phaddsw' +.*:23: Error: register type mismatch for `phsubw' +.*:24: Error: register type mismatch for `pmaddubsw' +.*:25: Error: register type mismatch for `pmulhrsw' +.*:26: Error: register type mismatch for `pshufb' +.*:27: Error: register type mismatch for `psignb' +.*:28: Error: register type mismatch for `psignw' +.*:29: Error: register type mismatch for `psignd' +.*:30: Error: register type mismatch for `palignr' +.*:31: Error: register type mismatch for `pabsb' +.*:32: Error: register type mismatch for `pabsw' +.*:33: Error: register type mismatch for `pabsd' +.*:34: Error: register type mismatch for `blendpd' +.*:35: Error: register type mismatch for `blendps' +.*:36: Error: register type mismatch for `blendvpd' +.*:37: Error: register type mismatch for `blendvps' +.*:38: Error: register type mismatch for `blendvpd' +.*:39: Error: register type mismatch for `blendvps' +.*:40: Error: register type mismatch for `dppd' +.*:41: Error: register type mismatch for `dpps' +.*:42: Error: register type mismatch for `extractps' +.*:43: Error: register type mismatch for `extractps' +.*:44: Error: register type mismatch for `insertps' +.*:45: Error: register type mismatch for `movntdqa' +.*:46: Error: register type mismatch for `mpsadbw' +.*:47: Error: register type mismatch for `packusdw' +.*:48: Error: register type mismatch for `pblendvb' +.*:49: Error: register type mismatch for `pblendvb' +.*:50: Error: register type mismatch for `pblendw' +.*:51: Error: register type mismatch for `pcmpeqq' +.*:52: Error: register type mismatch for `pextrb' +.*:53: Error: register type mismatch for `pextrw' +.*:54: Error: register type mismatch for `pextrb' +.*:55: Error: register type mismatch for `pextrd' +.*:56: Error: register type mismatch for `pextrd' +.*:57: Error: register type mismatch for `phminposuw' +.*:58: Error: register type mismatch for `pinsrb' +.*:59: Error: register type mismatch for `pinsrb' +.*:60: Error: register type mismatch for `pinsrd' +.*:61: Error: register type mismatch for `pinsrd' +.*:62: Error: register type mismatch for `pinsrq' +.*:63: Error: register type mismatch for `pinsrq' +.*:64: Error: register type mismatch for `pmaxsb' +.*:65: Error: register type mismatch for `pmaxsd' +.*:66: Error: register type mismatch for `pmaxud' +.*:67: Error: register type mismatch for `pmaxuw' +.*:68: Error: register type mismatch for `pminsb' +.*:69: Error: register type mismatch for `pminsd' +.*:70: Error: register type mismatch for `pminud' +.*:71: Error: register type mismatch for `pminuw' +.*:72: Error: register type mismatch for `pmovsxbw' +.*:73: Error: register type mismatch for `pmovsxbd' +.*:74: Error: register type mismatch for `pmovsxbq' +.*:75: Error: register type mismatch for `pmovsxwd' +.*:76: Error: register type mismatch for `pmovsxwq' +.*:77: Error: register type mismatch for `pmovsxdq' +.*:78: Error: register type mismatch for `pmovsxbw' +.*:79: Error: register type mismatch for `pmovzxbd' +.*:80: Error: register type mismatch for `pmovzxbq' +.*:81: Error: register type mismatch for `pmovzxwd' +.*:82: Error: register type mismatch for `pmovzxwq' +.*:83: Error: register type mismatch for `pmovzxdq' +.*:84: Error: register type mismatch for `pmuldq' +.*:85: Error: register type mismatch for `pmulld' +.*:86: Error: register type mismatch for `roundpd' +.*:87: Error: register type mismatch for `roundps' +.*:88: Error: register type mismatch for `roundsd' +.*:89: Error: register type mismatch for `roundss' +.*:90: Error: register type mismatch for `pcmpgtq' +.*:91: Error: register type mismatch for `pcmpestri' +.*:92: Error: register type mismatch for `pcmpestrm' +.*:93: Error: register type mismatch for `pcmpistri' +.*:94: Error: register type mismatch for `pcmpistrm' +.*:96: Error: register type mismatch for `aesdec' +.*:97: Error: register type mismatch for `aesdeclast' +.*:98: Error: register type mismatch for `aesenc' +.*:99: Error: register type mismatch for `aesenclast' +.*:100: Error: register type mismatch for `aesimc' +.*:101: Error: register type mismatch for `aeskeygenassist' +.*:102: Error: register type mismatch for `pclmulqdq' +.*:103: Error: register type mismatch for `pclmullqlqdq' +.*:104: Error: register type mismatch for `pclmulhqlqdq' +.*:105: Error: register type mismatch for `pclmullqhqdq' +.*:106: Error: register type mismatch for `pclmulhqhqdq' +.*:108: Error: register type mismatch for `gf2p8affineqb' +.*:109: Error: register type mismatch for `gf2p8affineinvqb' +.*:110: Error: register type mismatch for `gf2p8mulb' +.*:112: Error: register type mismatch for `vblendpd' +.*:113: Error: register type mismatch for `vblendpd' +.*:114: Error: register type mismatch for `vblendps' +.*:115: Error: register type mismatch for `vblendps' +.*:116: Error: register type mismatch for `vblendvpd' +.*:117: Error: register type mismatch for `vblendvpd' +.*:118: Error: register type mismatch for `vblendvps' +.*:119: Error: register type mismatch for `vblendvps' +.*:120: Error: register type mismatch for `vdppd' +.*:121: Error: register type mismatch for `vdpps' +.*:122: Error: register type mismatch for `vdpps' +.*:123: Error: register type mismatch for `vhaddpd' +.*:124: Error: register type mismatch for `vhaddpd' +.*:125: Error: register type mismatch for `vhsubps' +.*:126: Error: register type mismatch for `vhsubps' +.*:127: Error: register type mismatch for `vlddqu' +.*:128: Error: register type mismatch for `vlddqu' +.*:129: Error: register type mismatch for `vldmxcsr' +.*:130: Error: register type mismatch for `vmaskmovpd' +.*:131: Error: register type mismatch for `vmaskmovpd' +.*:132: Error: register type mismatch for `vmaskmovps' +.*:133: Error: register type mismatch for `vmaskmovps' +.*:134: Error: register type mismatch for `vmaskmovpd' +.*:135: Error: register type mismatch for `vmaskmovpd' +.*:136: Error: register type mismatch for `vmaskmovps' +.*:137: Error: register type mismatch for `vmaskmovps' +.*:138: Error: register type mismatch for `vmovmskpd' +.*:139: Error: register type mismatch for `vmovmskpd' +.*:140: Error: register type mismatch for `vmovmskps' +.*:141: Error: register type mismatch for `vmovmskps' +.*:142: Error: register type mismatch for `vpblendvb' +.*:143: Error: register type mismatch for `vpblendvb' +.*:144: Error: register type mismatch for `vpblendw' +.*:145: Error: register type mismatch for `vpblendw' +.*:146: Error: register type mismatch for `vpcmpestri' +.*:147: Error: register type mismatch for `vpcmpestrm' +.*:148: Error: register type mismatch for `vperm2f128' +.*:149: Error: register type mismatch for `vphaddd' +.*:150: Error: register type mismatch for `vphaddsw' +.*:151: Error: register type mismatch for `vphaddw' +.*:152: Error: register type mismatch for `vphsubd' +.*:153: Error: register type mismatch for `vphsubsw' +.*:154: Error: register type mismatch for `vphsubw' +.*:155: Error: register type mismatch for `vphaddd' +.*:156: Error: register type mismatch for `vphaddsw' +.*:157: Error: register type mismatch for `vphaddw' +.*:158: Error: register type mismatch for `vphsubd' +.*:159: Error: register type mismatch for `vphsubsw' +.*:160: Error: register type mismatch for `vphsubw' +.*:161: Error: register type mismatch for `vphminposuw' +.*:162: Error: register type mismatch for `vpmovmskb' +.*:163: Error: register type mismatch for `vpmovmskb' +.*:164: Error: register type mismatch for `vpsignb' +.*:165: Error: register type mismatch for `vpsignw' +.*:166: Error: register type mismatch for `vpsignd' +.*:167: Error: register type mismatch for `vpsignb' +.*:168: Error: register type mismatch for `vpsignw' +.*:169: Error: register type mismatch for `vpsignd' +.*:170: Error: register type mismatch for `vptest' +.*:171: Error: register type mismatch for `vptest' +.*:172: Error: register type mismatch for `vrcpps' +.*:173: Error: register type mismatch for `vrcpps' +.*:174: Error: register type mismatch for `vrcpss' +.*:175: Error: register type mismatch for `vrsqrtps' +.*:176: Error: register type mismatch for `vrsqrtps' +.*:177: Error: register type mismatch for `vrsqrtss' +.*:178: Error: register type mismatch for `vstmxcsr' +.*:179: Error: register type mismatch for `vtestps' +.*:180: Error: register type mismatch for `vtestps' +.*:181: Error: register type mismatch for `vtestpd' +.*:182: Error: register type mismatch for `vtestps' +.*:183: Error: register type mismatch for `vtestpd' +.*:184: Error: register type mismatch for `vpblendd' +.*:185: Error: register type mismatch for `vpblendd' +.*:186: Error: register type mismatch for `vperm2i128' +.*:187: Error: register type mismatch for `vpmaskmovd' +.*:188: Error: register type mismatch for `vpmaskmovd' +.*:189: Error: register type mismatch for `vpmaskmovq' +.*:190: Error: register type mismatch for `vpmaskmovq' +.*:191: Error: register type mismatch for `vpmaskmovd' +.*:192: Error: register type mismatch for `vpmaskmovd' +.*:193: Error: register type mismatch for `vpmaskmovq' +.*:194: Error: register type mismatch for `vpmaskmovq' +.*:195: Error: register type mismatch for `vaesimc' +.*:196: Error: register type mismatch for `vaeskeygenassist' +.*:197: Error: register type mismatch for `vroundpd' +.*:198: Error: register type mismatch for `vroundps' +.*:199: Error: register type mismatch for `vroundsd' +.*:200: Error: register type mismatch for `vroundss' +.*:201: Error: register type mismatch for `vpcmpistri' +.*:202: Error: register type mismatch for `vpcmpistrm' +.*:203: Error: register type mismatch for `vpcmpeqb' +.*:204: Error: register type mismatch for `vpcmpeqw' +.*:205: Error: register type mismatch for `vpcmpeqd' +.*:206: Error: register type mismatch for `vpcmpeqq' +.*:207: Error: register type mismatch for `vpcmpgtb' +.*:208: Error: register type mismatch for `vpcmpgtw' +.*:209: Error: register type mismatch for `vpcmpgtd' +.*:210: Error: register type mismatch for `vpcmpgtq' GAS LISTING .* #... -[ ]*1[ ]+\# Check Illegal 64bit APX instructions +[ ]*1[ ]+\# Check illegal 64bit APX instructions [ ]*2[ ]+\.text [ ]*3[ ]+\.arch \.noapx_f [ ]*4[ ]+test \$0x7, %r17d diff --git a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s index 5249b888046..cbac896fd28 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s +++ b/gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s @@ -1,4 +1,4 @@ -# Check Illegal 64bit APX instructions +# Check illegal 64bit APX instructions .text .arch .noapx_f test $0x7, %r17d @@ -16,3 +16,195 @@ xsaveopt64 (%r16, %rbx) xsavec (%r16, %rbx) xsavec64 (%r16, %rbx) +#SSE + phaddw (%r17),%xmm0 + phaddd (%r17),%xmm0 + phaddsw (%r17),%xmm0 + phsubw (%r17),%xmm0 + pmaddubsw (%r17),%xmm0 + pmulhrsw (%r17),%xmm0 + pshufb (%r17),%xmm0 + psignb (%r17),%xmm0 + psignw (%r17),%xmm0 + psignd (%r17),%xmm0 + palignr $100,(%r17),%xmm6 + pabsb (%r17),%xmm0 + pabsw (%r17),%xmm0 + pabsd (%r17),%xmm0 + blendpd $100,(%r18),%xmm6 + blendps $100,(%r18),%xmm6 + blendvpd %xmm0,(%r19),%xmm6 + blendvps %xmm0,(%r19),%xmm6 + blendvpd (%r19),%xmm6 + blendvps (%r19),%xmm6 + dppd $100,(%r20),%xmm6 + dpps $100,(%r20),%xmm6 + extractps $100,%xmm4,(%r21) + extractps $100,%xmm4,%r21 + insertps $100,(%r21),%xmm6 + movntdqa (%r21),%xmm4 + mpsadbw $100,(%r21),%xmm6 + packusdw (%r21),%xmm6 + pblendvb %xmm0,(%r22),%xmm6 + pblendvb (%r22),%xmm6 + pblendw $100,(%r22),%xmm6 + pcmpeqq (%r22),%xmm6 + pextrb $100,%xmm4,(%r22) + pextrw $100,%xmm4,(%r22) + pextrb $100,%xmm4,%r22 + pextrd $100,%xmm4,%r22d + pextrd $100,%xmm4,(%r22) + phminposuw (%r23),%xmm4 + pinsrb $100,%r23,%xmm4 + pinsrb $100,(%r23),%xmm4 + pinsrd $100, %r23d, %xmm4 + pinsrd $100,(%r23),%xmm4 + pinsrq $100, %r24, %xmm4 + pinsrq $100,(%r24),%xmm4 + pmaxsb (%r24),%xmm6 + pmaxsd (%r24),%xmm6 + pmaxud (%r24),%xmm6 + pmaxuw (%r24),%xmm6 + pminsb (%r24),%xmm6 + pminsd (%r24),%xmm6 + pminud (%r24),%xmm6 + pminuw (%r24),%xmm6 + pmovsxbw (%r24),%xmm4 + pmovsxbd (%r24),%xmm4 + pmovsxbq (%r24),%xmm4 + pmovsxwd (%r24),%xmm4 + pmovsxwq (%r24),%xmm4 + pmovsxdq (%r24),%xmm4 + pmovsxbw (%r24),%xmm4 + pmovzxbd (%r24),%xmm4 + pmovzxbq (%r24),%xmm4 + pmovzxwd (%r24),%xmm4 + pmovzxwq (%r24),%xmm4 + pmovzxdq (%r24),%xmm4 + pmuldq (%r24),%xmm4 + pmulld (%r24),%xmm4 + roundpd $100,(%r24),%xmm6 + roundps $100,(%r24),%xmm6 + roundsd $100,(%r24),%xmm6 + roundss $100,(%r24),%xmm6 + pcmpgtq (%r25),%xmm4 + pcmpestri $100,(%r25),%xmm6 + pcmpestrm $100,(%r25),%xmm6 + pcmpistri $100,(%r25),%xmm6 + pcmpistrm $100,(%r25),%xmm6 +#AES + aesdec (%r26),%xmm6 + aesdeclast (%r26),%xmm6 + aesenc (%r26),%xmm6 + aesenclast (%r26),%xmm6 + aesimc (%r26),%xmm6 + aeskeygenassist $100,(%r26),%xmm6 + pclmulqdq $100,(%r26),%xmm6 + pclmullqlqdq (%r26),%xmm6 + pclmulhqlqdq (%r26),%xmm6 + pclmullqhqdq (%r26),%xmm6 + pclmulhqhqdq (%r26),%xmm6 +#GFNI + gf2p8affineqb $100,(%r26),%xmm6 + gf2p8affineinvqb $100,(%r26),%xmm6 + gf2p8mulb (%r26),%xmm6 +#VEX without evex + vblendpd $7,(%r27),%xmm6,%xmm2 + vblendpd $7,(%r27),%ymm6,%ymm2 + vblendps $7,(%r27),%xmm6,%xmm2 + vblendps $7,(%r27),%ymm6,%ymm2 + vblendvpd %xmm4,(%r27),%xmm2,%xmm7 + vblendvpd %ymm4,(%r27),%ymm2,%ymm7 + vblendvps %xmm4,(%r27),%xmm2,%xmm7 + vblendvps %ymm4,(%r27),%ymm2,%ymm7 + vdppd $7,(%r27),%xmm6,%xmm2 + vdpps $7,(%r27),%xmm6,%xmm2 + vdpps $7,(%r27),%ymm6,%ymm2 + vhaddpd (%r27),%xmm6,%xmm5 + vhaddpd (%r27),%ymm6,%ymm5 + vhsubps (%r27),%xmm6,%xmm5 + vhsubps (%r27),%ymm6,%ymm5 + vlddqu (%r27),%xmm4 + vlddqu (%r27),%ymm4 + vldmxcsr (%r27) + vmaskmovpd (%r27),%xmm4,%xmm6 + vmaskmovpd %xmm4,%xmm6,(%r27) + vmaskmovps (%r27),%xmm4,%xmm6 + vmaskmovps %xmm4,%xmm6,(%r27) + vmaskmovpd (%r27),%ymm4,%ymm6 + vmaskmovpd %ymm4,%ymm6,(%r27) + vmaskmovps (%r27),%ymm4,%ymm6 + vmaskmovps %ymm4,%ymm6,(%r27) + vmovmskpd %xmm4,%r27d + vmovmskpd %xmm8,%r27d + vmovmskps %xmm4,%r27d + vmovmskps %ymm8,%r27d + vpblendvb %xmm4,(%r27),%xmm2,%xmm7 + vpblendvb %ymm4,(%r27),%ymm2,%ymm7 + vpblendw $7,(%r27),%xmm6,%xmm2 + vpblendw $7,(%r27),%ymm6,%ymm2 + vpcmpestri $7,(%r27),%xmm6 + vpcmpestrm $7,(%r27),%xmm6 + vperm2f128 $7,(%r27),%ymm6,%ymm2 + vphaddd (%r27),%xmm6,%xmm7 + vphaddsw (%r27),%xmm6,%xmm7 + vphaddw (%r27),%xmm6,%xmm7 + vphsubd (%r27),%xmm6,%xmm7 + vphsubsw (%r27),%xmm6,%xmm7 + vphsubw (%r27),%xmm6,%xmm7 + vphaddd (%r27),%ymm6,%ymm7 + vphaddsw (%r27),%ymm6,%ymm7 + vphaddw (%r27),%ymm6,%ymm7 + vphsubd (%r27),%ymm6,%ymm7 + vphsubsw (%r27),%ymm6,%ymm7 + vphsubw (%r27),%ymm6,%ymm7 + vphminposuw (%r27),%xmm6 + vpmovmskb %xmm4,%r27 + vpmovmskb %ymm4,%r27d + vpsignb (%r27),%xmm6,%xmm7 + vpsignw (%r27),%xmm6,%xmm7 + vpsignd (%r27),%xmm6,%xmm7 + vpsignb (%r27),%xmm6,%xmm7 + vpsignw (%r27),%xmm6,%xmm7 + vpsignd (%r27),%xmm6,%xmm7 + vptest (%r27),%xmm6 + vptest (%r27),%ymm6 + vrcpps (%r27),%xmm6 + vrcpps (%r27),%ymm6 + vrcpss (%r27),%xmm6,%xmm6 + vrsqrtps (%r27),%xmm6 + vrsqrtps (%r27),%ymm6 + vrsqrtss (%r27),%xmm6,%xmm6 + vstmxcsr (%r27) + vtestps (%r27),%xmm6 + vtestps (%r27),%ymm6 + vtestpd (%r27),%xmm6 + vtestps (%r27),%ymm6 + vtestpd (%r27),%ymm6 + vpblendd $7,(%r27),%xmm6,%xmm2 + vpblendd $7,(%r27),%ymm6,%ymm2 + vperm2i128 $7,(%r27),%ymm6,%ymm2 + vpmaskmovd (%r27),%xmm4,%xmm6 + vpmaskmovd %xmm4,%xmm6,(%r27) + vpmaskmovq (%r27),%xmm4,%xmm6 + vpmaskmovq %xmm4,%xmm6,(%r27) + vpmaskmovd (%r27),%ymm4,%ymm6 + vpmaskmovd %ymm4,%ymm6,(%r27) + vpmaskmovq (%r27),%ymm4,%ymm6 + vpmaskmovq %ymm4,%ymm6,(%r27) + vaesimc (%r27), %xmm3 + vaeskeygenassist $7,(%r27),%xmm3 + vroundpd $100,(%r24),%xmm6 + vroundps $100,(%r24),%xmm6 + vroundsd $100,(%r24),%xmm6,%xmm3 + vroundss $100,(%r24),%xmm6,%xmm3 + vpcmpistri $100,(%r25),%xmm6 + vpcmpistrm $100,(%r25),%xmm6 + vpcmpeqb (%r26),%ymm6,%ymm2 + vpcmpeqw (%r16),%ymm6,%ymm2 + vpcmpeqd (%r26),%ymm6,%ymm2 + vpcmpeqq (%r16),%ymm6,%ymm2 + vpcmpgtb (%r26),%ymm6,%ymm2 + vpcmpgtw (%r16),%ymm6,%ymm2 + vpcmpgtd (%r26),%ymm6,%ymm2 + vpcmpgtq (%r16),%ymm6,%ymm2 diff --git a/gas/testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l b/gas/testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l new file mode 100644 index 00000000000..07f18c8ba33 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l @@ -0,0 +1,17 @@ +.*: Assembler messages: +.*:5: Error: `movbe' is not supported on `x86_64.nomovbe' +.*:6: Error: `movbe' is not supported on `x86_64.nomovbe' +.*:8: Error: `invept' is not supported on `x86_64.nomovbe.noept' +.*:9: Error: `invept' is not supported on `x86_64.nomovbe.noept' +.*:11: Error: `kmovq' is not supported on `x86_64.nomovbe.noept.noavx512bw' +.*:12: Error: `kmovq' is not supported on `x86_64.nomovbe.noept.noavx512bw' +.*:14: Error: `kmovb' is not supported on `x86_64.nomovbe.noept.noavx512bw.noavx512dq' +.*:15: Error: `kmovb' is not supported on `x86_64.nomovbe.noept.noavx512bw.noavx512dq' +.*:17: Error: `kmovw' is not supported on `x86_64.nomovbe.noept.noavx512bw.noavx512dq.noavx512f' +.*:18: Error: `kmovw' is not supported on `x86_64.nomovbe.noept.noavx512bw.noavx512dq.noavx512f' +GAS LISTING .* +#... +[ ]*1[ ]+\# Check illegal 64bit APX EVEX promoted instructions +[ ]*2[ ]+\.text +[ ]*3[ ]+\.arch \.apx_f +#pass diff --git a/gas/testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s b/gas/testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s new file mode 100644 index 00000000000..23d6fd13475 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s @@ -0,0 +1,18 @@ +# Check illegal 64bit APX EVEX promoted instructions + .text + .arch .apx_f + .arch .nomovbe + movbe (%r16), %r17 + movbe (%rax), %rcx + .arch .noept + invept (%r16), %r17 + invept (%rax), %rcx + .arch .noavx512bw + kmovq %k1, (%r16) + kmovq %k1, (%r8) + .arch .noavx512dq + kmovb %k1, %r16d + kmovb %k1, %r8d + .arch .noavx512f + kmovw %k1, %r16d + kmovw %k1, %r8d diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-egpr.d b/gas/testsuite/gas/i386/x86-64-apx-evex-egpr.d new file mode 100644 index 00000000000..29b685f7bef --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-egpr.d @@ -0,0 +1,22 @@ +#as: +#objdump: -dw +#name: x86-64 APX old evex insn use gpr32 with extend-evex prefix +#source: x86-64-apx-evex-egpr.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 fb 79 48 19 04 08 01 vextractf32x4 \$0x1,%zmm0,\(%r16,%r17,1\) +\s*[a-f0-9]+:\s*62 fa 79 48 5a 04 08 vbroadcasti32x4 \(%r16,%r17,1\),%zmm0 +\s*[a-f0-9]+:\s*62 f9 f9 48 72 04 08 00 vprorq \$0x0,\(%r16,%r17,1\),%zmm0 +\s*[a-f0-9]+:\s*62 f9 f9 48 72 0c 08 00 vprolq \$0x0,\(%r16,%r17,1\),%zmm0 +\s*[a-f0-9]+:\s*62 f9 f9 48 73 14 08 00 vpsrlq \$0x0,\(%r16,%r17,1\),%zmm0 +\s*[a-f0-9]+:\s*62 f9 79 48 73 1c 08 00 vpsrldq \$0x0,\(%r16,%r17,1\),%zmm0 +\s*[a-f0-9]+:\s*62 f9 f9 48 72 24 08 00 vpsraq \$0x0,\(%r16,%r17,1\),%zmm0 +\s*[a-f0-9]+:\s*62 f9 f9 48 73 34 08 00 vpsllq \$0x0,\(%r16,%r17,1\),%zmm0 +\s*[a-f0-9]+:\s*62 f9 79 48 73 3c 08 00 vpslldq \$0x0,\(%r16,%r17,1\),%zmm0 +\s*[a-f0-9]+:\s*62 eb 7d 08 17 c0 01 vextractps \$0x1,%xmm16,%r16d +#pass diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-egpr.s b/gas/testsuite/gas/i386/x86-64-apx-evex-egpr.s new file mode 100644 index 00000000000..29b076821f0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-egpr.s @@ -0,0 +1,25 @@ +# Check 64bit old evex instructions use gpr32 with evex prefix encoding + + .allow_index_reg + .text +_start: +## MRMDestMem + vextractf32x4 $1, %zmm0, (%r16,%r17) +## MRMSrcMem + vbroadcasti32x4 (%r16,%r17), %zmm0 +## MRM0m + vprorq $0, (%r16,%r17), %zmm0 +## MRM1m + vprolq $0, (%r16,%r17), %zmm0 +## MRM2m + vpsrlq $0, (%r16,%r17), %zmm0 +## MRM3m + vpsrldq $0, (%r16,%r17), %zmm0 +## MRM4m + vpsraq $0, (%r16,%r17), %zmm0 +## MRM6m + vpsllq $0, (%r16,%r17), %zmm0 +## MRM7m + vpslldq $0, (%r16,%r17), %zmm0 +## MRMDestReg + vextractps $1, %xmm16, %r16d diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d new file mode 100644 index 00000000000..3528943a10c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d @@ -0,0 +1,740 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 APX_F EVEX-Promoted insns (Intel disassembly) +#source: x86-64-apx-evex-promoted.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 4c 7c 08 fc 8c 87 23 01 00 00\s+aadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*62 4c fc 08 fc bc 87 23 01 00 00\s+aadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*62 4c 7d 08 fc 8c 87 23 01 00 00\s+aand\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*62 4c fd 08 fc bc 87 23 01 00 00\s+aand\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*d5 10 80 d0 7b\s+adc\s+r16b,0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 d2 7b\s+adc\s+r18w,0x7b +\s*[a-f0-9]+:\s*d5 11 83 d1 7b\s+adc\s+r25d,0x7b +\s*[a-f0-9]+:\s*d5 19 83 d7 7b\s+adc\s+r31,0x7b +\s*[a-f0-9]+:\s*d5 10 80 94 80 23 01 00 00 7b\s+adc\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 94 80 23 01 00 00 7b\s+adc\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 83 94 80 23 01 00 00 7b\s+adc\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 18 83 94 80 23 01 00 00 7b\s+adc\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 11 83 94 87 23 01 00 00 7b\s+adc\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 11 83 94 87 23 01 00 00 7b\s+adc\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 19 83 94 87 23 01 00 00 7b\s+adc\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 40 10 c2\s+adc\s+dl,r16b +\s*[a-f0-9]+:\s*d5 51 10 84 87 23 01 00 00\s+adc\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\],r16b +\s*[a-f0-9]+:\s*66 d5 40 11 d0\s+adc\s+ax,r18w +\s*[a-f0-9]+:\s*66 d5 50 11 94 80 23 01 00 00\s+adc\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*66 d5 51 11 94 87 23 01 00 00\s+adc\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*d5 44 11 ca\s+adc\s+edx,r25d +\s*[a-f0-9]+:\s*d5 55 11 8c 87 23 01 00 00\s+adc\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*d5 4d 11 ff\s+adc\s+r15,r31 +\s*[a-f0-9]+:\s*d5 5d 11 bc 87 23 01 00 00\s+adc\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*d5 50 12 84 80 23 01 00 00\s+adc\s+r16b,BYTE PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5c 13 bc 80 23 01 00 00\s+adc\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 51 13 94 87 23 01 00 00\s+adc\s+r18w,WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 55 13 8c 87 23 01 00 00\s+adc\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5d 13 bc 87 23 01 00 00\s+adc\s+r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 dc 7d 08 66 d1\s+adcx\s+edx,r25d +\s*[a-f0-9]+:\s*62 5c fd 08 66 ff\s+adcx\s+r15,r31 +\s*[a-f0-9]+:\s*62 6c fd 08 66 bc 80 23 01 00 00\s+adcx\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 4c 7d 08 66 8c 87 23 01 00 00\s+adcx\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 80 c0 7b\s+add\s+r16b,0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 c2 7b\s+add\s+r18w,0x7b +\s*[a-f0-9]+:\s*d5 11 83 c1 7b\s+add\s+r25d,0x7b +\s*[a-f0-9]+:\s*d5 19 83 c7 7b\s+add\s+r31,0x7b +\s*[a-f0-9]+:\s*d5 10 80 84 80 23 01 00 00 7b\s+add\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 84 80 23 01 00 00 7b\s+add\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 83 84 80 23 01 00 00 7b\s+add\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 18 83 84 80 23 01 00 00 7b\s+add\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 11 83 84 87 23 01 00 00 7b\s+add\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 11 83 84 87 23 01 00 00 7b\s+add\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 19 83 84 87 23 01 00 00 7b\s+add\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 40 00 c2\s+add\s+dl,r16b +\s*[a-f0-9]+:\s*d5 51 00 84 87 23 01 00 00\s+add\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\],r16b +\s*[a-f0-9]+:\s*66 d5 40 01 d0\s+add\s+ax,r18w +\s*[a-f0-9]+:\s*66 d5 50 01 94 80 23 01 00 00\s+add\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*66 d5 51 01 94 87 23 01 00 00\s+add\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*d5 44 01 ca\s+add\s+edx,r25d +\s*[a-f0-9]+:\s*d5 55 01 8c 87 23 01 00 00\s+add\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*d5 4d 01 ff\s+add\s+r15,r31 +\s*[a-f0-9]+:\s*d5 5d 01 bc 87 23 01 00 00\s+add\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*d5 50 02 84 80 23 01 00 00\s+add\s+r16b,BYTE PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5c 03 bc 80 23 01 00 00\s+add\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 51 03 94 87 23 01 00 00\s+add\s+r18w,WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 55 03 8c 87 23 01 00 00\s+add\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5d 03 bc 87 23 01 00 00\s+add\s+r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 dc 7e 08 66 d1\s+adox\s+edx,r25d +\s*[a-f0-9]+:\s*62 5c fe 08 66 ff\s+adox\s+r15,r31 +\s*[a-f0-9]+:\s*62 6c fe 08 66 bc 80 23 01 00 00\s+adox\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 4c 7e 08 66 8c 87 23 01 00 00\s+adox\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 cc 7e 08 dd b4 87 23 01 00 00\s+aesdec128kl xmm22,\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 cc 7e 08 df b4 87 23 01 00 00\s+aesdec256kl xmm22,\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 dc 7e 08 d8 8c 87 23 01 00 00\s+aesdecwide128kl\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 dc 7e 08 d8 9c 87 23 01 00 00\s+aesdecwide256kl\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 cc 7e 08 dc b4 87 23 01 00 00\s+aesenc128kl xmm22,\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 cc 7e 08 de b4 87 23 01 00 00\s+aesenc256kl xmm22,\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 dc 7e 08 d8 84 87 23 01 00 00\s+aesencwide128kl\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 dc 7e 08 d8 94 87 23 01 00 00\s+aesencwide256kl\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 80 e0 7b\s+and\s+r16b,0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 e2 7b\s+and\s+r18w,0x7b +\s*[a-f0-9]+:\s*d5 11 83 e1 7b\s+and\s+r25d,0x7b +\s*[a-f0-9]+:\s*d5 19 83 e7 7b\s+and\s+r31,0x7b +\s*[a-f0-9]+:\s*d5 10 80 a4 80 23 01 00 00 7b\s+and\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 a4 80 23 01 00 00 7b\s+and\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 83 a4 80 23 01 00 00 7b\s+and\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 18 83 a4 80 23 01 00 00 7b\s+and\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 11 83 a4 87 23 01 00 00 7b\s+and\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 11 83 a4 87 23 01 00 00 7b\s+and\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 19 83 a4 87 23 01 00 00 7b\s+and\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 40 20 c2\s+and\s+dl,r16b +\s*[a-f0-9]+:\s*d5 51 20 84 87 23 01 00 00\s+and\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\],r16b +\s*[a-f0-9]+:\s*66 d5 40 21 d0\s+and\s+ax,r18w +\s*[a-f0-9]+:\s*66 d5 50 21 94 80 23 01 00 00\s+and\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*66 d5 51 21 94 87 23 01 00 00\s+and\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*d5 44 21 ca\s+and\s+edx,r25d +\s*[a-f0-9]+:\s*d5 55 21 8c 87 23 01 00 00\s+and\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*d5 4d 21 ff\s+and\s+r15,r31 +\s*[a-f0-9]+:\s*d5 5d 21 bc 87 23 01 00 00\s+and\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*d5 50 22 84 80 23 01 00 00\s+and\s+r16b,BYTE PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5c 23 bc 80 23 01 00 00\s+and\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 51 23 94 87 23 01 00 00\s+and\s+r18w,WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 55 23 8c 87 23 01 00 00\s+and\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5d 23 bc 87 23 01 00 00\s+and\s+r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 5a 6c 08 f2 d1\s+andn\s+r10d,edx,r25d +\s*[a-f0-9]+:\s*62 5a 84 08 f2 df\s+andn\s+r11,r15,r31 +\s*[a-f0-9]+:\s*62 da 34 00 f2 94 87 23 01 00 00\s+andn\s+edx,r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 5a 84 00 f2 bc 87 23 01 00 00\s+andn\s+r15,r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 4c 7f 08 fc 8c 87 23 01 00 00\s+aor\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*62 4c ff 08 fc bc 87 23 01 00 00\s+aor\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*62 4c 7e 08 fc 8c 87 23 01 00 00\s+axor\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*62 4c fe 08 fc bc 87 23 01 00 00\s+axor\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*62 72 34 00 f7 d2\s+bextr\s+r10d,edx,r25d +\s*[a-f0-9]+:\s*62 da 34 00 f7 94 87 23 01 00 00\s+bextr\s+edx,DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*62 52 84 00 f7 df\s+bextr\s+r11,r15,r31 +\s*[a-f0-9]+:\s*62 5a 84 00 f7 bc 87 23 01 00 00\s+bextr\s+r15,QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*62 da 6c 08 f3 d9\s+blsi\s+edx,r25d +\s*[a-f0-9]+:\s*62 da 84 08 f3 df\s+blsi\s+r15,r31 +\s*[a-f0-9]+:\s*62 da 34 00 f3 9c 87 23 01 00 00\s+blsi\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 da 84 00 f3 9c 87 23 01 00 00\s+blsi\s+r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 da 6c 08 f3 d1\s+blsmsk\s+edx,r25d +\s*[a-f0-9]+:\s*62 da 84 08 f3 d7\s+blsmsk\s+r15,r31 +\s*[a-f0-9]+:\s*62 da 34 00 f3 94 87 23 01 00 00\s+blsmsk\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 da 84 00 f3 94 87 23 01 00 00\s+blsmsk\s+r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 da 6c 08 f3 c9\s+blsr\s+edx,r25d +\s*[a-f0-9]+:\s*62 da 84 08 f3 cf\s+blsr\s+r15,r31 +\s*[a-f0-9]+:\s*62 da 34 00 f3 8c 87 23 01 00 00\s+blsr\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 da 84 00 f3 8c 87 23 01 00 00\s+blsr\s+r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 72 34 00 f5 d2\s+bzhi\s+r10d,edx,r25d +\s*[a-f0-9]+:\s*62 da 34 00 f5 94 87 23 01 00 00\s+bzhi\s+edx,DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*62 52 84 00 f5 df\s+bzhi\s+r11,r15,r31 +\s*[a-f0-9]+:\s*62 5a 84 00 f5 bc 87 23 01 00 00\s+bzhi\s+r15,QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*62 da 35 00 e6 94 87 23 01 00 00\s+cmpbexadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 e6 bc 87 23 01 00 00\s+cmpbexadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 e2 94 87 23 01 00 00\s+cmpbxadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 e2 bc 87 23 01 00 00\s+cmpbxadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 ec 94 87 23 01 00 00\s+cmplxadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 ec bc 87 23 01 00 00\s+cmplxadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 e7 94 87 23 01 00 00\s+cmpnbexadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 e7 bc 87 23 01 00 00\s+cmpnbexadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 e3 94 87 23 01 00 00\s+cmpnbxadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 e3 bc 87 23 01 00 00\s+cmpnbxadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 ef 94 87 23 01 00 00\s+cmpnlexadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 ef bc 87 23 01 00 00\s+cmpnlexadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 ed 94 87 23 01 00 00\s+cmpnlxadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 ed bc 87 23 01 00 00\s+cmpnlxadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 e1 94 87 23 01 00 00\s+cmpnoxadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 e1 bc 87 23 01 00 00\s+cmpnoxadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 eb 94 87 23 01 00 00\s+cmpnpxadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 eb bc 87 23 01 00 00\s+cmpnpxadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 e9 94 87 23 01 00 00\s+cmpnsxadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 e9 bc 87 23 01 00 00\s+cmpnsxadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 e5 94 87 23 01 00 00\s+cmpnzxadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 e5 bc 87 23 01 00 00\s+cmpnzxadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 e0 94 87 23 01 00 00\s+cmpoxadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 e0 bc 87 23 01 00 00\s+cmpoxadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 ea 94 87 23 01 00 00\s+cmppxadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 ea bc 87 23 01 00 00\s+cmppxadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 e8 94 87 23 01 00 00\s+cmpsxadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 e8 bc 87 23 01 00 00\s+cmpsxadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*62 da 35 00 e4 94 87 23 01 00 00\s+cmpzxadd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],edx,r25d +\s*[a-f0-9]+:\s*62 5a 85 00 e4 bc 87 23 01 00 00\s+cmpzxadd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r15,r31 +\s*[a-f0-9]+:\s*d5 10 fe c8\s+dec\s+r16b +\s*[a-f0-9]+:\s*66 d5 10 ff ca\s+dec\s+r18w +\s*[a-f0-9]+:\s*d5 11 ff c9\s+dec\s+r25d +\s*[a-f0-9]+:\s*d5 19 ff cf\s+dec\s+r31 +\s*[a-f0-9]+:\s*66 d5 10 ff 8c 80 23 01 00 00\s+dec\s+WORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 ff 8c 80 23 01 00 00\s+dec\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 18 ff 8c 80 23 01 00 00\s+dec\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 fe 8c 87 23 01 00 00\s+dec\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 11 ff 8c 87 23 01 00 00\s+dec\s+WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 ff 8c 87 23 01 00 00\s+dec\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 19 ff 8c 87 23 01 00 00\s+dec\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 f6 f0\s+div\s+r16b +\s*[a-f0-9]+:\s*66 d5 10 f7 f2\s+div\s+r18w +\s*[a-f0-9]+:\s*d5 11 f7 f1\s+div\s+r25d +\s*[a-f0-9]+:\s*d5 19 f7 f7\s+div\s+r31 +\s*[a-f0-9]+:\s*66 d5 10 f7 b4 80 23 01 00 00\s+div\s+WORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 f7 b4 80 23 01 00 00\s+div\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 18 f7 b4 80 23 01 00 00\s+div\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 f6 b4 87 23 01 00 00\s+div\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 11 f7 b4 87 23 01 00 00\s+div\s+WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 f7 b4 87 23 01 00 00\s+div\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 19 f7 b4 87 23 01 00 00\s+div\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 dc 7e 08 da d1\s+encodekey128\s+edx,r25d +\s*[a-f0-9]+:\s*62 dc 7e 08 db d1\s+encodekey256\s+edx,r25d +\s*[a-f0-9]+:\s*67 62 4c 7f 08 f8 8c 87 23 01 00 00\s+enqcmd\s+r25d,\[r31d\+eax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 4c 7f 08 f8 bc 87 23 01 00 00\s+enqcmd\s+r31,\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*67 62 4c 7e 08 f8 8c 87 23 01 00 00\s+enqcmds\s+r25d,\[r31d\+eax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 4c 7e 08 f8 bc 87 23 01 00 00\s+enqcmds\s+r31,\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 f6 f8\s+idiv\s+r16b +\s*[a-f0-9]+:\s*66 d5 10 f7 fa\s+idiv\s+r18w +\s*[a-f0-9]+:\s*d5 11 f7 f9\s+idiv\s+r25d +\s*[a-f0-9]+:\s*d5 19 f7 ff\s+idiv\s+r31 +\s*[a-f0-9]+:\s*66 d5 10 f7 bc 80 23 01 00 00\s+idiv\s+WORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 f7 bc 80 23 01 00 00\s+idiv\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 18 f7 bc 80 23 01 00 00\s+idiv\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 f6 bc 87 23 01 00 00\s+idiv\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 11 f7 bc 87 23 01 00 00\s+idiv\s+WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 f7 bc 87 23 01 00 00\s+idiv\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 19 f7 bc 87 23 01 00 00\s+idiv\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 10 6b c2 7b\s+imul\s+ax,r18w,0x7b +\s*[a-f0-9]+:\s*d5 11 6b d1 7b\s+imul\s+edx,r25d,0x7b +\s*[a-f0-9]+:\s*d5 1d 6b ff 7b\s+imul\s+r15,r31,0x7b +\s*[a-f0-9]+:\s*d5 54 6b 8c 80 23 01 00 00 7b\s+imul\s+r25d,DWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 5c 6b bc 80 23 01 00 00 7b\s+imul\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 51 6b 94 87 23 01 00 00 7b\s+imul\s+r18w,WORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 55 6b 8c 87 23 01 00 00 7b\s+imul\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 5d 6b bc 87 23 01 00 00 7b\s+imul\s+r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 f6 e8\s+imul\s+r16b +\s*[a-f0-9]+:\s*66 d5 10 f7 ea\s+imul\s+r18w +\s*[a-f0-9]+:\s*66 d5 90 af c2\s+imul\s+ax,r18w +\s*[a-f0-9]+:\s*d5 11 f7 e9\s+imul\s+r25d +\s*[a-f0-9]+:\s*d5 91 af d1\s+imul\s+edx,r25d +\s*[a-f0-9]+:\s*d5 19 f7 ef\s+imul\s+r31 +\s*[a-f0-9]+:\s*d5 9d af ff\s+imul\s+r15,r31 +\s*[a-f0-9]+:\s*d5 10 f6 ac 80 23 01 00 00\s+imul\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 10 f7 ac 80 23 01 00 00\s+imul\s+WORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 f7 ac 80 23 01 00 00\s+imul\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 d0 af 94 80 23 01 00 00\s+imul\s+r18w,WORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 d4 af 8c 80 23 01 00 00\s+imul\s+r25d,DWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 dc af bc 80 23 01 00 00\s+imul\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 18 f7 ac 80 23 01 00 00\s+imul\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 11 f7 ac 87 23 01 00 00\s+imul\s+WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 f7 ac 87 23 01 00 00\s+imul\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 19 f7 ac 87 23 01 00 00\s+imul\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 fe c0\s+inc\s+r16b +\s*[a-f0-9]+:\s*66 d5 10 ff c2\s+inc\s+r18w +\s*[a-f0-9]+:\s*d5 11 ff c1\s+inc\s+r25d +\s*[a-f0-9]+:\s*d5 19 ff c7\s+inc\s+r31 +\s*[a-f0-9]+:\s*66 d5 10 ff 84 80 23 01 00 00\s+inc\s+WORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 ff 84 80 23 01 00 00\s+inc\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 18 ff 84 80 23 01 00 00\s+inc\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 fe 84 87 23 01 00 00\s+inc\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 11 ff 84 87 23 01 00 00\s+inc\s+WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 ff 84 87 23 01 00 00\s+inc\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 19 ff 84 87 23 01 00 00\s+inc\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 4c 7e 08 f0 bc 87 23 01 00 00\s+invept\s+r31,OWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 4c 7e 08 f2 bc 87 23 01 00 00\s+invpcid\s+r31,\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 4c 7e 08 f1 bc 87 23 01 00 00\s+invvpid\s+r31,OWORD PTR \[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*c5 f9 90 eb\s+kmovb\s+k5,k3 +\s*[a-f0-9]+:\s*62 61 7d 08 93 cd\s+kmovb\s+r25d,k5 +\s*[a-f0-9]+:\s*62 d9 7d 08 91 ac 87 23 01 00 00\s+kmovb\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\],k5 +\s*[a-f0-9]+:\s*62 d9 7d 08 92 e9\s+kmovb\s+k5,r25d +\s*[a-f0-9]+:\s*62 d9 7d 08 90 ac 87 23 01 00 00\s+kmovb\s+k5,BYTE PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*c4 e1 f9 90 eb\s+kmovd\s+k5,k3 +\s*[a-f0-9]+:\s*62 61 7f 08 93 cd\s+kmovd\s+r25d,k5 +\s*[a-f0-9]+:\s*62 d9 fd 08 91 ac 87 23 01 00 00\s+kmovd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],k5 +\s*[a-f0-9]+:\s*62 d9 7f 08 92 e9\s+kmovd\s+k5,r25d +\s*[a-f0-9]+:\s*62 d9 fd 08 90 ac 87 23 01 00 00\s+kmovd\s+k5,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*c4 e1 f8 90 eb\s+kmovq\s+k5,k3 +\s*[a-f0-9]+:\s*62 61 ff 08 93 fd\s+kmovq\s+r31,k5 +\s*[a-f0-9]+:\s*62 d9 fc 08 91 ac 87 23 01 00 00\s+kmovq\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],k5 +\s*[a-f0-9]+:\s*62 d9 ff 08 92 ef\s+kmovq\s+k5,r31 +\s*[a-f0-9]+:\s*62 d9 fc 08 90 ac 87 23 01 00 00\s+kmovq\s+k5,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*c5 f8 90 eb\s+kmovw\s+k5,k3 +\s*[a-f0-9]+:\s*62 61 7c 08 93 cd\s+kmovw\s+r25d,k5 +\s*[a-f0-9]+:\s*62 d9 7c 08 91 ac 87 23 01 00 00\s+kmovw\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],k5 +\s*[a-f0-9]+:\s*62 d9 7c 08 92 e9\s+kmovw\s+k5,r25d +\s*[a-f0-9]+:\s*62 d9 7c 08 90 ac 87 23 01 00 00\s+kmovw\s+k5,WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 da 7c 08 49 84 87 23 01 00 00\s+ldtilecfg\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 f3 d5 90 bd c2\s+lzcnt\s+ax,r18w +\s*[a-f0-9]+:\s*f3 d5 91 bd d1\s+lzcnt\s+edx,r25d +\s*[a-f0-9]+:\s*f3 d5 9d bd ff\s+lzcnt\s+r15,r31 +\s*[a-f0-9]+:\s*66 f3 d5 d0 bd 94 80 23 01 00 00\s+lzcnt\s+r18w,WORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*f3 d5 dc bd bc 80 23 01 00 00\s+lzcnt\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 f3 d5 d1 bd 94 87 23 01 00 00\s+lzcnt\s+r18w,WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*f3 d5 d5 bd 8c 87 23 01 00 00\s+lzcnt\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 fc 7d 08 60 c2\s+movbe\s+ax,r18w +\s*[a-f0-9]+:\s*62 ec 7d 08 61 94 80 23 01 00 00\s+movbe\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*62 cc 7d 08 61 94 87 23 01 00 00\s+movbe\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*62 dc 7c 08 60 d1\s+movbe\s+edx,r25d +\s*[a-f0-9]+:\s*62 6c 7c 08 61 8c 80 23 01 00 00\s+movbe\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*62 5c fc 08 60 ff\s+movbe\s+r15,r31 +\s*[a-f0-9]+:\s*62 6c fc 08 61 bc 80 23 01 00 00\s+movbe\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*62 4c fc 08 61 bc 87 23 01 00 00\s+movbe\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*62 6c fc 08 60 bc 80 23 01 00 00\s+movbe\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 cc 7d 08 60 94 87 23 01 00 00\s+movbe\s+r18w,WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 4c 7c 08 60 8c 87 23 01 00 00\s+movbe\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*67 62 4c 7d 08 f8 8c 87 23 01 00 00\s+movdir64b\s+r25d,\[r31d\+eax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 4c 7d 08 f8 bc 87 23 01 00 00\s+movdir64b\s+r31,\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 4c 7c 08 f9 8c 87 23 01 00 00\s+movdiri\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*62 4c fc 08 f9 bc 87 23 01 00 00\s+movdiri\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*d5 10 f6 e0\s+mul\s+r16b +\s*[a-f0-9]+:\s*66 d5 10 f7 e2\s+mul\s+r18w +\s*[a-f0-9]+:\s*d5 11 f7 e1\s+mul\s+r25d +\s*[a-f0-9]+:\s*d5 19 f7 e7\s+mul\s+r31 +\s*[a-f0-9]+:\s*66 d5 10 f7 a4 80 23 01 00 00\s+mul\s+WORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 f7 a4 80 23 01 00 00\s+mul\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 18 f7 a4 80 23 01 00 00\s+mul\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 f6 a4 87 23 01 00 00\s+mul\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 11 f7 a4 87 23 01 00 00\s+mul\s+WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 f7 a4 87 23 01 00 00\s+mul\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 19 f7 a4 87 23 01 00 00\s+mul\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 5a 6f 08 f6 d1\s+mulx\s+r10d,edx,r25d +\s*[a-f0-9]+:\s*62 5a 87 08 f6 df\s+mulx\s+r11,r15,r31 +\s*[a-f0-9]+:\s*62 da 37 00 f6 94 87 23 01 00 00\s+mulx\s+edx,r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 5a 87 00 f6 bc 87 23 01 00 00\s+mulx\s+r15,r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 f6 d8\s+neg\s+r16b +\s*[a-f0-9]+:\s*66 d5 10 f7 da\s+neg\s+r18w +\s*[a-f0-9]+:\s*d5 11 f7 d9\s+neg\s+r25d +\s*[a-f0-9]+:\s*d5 19 f7 df\s+neg\s+r31 +\s*[a-f0-9]+:\s*66 d5 10 f7 9c 80 23 01 00 00\s+neg\s+WORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 f7 9c 80 23 01 00 00\s+neg\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 18 f7 9c 80 23 01 00 00\s+neg\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 f6 9c 87 23 01 00 00\s+neg\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 11 f7 9c 87 23 01 00 00\s+neg\s+WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 f7 9c 87 23 01 00 00\s+neg\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 19 f7 9c 87 23 01 00 00\s+neg\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 f6 d0\s+not\s+r16b +\s*[a-f0-9]+:\s*66 d5 10 f7 d2\s+not\s+r18w +\s*[a-f0-9]+:\s*d5 11 f7 d1\s+not\s+r25d +\s*[a-f0-9]+:\s*d5 19 f7 d7\s+not\s+r31 +\s*[a-f0-9]+:\s*66 d5 10 f7 94 80 23 01 00 00\s+not\s+WORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 f7 94 80 23 01 00 00\s+not\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 18 f7 94 80 23 01 00 00\s+not\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 f6 94 87 23 01 00 00\s+not\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 11 f7 94 87 23 01 00 00\s+not\s+WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 11 f7 94 87 23 01 00 00\s+not\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 19 f7 94 87 23 01 00 00\s+not\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 80 c8 7b\s+or\s+r16b,0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 ca 7b\s+or\s+r18w,0x7b +\s*[a-f0-9]+:\s*d5 11 83 c9 7b\s+or\s+r25d,0x7b +\s*[a-f0-9]+:\s*d5 19 83 cf 7b\s+or\s+r31,0x7b +\s*[a-f0-9]+:\s*d5 10 80 8c 80 23 01 00 00 7b\s+or\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 8c 80 23 01 00 00 7b\s+or\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 83 8c 80 23 01 00 00 7b\s+or\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 18 83 8c 80 23 01 00 00 7b\s+or\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 11 83 8c 87 23 01 00 00 7b\s+or\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 11 83 8c 87 23 01 00 00 7b\s+or\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 19 83 8c 87 23 01 00 00 7b\s+or\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 40 08 c2\s+or\s+dl,r16b +\s*[a-f0-9]+:\s*d5 51 08 84 87 23 01 00 00\s+or\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\],r16b +\s*[a-f0-9]+:\s*66 d5 40 09 d0\s+or\s+ax,r18w +\s*[a-f0-9]+:\s*66 d5 50 09 94 80 23 01 00 00\s+or\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*66 d5 51 09 94 87 23 01 00 00\s+or\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*d5 44 09 ca\s+or\s+edx,r25d +\s*[a-f0-9]+:\s*d5 55 09 8c 87 23 01 00 00\s+or\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*d5 4d 09 ff\s+or\s+r15,r31 +\s*[a-f0-9]+:\s*d5 5d 09 bc 87 23 01 00 00\s+or\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*d5 50 0a 84 80 23 01 00 00\s+or\s+r16b,BYTE PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5c 0b bc 80 23 01 00 00\s+or\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 51 0b 94 87 23 01 00 00\s+or\s+r18w,WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 55 0b 8c 87 23 01 00 00\s+or\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5d 0b bc 87 23 01 00 00\s+or\s+r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 5a 6f 08 f5 d1\s+pdep\s+r10d,edx,r25d +\s*[a-f0-9]+:\s*62 5a 87 08 f5 df\s+pdep\s+r11,r15,r31 +\s*[a-f0-9]+:\s*62 da 37 00 f5 94 87 23 01 00 00\s+pdep\s+edx,r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 5a 87 00 f5 bc 87 23 01 00 00\s+pdep\s+r15,r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 5a 6e 08 f5 d1\s+pext\s+r10d,edx,r25d +\s*[a-f0-9]+:\s*62 5a 86 08 f5 df\s+pext\s+r11,r15,r31 +\s*[a-f0-9]+:\s*62 da 36 00 f5 94 87 23 01 00 00\s+pext\s+edx,r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 5a 86 00 f5 bc 87 23 01 00 00\s+pext\s+r15,r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 f3 d5 90 b8 c2\s+popcnt\s+ax,r18w +\s*[a-f0-9]+:\s*f3 d5 91 b8 d1\s+popcnt\s+edx,r25d +\s*[a-f0-9]+:\s*f3 d5 9d b8 ff\s+popcnt\s+r15,r31 +\s*[a-f0-9]+:\s*66 f3 d5 d0 b8 94 80 23 01 00 00\s+popcnt\s+r18w,WORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*f3 d5 dc b8 bc 80 23 01 00 00\s+popcnt\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 f3 d5 d1 b8 94 87 23 01 00 00\s+popcnt\s+r18w,WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*f3 d5 d5 b8 8c 87 23 01 00 00\s+popcnt\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 c0 d0 7b\s+rcl\s+r16b,0x7b +\s*[a-f0-9]+:\s*66 d5 10 c1 d2 7b\s+rcl\s+r18w,0x7b +\s*[a-f0-9]+:\s*d5 11 c1 d1 7b\s+rcl\s+r25d,0x7b +\s*[a-f0-9]+:\s*d5 19 c1 d7 7b\s+rcl\s+r31,0x7b +\s*[a-f0-9]+:\s*d5 10 c0 94 80 23 01 00 00 7b\s+rcl\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 10 c1 94 80 23 01 00 00 7b\s+rcl\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 c1 94 80 23 01 00 00 7b\s+rcl\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 18 c1 94 80 23 01 00 00 7b\s+rcl\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 11 c1 94 87 23 01 00 00 7b\s+rcl\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 11 c1 94 87 23 01 00 00 7b\s+rcl\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 19 c1 94 87 23 01 00 00 7b\s+rcl\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 d0 d0\s+rcl\s+r16b,1 +\s*[a-f0-9]+:\s*66 d5 10 d1 d2\s+rcl\s+r18w,1 +\s*[a-f0-9]+:\s*d5 11 d1 d1\s+rcl\s+r25d,1 +\s*[a-f0-9]+:\s*d5 19 d1 d7\s+rcl\s+r31,1 +\s*[a-f0-9]+:\s*d5 10 d0 94 80 23 01 00 00\s+rcl\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*66 d5 10 d1 94 80 23 01 00 00\s+rcl\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 10 d1 94 80 23 01 00 00\s+rcl\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 18 d1 94 80 23 01 00 00\s+rcl\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*66 d5 11 d1 94 87 23 01 00 00\s+rcl\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 11 d1 94 87 23 01 00 00\s+rcl\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 19 d1 94 87 23 01 00 00\s+rcl\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 10 d2 d0\s+rcl\s+r16b,cl +\s*[a-f0-9]+:\s*66 d5 10 d3 d2\s+rcl\s+r18w,cl +\s*[a-f0-9]+:\s*d5 11 d3 d1\s+rcl\s+r25d,cl +\s*[a-f0-9]+:\s*d5 19 d3 d7\s+rcl\s+r31,cl +\s*[a-f0-9]+:\s*d5 10 d2 94 80 23 01 00 00\s+rcl\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*66 d5 10 d3 94 80 23 01 00 00\s+rcl\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 10 d3 94 80 23 01 00 00\s+rcl\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 18 d3 94 80 23 01 00 00\s+rcl\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*66 d5 11 d3 94 87 23 01 00 00\s+rcl\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 11 d3 94 87 23 01 00 00\s+rcl\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 19 d3 94 87 23 01 00 00\s+rcl\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 10 c0 d8 7b\s+rcr\s+r16b,0x7b +\s*[a-f0-9]+:\s*66 d5 10 c1 da 7b\s+rcr\s+r18w,0x7b +\s*[a-f0-9]+:\s*d5 11 c1 d9 7b\s+rcr\s+r25d,0x7b +\s*[a-f0-9]+:\s*d5 19 c1 df 7b\s+rcr\s+r31,0x7b +\s*[a-f0-9]+:\s*d5 10 c0 9c 80 23 01 00 00 7b\s+rcr\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 10 c1 9c 80 23 01 00 00 7b\s+rcr\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 c1 9c 80 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23 01 00 00\s+sarx\s+edx,DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*62 52 86 00 f7 df\s+sarx\s+r11,r15,r31 +\s*[a-f0-9]+:\s*62 5a 86 00 f7 bc 87 23 01 00 00\s+sarx\s+r15,QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*d5 10 80 d8 7b\s+sbb\s+r16b,0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 da 7b\s+sbb\s+r18w,0x7b +\s*[a-f0-9]+:\s*d5 11 83 d9 7b\s+sbb\s+r25d,0x7b +\s*[a-f0-9]+:\s*d5 19 83 df 7b\s+sbb\s+r31,0x7b +\s*[a-f0-9]+:\s*d5 10 80 9c 80 23 01 00 00 7b\s+sbb\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 9c 80 23 01 00 00 7b\s+sbb\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 83 9c 80 23 01 00 00 7b\s+sbb\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 18 83 9c 80 23 01 00 00 7b\s+sbb\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 11 83 9c 87 23 01 00 00 7b\s+sbb\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 11 83 9c 87 23 01 00 00 7b\s+sbb\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 19 83 9c 87 23 01 00 00 7b\s+sbb\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 40 18 c2\s+sbb\s+dl,r16b +\s*[a-f0-9]+:\s*d5 51 18 84 87 23 01 00 00\s+sbb\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\],r16b +\s*[a-f0-9]+:\s*66 d5 40 19 d0\s+sbb\s+ax,r18w +\s*[a-f0-9]+:\s*66 d5 50 19 94 80 23 01 00 00\s+sbb\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*66 d5 51 19 94 87 23 01 00 00\s+sbb\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*d5 44 19 ca\s+sbb\s+edx,r25d +\s*[a-f0-9]+:\s*d5 55 19 8c 87 23 01 00 00\s+sbb\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*d5 4d 19 ff\s+sbb\s+r15,r31 +\s*[a-f0-9]+:\s*d5 5d 19 bc 87 23 01 00 00\s+sbb\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*d5 50 1a 84 80 23 01 00 00\s+sbb\s+r16b,BYTE PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5c 1b bc 80 23 01 00 00\s+sbb\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 51 1b 94 87 23 01 00 00\s+sbb\s+r18w,WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 55 1b 8c 87 23 01 00 00\s+sbb\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5d 1b bc 87 23 01 00 00\s+sbb\s+r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 a4 7c 08 d9 f7\s+sha1msg1 xmm22,xmm23 +\s*[a-f0-9]+:\s*62 cc 7c 08 d9 b4 87 23 01 00 00\s+sha1msg1 xmm22,XMMWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 a4 7c 08 da f7\s+sha1msg2 xmm22,xmm23 +\s*[a-f0-9]+:\s*62 cc 7c 08 da b4 87 23 01 00 00\s+sha1msg2 xmm22,XMMWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 a4 7c 08 d8 f7\s+sha1nexte xmm22,xmm23 +\s*[a-f0-9]+:\s*62 cc 7c 08 d8 b4 87 23 01 00 00\s+sha1nexte xmm22,XMMWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 a4 7c 08 d4 f7 7b\s+sha1rnds4 xmm22,xmm23,0x7b +\s*[a-f0-9]+:\s*62 cc 7c 08 d4 b4 87 23 01 00 00 7b\s+sha1rnds4 xmm22,XMMWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 a4 7c 08 dc f7\s+sha256msg1 xmm22,xmm23 +\s*[a-f0-9]+:\s*62 cc 7c 08 dc b4 87 23 01 00 00\s+sha256msg1 xmm22,XMMWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 a4 7c 08 dd f7\s+sha256msg2 xmm22,xmm23 +\s*[a-f0-9]+:\s*62 cc 7c 08 dd b4 87 23 01 00 00\s+sha256msg2 xmm22,XMMWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 5c 7c 08 db a4 87 23 01 00 00\s+sha256rnds2 xmm12,XMMWORD PTR\s+\[r31\+rax\*4\+0x123\],xmm0 +\s*[a-f0-9]+:\s*d5 10 c0 e0 7b\s+shl\s+r16b,0x7b +\s*[a-f0-9]+:\s*66 d5 10 c1 e2 7b\s+shl\s+r18w,0x7b +\s*[a-f0-9]+:\s*d5 11 c1 e1 7b\s+shl\s+r25d,0x7b +\s*[a-f0-9]+:\s*d5 19 c1 e7 7b\s+shl\s+r31,0x7b +\s*[a-f0-9]+:\s*d5 10 c0 a4 80 23 01 00 00 7b\s+shl\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 10 c1 a4 80 23 01 00 00 7b\s+shl\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 c1 a4 80 23 01 00 00 7b\s+shl\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 18 c1 a4 80 23 01 00 00 7b\s+shl\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 11 c0 a4 87 23 01 00 00 7b\s+shl\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 11 c1 a4 87 23 01 00 00 7b\s+shl\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 11 c1 a4 87 23 01 00 00 7b\s+shl\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 19 c1 a4 87 23 01 00 00 7b\s+shl\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 d0 e0\s+shl\s+r16b,1 +\s*[a-f0-9]+:\s*66 d5 10 d1 e2\s+shl\s+r18w,1 +\s*[a-f0-9]+:\s*d5 11 d1 e1\s+shl\s+r25d,1 +\s*[a-f0-9]+:\s*d5 19 d1 e7\s+shl\s+r31,1 +\s*[a-f0-9]+:\s*d5 10 d0 a4 80 23 01 00 00\s+shl\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*66 d5 10 d1 a4 80 23 01 00 00\s+shl\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 10 d1 a4 80 23 01 00 00\s+shl\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 18 d1 a4 80 23 01 00 00\s+shl\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*66 d5 11 d1 a4 87 23 01 00 00\s+shl\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 11 d1 a4 87 23 01 00 00\s+shl\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 19 d1 a4 87 23 01 00 00\s+shl\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 10 d2 e0\s+shl\s+r16b,cl +\s*[a-f0-9]+:\s*66 d5 10 d3 e2\s+shl\s+r18w,cl +\s*[a-f0-9]+:\s*d5 11 d3 e1\s+shl\s+r25d,cl +\s*[a-f0-9]+:\s*d5 19 d3 e7\s+shl\s+r31,cl +\s*[a-f0-9]+:\s*d5 10 d2 a4 80 23 01 00 00\s+shl\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*66 d5 10 d3 a4 80 23 01 00 00\s+shl\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 10 d3 a4 80 23 01 00 00\s+shl\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 18 d3 a4 80 23 01 00 00\s+shl\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 11 d2 a4 87 23 01 00 00\s+shl\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*66 d5 11 d3 a4 87 23 01 00 00\s+shl\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 11 d3 a4 87 23 01 00 00\s+shl\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 19 d3 a4 87 23 01 00 00\s+shl\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*66 d5 c0 a4 d0 7b\s+shld\s+ax,r18w,0x7b +\s*[a-f0-9]+:\s*66 d5 d1 a4 94 87 23 01 00 00 7b\s+shld\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],r18w,0x7b +\s*[a-f0-9]+:\s*d5 c4 a4 ca 7b\s+shld\s+edx,r25d,0x7b +\s*[a-f0-9]+:\s*d5 d5 a4 8c 87 23 01 00 00 7b\s+shld\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d,0x7b +\s*[a-f0-9]+:\s*d5 cd a4 ff 7b\s+shld\s+r15,r31,0x7b +\s*[a-f0-9]+:\s*d5 dc a4 bc 80 23 01 00 00 7b\s+shld\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],r31,0x7b +\s*[a-f0-9]+:\s*66 d5 c0 a5 d0\s+shld\s+ax,r18w,cl +\s*[a-f0-9]+:\s*66 d5 d0 a5 94 80 23 01 00 00\s+shld\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],r18w,cl +\s*[a-f0-9]+:\s*d5 c4 a5 ca\s+shld\s+edx,r25d,cl +\s*[a-f0-9]+:\s*d5 d4 a5 8c 80 23 01 00 00\s+shld\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],r25d,cl +\s*[a-f0-9]+:\s*d5 d5 a5 8c 87 23 01 00 00\s+shld\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d,cl +\s*[a-f0-9]+:\s*d5 cd a5 ff\s+shld\s+r15,r31,cl +\s*[a-f0-9]+:\s*d5 dd a5 bc 87 23 01 00 00\s+shld\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31,cl +\s*[a-f0-9]+:\s*62 72 35 00 f7 d2\s+shlx\s+r10d,edx,r25d +\s*[a-f0-9]+:\s*62 da 35 00 f7 94 87 23 01 00 00\s+shlx\s+edx,DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*62 52 85 00 f7 df\s+shlx\s+r11,r15,r31 +\s*[a-f0-9]+:\s*62 5a 85 00 f7 bc 87 23 01 00 00\s+shlx\s+r15,QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*d5 10 c0 e8 7b\s+shr\s+r16b,0x7b +\s*[a-f0-9]+:\s*66 d5 10 c1 ea 7b\s+shr\s+r18w,0x7b +\s*[a-f0-9]+:\s*d5 11 c1 e9 7b\s+shr\s+r25d,0x7b +\s*[a-f0-9]+:\s*d5 19 c1 ef 7b\s+shr\s+r31,0x7b +\s*[a-f0-9]+:\s*d5 10 c0 ac 80 23 01 00 00 7b\s+shr\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 10 c1 ac 80 23 01 00 00 7b\s+shr\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 c1 ac 80 23 01 00 00 7b\s+shr\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 18 c1 ac 80 23 01 00 00 7b\s+shr\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 11 c1 ac 87 23 01 00 00 7b\s+shr\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 11 c1 ac 87 23 01 00 00 7b\s+shr\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 19 c1 ac 87 23 01 00 00 7b\s+shr\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 d0 e8\s+shr\s+r16b,1 +\s*[a-f0-9]+:\s*66 d5 10 d1 ea\s+shr\s+r18w,1 +\s*[a-f0-9]+:\s*d5 11 d1 e9\s+shr\s+r25d,1 +\s*[a-f0-9]+:\s*d5 19 d1 ef\s+shr\s+r31,1 +\s*[a-f0-9]+:\s*d5 10 d0 ac 80 23 01 00 00\s+shr\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*66 d5 10 d1 ac 80 23 01 00 00\s+shr\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 10 d1 ac 80 23 01 00 00\s+shr\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 18 d1 ac 80 23 01 00 00\s+shr\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*66 d5 11 d1 ac 87 23 01 00 00\s+shr\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 11 d1 ac 87 23 01 00 00\s+shr\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 19 d1 ac 87 23 01 00 00\s+shr\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*d5 10 d2 e8\s+shr\s+r16b,cl +\s*[a-f0-9]+:\s*66 d5 10 d3 ea\s+shr\s+r18w,cl +\s*[a-f0-9]+:\s*d5 11 d3 e9\s+shr\s+r25d,cl +\s*[a-f0-9]+:\s*d5 19 d3 ef\s+shr\s+r31,cl +\s*[a-f0-9]+:\s*d5 10 d2 ac 80 23 01 00 00\s+shr\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*66 d5 10 d3 ac 80 23 01 00 00\s+shr\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 10 d3 ac 80 23 01 00 00\s+shr\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 18 d3 ac 80 23 01 00 00\s+shr\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*66 d5 11 d3 ac 87 23 01 00 00\s+shr\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 11 d3 ac 87 23 01 00 00\s+shr\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*d5 19 d3 ac 87 23 01 00 00\s+shr\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*66 d5 c0 ac d0 7b\s+shrd\s+ax,r18w,0x7b +\s*[a-f0-9]+:\s*66 d5 d1 ac 94 87 23 01 00 00 7b\s+shrd\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],r18w,0x7b +\s*[a-f0-9]+:\s*d5 c4 ac ca 7b\s+shrd\s+edx,r25d,0x7b +\s*[a-f0-9]+:\s*d5 d5 ac 8c 87 23 01 00 00 7b\s+shrd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d,0x7b +\s*[a-f0-9]+:\s*d5 cd ac ff 7b\s+shrd\s+r15,r31,0x7b +\s*[a-f0-9]+:\s*d5 dc ac bc 80 23 01 00 00 7b\s+shrd\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],r31,0x7b +\s*[a-f0-9]+:\s*66 d5 c0 ad d0\s+shrd\s+ax,r18w,cl +\s*[a-f0-9]+:\s*66 d5 d0 ad 94 80 23 01 00 00\s+shrd\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],r18w,cl +\s*[a-f0-9]+:\s*d5 c4 ad ca\s+shrd\s+edx,r25d,cl +\s*[a-f0-9]+:\s*d5 d4 ad 8c 80 23 01 00 00\s+shrd\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],r25d,cl +\s*[a-f0-9]+:\s*d5 d5 ad 8c 87 23 01 00 00\s+shrd\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d,cl +\s*[a-f0-9]+:\s*d5 cd ad ff\s+shrd\s+r15,r31,cl +\s*[a-f0-9]+:\s*d5 dd ad bc 87 23 01 00 00\s+shrd\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31,cl +\s*[a-f0-9]+:\s*62 72 37 00 f7 d2\s+shrx\s+r10d,edx,r25d +\s*[a-f0-9]+:\s*62 da 37 00 f7 94 87 23 01 00 00\s+shrx\s+edx,DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*62 52 87 00 f7 df\s+shrx\s+r11,r15,r31 +\s*[a-f0-9]+:\s*62 5a 87 00 f7 bc 87 23 01 00 00\s+shrx\s+r15,QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*62 da 7d 08 49 84 87 23 01 00 00\s+sttilecfg\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 10 80 e8 7b\s+sub\s+r16b,0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 ea 7b\s+sub\s+r18w,0x7b +\s*[a-f0-9]+:\s*d5 11 83 e9 7b\s+sub\s+r25d,0x7b +\s*[a-f0-9]+:\s*d5 19 83 ef 7b\s+sub\s+r31,0x7b +\s*[a-f0-9]+:\s*d5 10 80 ac 80 23 01 00 00 7b\s+sub\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 ac 80 23 01 00 00 7b\s+sub\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 83 ac 80 23 01 00 00 7b\s+sub\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 18 83 ac 80 23 01 00 00 7b\s+sub\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 11 83 ac 87 23 01 00 00 7b\s+sub\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 11 83 ac 87 23 01 00 00 7b\s+sub\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 19 83 ac 87 23 01 00 00 7b\s+sub\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 40 28 c2\s+sub\s+dl,r16b +\s*[a-f0-9]+:\s*d5 51 28 84 87 23 01 00 00\s+sub\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\],r16b +\s*[a-f0-9]+:\s*66 d5 40 29 d0\s+sub\s+ax,r18w +\s*[a-f0-9]+:\s*66 d5 50 29 94 80 23 01 00 00\s+sub\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*66 d5 51 29 94 87 23 01 00 00\s+sub\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*d5 44 29 ca\s+sub\s+edx,r25d +\s*[a-f0-9]+:\s*d5 55 29 8c 87 23 01 00 00\s+sub\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*d5 4d 29 ff\s+sub\s+r15,r31 +\s*[a-f0-9]+:\s*d5 5d 29 bc 87 23 01 00 00\s+sub\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*d5 50 2a 84 80 23 01 00 00\s+sub\s+r16b,BYTE PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5c 2b bc 80 23 01 00 00\s+sub\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 51 2b 94 87 23 01 00 00\s+sub\s+r18w,WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 55 2b 8c 87 23 01 00 00\s+sub\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5d 2b bc 87 23 01 00 00\s+sub\s+r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 da 7f 08 4b b4 87 23 01 00 00\s+tileloadd tmm6,\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 da 7d 08 4b b4 87 23 01 00 00\s+tileloaddt1 tmm6,\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 da 7e 08 4b b4 87 23 01 00 00\s+tilestored\s+\[r31\+rax\*4\+0x123\],tmm6 +\s*[a-f0-9]+:\s*66 f3 d5 90 bc c2\s+tzcnt\s+ax,r18w +\s*[a-f0-9]+:\s*f3 d5 91 bc d1\s+tzcnt\s+edx,r25d +\s*[a-f0-9]+:\s*f3 d5 9d bc ff\s+tzcnt\s+r15,r31 +\s*[a-f0-9]+:\s*66 f3 d5 d0 bc 94 80 23 01 00 00\s+tzcnt\s+r18w,WORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*f3 d5 dc bc bc 80 23 01 00 00\s+tzcnt\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 f3 d5 d1 bc 94 87 23 01 00 00\s+tzcnt\s+r18w,WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*f3 d5 d5 bc 8c 87 23 01 00 00\s+tzcnt\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 4c 7c 08 66 8c 87 23 01 00 00\s+wrssd\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*62 4c fc 08 66 bc 87 23 01 00 00\s+wrssq\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*62 4c 7d 08 65 8c 87 23 01 00 00\s+wrussd\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*62 4c fd 08 65 bc 87 23 01 00 00\s+wrussq\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*d5 10 80 f0 7b\s+xor\s+r16b,0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 f2 7b\s+xor\s+r18w,0x7b +\s*[a-f0-9]+:\s*d5 11 83 f1 7b\s+xor\s+r25d,0x7b +\s*[a-f0-9]+:\s*d5 19 83 f7 7b\s+xor\s+r31,0x7b +\s*[a-f0-9]+:\s*d5 10 80 b4 80 23 01 00 00 7b\s+xor\s+BYTE PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 10 83 b4 80 23 01 00 00 7b\s+xor\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 10 83 b4 80 23 01 00 00 7b\s+xor\s+DWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 18 83 b4 80 23 01 00 00 7b\s+xor\s+QWORD PTR\s+\[r16\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*66 d5 11 83 b4 87 23 01 00 00 7b\s+xor\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 11 83 b4 87 23 01 00 00 7b\s+xor\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 19 83 b4 87 23 01 00 00 7b\s+xor\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*d5 40 30 c2\s+xor\s+dl,r16b +\s*[a-f0-9]+:\s*d5 51 30 84 87 23 01 00 00\s+xor\s+BYTE PTR\s+\[r31\+rax\*4\+0x123\],r16b +\s*[a-f0-9]+:\s*66 d5 40 31 d0\s+xor\s+ax,r18w +\s*[a-f0-9]+:\s*66 d5 50 31 94 80 23 01 00 00\s+xor\s+WORD PTR\s+\[r16\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*66 d5 51 31 94 87 23 01 00 00\s+xor\s+WORD PTR\s+\[r31\+rax\*4\+0x123\],r18w +\s*[a-f0-9]+:\s*d5 44 31 ca\s+xor\s+edx,r25d +\s*[a-f0-9]+:\s*d5 55 31 8c 87 23 01 00 00\s+xor\s+DWORD PTR\s+\[r31\+rax\*4\+0x123\],r25d +\s*[a-f0-9]+:\s*d5 4d 31 ff\s+xor\s+r15,r31 +\s*[a-f0-9]+:\s*d5 5d 31 bc 87 23 01 00 00\s+xor\s+QWORD PTR\s+\[r31\+rax\*4\+0x123\],r31 +\s*[a-f0-9]+:\s*d5 50 32 84 80 23 01 00 00\s+xor\s+r16b,BYTE PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5c 33 bc 80 23 01 00 00\s+xor\s+r31,QWORD PTR\s+\[r16\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*66 d5 51 33 94 87 23 01 00 00\s+xor\s+r18w,WORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 55 33 8c 87 23 01 00 00\s+xor\s+r25d,DWORD PTR\s+\[r31\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*d5 5d 33 bc 87 23 01 00 00\s+xor\s+r31,QWORD PTR\s+\[r31\+rax\*4\+0x123\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d new file mode 100644 index 00000000000..be85a750232 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d @@ -0,0 +1,740 @@ +#as: +#objdump: -dw +#name: x86_64 APX_F EVEX-Promoted insns +#source: x86-64-apx-evex-promoted.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 4c 7c 08 fc 8c 87 23 01 00 00\s+aadd\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 4c fc 08 fc bc 87 23 01 00 00\s+aadd\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 4c 7d 08 fc 8c 87 23 01 00 00\s+aand\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 4c fd 08 fc bc 87 23 01 00 00\s+aand\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 80 d0 7b\s+adc\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 83 d2 7b\s+adc\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 83 d1 7b\s+adc\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 83 d7 7b\s+adc\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 80 94 80 23 01 00 00 7b\s+adcb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 83 94 80 23 01 00 00 7b\s+adcw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 83 94 80 23 01 00 00 7b\s+adcl\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 83 94 80 23 01 00 00 7b\s+adcq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 83 94 87 23 01 00 00 7b\s+adcw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 83 94 87 23 01 00 00 7b\s+adcl\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 83 94 87 23 01 00 00 7b\s+adcq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 40 10 c2\s+adc\s+%r16b,%dl +\s*[a-f0-9]+:\s*d5 51 10 84 87 23 01 00 00\s+adc\s+%r16b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 40 11 d0\s+adc\s+%r18w,%ax +\s*[a-f0-9]+:\s*66 d5 50 11 94 80 23 01 00 00\s+adc\s+%r18w,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 51 11 94 87 23 01 00 00\s+adc\s+%r18w,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 44 11 ca\s+adc\s+%r25d,%edx +\s*[a-f0-9]+:\s*d5 55 11 8c 87 23 01 00 00\s+adc\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 4d 11 ff\s+adc\s+%r31,%r15 +\s*[a-f0-9]+:\s*d5 5d 11 bc 87 23 01 00 00\s+adc\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 50 12 84 80 23 01 00 00\s+adc\s+0x123\(%r16,%rax,4\),%r16b +\s*[a-f0-9]+:\s*d5 5c 13 bc 80 23 01 00 00\s+adc\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*66 d5 51 13 94 87 23 01 00 00\s+adc\s+0x123\(%r31,%rax,4\),%r18w +\s*[a-f0-9]+:\s*d5 55 13 8c 87 23 01 00 00\s+adc\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*d5 5d 13 bc 87 23 01 00 00\s+adc\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 dc 7d 08 66 d1\s+adcx\s+%r25d,%edx +\s*[a-f0-9]+:\s*62 5c fd 08 66 ff\s+adcx\s+%r31,%r15 +\s*[a-f0-9]+:\s*62 6c fd 08 66 bc 80 23 01 00 00\s+adcx\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 4c 7d 08 66 8c 87 23 01 00 00\s+adcx\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*d5 10 80 c0 7b\s+add\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 83 c2 7b\s+add\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 83 c1 7b\s+add\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 83 c7 7b\s+add\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 80 84 80 23 01 00 00 7b\s+addb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 83 84 80 23 01 00 00 7b\s+addw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 83 84 80 23 01 00 00 7b\s+addl\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 83 84 80 23 01 00 00 7b\s+addq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 83 84 87 23 01 00 00 7b\s+addw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 83 84 87 23 01 00 00 7b\s+addl\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 83 84 87 23 01 00 00 7b\s+addq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 40 00 c2\s+add\s+%r16b,%dl +\s*[a-f0-9]+:\s*d5 51 00 84 87 23 01 00 00\s+add\s+%r16b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 40 01 d0\s+add\s+%r18w,%ax +\s*[a-f0-9]+:\s*66 d5 50 01 94 80 23 01 00 00\s+add\s+%r18w,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 51 01 94 87 23 01 00 00\s+add\s+%r18w,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 44 01 ca\s+add\s+%r25d,%edx +\s*[a-f0-9]+:\s*d5 55 01 8c 87 23 01 00 00\s+add\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 4d 01 ff\s+add\s+%r31,%r15 +\s*[a-f0-9]+:\s*d5 5d 01 bc 87 23 01 00 00\s+add\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 50 02 84 80 23 01 00 00\s+add\s+0x123\(%r16,%rax,4\),%r16b +\s*[a-f0-9]+:\s*d5 5c 03 bc 80 23 01 00 00\s+add\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*66 d5 51 03 94 87 23 01 00 00\s+add\s+0x123\(%r31,%rax,4\),%r18w +\s*[a-f0-9]+:\s*d5 55 03 8c 87 23 01 00 00\s+add\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*d5 5d 03 bc 87 23 01 00 00\s+add\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 dc 7e 08 66 d1\s+adox\s+%r25d,%edx +\s*[a-f0-9]+:\s*62 5c fe 08 66 ff\s+adox\s+%r31,%r15 +\s*[a-f0-9]+:\s*62 6c fe 08 66 bc 80 23 01 00 00\s+adox\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 4c 7e 08 66 8c 87 23 01 00 00\s+adox\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*62 cc 7e 08 dd b4 87 23 01 00 00\s+aesdec128kl\s+0x123\(%r31,%rax,4\),%xmm22 +\s*[a-f0-9]+:\s*62 cc 7e 08 df b4 87 23 01 00 00\s+aesdec256kl\s+0x123\(%r31,%rax,4\),%xmm22 +\s*[a-f0-9]+:\s*62 dc 7e 08 d8 8c 87 23 01 00 00\s+aesdecwide128kl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 dc 7e 08 d8 9c 87 23 01 00 00\s+aesdecwide256kl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 cc 7e 08 dc b4 87 23 01 00 00\s+aesenc128kl\s+0x123\(%r31,%rax,4\),%xmm22 +\s*[a-f0-9]+:\s*62 cc 7e 08 de b4 87 23 01 00 00\s+aesenc256kl\s+0x123\(%r31,%rax,4\),%xmm22 +\s*[a-f0-9]+:\s*62 dc 7e 08 d8 84 87 23 01 00 00\s+aesencwide128kl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 dc 7e 08 d8 94 87 23 01 00 00\s+aesencwide256kl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 80 e0 7b\s+and\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 83 e2 7b\s+and\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 83 e1 7b\s+and\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 83 e7 7b\s+and\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 80 a4 80 23 01 00 00 7b\s+andb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 83 a4 80 23 01 00 00 7b\s+andw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 83 a4 80 23 01 00 00 7b\s+andl\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 83 a4 80 23 01 00 00 7b\s+andq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 83 a4 87 23 01 00 00 7b\s+andw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 83 a4 87 23 01 00 00 7b\s+andl\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 83 a4 87 23 01 00 00 7b\s+andq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 40 20 c2\s+and\s+%r16b,%dl +\s*[a-f0-9]+:\s*d5 51 20 84 87 23 01 00 00\s+and\s+%r16b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 40 21 d0\s+and\s+%r18w,%ax +\s*[a-f0-9]+:\s*66 d5 50 21 94 80 23 01 00 00\s+and\s+%r18w,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 51 21 94 87 23 01 00 00\s+and\s+%r18w,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 44 21 ca\s+and\s+%r25d,%edx +\s*[a-f0-9]+:\s*d5 55 21 8c 87 23 01 00 00\s+and\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 4d 21 ff\s+and\s+%r31,%r15 +\s*[a-f0-9]+:\s*d5 5d 21 bc 87 23 01 00 00\s+and\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 50 22 84 80 23 01 00 00\s+and\s+0x123\(%r16,%rax,4\),%r16b +\s*[a-f0-9]+:\s*d5 5c 23 bc 80 23 01 00 00\s+and\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*66 d5 51 23 94 87 23 01 00 00\s+and\s+0x123\(%r31,%rax,4\),%r18w +\s*[a-f0-9]+:\s*d5 55 23 8c 87 23 01 00 00\s+and\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*d5 5d 23 bc 87 23 01 00 00\s+and\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 5a 6c 08 f2 d1\s+andn\s+%r25d,%edx,%r10d +\s*[a-f0-9]+:\s*62 5a 84 08 f2 df\s+andn\s+%r31,%r15,%r11 +\s*[a-f0-9]+:\s*62 da 34 00 f2 94 87 23 01 00 00\s+andn\s+0x123\(%r31,%rax,4\),%r25d,%edx +\s*[a-f0-9]+:\s*62 5a 84 00 f2 bc 87 23 01 00 00\s+andn\s+0x123\(%r31,%rax,4\),%r31,%r15 +\s*[a-f0-9]+:\s*62 4c 7f 08 fc 8c 87 23 01 00 00\s+aor\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 4c ff 08 fc bc 87 23 01 00 00\s+aor\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 4c 7e 08 fc 8c 87 23 01 00 00\s+axor\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 4c fe 08 fc bc 87 23 01 00 00\s+axor\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 72 34 00 f7 d2\s+bextr\s+%r25d,%edx,%r10d +\s*[a-f0-9]+:\s*62 da 34 00 f7 94 87 23 01 00 00\s+bextr\s+%r25d,0x123\(%r31,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 52 84 00 f7 df\s+bextr\s+%r31,%r15,%r11 +\s*[a-f0-9]+:\s*62 5a 84 00 f7 bc 87 23 01 00 00\s+bextr\s+%r31,0x123\(%r31,%rax,4\),%r15 +\s*[a-f0-9]+:\s*62 da 6c 08 f3 d9\s+blsi\s+%r25d,%edx +\s*[a-f0-9]+:\s*62 da 84 08 f3 df\s+blsi\s+%r31,%r15 +\s*[a-f0-9]+:\s*62 da 34 00 f3 9c 87 23 01 00 00\s+blsi\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*62 da 84 00 f3 9c 87 23 01 00 00\s+blsi\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 da 6c 08 f3 d1\s+blsmsk\s+%r25d,%edx +\s*[a-f0-9]+:\s*62 da 84 08 f3 d7\s+blsmsk\s+%r31,%r15 +\s*[a-f0-9]+:\s*62 da 34 00 f3 94 87 23 01 00 00\s+blsmsk\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*62 da 84 00 f3 94 87 23 01 00 00\s+blsmsk\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 da 6c 08 f3 c9\s+blsr\s+%r25d,%edx +\s*[a-f0-9]+:\s*62 da 84 08 f3 cf\s+blsr\s+%r31,%r15 +\s*[a-f0-9]+:\s*62 da 34 00 f3 8c 87 23 01 00 00\s+blsr\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*62 da 84 00 f3 8c 87 23 01 00 00\s+blsr\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 72 34 00 f5 d2\s+bzhi\s+%r25d,%edx,%r10d +\s*[a-f0-9]+:\s*62 da 34 00 f5 94 87 23 01 00 00\s+bzhi\s+%r25d,0x123\(%r31,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 52 84 00 f5 df\s+bzhi\s+%r31,%r15,%r11 +\s*[a-f0-9]+:\s*62 5a 84 00 f5 bc 87 23 01 00 00\s+bzhi\s+%r31,0x123\(%r31,%rax,4\),%r15 +\s*[a-f0-9]+:\s*62 da 35 00 e6 94 87 23 01 00 00\s+cmpbexadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 e6 bc 87 23 01 00 00\s+cmpbexadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 e2 94 87 23 01 00 00\s+cmpbxadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 e2 bc 87 23 01 00 00\s+cmpbxadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 ec 94 87 23 01 00 00\s+cmplxadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 ec bc 87 23 01 00 00\s+cmplxadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 e7 94 87 23 01 00 00\s+cmpnbexadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 e7 bc 87 23 01 00 00\s+cmpnbexadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 e3 94 87 23 01 00 00\s+cmpnbxadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 e3 bc 87 23 01 00 00\s+cmpnbxadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 ef 94 87 23 01 00 00\s+cmpnlexadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 ef bc 87 23 01 00 00\s+cmpnlexadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 ed 94 87 23 01 00 00\s+cmpnlxadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 ed bc 87 23 01 00 00\s+cmpnlxadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 e1 94 87 23 01 00 00\s+cmpnoxadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 e1 bc 87 23 01 00 00\s+cmpnoxadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 eb 94 87 23 01 00 00\s+cmpnpxadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 eb bc 87 23 01 00 00\s+cmpnpxadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 e9 94 87 23 01 00 00\s+cmpnsxadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 e9 bc 87 23 01 00 00\s+cmpnsxadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 e5 94 87 23 01 00 00\s+cmpnzxadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 e5 bc 87 23 01 00 00\s+cmpnzxadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 e0 94 87 23 01 00 00\s+cmpoxadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 e0 bc 87 23 01 00 00\s+cmpoxadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 ea 94 87 23 01 00 00\s+cmppxadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 ea bc 87 23 01 00 00\s+cmppxadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 e8 94 87 23 01 00 00\s+cmpsxadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 e8 bc 87 23 01 00 00\s+cmpsxadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 da 35 00 e4 94 87 23 01 00 00\s+cmpzxadd\s+%r25d,%edx,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 85 00 e4 bc 87 23 01 00 00\s+cmpzxadd\s+%r31,%r15,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 fe c8\s+dec\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 ff ca\s+dec\s+%r18w +\s*[a-f0-9]+:\s*d5 11 ff c9\s+dec\s+%r25d +\s*[a-f0-9]+:\s*d5 19 ff cf\s+dec\s+%r31 +\s*[a-f0-9]+:\s*66 d5 10 ff 8c 80 23 01 00 00\s+decw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 ff 8c 80 23 01 00 00\s+decl\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 ff 8c 80 23 01 00 00\s+decq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 fe 8c 87 23 01 00 00\s+decb\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 ff 8c 87 23 01 00 00\s+decw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 ff 8c 87 23 01 00 00\s+decl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 ff 8c 87 23 01 00 00\s+decq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 f6 f0\s+div\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 f7 f2\s+div\s+%r18w +\s*[a-f0-9]+:\s*d5 11 f7 f1\s+div\s+%r25d +\s*[a-f0-9]+:\s*d5 19 f7 f7\s+div\s+%r31 +\s*[a-f0-9]+:\s*66 d5 10 f7 b4 80 23 01 00 00\s+divw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 f7 b4 80 23 01 00 00\s+divl\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 f7 b4 80 23 01 00 00\s+divq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 f6 b4 87 23 01 00 00\s+divb\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 f7 b4 87 23 01 00 00\s+divw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 f7 b4 87 23 01 00 00\s+divl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 f7 b4 87 23 01 00 00\s+divq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 dc 7e 08 da d1\s+encodekey128\s+%r25d,%edx +\s*[a-f0-9]+:\s*62 dc 7e 08 db d1\s+encodekey256\s+%r25d,%edx +\s*[a-f0-9]+:\s*67 62 4c 7f 08 f8 8c 87 23 01 00 00\s+enqcmd\s+0x123\(%r31d,%eax,4\),%r25d +\s*[a-f0-9]+:\s*62 4c 7f 08 f8 bc 87 23 01 00 00\s+enqcmd\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*67 62 4c 7e 08 f8 8c 87 23 01 00 00\s+enqcmds\s+0x123\(%r31d,%eax,4\),%r25d +\s*[a-f0-9]+:\s*62 4c 7e 08 f8 bc 87 23 01 00 00\s+enqcmds\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*d5 10 f6 f8\s+idiv\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 f7 fa\s+idiv\s+%r18w +\s*[a-f0-9]+:\s*d5 11 f7 f9\s+idiv\s+%r25d +\s*[a-f0-9]+:\s*d5 19 f7 ff\s+idiv\s+%r31 +\s*[a-f0-9]+:\s*66 d5 10 f7 bc 80 23 01 00 00\s+idivw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 f7 bc 80 23 01 00 00\s+idivl\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 f7 bc 80 23 01 00 00\s+idivq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 f6 bc 87 23 01 00 00\s+idivb\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 f7 bc 87 23 01 00 00\s+idivw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 f7 bc 87 23 01 00 00\s+idivl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 f7 bc 87 23 01 00 00\s+idivq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 6b c2 7b\s+imul\s+\$0x7b,%r18w,%ax +\s*[a-f0-9]+:\s*d5 11 6b d1 7b\s+imul\s+\$0x7b,%r25d,%edx +\s*[a-f0-9]+:\s*d5 1d 6b ff 7b\s+imul\s+\$0x7b,%r31,%r15 +\s*[a-f0-9]+:\s*d5 54 6b 8c 80 23 01 00 00 7b\s+imul\s+\$0x7b,0x123\(%r16,%rax,4\),%r25d +\s*[a-f0-9]+:\s*d5 5c 6b bc 80 23 01 00 00 7b\s+imul\s+\$0x7b,0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*66 d5 51 6b 94 87 23 01 00 00 7b\s+imul\s+\$0x7b,0x123\(%r31,%rax,4\),%r18w +\s*[a-f0-9]+:\s*d5 55 6b 8c 87 23 01 00 00 7b\s+imul\s+\$0x7b,0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*d5 5d 6b bc 87 23 01 00 00 7b\s+imul\s+\$0x7b,0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*d5 10 f6 e8\s+imul\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 f7 ea\s+imul\s+%r18w +\s*[a-f0-9]+:\s*66 d5 90 af c2\s+imul\s+%r18w,%ax +\s*[a-f0-9]+:\s*d5 11 f7 e9\s+imul\s+%r25d +\s*[a-f0-9]+:\s*d5 91 af d1\s+imul\s+%r25d,%edx +\s*[a-f0-9]+:\s*d5 19 f7 ef\s+imul\s+%r31 +\s*[a-f0-9]+:\s*d5 9d af ff\s+imul\s+%r31,%r15 +\s*[a-f0-9]+:\s*d5 10 f6 ac 80 23 01 00 00\s+imulb\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 f7 ac 80 23 01 00 00\s+imulw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 f7 ac 80 23 01 00 00\s+imull\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 d0 af 94 80 23 01 00 00\s+imul\s+0x123\(%r16,%rax,4\),%r18w +\s*[a-f0-9]+:\s*d5 d4 af 8c 80 23 01 00 00\s+imul\s+0x123\(%r16,%rax,4\),%r25d +\s*[a-f0-9]+:\s*d5 dc af bc 80 23 01 00 00\s+imul\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*d5 18 f7 ac 80 23 01 00 00\s+imulq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 f7 ac 87 23 01 00 00\s+imulw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 f7 ac 87 23 01 00 00\s+imull\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 f7 ac 87 23 01 00 00\s+imulq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 fe c0\s+inc\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 ff c2\s+inc\s+%r18w +\s*[a-f0-9]+:\s*d5 11 ff c1\s+inc\s+%r25d +\s*[a-f0-9]+:\s*d5 19 ff c7\s+inc\s+%r31 +\s*[a-f0-9]+:\s*66 d5 10 ff 84 80 23 01 00 00\s+incw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 ff 84 80 23 01 00 00\s+incl\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 ff 84 80 23 01 00 00\s+incq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 fe 84 87 23 01 00 00\s+incb\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 ff 84 87 23 01 00 00\s+incw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 ff 84 87 23 01 00 00\s+incl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 ff 84 87 23 01 00 00\s+incq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 4c 7e 08 f0 bc 87 23 01 00 00\s+invept\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 4c 7e 08 f2 bc 87 23 01 00 00\s+invpcid\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 4c 7e 08 f1 bc 87 23 01 00 00\s+invvpid\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*c5 f9 90 eb\s+kmovb\s+%k3,%k5 +\s*[a-f0-9]+:\s*62 61 7d 08 93 cd\s+kmovb\s+%k5,%r25d +\s*[a-f0-9]+:\s*62 d9 7d 08 91 ac 87 23 01 00 00\s+kmovb\s+%k5,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 d9 7d 08 92 e9\s+kmovb\s+%r25d,%k5 +\s*[a-f0-9]+:\s*62 d9 7d 08 90 ac 87 23 01 00 00\s+kmovb\s+0x123\(%r31,%rax,4\),%k5 +\s*[a-f0-9]+:\s*c4 e1 f9 90 eb\s+kmovd\s+%k3,%k5 +\s*[a-f0-9]+:\s*62 61 7f 08 93 cd\s+kmovd\s+%k5,%r25d +\s*[a-f0-9]+:\s*62 d9 fd 08 91 ac 87 23 01 00 00\s+kmovd\s+%k5,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 d9 7f 08 92 e9\s+kmovd\s+%r25d,%k5 +\s*[a-f0-9]+:\s*62 d9 fd 08 90 ac 87 23 01 00 00\s+kmovd\s+0x123\(%r31,%rax,4\),%k5 +\s*[a-f0-9]+:\s*c4 e1 f8 90 eb\s+kmovq\s+%k3,%k5 +\s*[a-f0-9]+:\s*62 61 ff 08 93 fd\s+kmovq\s+%k5,%r31 +\s*[a-f0-9]+:\s*62 d9 fc 08 91 ac 87 23 01 00 00\s+kmovq\s+%k5,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 d9 ff 08 92 ef\s+kmovq\s+%r31,%k5 +\s*[a-f0-9]+:\s*62 d9 fc 08 90 ac 87 23 01 00 00\s+kmovq\s+0x123\(%r31,%rax,4\),%k5 +\s*[a-f0-9]+:\s*c5 f8 90 eb\s+kmovw\s+%k3,%k5 +\s*[a-f0-9]+:\s*62 61 7c 08 93 cd\s+kmovw\s+%k5,%r25d +\s*[a-f0-9]+:\s*62 d9 7c 08 91 ac 87 23 01 00 00\s+kmovw\s+%k5,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 d9 7c 08 92 e9\s+kmovw\s+%r25d,%k5 +\s*[a-f0-9]+:\s*62 d9 7c 08 90 ac 87 23 01 00 00\s+kmovw\s+0x123\(%r31,%rax,4\),%k5 +\s*[a-f0-9]+:\s*62 da 7c 08 49 84 87 23 01 00 00\s+ldtilecfg\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 f3 d5 90 bd c2\s+lzcnt\s+%r18w,%ax +\s*[a-f0-9]+:\s*f3 d5 91 bd d1\s+lzcnt\s+%r25d,%edx +\s*[a-f0-9]+:\s*f3 d5 9d bd ff\s+lzcnt\s+%r31,%r15 +\s*[a-f0-9]+:\s*66 f3 d5 d0 bd 94 80 23 01 00 00\s+lzcnt\s+0x123\(%r16,%rax,4\),%r18w +\s*[a-f0-9]+:\s*f3 d5 dc bd bc 80 23 01 00 00\s+lzcnt\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*66 f3 d5 d1 bd 94 87 23 01 00 00\s+lzcnt\s+0x123\(%r31,%rax,4\),%r18w +\s*[a-f0-9]+:\s*f3 d5 d5 bd 8c 87 23 01 00 00\s+lzcnt\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*62 fc 7d 08 60 c2\s+movbe\s+%r18w,%ax +\s*[a-f0-9]+:\s*62 ec 7d 08 61 94 80 23 01 00 00\s+movbe\s+%r18w,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*62 cc 7d 08 61 94 87 23 01 00 00\s+movbe\s+%r18w,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 dc 7c 08 60 d1\s+movbe\s+%r25d,%edx +\s*[a-f0-9]+:\s*62 6c 7c 08 61 8c 80 23 01 00 00\s+movbe\s+%r25d,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*62 5c fc 08 60 ff\s+movbe\s+%r31,%r15 +\s*[a-f0-9]+:\s*62 6c fc 08 61 bc 80 23 01 00 00\s+movbe\s+%r31,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*62 4c fc 08 61 bc 87 23 01 00 00\s+movbe\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 6c fc 08 60 bc 80 23 01 00 00\s+movbe\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 cc 7d 08 60 94 87 23 01 00 00\s+movbe\s+0x123\(%r31,%rax,4\),%r18w +\s*[a-f0-9]+:\s*62 4c 7c 08 60 8c 87 23 01 00 00\s+movbe\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*67 62 4c 7d 08 f8 8c 87 23 01 00 00\s+movdir64b\s+0x123\(%r31d,%eax,4\),%r25d +\s*[a-f0-9]+:\s*62 4c 7d 08 f8 bc 87 23 01 00 00\s+movdir64b\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 4c 7c 08 f9 8c 87 23 01 00 00\s+movdiri\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 4c fc 08 f9 bc 87 23 01 00 00\s+movdiri\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 f6 e0\s+mul\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 f7 e2\s+mul\s+%r18w +\s*[a-f0-9]+:\s*d5 11 f7 e1\s+mul\s+%r25d +\s*[a-f0-9]+:\s*d5 19 f7 e7\s+mul\s+%r31 +\s*[a-f0-9]+:\s*66 d5 10 f7 a4 80 23 01 00 00\s+mulw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 f7 a4 80 23 01 00 00\s+mull\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 f7 a4 80 23 01 00 00\s+mulq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 f6 a4 87 23 01 00 00\s+mulb\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 f7 a4 87 23 01 00 00\s+mulw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 f7 a4 87 23 01 00 00\s+mull\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 f7 a4 87 23 01 00 00\s+mulq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 5a 6f 08 f6 d1\s+mulx\s+%r25d,%edx,%r10d +\s*[a-f0-9]+:\s*62 5a 87 08 f6 df\s+mulx\s+%r31,%r15,%r11 +\s*[a-f0-9]+:\s*62 da 37 00 f6 94 87 23 01 00 00\s+mulx\s+0x123\(%r31,%rax,4\),%r25d,%edx +\s*[a-f0-9]+:\s*62 5a 87 00 f6 bc 87 23 01 00 00\s+mulx\s+0x123\(%r31,%rax,4\),%r31,%r15 +\s*[a-f0-9]+:\s*d5 10 f6 d8\s+neg\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 f7 da\s+neg\s+%r18w +\s*[a-f0-9]+:\s*d5 11 f7 d9\s+neg\s+%r25d +\s*[a-f0-9]+:\s*d5 19 f7 df\s+neg\s+%r31 +\s*[a-f0-9]+:\s*66 d5 10 f7 9c 80 23 01 00 00\s+negw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 f7 9c 80 23 01 00 00\s+negl\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 f7 9c 80 23 01 00 00\s+negq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 f6 9c 87 23 01 00 00\s+negb\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 f7 9c 87 23 01 00 00\s+negw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 f7 9c 87 23 01 00 00\s+negl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 f7 9c 87 23 01 00 00\s+negq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 f6 d0\s+not\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 f7 d2\s+not\s+%r18w +\s*[a-f0-9]+:\s*d5 11 f7 d1\s+not\s+%r25d +\s*[a-f0-9]+:\s*d5 19 f7 d7\s+not\s+%r31 +\s*[a-f0-9]+:\s*66 d5 10 f7 94 80 23 01 00 00\s+notw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 f7 94 80 23 01 00 00\s+notl\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 f7 94 80 23 01 00 00\s+notq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 f6 94 87 23 01 00 00\s+notb\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 f7 94 87 23 01 00 00\s+notw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 f7 94 87 23 01 00 00\s+notl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 f7 94 87 23 01 00 00\s+notq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 80 c8 7b\s+or\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 83 ca 7b\s+or\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 83 c9 7b\s+or\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 83 cf 7b\s+or\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 80 8c 80 23 01 00 00 7b\s+orb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 83 8c 80 23 01 00 00 7b\s+orw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 83 8c 80 23 01 00 00 7b\s+orl\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 83 8c 80 23 01 00 00 7b\s+orq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 83 8c 87 23 01 00 00 7b\s+orw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 83 8c 87 23 01 00 00 7b\s+orl\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 83 8c 87 23 01 00 00 7b\s+orq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 40 08 c2\s+or\s+%r16b,%dl +\s*[a-f0-9]+:\s*d5 51 08 84 87 23 01 00 00\s+or\s+%r16b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 40 09 d0\s+or\s+%r18w,%ax +\s*[a-f0-9]+:\s*66 d5 50 09 94 80 23 01 00 00\s+or\s+%r18w,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 51 09 94 87 23 01 00 00\s+or\s+%r18w,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 44 09 ca\s+or\s+%r25d,%edx +\s*[a-f0-9]+:\s*d5 55 09 8c 87 23 01 00 00\s+or\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 4d 09 ff\s+or\s+%r31,%r15 +\s*[a-f0-9]+:\s*d5 5d 09 bc 87 23 01 00 00\s+or\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 50 0a 84 80 23 01 00 00\s+or\s+0x123\(%r16,%rax,4\),%r16b +\s*[a-f0-9]+:\s*d5 5c 0b bc 80 23 01 00 00\s+or\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*66 d5 51 0b 94 87 23 01 00 00\s+or\s+0x123\(%r31,%rax,4\),%r18w +\s*[a-f0-9]+:\s*d5 55 0b 8c 87 23 01 00 00\s+or\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*d5 5d 0b bc 87 23 01 00 00\s+or\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 5a 6f 08 f5 d1\s+pdep\s+%r25d,%edx,%r10d +\s*[a-f0-9]+:\s*62 5a 87 08 f5 df\s+pdep\s+%r31,%r15,%r11 +\s*[a-f0-9]+:\s*62 da 37 00 f5 94 87 23 01 00 00\s+pdep\s+0x123\(%r31,%rax,4\),%r25d,%edx +\s*[a-f0-9]+:\s*62 5a 87 00 f5 bc 87 23 01 00 00\s+pdep\s+0x123\(%r31,%rax,4\),%r31,%r15 +\s*[a-f0-9]+:\s*62 5a 6e 08 f5 d1\s+pext\s+%r25d,%edx,%r10d +\s*[a-f0-9]+:\s*62 5a 86 08 f5 df\s+pext\s+%r31,%r15,%r11 +\s*[a-f0-9]+:\s*62 da 36 00 f5 94 87 23 01 00 00\s+pext\s+0x123\(%r31,%rax,4\),%r25d,%edx +\s*[a-f0-9]+:\s*62 5a 86 00 f5 bc 87 23 01 00 00\s+pext\s+0x123\(%r31,%rax,4\),%r31,%r15 +\s*[a-f0-9]+:\s*66 f3 d5 90 b8 c2\s+popcnt\s+%r18w,%ax +\s*[a-f0-9]+:\s*f3 d5 91 b8 d1\s+popcnt\s+%r25d,%edx +\s*[a-f0-9]+:\s*f3 d5 9d b8 ff\s+popcnt\s+%r31,%r15 +\s*[a-f0-9]+:\s*66 f3 d5 d0 b8 94 80 23 01 00 00\s+popcnt\s+0x123\(%r16,%rax,4\),%r18w +\s*[a-f0-9]+:\s*f3 d5 dc b8 bc 80 23 01 00 00\s+popcnt\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*66 f3 d5 d1 b8 94 87 23 01 00 00\s+popcnt\s+0x123\(%r31,%rax,4\),%r18w +\s*[a-f0-9]+:\s*f3 d5 d5 b8 8c 87 23 01 00 00\s+popcnt\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*d5 10 c0 d0 7b\s+rcl\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 c1 d2 7b\s+rcl\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 c1 d1 7b\s+rcl\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 c1 d7 7b\s+rcl\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 c0 94 80 23 01 00 00 7b\s+rclb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 c1 94 80 23 01 00 00 7b\s+rclw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 c1 94 80 23 01 00 00 7b\s+rcll\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 c1 94 80 23 01 00 00 7b\s+rclq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 c1 94 87 23 01 00 00 7b\s+rclw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 c1 94 87 23 01 00 00 7b\s+rcll\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 c1 94 87 23 01 00 00 7b\s+rclq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d0 d0\s+rcl\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 d1 d2\s+rcl\s+%r18w +\s*[a-f0-9]+:\s*d5 11 d1 d1\s+rcl\s+%r25d +\s*[a-f0-9]+:\s*d5 19 d1 d7\s+rcl\s+%r31 +\s*[a-f0-9]+:\s*d5 10 d0 94 80 23 01 00 00\s+rclb\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d1 94 80 23 01 00 00\s+rclw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d1 94 80 23 01 00 00\s+rcll\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d1 94 80 23 01 00 00\s+rclq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d1 94 87 23 01 00 00\s+rclw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d1 94 87 23 01 00 00\s+rcll\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d1 94 87 23 01 00 00\s+rclq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d2 d0\s+rcl\s+%cl,%r16b +\s*[a-f0-9]+:\s*66 d5 10 d3 d2\s+rcl\s+%cl,%r18w +\s*[a-f0-9]+:\s*d5 11 d3 d1\s+rcl\s+%cl,%r25d +\s*[a-f0-9]+:\s*d5 19 d3 d7\s+rcl\s+%cl,%r31 +\s*[a-f0-9]+:\s*d5 10 d2 94 80 23 01 00 00\s+rclb\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d3 94 80 23 01 00 00\s+rclw\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d3 94 80 23 01 00 00\s+rcll\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d3 94 80 23 01 00 00\s+rclq\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d3 94 87 23 01 00 00\s+rclw\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d3 94 87 23 01 00 00\s+rcll\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d3 94 87 23 01 00 00\s+rclq\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 c0 d8 7b\s+rcr\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 c1 da 7b\s+rcr\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 c1 d9 7b\s+rcr\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 c1 df 7b\s+rcr\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 c0 9c 80 23 01 00 00 7b\s+rcrb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 c1 9c 80 23 01 00 00 7b\s+rcrw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 c1 9c 80 23 01 00 00 7b\s+rcrl\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 c1 9c 80 23 01 00 00 7b\s+rcrq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 c1 9c 87 23 01 00 00 7b\s+rcrw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 c1 9c 87 23 01 00 00 7b\s+rcrl\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 c1 9c 87 23 01 00 00 7b\s+rcrq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d0 d8\s+rcr\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 d1 da\s+rcr\s+%r18w +\s*[a-f0-9]+:\s*d5 11 d1 d9\s+rcr\s+%r25d +\s*[a-f0-9]+:\s*d5 19 d1 df\s+rcr\s+%r31 +\s*[a-f0-9]+:\s*d5 10 d0 9c 80 23 01 00 00\s+rcrb\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d1 9c 80 23 01 00 00\s+rcrw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d1 9c 80 23 01 00 00\s+rcrl\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d1 9c 80 23 01 00 00\s+rcrq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d1 9c 87 23 01 00 00\s+rcrw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d1 9c 87 23 01 00 00\s+rcrl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d1 9c 87 23 01 00 00\s+rcrq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d2 d8\s+rcr\s+%cl,%r16b +\s*[a-f0-9]+:\s*66 d5 10 d3 da\s+rcr\s+%cl,%r18w +\s*[a-f0-9]+:\s*d5 11 d3 d9\s+rcr\s+%cl,%r25d +\s*[a-f0-9]+:\s*d5 19 d3 df\s+rcr\s+%cl,%r31 +\s*[a-f0-9]+:\s*d5 10 d2 9c 80 23 01 00 00\s+rcrb\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d3 9c 80 23 01 00 00\s+rcrw\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d3 9c 80 23 01 00 00\s+rcrl\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d3 9c 80 23 01 00 00\s+rcrq\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d3 9c 87 23 01 00 00\s+rcrw\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d3 9c 87 23 01 00 00\s+rcrl\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d3 9c 87 23 01 00 00\s+rcrq\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 c0 c0 7b\s+rol\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 c1 c2 7b\s+rol\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 c1 c1 7b\s+rol\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 c1 c7 7b\s+rol\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 c0 84 80 23 01 00 00 7b\s+rolb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 c1 84 80 23 01 00 00 7b\s+rolw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 c1 84 80 23 01 00 00 7b\s+roll\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 c1 84 80 23 01 00 00 7b\s+rolq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 c1 84 87 23 01 00 00 7b\s+rolw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 c1 84 87 23 01 00 00 7b\s+roll\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 c1 84 87 23 01 00 00 7b\s+rolq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d0 c0\s+rol\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 d1 c2\s+rol\s+%r18w +\s*[a-f0-9]+:\s*d5 11 d1 c1\s+rol\s+%r25d +\s*[a-f0-9]+:\s*d5 19 d1 c7\s+rol\s+%r31 +\s*[a-f0-9]+:\s*d5 10 d0 84 80 23 01 00 00\s+rolb\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d1 84 80 23 01 00 00\s+rolw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d1 84 80 23 01 00 00\s+roll\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d1 84 80 23 01 00 00\s+rolq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d1 84 87 23 01 00 00\s+rolw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d1 84 87 23 01 00 00\s+roll\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d1 84 87 23 01 00 00\s+rolq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d2 c0\s+rol\s+%cl,%r16b +\s*[a-f0-9]+:\s*66 d5 10 d3 c2\s+rol\s+%cl,%r18w +\s*[a-f0-9]+:\s*d5 11 d3 c1\s+rol\s+%cl,%r25d +\s*[a-f0-9]+:\s*d5 19 d3 c7\s+rol\s+%cl,%r31 +\s*[a-f0-9]+:\s*d5 10 d2 84 80 23 01 00 00\s+rolb\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d3 84 80 23 01 00 00\s+rolw\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d3 84 80 23 01 00 00\s+roll\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d3 84 80 23 01 00 00\s+rolq\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d3 84 87 23 01 00 00\s+rolw\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d3 84 87 23 01 00 00\s+roll\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d3 84 87 23 01 00 00\s+rolq\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 c0 c8 7b\s+ror\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 c1 ca 7b\s+ror\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 c1 c9 7b\s+ror\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 c1 cf 7b\s+ror\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 c0 8c 80 23 01 00 00 7b\s+rorb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 c1 8c 80 23 01 00 00 7b\s+rorw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 c1 8c 80 23 01 00 00 7b\s+rorl\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 c1 8c 80 23 01 00 00 7b\s+rorq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 c1 8c 87 23 01 00 00 7b\s+rorw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 c1 8c 87 23 01 00 00 7b\s+rorl\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 c1 8c 87 23 01 00 00 7b\s+rorq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d0 c8\s+ror\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 d1 ca\s+ror\s+%r18w +\s*[a-f0-9]+:\s*d5 11 d1 c9\s+ror\s+%r25d +\s*[a-f0-9]+:\s*d5 19 d1 cf\s+ror\s+%r31 +\s*[a-f0-9]+:\s*d5 10 d0 8c 80 23 01 00 00\s+rorb\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d1 8c 80 23 01 00 00\s+rorw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d1 8c 80 23 01 00 00\s+rorl\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d1 8c 80 23 01 00 00\s+rorq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d1 8c 87 23 01 00 00\s+rorw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d1 8c 87 23 01 00 00\s+rorl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d1 8c 87 23 01 00 00\s+rorq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d2 c8\s+ror\s+%cl,%r16b +\s*[a-f0-9]+:\s*66 d5 10 d3 ca\s+ror\s+%cl,%r18w +\s*[a-f0-9]+:\s*d5 11 d3 c9\s+ror\s+%cl,%r25d +\s*[a-f0-9]+:\s*d5 19 d3 cf\s+ror\s+%cl,%r31 +\s*[a-f0-9]+:\s*d5 10 d2 8c 80 23 01 00 00\s+rorb\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d3 8c 80 23 01 00 00\s+rorw\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d3 8c 80 23 01 00 00\s+rorl\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d3 8c 80 23 01 00 00\s+rorq\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d3 8c 87 23 01 00 00\s+rorw\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d3 8c 87 23 01 00 00\s+rorl\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d3 8c 87 23 01 00 00\s+rorq\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 db 7f 08 f0 d1 7b\s+rorx\s+\$0x7b,%r25d,%edx +\s*[a-f0-9]+:\s*62 5b ff 08 f0 ff 7b\s+rorx\s+\$0x7b,%r31,%r15 +\s*[a-f0-9]+:\s*62 4b 7f 08 f0 8c 87 23 01 00 00 7b\s+rorx\s+\$0x7b,0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*62 4b ff 08 f0 bc 87 23 01 00 00 7b\s+rorx\s+\$0x7b,0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*d5 10 c0 f8 7b\s+sar\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 c1 fa 7b\s+sar\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 c1 f9 7b\s+sar\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 c1 ff 7b\s+sar\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 c0 bc 80 23 01 00 00 7b\s+sarb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 c1 bc 80 23 01 00 00 7b\s+sarw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 c1 bc 80 23 01 00 00 7b\s+sarl\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 c1 bc 80 23 01 00 00 7b\s+sarq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 c1 bc 87 23 01 00 00 7b\s+sarw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 c1 bc 87 23 01 00 00 7b\s+sarl\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 c1 bc 87 23 01 00 00 7b\s+sarq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d0 f8\s+sar\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 d1 fa\s+sar\s+%r18w +\s*[a-f0-9]+:\s*d5 11 d1 f9\s+sar\s+%r25d +\s*[a-f0-9]+:\s*d5 19 d1 ff\s+sar\s+%r31 +\s*[a-f0-9]+:\s*d5 10 d0 bc 80 23 01 00 00\s+sarb\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d1 bc 80 23 01 00 00\s+sarw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d1 bc 80 23 01 00 00\s+sarl\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d1 bc 80 23 01 00 00\s+sarq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d1 bc 87 23 01 00 00\s+sarw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d1 bc 87 23 01 00 00\s+sarl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d1 bc 87 23 01 00 00\s+sarq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d2 f8\s+sar\s+%cl,%r16b +\s*[a-f0-9]+:\s*66 d5 10 d3 fa\s+sar\s+%cl,%r18w +\s*[a-f0-9]+:\s*d5 11 d3 f9\s+sar\s+%cl,%r25d +\s*[a-f0-9]+:\s*d5 19 d3 ff\s+sar\s+%cl,%r31 +\s*[a-f0-9]+:\s*d5 10 d2 bc 80 23 01 00 00\s+sarb\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d3 bc 80 23 01 00 00\s+sarw\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d3 bc 80 23 01 00 00\s+sarl\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d3 bc 80 23 01 00 00\s+sarq\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d3 bc 87 23 01 00 00\s+sarw\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d3 bc 87 23 01 00 00\s+sarl\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d3 bc 87 23 01 00 00\s+sarq\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 72 36 00 f7 d2\s+sarx\s+%r25d,%edx,%r10d +\s*[a-f0-9]+:\s*62 da 36 00 f7 94 87 23 01 00 00\s+sarx\s+%r25d,0x123\(%r31,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 52 86 00 f7 df\s+sarx\s+%r31,%r15,%r11 +\s*[a-f0-9]+:\s*62 5a 86 00 f7 bc 87 23 01 00 00\s+sarx\s+%r31,0x123\(%r31,%rax,4\),%r15 +\s*[a-f0-9]+:\s*d5 10 80 d8 7b\s+sbb\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 83 da 7b\s+sbb\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 83 d9 7b\s+sbb\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 83 df 7b\s+sbb\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 80 9c 80 23 01 00 00 7b\s+sbbb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 83 9c 80 23 01 00 00 7b\s+sbbw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 83 9c 80 23 01 00 00 7b\s+sbbl\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 83 9c 80 23 01 00 00 7b\s+sbbq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 83 9c 87 23 01 00 00 7b\s+sbbw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 83 9c 87 23 01 00 00 7b\s+sbbl\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 83 9c 87 23 01 00 00 7b\s+sbbq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 40 18 c2\s+sbb\s+%r16b,%dl +\s*[a-f0-9]+:\s*d5 51 18 84 87 23 01 00 00\s+sbb\s+%r16b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 40 19 d0\s+sbb\s+%r18w,%ax +\s*[a-f0-9]+:\s*66 d5 50 19 94 80 23 01 00 00\s+sbb\s+%r18w,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 51 19 94 87 23 01 00 00\s+sbb\s+%r18w,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 44 19 ca\s+sbb\s+%r25d,%edx +\s*[a-f0-9]+:\s*d5 55 19 8c 87 23 01 00 00\s+sbb\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 4d 19 ff\s+sbb\s+%r31,%r15 +\s*[a-f0-9]+:\s*d5 5d 19 bc 87 23 01 00 00\s+sbb\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 50 1a 84 80 23 01 00 00\s+sbb\s+0x123\(%r16,%rax,4\),%r16b +\s*[a-f0-9]+:\s*d5 5c 1b bc 80 23 01 00 00\s+sbb\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*66 d5 51 1b 94 87 23 01 00 00\s+sbb\s+0x123\(%r31,%rax,4\),%r18w +\s*[a-f0-9]+:\s*d5 55 1b 8c 87 23 01 00 00\s+sbb\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*d5 5d 1b bc 87 23 01 00 00\s+sbb\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 a4 7c 08 d9 f7\s+sha1msg1\s+%xmm23,%xmm22 +\s*[a-f0-9]+:\s*62 cc 7c 08 d9 b4 87 23 01 00 00\s+sha1msg1\s+0x123\(%r31,%rax,4\),%xmm22 +\s*[a-f0-9]+:\s*62 a4 7c 08 da f7\s+sha1msg2\s+%xmm23,%xmm22 +\s*[a-f0-9]+:\s*62 cc 7c 08 da b4 87 23 01 00 00\s+sha1msg2\s+0x123\(%r31,%rax,4\),%xmm22 +\s*[a-f0-9]+:\s*62 a4 7c 08 d8 f7\s+sha1nexte\s+%xmm23,%xmm22 +\s*[a-f0-9]+:\s*62 cc 7c 08 d8 b4 87 23 01 00 00\s+sha1nexte\s+0x123\(%r31,%rax,4\),%xmm22 +\s*[a-f0-9]+:\s*62 a4 7c 08 d4 f7 7b\s+sha1rnds4\s+\$0x7b,%xmm23,%xmm22 +\s*[a-f0-9]+:\s*62 cc 7c 08 d4 b4 87 23 01 00 00 7b\s+sha1rnds4\s+\$0x7b,0x123\(%r31,%rax,4\),%xmm22 +\s*[a-f0-9]+:\s*62 a4 7c 08 dc f7\s+sha256msg1\s+%xmm23,%xmm22 +\s*[a-f0-9]+:\s*62 cc 7c 08 dc b4 87 23 01 00 00\s+sha256msg1\s+0x123\(%r31,%rax,4\),%xmm22 +\s*[a-f0-9]+:\s*62 a4 7c 08 dd f7\s+sha256msg2\s+%xmm23,%xmm22 +\s*[a-f0-9]+:\s*62 cc 7c 08 dd b4 87 23 01 00 00\s+sha256msg2\s+0x123\(%r31,%rax,4\),%xmm22 +\s*[a-f0-9]+:\s*62 5c 7c 08 db a4 87 23 01 00 00\s+sha256rnds2\s+%xmm0,0x123\(%r31,%rax,4\),%xmm12 +\s*[a-f0-9]+:\s*d5 10 c0 e0 7b\s+shl\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 c1 e2 7b\s+shl\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 c1 e1 7b\s+shl\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 c1 e7 7b\s+shl\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 c0 a4 80 23 01 00 00 7b\s+shlb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 c1 a4 80 23 01 00 00 7b\s+shlw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 c1 a4 80 23 01 00 00 7b\s+shll\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 c1 a4 80 23 01 00 00 7b\s+shlq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 c0 a4 87 23 01 00 00 7b\s+shlb\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 c1 a4 87 23 01 00 00 7b\s+shlw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 c1 a4 87 23 01 00 00 7b\s+shll\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 c1 a4 87 23 01 00 00 7b\s+shlq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d0 e0\s+shl\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 d1 e2\s+shl\s+%r18w +\s*[a-f0-9]+:\s*d5 11 d1 e1\s+shl\s+%r25d +\s*[a-f0-9]+:\s*d5 19 d1 e7\s+shl\s+%r31 +\s*[a-f0-9]+:\s*d5 10 d0 a4 80 23 01 00 00\s+shlb\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d1 a4 80 23 01 00 00\s+shlw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d1 a4 80 23 01 00 00\s+shll\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d1 a4 80 23 01 00 00\s+shlq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d1 a4 87 23 01 00 00\s+shlw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d1 a4 87 23 01 00 00\s+shll\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d1 a4 87 23 01 00 00\s+shlq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d2 e0\s+shl\s+%cl,%r16b +\s*[a-f0-9]+:\s*66 d5 10 d3 e2\s+shl\s+%cl,%r18w +\s*[a-f0-9]+:\s*d5 11 d3 e1\s+shl\s+%cl,%r25d +\s*[a-f0-9]+:\s*d5 19 d3 e7\s+shl\s+%cl,%r31 +\s*[a-f0-9]+:\s*d5 10 d2 a4 80 23 01 00 00\s+shlb\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d3 a4 80 23 01 00 00\s+shlw\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d3 a4 80 23 01 00 00\s+shll\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d3 a4 80 23 01 00 00\s+shlq\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d2 a4 87 23 01 00 00\s+shlb\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d3 a4 87 23 01 00 00\s+shlw\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d3 a4 87 23 01 00 00\s+shll\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d3 a4 87 23 01 00 00\s+shlq\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 c0 a4 d0 7b\s+shld\s+\$0x7b,%r18w,%ax +\s*[a-f0-9]+:\s*66 d5 d1 a4 94 87 23 01 00 00 7b\s+shld\s+\$0x7b,%r18w,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 c4 a4 ca 7b\s+shld\s+\$0x7b,%r25d,%edx +\s*[a-f0-9]+:\s*d5 d5 a4 8c 87 23 01 00 00 7b\s+shld\s+\$0x7b,%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 cd a4 ff 7b\s+shld\s+\$0x7b,%r31,%r15 +\s*[a-f0-9]+:\s*d5 dc a4 bc 80 23 01 00 00 7b\s+shld\s+\$0x7b,%r31,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 c0 a5 d0\s+shld\s+%cl,%r18w,%ax +\s*[a-f0-9]+:\s*66 d5 d0 a5 94 80 23 01 00 00\s+shld\s+%cl,%r18w,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 c4 a5 ca\s+shld\s+%cl,%r25d,%edx +\s*[a-f0-9]+:\s*d5 d4 a5 8c 80 23 01 00 00\s+shld\s+%cl,%r25d,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 d5 a5 8c 87 23 01 00 00\s+shld\s+%cl,%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 cd a5 ff\s+shld\s+%cl,%r31,%r15 +\s*[a-f0-9]+:\s*d5 dd a5 bc 87 23 01 00 00\s+shld\s+%cl,%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 72 35 00 f7 d2\s+shlx\s+%r25d,%edx,%r10d +\s*[a-f0-9]+:\s*62 da 35 00 f7 94 87 23 01 00 00\s+shlx\s+%r25d,0x123\(%r31,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 52 85 00 f7 df\s+shlx\s+%r31,%r15,%r11 +\s*[a-f0-9]+:\s*62 5a 85 00 f7 bc 87 23 01 00 00\s+shlx\s+%r31,0x123\(%r31,%rax,4\),%r15 +\s*[a-f0-9]+:\s*d5 10 c0 e8 7b\s+shr\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 c1 ea 7b\s+shr\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 c1 e9 7b\s+shr\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 c1 ef 7b\s+shr\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 c0 ac 80 23 01 00 00 7b\s+shrb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 c1 ac 80 23 01 00 00 7b\s+shrw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 c1 ac 80 23 01 00 00 7b\s+shrl\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 c1 ac 80 23 01 00 00 7b\s+shrq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 c1 ac 87 23 01 00 00 7b\s+shrw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 c1 ac 87 23 01 00 00 7b\s+shrl\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 c1 ac 87 23 01 00 00 7b\s+shrq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d0 e8\s+shr\s+%r16b +\s*[a-f0-9]+:\s*66 d5 10 d1 ea\s+shr\s+%r18w +\s*[a-f0-9]+:\s*d5 11 d1 e9\s+shr\s+%r25d +\s*[a-f0-9]+:\s*d5 19 d1 ef\s+shr\s+%r31 +\s*[a-f0-9]+:\s*d5 10 d0 ac 80 23 01 00 00\s+shrb\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d1 ac 80 23 01 00 00\s+shrw\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d1 ac 80 23 01 00 00\s+shrl\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d1 ac 80 23 01 00 00\s+shrq\s+0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d1 ac 87 23 01 00 00\s+shrw\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d1 ac 87 23 01 00 00\s+shrl\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d1 ac 87 23 01 00 00\s+shrq\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d2 e8\s+shr\s+%cl,%r16b +\s*[a-f0-9]+:\s*66 d5 10 d3 ea\s+shr\s+%cl,%r18w +\s*[a-f0-9]+:\s*d5 11 d3 e9\s+shr\s+%cl,%r25d +\s*[a-f0-9]+:\s*d5 19 d3 ef\s+shr\s+%cl,%r31 +\s*[a-f0-9]+:\s*d5 10 d2 ac 80 23 01 00 00\s+shrb\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 d3 ac 80 23 01 00 00\s+shrw\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 d3 ac 80 23 01 00 00\s+shrl\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 d3 ac 80 23 01 00 00\s+shrq\s+%cl,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 d3 ac 87 23 01 00 00\s+shrw\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 d3 ac 87 23 01 00 00\s+shrl\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 d3 ac 87 23 01 00 00\s+shrq\s+%cl,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 c0 ac d0 7b\s+shrd\s+\$0x7b,%r18w,%ax +\s*[a-f0-9]+:\s*66 d5 d1 ac 94 87 23 01 00 00 7b\s+shrd\s+\$0x7b,%r18w,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 c4 ac ca 7b\s+shrd\s+\$0x7b,%r25d,%edx +\s*[a-f0-9]+:\s*d5 d5 ac 8c 87 23 01 00 00 7b\s+shrd\s+\$0x7b,%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 cd ac ff 7b\s+shrd\s+\$0x7b,%r31,%r15 +\s*[a-f0-9]+:\s*d5 dc ac bc 80 23 01 00 00 7b\s+shrd\s+\$0x7b,%r31,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 c0 ad d0\s+shrd\s+%cl,%r18w,%ax +\s*[a-f0-9]+:\s*66 d5 d0 ad 94 80 23 01 00 00\s+shrd\s+%cl,%r18w,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 c4 ad ca\s+shrd\s+%cl,%r25d,%edx +\s*[a-f0-9]+:\s*d5 d4 ad 8c 80 23 01 00 00\s+shrd\s+%cl,%r25d,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 d5 ad 8c 87 23 01 00 00\s+shrd\s+%cl,%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 cd ad ff\s+shrd\s+%cl,%r31,%r15 +\s*[a-f0-9]+:\s*d5 dd ad bc 87 23 01 00 00\s+shrd\s+%cl,%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 72 37 00 f7 d2\s+shrx\s+%r25d,%edx,%r10d +\s*[a-f0-9]+:\s*62 da 37 00 f7 94 87 23 01 00 00\s+shrx\s+%r25d,0x123\(%r31,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 52 87 00 f7 df\s+shrx\s+%r31,%r15,%r11 +\s*[a-f0-9]+:\s*62 5a 87 00 f7 bc 87 23 01 00 00\s+shrx\s+%r31,0x123\(%r31,%rax,4\),%r15 +\s*[a-f0-9]+:\s*62 da 7d 08 49 84 87 23 01 00 00\s+sttilecfg\s+0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 80 e8 7b\s+sub\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 83 ea 7b\s+sub\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 83 e9 7b\s+sub\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 83 ef 7b\s+sub\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 80 ac 80 23 01 00 00 7b\s+subb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 83 ac 80 23 01 00 00 7b\s+subw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 83 ac 80 23 01 00 00 7b\s+subl\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 83 ac 80 23 01 00 00 7b\s+subq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 83 ac 87 23 01 00 00 7b\s+subw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 83 ac 87 23 01 00 00 7b\s+subl\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 83 ac 87 23 01 00 00 7b\s+subq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 40 28 c2\s+sub\s+%r16b,%dl +\s*[a-f0-9]+:\s*d5 51 28 84 87 23 01 00 00\s+sub\s+%r16b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 40 29 d0\s+sub\s+%r18w,%ax +\s*[a-f0-9]+:\s*66 d5 50 29 94 80 23 01 00 00\s+sub\s+%r18w,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 51 29 94 87 23 01 00 00\s+sub\s+%r18w,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 44 29 ca\s+sub\s+%r25d,%edx +\s*[a-f0-9]+:\s*d5 55 29 8c 87 23 01 00 00\s+sub\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 4d 29 ff\s+sub\s+%r31,%r15 +\s*[a-f0-9]+:\s*d5 5d 29 bc 87 23 01 00 00\s+sub\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 50 2a 84 80 23 01 00 00\s+sub\s+0x123\(%r16,%rax,4\),%r16b +\s*[a-f0-9]+:\s*d5 5c 2b bc 80 23 01 00 00\s+sub\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*66 d5 51 2b 94 87 23 01 00 00\s+sub\s+0x123\(%r31,%rax,4\),%r18w +\s*[a-f0-9]+:\s*d5 55 2b 8c 87 23 01 00 00\s+sub\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*d5 5d 2b bc 87 23 01 00 00\s+sub\s+0x123\(%r31,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 da 7f 08 4b b4 87 23 01 00 00\s+tileloadd\s+0x123\(%r31,%rax,4\),%tmm6 +\s*[a-f0-9]+:\s*62 da 7d 08 4b b4 87 23 01 00 00\s+tileloaddt1\s+0x123\(%r31,%rax,4\),%tmm6 +\s*[a-f0-9]+:\s*62 da 7e 08 4b b4 87 23 01 00 00\s+tilestored\s+%tmm6,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 f3 d5 90 bc c2\s+tzcnt\s+%r18w,%ax +\s*[a-f0-9]+:\s*f3 d5 91 bc d1\s+tzcnt\s+%r25d,%edx +\s*[a-f0-9]+:\s*f3 d5 9d bc ff\s+tzcnt\s+%r31,%r15 +\s*[a-f0-9]+:\s*66 f3 d5 d0 bc 94 80 23 01 00 00\s+tzcnt\s+0x123\(%r16,%rax,4\),%r18w +\s*[a-f0-9]+:\s*f3 d5 dc bc bc 80 23 01 00 00\s+tzcnt\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*66 f3 d5 d1 bc 94 87 23 01 00 00\s+tzcnt\s+0x123\(%r31,%rax,4\),%r18w +\s*[a-f0-9]+:\s*f3 d5 d5 bc 8c 87 23 01 00 00\s+tzcnt\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*62 4c 7c 08 66 8c 87 23 01 00 00\s+wrssd\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 4c fc 08 66 bc 87 23 01 00 00\s+wrssq\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 4c 7d 08 65 8c 87 23 01 00 00\s+wrussd\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*62 4c fd 08 65 bc 87 23 01 00 00\s+wrussq\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 80 f0 7b\s+xor\s+\$0x7b,%r16b +\s*[a-f0-9]+:\s*66 d5 10 83 f2 7b\s+xor\s+\$0x7b,%r18w +\s*[a-f0-9]+:\s*d5 11 83 f1 7b\s+xor\s+\$0x7b,%r25d +\s*[a-f0-9]+:\s*d5 19 83 f7 7b\s+xor\s+\$0x7b,%r31 +\s*[a-f0-9]+:\s*d5 10 80 b4 80 23 01 00 00 7b\s+xorb\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 10 83 b4 80 23 01 00 00 7b\s+xorw\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 10 83 b4 80 23 01 00 00 7b\s+xorl\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*d5 18 83 b4 80 23 01 00 00 7b\s+xorq\s+\$0x7b,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 11 83 b4 87 23 01 00 00 7b\s+xorw\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 11 83 b4 87 23 01 00 00 7b\s+xorl\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 19 83 b4 87 23 01 00 00 7b\s+xorq\s+\$0x7b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 40 30 c2\s+xor\s+%r16b,%dl +\s*[a-f0-9]+:\s*d5 51 30 84 87 23 01 00 00\s+xor\s+%r16b,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 40 31 d0\s+xor\s+%r18w,%ax +\s*[a-f0-9]+:\s*66 d5 50 31 94 80 23 01 00 00\s+xor\s+%r18w,0x123\(%r16,%rax,4\) +\s*[a-f0-9]+:\s*66 d5 51 31 94 87 23 01 00 00\s+xor\s+%r18w,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 44 31 ca\s+xor\s+%r25d,%edx +\s*[a-f0-9]+:\s*d5 55 31 8c 87 23 01 00 00\s+xor\s+%r25d,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 4d 31 ff\s+xor\s+%r31,%r15 +\s*[a-f0-9]+:\s*d5 5d 31 bc 87 23 01 00 00\s+xor\s+%r31,0x123\(%r31,%rax,4\) +\s*[a-f0-9]+:\s*d5 50 32 84 80 23 01 00 00\s+xor\s+0x123\(%r16,%rax,4\),%r16b +\s*[a-f0-9]+:\s*d5 5c 33 bc 80 23 01 00 00\s+xor\s+0x123\(%r16,%rax,4\),%r31 +\s*[a-f0-9]+:\s*66 d5 51 33 94 87 23 01 00 00\s+xor\s+0x123\(%r31,%rax,4\),%r18w +\s*[a-f0-9]+:\s*d5 55 33 8c 87 23 01 00 00\s+xor\s+0x123\(%r31,%rax,4\),%r25d +\s*[a-f0-9]+:\s*d5 5d 33 bc 87 23 01 00 00\s+xor\s+0x123\(%r31,%rax,4\),%r31 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s new file mode 100644 index 00000000000..9a17c18e363 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s @@ -0,0 +1,1464 @@ +# Check 64bit APX_F EVEX-Promoted instructions. + + .text +_start: + aadd %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + aadd %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + aand %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + aand %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + adc $0x7b,%r16b #APX_F OPC_EVEX_EVEX + adc $0x7b,%r18w #APX_F OPC_EVEX_EVEX + adc $0x7b,%r25d #APX_F OPC_EVEX_EVEX + adc $0x7b,%r31 #APX_F OPC_EVEX_EVEX + adcb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + adcw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + adcl $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + adcq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + adcw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + adcl $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + adcq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + adc %r16b,%dl #APX_F OPC_EVEX_EVEX + adc %r16b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + adc %r18w,%ax #APX_F OPC_EVEX_EVEX + adc %r18w,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + adc %r18w,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + adc %r25d,%edx #APX_F OPC_EVEX_EVEX + adc %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + adc %r31,%r15 #APX_F OPC_EVEX_EVEX + adc %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + adc 0x123(%r16,%rax,4),%r16b #APX_F OPC_EVEX_EVEX + adc 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + adc 0x123(%r31,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + adc 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + adc 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + adcx %r25d,%edx #APX_F OPC_EVEX_EVEX + adcx %r31,%r15 #APX_F OPC_EVEX_EVEX + adcx 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + adcx 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + add $0x7b,%r16b #APX_F OPC_EVEX_EVEX + add $0x7b,%r18w #APX_F OPC_EVEX_EVEX + add $0x7b,%r25d #APX_F OPC_EVEX_EVEX + add $0x7b,%r31 #APX_F OPC_EVEX_EVEX + addb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + addw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + addl $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + addq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + addw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + addl $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + addq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + add %r16b,%dl #APX_F OPC_EVEX_EVEX + add %r16b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + add %r18w,%ax #APX_F OPC_EVEX_EVEX + add %r18w,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + add %r18w,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + add %r25d,%edx #APX_F OPC_EVEX_EVEX + add %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + add %r31,%r15 #APX_F OPC_EVEX_EVEX + add %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + add 0x123(%r16,%rax,4),%r16b #APX_F OPC_EVEX_EVEX + add 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + add 0x123(%r31,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + add 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + add 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + adox %r25d,%edx #APX_F OPC_EVEX_EVEX + adox %r31,%r15 #APX_F OPC_EVEX_EVEX + adox 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + adox 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + aesdec128kl 0x123(%r31,%rax,4),%xmm22 #APX_F OPC_EVEX_EVEX + aesdec256kl 0x123(%r31,%rax,4),%xmm22 #APX_F OPC_EVEX_EVEX + aesdecwide128kl 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + aesdecwide256kl 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + aesenc128kl 0x123(%r31,%rax,4),%xmm22 #APX_F OPC_EVEX_EVEX + aesenc256kl 0x123(%r31,%rax,4),%xmm22 #APX_F OPC_EVEX_EVEX + aesencwide128kl 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + aesencwide256kl 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + and $0x7b,%r16b #APX_F OPC_EVEX_EVEX + and $0x7b,%r18w #APX_F OPC_EVEX_EVEX + and $0x7b,%r25d #APX_F OPC_EVEX_EVEX + and $0x7b,%r31 #APX_F OPC_EVEX_EVEX + andb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + andw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + andl $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + andq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + andw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + andl $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + andq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + and %r16b,%dl #APX_F OPC_EVEX_EVEX + and %r16b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + and %r18w,%ax #APX_F OPC_EVEX_EVEX + and %r18w,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + and %r18w,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + and %r25d,%edx #APX_F OPC_EVEX_EVEX + and %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + and %r31,%r15 #APX_F OPC_EVEX_EVEX + and %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + and 0x123(%r16,%rax,4),%r16b #APX_F OPC_EVEX_EVEX + and 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + and 0x123(%r31,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + and 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + and 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + andn %r25d,%edx,%r10d #APX_F OPC_EVEX_EVEX + andn %r31,%r15,%r11 #APX_F OPC_EVEX_EVEX + andn 0x123(%r31,%rax,4),%r25d,%edx #APX_F OPC_EVEX_EVEX + andn 0x123(%r31,%rax,4),%r31,%r15 #APX_F OPC_EVEX_EVEX + aor %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + aor %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + axor %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + axor %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + bextr %r25d,%edx,%r10d #APX_F OPC_EVEX_EVEX + bextr %r25d,0x123(%r31,%rax,4),%edx #APX_F OPC_EVEX_EVEX + bextr %r31,%r15,%r11 #APX_F OPC_EVEX_EVEX + bextr %r31,0x123(%r31,%rax,4),%r15 #APX_F OPC_EVEX_EVEX + blsi %r25d,%edx #APX_F OPC_EVEX_EVEX + blsi %r31,%r15 #APX_F OPC_EVEX_EVEX + blsi 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + blsi 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + blsmsk %r25d,%edx #APX_F OPC_EVEX_EVEX + blsmsk %r31,%r15 #APX_F OPC_EVEX_EVEX + blsmsk 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + blsmsk 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + blsr %r25d,%edx #APX_F OPC_EVEX_EVEX + blsr %r31,%r15 #APX_F OPC_EVEX_EVEX + blsr 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + blsr 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + bzhi %r25d,%edx,%r10d #APX_F OPC_EVEX_EVEX + bzhi %r25d,0x123(%r31,%rax,4),%edx #APX_F OPC_EVEX_EVEX + bzhi %r31,%r15,%r11 #APX_F OPC_EVEX_EVEX + bzhi %r31,0x123(%r31,%rax,4),%r15 #APX_F OPC_EVEX_EVEX + cmpbexadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpbexadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpbxadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpbxadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmplxadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmplxadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnbexadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnbexadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnbxadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnbxadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnlexadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnlexadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnlxadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnlxadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnoxadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnoxadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnpxadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnpxadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnsxadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnsxadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnzxadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpnzxadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpoxadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpoxadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmppxadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmppxadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpsxadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpsxadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpzxadd %r25d,%edx,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + cmpzxadd %r31,%r15,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + dec %r16b #APX_F OPC_EVEX_EVEX + dec %r18w #APX_F OPC_EVEX_EVEX + dec %r25d #APX_F OPC_EVEX_EVEX + dec %r31 #APX_F OPC_EVEX_EVEX + decw 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + decl 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + decq 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + decb 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + decw 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + decl 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + decq 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + div %r16b #APX_F OPC_EVEX_EVEX + div %r18w #APX_F OPC_EVEX_EVEX + div %r25d #APX_F OPC_EVEX_EVEX + div %r31 #APX_F OPC_EVEX_EVEX + divw 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + divl 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + divq 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + divb 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + divw 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + divl 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + divq 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + encodekey128 %r25d,%edx #APX_F OPC_EVEX_EVEX + encodekey256 %r25d,%edx #APX_F OPC_EVEX_EVEX + enqcmd 0x123(%r31d,%eax,4),%r25d #APX_F OPC_EVEX_EVEX + enqcmd 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + enqcmds 0x123(%r31d,%eax,4),%r25d #APX_F OPC_EVEX_EVEX + enqcmds 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + idiv %r16b #APX_F OPC_EVEX_EVEX + idiv %r18w #APX_F OPC_EVEX_EVEX + idiv %r25d #APX_F OPC_EVEX_EVEX + idiv %r31 #APX_F OPC_EVEX_EVEX + idivw 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + idivl 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + idivq 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + idivb 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + idivw 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + idivl 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + idivq 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + imul $0x7b,%r18w,%ax #APX_F + imul $0x7b,%r25d,%edx #APX_F + imul $0x7b,%r31,%r15 #APX_F + imul $0x7b,0x123(%r16,%rax,4),%r25d #APX_F + imul $0x7b,0x123(%r16,%rax,4),%r31 #APX_F + imul $0x7b,0x123(%r31,%rax,4),%r18w #APX_F + imul $0x7b,0x123(%r31,%rax,4),%r25d #APX_F + imul $0x7b,0x123(%r31,%rax,4),%r31 #APX_F + imul %r16b #APX_F OPC_EVEX_EVEX + imul %r18w #APX_F OPC_EVEX_EVEX + imul %r18w,%ax #APX_F OPC_EVEX_EVEX + imul %r25d #APX_F OPC_EVEX_EVEX + imul %r25d,%edx #APX_F OPC_EVEX_EVEX + imul %r31 #APX_F OPC_EVEX_EVEX + imul %r31,%r15 #APX_F OPC_EVEX_EVEX + imulb 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + imulw 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + imull 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + imul 0x123(%r16,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + imul 0x123(%r16,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + imul 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + imulq 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + imulw 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + imull 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + imulq 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + inc %r16b #APX_F OPC_EVEX_EVEX + inc %r18w #APX_F OPC_EVEX_EVEX + inc %r25d #APX_F OPC_EVEX_EVEX + inc %r31 #APX_F OPC_EVEX_EVEX + incw 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + incl 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + incq 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + incb 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + incw 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + incl 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + incq 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + invept 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + invpcid 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + invvpid 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + kmovb %k3,%k5 #APX_F OPC_EVEX_EVEX + kmovb %k5,%r25d #APX_F OPC_EVEX_EVEX + kmovb %k5,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + kmovb %r25d,%k5 #APX_F OPC_EVEX_EVEX + kmovb 0x123(%r31,%rax,4),%k5 #APX_F OPC_EVEX_EVEX + kmovd %k3,%k5 #APX_F OPC_EVEX_EVEX + kmovd %k5,%r25d #APX_F OPC_EVEX_EVEX + kmovd %k5,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + kmovd %r25d,%k5 #APX_F OPC_EVEX_EVEX + kmovd 0x123(%r31,%rax,4),%k5 #APX_F OPC_EVEX_EVEX + kmovq %k3,%k5 #APX_F OPC_EVEX_EVEX + kmovq %k5,%r31 #APX_F OPC_EVEX_EVEX + kmovq %k5,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + kmovq %r31,%k5 #APX_F OPC_EVEX_EVEX + kmovq 0x123(%r31,%rax,4),%k5 #APX_F OPC_EVEX_EVEX + kmovw %k3,%k5 #APX_F OPC_EVEX_EVEX + kmovw %k5,%r25d #APX_F OPC_EVEX_EVEX + kmovw %k5,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + kmovw %r25d,%k5 #APX_F OPC_EVEX_EVEX + kmovw 0x123(%r31,%rax,4),%k5 #APX_F OPC_EVEX_EVEX + ldtilecfg 0x123(%r31,%rax,4) #APX_F + lzcnt %r18w,%ax #APX_F OPC_EVEX_EVEX + lzcnt %r25d,%edx #APX_F OPC_EVEX_EVEX + lzcnt %r31,%r15 #APX_F OPC_EVEX_EVEX + lzcnt 0x123(%r16,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + lzcnt 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + lzcnt 0x123(%r31,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + lzcnt 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + movbe %r18w,%ax #APX_F OPC_EVEX_EVEX + movbe %r18w,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + movbe %r18w,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + movbe %r25d,%edx #APX_F OPC_EVEX_EVEX + movbe %r25d,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + movbe %r31,%r15 #APX_F OPC_EVEX_EVEX + movbe %r31,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + movbe %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + movbe 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + movbe 0x123(%r31,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + movbe 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + movdir64b 0x123(%r31d,%eax,4),%r25d #APX_F OPC_EVEX_EVEX + movdir64b 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + movdiri %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + movdiri %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + mul %r16b #APX_F OPC_EVEX_EVEX + mul %r18w #APX_F OPC_EVEX_EVEX + mul %r25d #APX_F OPC_EVEX_EVEX + mul %r31 #APX_F OPC_EVEX_EVEX + mulw 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + mull 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + mulq 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + mulb 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + mulw 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + mull 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + mulq 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + mulx %r25d,%edx,%r10d #APX_F OPC_EVEX_EVEX + mulx %r31,%r15,%r11 #APX_F OPC_EVEX_EVEX + mulx 0x123(%r31,%rax,4),%r25d,%edx #APX_F OPC_EVEX_EVEX + mulx 0x123(%r31,%rax,4),%r31,%r15 #APX_F OPC_EVEX_EVEX + neg %r16b #APX_F OPC_EVEX_EVEX + neg %r18w #APX_F OPC_EVEX_EVEX + neg %r25d #APX_F OPC_EVEX_EVEX + neg %r31 #APX_F OPC_EVEX_EVEX + negw 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + negl 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + negq 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + negb 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + negw 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + negl 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + negq 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + not %r16b #APX_F OPC_EVEX_EVEX + not %r18w #APX_F OPC_EVEX_EVEX + not %r25d #APX_F OPC_EVEX_EVEX + not %r31 #APX_F OPC_EVEX_EVEX + notw 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + notl 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + notq 0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + notb 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + notw 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + notl 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + notq 0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + or $0x7b,%r16b #APX_F OPC_EVEX_EVEX + or $0x7b,%r18w #APX_F OPC_EVEX_EVEX + or $0x7b,%r25d #APX_F OPC_EVEX_EVEX + or $0x7b,%r31 #APX_F OPC_EVEX_EVEX + orb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + orw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + orl $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + orq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + orw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + orl $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + orq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + or %r16b,%dl #APX_F OPC_EVEX_EVEX + or %r16b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + or %r18w,%ax #APX_F OPC_EVEX_EVEX + or %r18w,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + or %r18w,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + or %r25d,%edx #APX_F OPC_EVEX_EVEX + or %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + or %r31,%r15 #APX_F OPC_EVEX_EVEX + or %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + or 0x123(%r16,%rax,4),%r16b #APX_F OPC_EVEX_EVEX + or 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + or 0x123(%r31,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + or 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + or 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + pdep %r25d,%edx,%r10d #APX_F OPC_EVEX_EVEX + pdep %r31,%r15,%r11 #APX_F OPC_EVEX_EVEX + pdep 0x123(%r31,%rax,4),%r25d,%edx #APX_F OPC_EVEX_EVEX + pdep 0x123(%r31,%rax,4),%r31,%r15 #APX_F OPC_EVEX_EVEX + pext %r25d,%edx,%r10d #APX_F OPC_EVEX_EVEX + pext %r31,%r15,%r11 #APX_F OPC_EVEX_EVEX + pext 0x123(%r31,%rax,4),%r25d,%edx #APX_F OPC_EVEX_EVEX + pext 0x123(%r31,%rax,4),%r31,%r15 #APX_F OPC_EVEX_EVEX + popcnt %r18w,%ax #APX_F OPC_EVEX_EVEX + popcnt %r25d,%edx #APX_F OPC_EVEX_EVEX + popcnt %r31,%r15 #APX_F OPC_EVEX_EVEX + popcnt 0x123(%r16,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + popcnt 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + popcnt 0x123(%r31,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + popcnt 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + rcl $0x7b,%r16b #APX_F OPC_EVEX_EVEX + rcl $0x7b,%r18w #APX_F OPC_EVEX_EVEX + rcl $0x7b,%r25d #APX_F OPC_EVEX_EVEX + rcl $0x7b,%r31 #APX_F OPC_EVEX_EVEX + rclb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rclw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcll $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rclq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rclw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcll $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rclq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcl $1,%r16b #APX_F OPC_EVEX_EVEX + rcl $1,%r18w #APX_F OPC_EVEX_EVEX + rcl $1,%r25d #APX_F OPC_EVEX_EVEX + rcl $1,%r31 #APX_F OPC_EVEX_EVEX + rclb $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rclw $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcll $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rclq $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rclw $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcll $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rclq $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcl %cl,%r16b #APX_F OPC_EVEX_EVEX + rcl %cl,%r18w #APX_F OPC_EVEX_EVEX + rcl %cl,%r25d #APX_F OPC_EVEX_EVEX + rcl %cl,%r31 #APX_F OPC_EVEX_EVEX + rclb %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rclw %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcll %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rclq %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rclw %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcll %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rclq %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcr $0x7b,%r16b #APX_F OPC_EVEX_EVEX + rcr $0x7b,%r18w #APX_F OPC_EVEX_EVEX + rcr $0x7b,%r25d #APX_F OPC_EVEX_EVEX + rcr $0x7b,%r31 #APX_F OPC_EVEX_EVEX + rcrb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcrw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcrl $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcrq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcrw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcrl $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcrq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcr $1,%r16b #APX_F OPC_EVEX_EVEX + rcr $1,%r18w #APX_F OPC_EVEX_EVEX + rcr $1,%r25d #APX_F OPC_EVEX_EVEX + rcr $1,%r31 #APX_F OPC_EVEX_EVEX + rcrb $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcrw $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcrl $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcrq $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcrw $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcrl $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcrq $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcr %cl,%r16b #APX_F OPC_EVEX_EVEX + rcr %cl,%r18w #APX_F OPC_EVEX_EVEX + rcr %cl,%r25d #APX_F OPC_EVEX_EVEX + rcr %cl,%r31 #APX_F OPC_EVEX_EVEX + rcrb %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcrw %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcrl %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcrq %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rcrw %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcrl %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rcrq %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rol $0x7b,%r16b #APX_F OPC_EVEX_EVEX + rol $0x7b,%r18w #APX_F OPC_EVEX_EVEX + rol $0x7b,%r25d #APX_F OPC_EVEX_EVEX + rol $0x7b,%r31 #APX_F OPC_EVEX_EVEX + rolb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rolw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + roll $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rolq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rolw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + roll $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rolq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rol $1,%r16b #APX_F OPC_EVEX_EVEX + rol $1,%r18w #APX_F OPC_EVEX_EVEX + rol $1,%r25d #APX_F OPC_EVEX_EVEX + rol $1,%r31 #APX_F OPC_EVEX_EVEX + rolb $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rolw $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + roll $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rolq $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rolw $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + roll $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rolq $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rol %cl,%r16b #APX_F OPC_EVEX_EVEX + rol %cl,%r18w #APX_F OPC_EVEX_EVEX + rol %cl,%r25d #APX_F OPC_EVEX_EVEX + rol %cl,%r31 #APX_F OPC_EVEX_EVEX + rolb %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rolw %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + roll %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rolq %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rolw %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + roll %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rolq %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + ror $0x7b,%r16b #APX_F OPC_EVEX_EVEX + ror $0x7b,%r18w #APX_F OPC_EVEX_EVEX + ror $0x7b,%r25d #APX_F OPC_EVEX_EVEX + ror $0x7b,%r31 #APX_F OPC_EVEX_EVEX + rorb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rorw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rorl $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rorq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rorw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rorl $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rorq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + ror $1,%r16b #APX_F OPC_EVEX_EVEX + ror $1,%r18w #APX_F OPC_EVEX_EVEX + ror $1,%r25d #APX_F OPC_EVEX_EVEX + ror $1,%r31 #APX_F OPC_EVEX_EVEX + rorb $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rorw $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rorl $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rorq $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rorw $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rorl $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rorq $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + ror %cl,%r16b #APX_F OPC_EVEX_EVEX + ror %cl,%r18w #APX_F OPC_EVEX_EVEX + ror %cl,%r25d #APX_F OPC_EVEX_EVEX + ror %cl,%r31 #APX_F OPC_EVEX_EVEX + rorb %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rorw %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rorl %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rorq %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + rorw %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rorl %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rorq %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + rorx $0x7b,%r25d,%edx #APX_F OPC_EVEX_EVEX + rorx $0x7b,%r31,%r15 #APX_F OPC_EVEX_EVEX + rorx $0x7b,0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + rorx $0x7b,0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + sar $0x7b,%r16b #APX_F OPC_EVEX_EVEX + sar $0x7b,%r18w #APX_F OPC_EVEX_EVEX + sar $0x7b,%r25d #APX_F OPC_EVEX_EVEX + sar $0x7b,%r31 #APX_F OPC_EVEX_EVEX + sarb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sarw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sarl $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sarq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sarw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sarl $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sarq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sar $1,%r16b #APX_F OPC_EVEX_EVEX + sar $1,%r18w #APX_F OPC_EVEX_EVEX + sar $1,%r25d #APX_F OPC_EVEX_EVEX + sar $1,%r31 #APX_F OPC_EVEX_EVEX + sarb $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sarw $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sarl $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sarq $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sarw $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sarl $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sarq $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sar %cl,%r16b #APX_F OPC_EVEX_EVEX + sar %cl,%r18w #APX_F OPC_EVEX_EVEX + sar %cl,%r25d #APX_F OPC_EVEX_EVEX + sar %cl,%r31 #APX_F OPC_EVEX_EVEX + sarb %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sarw %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sarl %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sarq %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sarw %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sarl %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sarq %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sarx %r25d,%edx,%r10d #APX_F OPC_EVEX_EVEX + sarx %r25d,0x123(%r31,%rax,4),%edx #APX_F OPC_EVEX_EVEX + sarx %r31,%r15,%r11 #APX_F OPC_EVEX_EVEX + sarx %r31,0x123(%r31,%rax,4),%r15 #APX_F OPC_EVEX_EVEX + sbb $0x7b,%r16b #APX_F OPC_EVEX_EVEX + sbb $0x7b,%r18w #APX_F OPC_EVEX_EVEX + sbb $0x7b,%r25d #APX_F OPC_EVEX_EVEX + sbb $0x7b,%r31 #APX_F OPC_EVEX_EVEX + sbbb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sbbw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sbbl $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sbbq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sbbw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sbbl $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sbbq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sbb %r16b,%dl #APX_F OPC_EVEX_EVEX + sbb %r16b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sbb %r18w,%ax #APX_F OPC_EVEX_EVEX + sbb %r18w,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sbb %r18w,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sbb %r25d,%edx #APX_F OPC_EVEX_EVEX + sbb %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sbb %r31,%r15 #APX_F OPC_EVEX_EVEX + sbb %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sbb 0x123(%r16,%rax,4),%r16b #APX_F OPC_EVEX_EVEX + sbb 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + sbb 0x123(%r31,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + sbb 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + sbb 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + sha1msg1 %xmm23,%xmm22 #APX_F OPC_EVEX_EVEX + sha1msg1 0x123(%r31,%rax,4),%xmm22 #APX_F OPC_EVEX_EVEX + sha1msg2 %xmm23,%xmm22 #APX_F OPC_EVEX_EVEX + sha1msg2 0x123(%r31,%rax,4),%xmm22 #APX_F OPC_EVEX_EVEX + sha1nexte %xmm23,%xmm22 #APX_F OPC_EVEX_EVEX + sha1nexte 0x123(%r31,%rax,4),%xmm22 #APX_F OPC_EVEX_EVEX + sha1rnds4 $0x7b,%xmm23,%xmm22 #APX_F OPC_EVEX_EVEX + sha1rnds4 $0x7b,0x123(%r31,%rax,4),%xmm22 #APX_F OPC_EVEX_EVEX + sha256msg1 %xmm23,%xmm22 #APX_F OPC_EVEX_EVEX + sha256msg1 0x123(%r31,%rax,4),%xmm22 #APX_F OPC_EVEX_EVEX + sha256msg2 %xmm23,%xmm22 #APX_F OPC_EVEX_EVEX + sha256msg2 0x123(%r31,%rax,4),%xmm22 #APX_F OPC_EVEX_EVEX + sha256rnds2 0x123(%r31,%rax,4),%xmm12 #APX_F OPC_EVEX_EVEX + shl $0x7b,%r16b #APX_F OPC_EVEX_EVEX + shl $0x7b,%r18w #APX_F OPC_EVEX_EVEX + shl $0x7b,%r25d #APX_F OPC_EVEX_EVEX + shl $0x7b,%r31 #APX_F OPC_EVEX_EVEX + shlb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shlw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shll $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shlq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shlb $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shlw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shll $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shlq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shl $1,%r16b #APX_F OPC_EVEX_EVEX + shl $1,%r18w #APX_F OPC_EVEX_EVEX + shl $1,%r25d #APX_F OPC_EVEX_EVEX + shl $1,%r31 #APX_F OPC_EVEX_EVEX + shlb $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shlw $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shll $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shlq $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shlw $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shll $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shlq $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shl %cl,%r16b #APX_F OPC_EVEX_EVEX + shl %cl,%r18w #APX_F OPC_EVEX_EVEX + shl %cl,%r25d #APX_F OPC_EVEX_EVEX + shl %cl,%r31 #APX_F OPC_EVEX_EVEX + shlb %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shlw %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shll %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shlq %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shlb %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shlw %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shll %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shlq %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shld $0x7b,%r18w,%ax #APX_F OPC_EVEX_EVEX + shld $0x7b,%r18w,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shld $0x7b,%r25d,%edx #APX_F OPC_EVEX_EVEX + shld $0x7b,%r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shld $0x7b,%r31,%r15 #APX_F OPC_EVEX_EVEX + shld $0x7b,%r31,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shld %cl,%r18w,%ax #APX_F OPC_EVEX_EVEX + shld %cl,%r18w,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shld %cl,%r25d,%edx #APX_F OPC_EVEX_EVEX + shld %cl,%r25d,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shld %cl,%r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shld %cl,%r31,%r15 #APX_F OPC_EVEX_EVEX + shld %cl,%r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shlx %r25d,%edx,%r10d #APX_F OPC_EVEX_EVEX + shlx %r25d,0x123(%r31,%rax,4),%edx #APX_F OPC_EVEX_EVEX + shlx %r31,%r15,%r11 #APX_F OPC_EVEX_EVEX + shlx %r31,0x123(%r31,%rax,4),%r15 #APX_F OPC_EVEX_EVEX + shr $0x7b,%r16b #APX_F OPC_EVEX_EVEX + shr $0x7b,%r18w #APX_F OPC_EVEX_EVEX + shr $0x7b,%r25d #APX_F OPC_EVEX_EVEX + shr $0x7b,%r31 #APX_F OPC_EVEX_EVEX + shrb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrl $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shrl $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shrq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shr $1,%r16b #APX_F OPC_EVEX_EVEX + shr $1,%r18w #APX_F OPC_EVEX_EVEX + shr $1,%r25d #APX_F OPC_EVEX_EVEX + shr $1,%r31 #APX_F OPC_EVEX_EVEX + shrb $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrw $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrl $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrq $1,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrw $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shrl $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shrq $1,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shr %cl,%r16b #APX_F OPC_EVEX_EVEX + shr %cl,%r18w #APX_F OPC_EVEX_EVEX + shr %cl,%r25d #APX_F OPC_EVEX_EVEX + shr %cl,%r31 #APX_F OPC_EVEX_EVEX + shrb %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrw %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrl %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrq %cl,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrw %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shrl %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shrq %cl,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shrd $0x7b,%r18w,%ax #APX_F OPC_EVEX_EVEX + shrd $0x7b,%r18w,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shrd $0x7b,%r25d,%edx #APX_F OPC_EVEX_EVEX + shrd $0x7b,%r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shrd $0x7b,%r31,%r15 #APX_F OPC_EVEX_EVEX + shrd $0x7b,%r31,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrd %cl,%r18w,%ax #APX_F OPC_EVEX_EVEX + shrd %cl,%r18w,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrd %cl,%r25d,%edx #APX_F OPC_EVEX_EVEX + shrd %cl,%r25d,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + shrd %cl,%r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shrd %cl,%r31,%r15 #APX_F OPC_EVEX_EVEX + shrd %cl,%r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + shrx %r25d,%edx,%r10d #APX_F OPC_EVEX_EVEX + shrx %r25d,0x123(%r31,%rax,4),%edx #APX_F OPC_EVEX_EVEX + shrx %r31,%r15,%r11 #APX_F OPC_EVEX_EVEX + shrx %r31,0x123(%r31,%rax,4),%r15 #APX_F OPC_EVEX_EVEX + sttilecfg 0x123(%r31,%rax,4) #APX_F + sub $0x7b,%r16b #APX_F OPC_EVEX_EVEX + sub $0x7b,%r18w #APX_F OPC_EVEX_EVEX + sub $0x7b,%r25d #APX_F OPC_EVEX_EVEX + sub $0x7b,%r31 #APX_F OPC_EVEX_EVEX + subb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + subw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + subl $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + subq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + subw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + subl $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + subq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sub %r16b,%dl #APX_F OPC_EVEX_EVEX + sub %r16b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sub %r18w,%ax #APX_F OPC_EVEX_EVEX + sub %r18w,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + sub %r18w,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sub %r25d,%edx #APX_F OPC_EVEX_EVEX + sub %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sub %r31,%r15 #APX_F OPC_EVEX_EVEX + sub %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + sub 0x123(%r16,%rax,4),%r16b #APX_F OPC_EVEX_EVEX + sub 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + sub 0x123(%r31,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + sub 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + sub 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + tileloadd 0x123(%r31,%rax,4),%tmm6 #APX_F + tileloaddt1 0x123(%r31,%rax,4),%tmm6 #APX_F + tilestored %tmm6,0x123(%r31,%rax,4) #APX_F + tzcnt %r18w,%ax #APX_F OPC_EVEX_EVEX + tzcnt %r25d,%edx #APX_F OPC_EVEX_EVEX + tzcnt %r31,%r15 #APX_F OPC_EVEX_EVEX + tzcnt 0x123(%r16,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + tzcnt 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + tzcnt 0x123(%r31,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + tzcnt 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + wrssd %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + wrssq %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + wrussd %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + wrussq %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + xor $0x7b,%r16b #APX_F OPC_EVEX_EVEX + xor $0x7b,%r18w #APX_F OPC_EVEX_EVEX + xor $0x7b,%r25d #APX_F OPC_EVEX_EVEX + xor $0x7b,%r31 #APX_F OPC_EVEX_EVEX + xorb $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + xorw $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + xorl $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + xorq $0x7b,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + xorw $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + xorl $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + xorq $0x7b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + xor %r16b,%dl #APX_F OPC_EVEX_EVEX + xor %r16b,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + xor %r18w,%ax #APX_F OPC_EVEX_EVEX + xor %r18w,0x123(%r16,%rax,4) #APX_F OPC_EVEX_EVEX + xor %r18w,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + xor %r25d,%edx #APX_F OPC_EVEX_EVEX + xor %r25d,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + xor %r31,%r15 #APX_F OPC_EVEX_EVEX + xor %r31,0x123(%r31,%rax,4) #APX_F OPC_EVEX_EVEX + xor 0x123(%r16,%rax,4),%r16b #APX_F OPC_EVEX_EVEX + xor 0x123(%r16,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + xor 0x123(%r31,%rax,4),%r18w #APX_F OPC_EVEX_EVEX + xor 0x123(%r31,%rax,4),%r25d #APX_F OPC_EVEX_EVEX + xor 0x123(%r31,%rax,4),%r31 #APX_F OPC_EVEX_EVEX + +.intel_syntax noprefix + aadd DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + aadd QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + aand DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + aand QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + adc r16b,0x7b #APX_F OPC_EVEX_EVEX + adc r18w,0x7b #APX_F OPC_EVEX_EVEX + adc r25d,0x7b #APX_F OPC_EVEX_EVEX + adc r31,0x7b #APX_F OPC_EVEX_EVEX + adc BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + adc WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + adc DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + adc QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + adc WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + adc DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + adc QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + adc dl,r16b #APX_F OPC_EVEX_EVEX + adc BYTE PTR [r31+rax*4+0x123],r16b #APX_F OPC_EVEX_EVEX + adc ax,r18w #APX_F OPC_EVEX_EVEX + adc WORD PTR [r16+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + adc WORD PTR [r31+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + adc edx,r25d #APX_F OPC_EVEX_EVEX + adc DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + adc r15,r31 #APX_F OPC_EVEX_EVEX + adc QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + adc r16b,BYTE PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + adc r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + adc r18w,WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + adc r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + adc r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + adcx edx,r25d #APX_F OPC_EVEX_EVEX + adcx r15,r31 #APX_F OPC_EVEX_EVEX + adcx r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + adcx r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + add r16b,0x7b #APX_F OPC_EVEX_EVEX + add r18w,0x7b #APX_F OPC_EVEX_EVEX + add r25d,0x7b #APX_F OPC_EVEX_EVEX + add r31,0x7b #APX_F OPC_EVEX_EVEX + add BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + add WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + add DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + add QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + add WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + add DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + add QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + add dl,r16b #APX_F OPC_EVEX_EVEX + add BYTE PTR [r31+rax*4+0x123],r16b #APX_F OPC_EVEX_EVEX + add ax,r18w #APX_F OPC_EVEX_EVEX + add WORD PTR [r16+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + add WORD PTR [r31+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + add edx,r25d #APX_F OPC_EVEX_EVEX + add DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + add r15,r31 #APX_F OPC_EVEX_EVEX + add QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + add r16b,BYTE PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + add r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + add r18w,WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + add r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + add r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + adox edx,r25d #APX_F OPC_EVEX_EVEX + adox r15,r31 #APX_F OPC_EVEX_EVEX + adox r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + adox r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + aesdec128kl xmm22,[r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + aesdec256kl xmm22,[r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + aesdecwide128kl [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + aesdecwide256kl [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + aesenc128kl xmm22,[r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + aesenc256kl xmm22,[r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + aesencwide128kl [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + aesencwide256kl [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + and r16b,0x7b #APX_F OPC_EVEX_EVEX + and r18w,0x7b #APX_F OPC_EVEX_EVEX + and r25d,0x7b #APX_F OPC_EVEX_EVEX + and r31,0x7b #APX_F OPC_EVEX_EVEX + and BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + and WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + and DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + and QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + and WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + and DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + and QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + and dl,r16b #APX_F OPC_EVEX_EVEX + and BYTE PTR [r31+rax*4+0x123],r16b #APX_F OPC_EVEX_EVEX + and ax,r18w #APX_F OPC_EVEX_EVEX + and WORD PTR [r16+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + and WORD PTR [r31+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + and edx,r25d #APX_F OPC_EVEX_EVEX + and DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + and r15,r31 #APX_F OPC_EVEX_EVEX + and QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + and r16b,BYTE PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + and r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + and r18w,WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + and r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + and r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + andn r10d,edx,r25d #APX_F OPC_EVEX_EVEX + andn r11,r15,r31 #APX_F OPC_EVEX_EVEX + andn edx,r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + andn r15,r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + aor DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + aor QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + axor DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + axor QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + bextr r10d,edx,r25d #APX_F OPC_EVEX_EVEX + bextr edx,DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + bextr r11,r15,r31 #APX_F OPC_EVEX_EVEX + bextr r15,QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + blsi edx,r25d #APX_F OPC_EVEX_EVEX + blsi r15,r31 #APX_F OPC_EVEX_EVEX + blsi r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + blsi r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + blsmsk edx,r25d #APX_F OPC_EVEX_EVEX + blsmsk r15,r31 #APX_F OPC_EVEX_EVEX + blsmsk r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + blsmsk r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + blsr edx,r25d #APX_F OPC_EVEX_EVEX + blsr r15,r31 #APX_F OPC_EVEX_EVEX + blsr r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + blsr r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + bzhi r10d,edx,r25d #APX_F OPC_EVEX_EVEX + bzhi edx,DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + bzhi r11,r15,r31 #APX_F OPC_EVEX_EVEX + bzhi r15,QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + cmpbexadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmpbexadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmpbxadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmpbxadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmplxadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmplxadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmpnbexadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmpnbexadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmpnbxadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmpnbxadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmpnlexadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmpnlexadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmpnlxadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmpnlxadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmpnoxadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmpnoxadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmpnpxadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmpnpxadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmpnsxadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmpnsxadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmpnzxadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmpnzxadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmpoxadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmpoxadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmppxadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmppxadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmpsxadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmpsxadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + cmpzxadd DWORD PTR [r31+rax*4+0x123],edx,r25d #APX_F OPC_EVEX_EVEX + cmpzxadd QWORD PTR [r31+rax*4+0x123],r15,r31 #APX_F OPC_EVEX_EVEX + dec r16b #APX_F OPC_EVEX_EVEX + dec r18w #APX_F OPC_EVEX_EVEX + dec r25d #APX_F OPC_EVEX_EVEX + dec r31 #APX_F OPC_EVEX_EVEX + dec WORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + dec DWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + dec QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + dec BYTE PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + dec WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + dec DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + dec QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + div r16b #APX_F OPC_EVEX_EVEX + div r18w #APX_F OPC_EVEX_EVEX + div r25d #APX_F OPC_EVEX_EVEX + div r31 #APX_F OPC_EVEX_EVEX + div WORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + div DWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + div QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + div BYTE PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + div WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + div DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + div QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + encodekey128 edx,r25d #APX_F OPC_EVEX_EVEX + encodekey256 edx,r25d #APX_F OPC_EVEX_EVEX + enqcmd r25d,[r31d+eax*4+0x123] #APX_F OPC_EVEX_EVEX + enqcmd r31,[r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + enqcmds r25d,[r31d+eax*4+0x123] #APX_F OPC_EVEX_EVEX + enqcmds r31,[r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + idiv r16b #APX_F OPC_EVEX_EVEX + idiv r18w #APX_F OPC_EVEX_EVEX + idiv r25d #APX_F OPC_EVEX_EVEX + idiv r31 #APX_F OPC_EVEX_EVEX + idiv WORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + idiv DWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + idiv QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + idiv BYTE PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + idiv WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + idiv DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + idiv QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + imul ax,r18w,0x7b #APX_F + imul edx,r25d,0x7b #APX_F + imul r15,r31,0x7b #APX_F + imul r25d,DWORD PTR [r16+rax*4+0x123],0x7b #APX_F + imul r31,QWORD PTR [r16+rax*4+0x123],0x7b #APX_F + imul r18w,WORD PTR [r31+rax*4+0x123],0x7b #APX_F + imul r25d,DWORD PTR [r31+rax*4+0x123],0x7b #APX_F + imul r31,QWORD PTR [r31+rax*4+0x123],0x7b #APX_F + imul r16b #APX_F OPC_EVEX_EVEX + imul r18w #APX_F OPC_EVEX_EVEX + imul ax,r18w #APX_F OPC_EVEX_EVEX + imul r25d #APX_F OPC_EVEX_EVEX + imul edx,r25d #APX_F OPC_EVEX_EVEX + imul r31 #APX_F OPC_EVEX_EVEX + imul r15,r31 #APX_F OPC_EVEX_EVEX + imul BYTE PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + imul WORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + imul DWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + imul r18w,WORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + imul r25d,DWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + imul r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + imul QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + imul WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + imul DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + imul QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + inc r16b #APX_F OPC_EVEX_EVEX + inc r18w #APX_F OPC_EVEX_EVEX + inc r25d #APX_F OPC_EVEX_EVEX + inc r31 #APX_F OPC_EVEX_EVEX + inc WORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + inc DWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + inc QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + inc BYTE PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + inc WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + inc DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + inc QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + invept r31,OWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + invpcid r31,[r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + invvpid r31,OWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + kmovb k5,k3 #APX_F OPC_EVEX_EVEX + kmovb r25d,k5 #APX_F OPC_EVEX_EVEX + kmovb BYTE PTR [r31+rax*4+0x123],k5 #APX_F OPC_EVEX_EVEX + kmovb k5,r25d #APX_F OPC_EVEX_EVEX + kmovb k5,BYTE PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + kmovd k5,k3 #APX_F OPC_EVEX_EVEX + kmovd r25d,k5 #APX_F OPC_EVEX_EVEX + kmovd DWORD PTR [r31+rax*4+0x123],k5 #APX_F OPC_EVEX_EVEX + kmovd k5,r25d #APX_F OPC_EVEX_EVEX + kmovd k5,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + kmovq k5,k3 #APX_F OPC_EVEX_EVEX + kmovq r31,k5 #APX_F OPC_EVEX_EVEX + kmovq QWORD PTR [r31+rax*4+0x123],k5 #APX_F OPC_EVEX_EVEX + kmovq k5,r31 #APX_F OPC_EVEX_EVEX + kmovq k5,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + kmovw k5,k3 #APX_F OPC_EVEX_EVEX + kmovw r25d,k5 #APX_F OPC_EVEX_EVEX + kmovw WORD PTR [r31+rax*4+0x123],k5 #APX_F OPC_EVEX_EVEX + kmovw k5,r25d #APX_F OPC_EVEX_EVEX + kmovw k5,WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + ldtilecfg [r31+rax*4+0x123] #APX_F + lzcnt ax,r18w #APX_F OPC_EVEX_EVEX + lzcnt edx,r25d #APX_F OPC_EVEX_EVEX + lzcnt r15,r31 #APX_F OPC_EVEX_EVEX + lzcnt r18w,WORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + lzcnt r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + lzcnt r18w,WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + lzcnt r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + movbe ax,r18w #APX_F OPC_EVEX_EVEX + movbe WORD PTR [r16+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + movbe WORD PTR [r31+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + movbe edx,r25d #APX_F OPC_EVEX_EVEX + movbe DWORD PTR [r16+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + movbe r15,r31 #APX_F OPC_EVEX_EVEX + movbe QWORD PTR [r16+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + movbe QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + movbe r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + movbe r18w,WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + movbe r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + movdir64b r25d,[r31d+eax*4+0x123] #APX_F OPC_EVEX_EVEX + movdir64b r31,[r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + movdiri DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + movdiri QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + mul r16b #APX_F OPC_EVEX_EVEX + mul r18w #APX_F OPC_EVEX_EVEX + mul r25d #APX_F OPC_EVEX_EVEX + mul r31 #APX_F OPC_EVEX_EVEX + mul WORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + mul DWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + mul QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + mul BYTE PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + mul WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + mul DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + mul QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + mulx r10d,edx,r25d #APX_F OPC_EVEX_EVEX + mulx r11,r15,r31 #APX_F OPC_EVEX_EVEX + mulx edx,r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + mulx r15,r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + neg r16b #APX_F OPC_EVEX_EVEX + neg r18w #APX_F OPC_EVEX_EVEX + neg r25d #APX_F OPC_EVEX_EVEX + neg r31 #APX_F OPC_EVEX_EVEX + neg WORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + neg DWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + neg QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + neg BYTE PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + neg WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + neg DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + neg QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + not r16b #APX_F OPC_EVEX_EVEX + not r18w #APX_F OPC_EVEX_EVEX + not r25d #APX_F OPC_EVEX_EVEX + not r31 #APX_F OPC_EVEX_EVEX + not WORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + not DWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + not QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + not BYTE PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + not WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + not DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + not QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + or r16b,0x7b #APX_F OPC_EVEX_EVEX + or r18w,0x7b #APX_F OPC_EVEX_EVEX + or r25d,0x7b #APX_F OPC_EVEX_EVEX + or r31,0x7b #APX_F OPC_EVEX_EVEX + or BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + or WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + or DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + or QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + or WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + or DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + or QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + or dl,r16b #APX_F OPC_EVEX_EVEX + or BYTE PTR [r31+rax*4+0x123],r16b #APX_F OPC_EVEX_EVEX + or ax,r18w #APX_F OPC_EVEX_EVEX + or WORD PTR [r16+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + or WORD PTR [r31+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + or edx,r25d #APX_F OPC_EVEX_EVEX + or DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + or r15,r31 #APX_F OPC_EVEX_EVEX + or QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + or r16b,BYTE PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + or r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + or r18w,WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + or r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + or r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + pdep r10d,edx,r25d #APX_F OPC_EVEX_EVEX + pdep r11,r15,r31 #APX_F OPC_EVEX_EVEX + pdep edx,r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + pdep r15,r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + pext r10d,edx,r25d #APX_F OPC_EVEX_EVEX + pext r11,r15,r31 #APX_F OPC_EVEX_EVEX + pext edx,r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + pext r15,r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + popcnt ax,r18w #APX_F OPC_EVEX_EVEX + popcnt edx,r25d #APX_F OPC_EVEX_EVEX + popcnt r15,r31 #APX_F OPC_EVEX_EVEX + popcnt r18w,WORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + popcnt r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + popcnt r18w,WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + popcnt r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + rcl r16b,0x7b #APX_F OPC_EVEX_EVEX + rcl r18w,0x7b #APX_F OPC_EVEX_EVEX + rcl r25d,0x7b #APX_F OPC_EVEX_EVEX + rcl r31,0x7b #APX_F OPC_EVEX_EVEX + rcl BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcl WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcl DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcl QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcl WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcl DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcl QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcl r16b,1 #APX_F OPC_EVEX_EVEX + rcl r18w,1 #APX_F OPC_EVEX_EVEX + rcl r25d,1 #APX_F OPC_EVEX_EVEX + rcl r31,1 #APX_F OPC_EVEX_EVEX + rcl BYTE PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcl WORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcl DWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcl QWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcl WORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcl DWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcl QWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcl r16b,cl #APX_F OPC_EVEX_EVEX + rcl r18w,cl #APX_F OPC_EVEX_EVEX + rcl r25d,cl #APX_F OPC_EVEX_EVEX + rcl r31,cl #APX_F OPC_EVEX_EVEX + rcl BYTE PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rcl WORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rcl DWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rcl QWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rcl WORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rcl DWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rcl QWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rcr r16b,0x7b #APX_F OPC_EVEX_EVEX + rcr r18w,0x7b #APX_F OPC_EVEX_EVEX + rcr r25d,0x7b #APX_F OPC_EVEX_EVEX + rcr r31,0x7b #APX_F OPC_EVEX_EVEX + rcr BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcr WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcr DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcr QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcr WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcr DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcr QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rcr r16b,1 #APX_F OPC_EVEX_EVEX + rcr r18w,1 #APX_F OPC_EVEX_EVEX + rcr r25d,1 #APX_F OPC_EVEX_EVEX + rcr r31,1 #APX_F OPC_EVEX_EVEX + rcr BYTE PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcr WORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcr DWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcr QWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcr WORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcr DWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcr QWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rcr r16b,cl #APX_F OPC_EVEX_EVEX + rcr r18w,cl #APX_F OPC_EVEX_EVEX + rcr r25d,cl #APX_F OPC_EVEX_EVEX + rcr r31,cl #APX_F OPC_EVEX_EVEX + rcr BYTE PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rcr WORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rcr DWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rcr QWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rcr WORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rcr DWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rcr QWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rol r16b,0x7b #APX_F OPC_EVEX_EVEX + rol r18w,0x7b #APX_F OPC_EVEX_EVEX + rol r25d,0x7b #APX_F OPC_EVEX_EVEX + rol r31,0x7b #APX_F OPC_EVEX_EVEX + rol BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rol WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rol DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rol QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rol WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rol DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rol QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rol r16b,1 #APX_F OPC_EVEX_EVEX + rol r18w,1 #APX_F OPC_EVEX_EVEX + rol r25d,1 #APX_F OPC_EVEX_EVEX + rol r31,1 #APX_F OPC_EVEX_EVEX + rol BYTE PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rol WORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rol DWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rol QWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rol WORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rol DWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rol QWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + rol r16b,cl #APX_F OPC_EVEX_EVEX + rol r18w,cl #APX_F OPC_EVEX_EVEX + rol r25d,cl #APX_F OPC_EVEX_EVEX + rol r31,cl #APX_F OPC_EVEX_EVEX + rol BYTE PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rol WORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rol DWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rol QWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rol WORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rol DWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rol QWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + ror r16b,0x7b #APX_F OPC_EVEX_EVEX + ror r18w,0x7b #APX_F OPC_EVEX_EVEX + ror r25d,0x7b #APX_F OPC_EVEX_EVEX + ror r31,0x7b #APX_F OPC_EVEX_EVEX + ror BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + ror WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + ror DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + ror QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + ror WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + ror DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + ror QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + ror r16b,1 #APX_F OPC_EVEX_EVEX + ror r18w,1 #APX_F OPC_EVEX_EVEX + ror r25d,1 #APX_F OPC_EVEX_EVEX + ror r31,1 #APX_F OPC_EVEX_EVEX + ror BYTE PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + ror WORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + ror DWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + ror QWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + ror WORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + ror DWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + ror QWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + ror r16b,cl #APX_F OPC_EVEX_EVEX + ror r18w,cl #APX_F OPC_EVEX_EVEX + ror r25d,cl #APX_F OPC_EVEX_EVEX + ror r31,cl #APX_F OPC_EVEX_EVEX + ror BYTE PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + ror WORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + ror DWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + ror QWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + ror WORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + ror DWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + ror QWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + rorx edx,r25d,0x7b #APX_F OPC_EVEX_EVEX + rorx r15,r31,0x7b #APX_F OPC_EVEX_EVEX + rorx r25d,DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + rorx r31,QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sar r16b,0x7b #APX_F OPC_EVEX_EVEX + sar r18w,0x7b #APX_F OPC_EVEX_EVEX + sar r25d,0x7b #APX_F OPC_EVEX_EVEX + sar r31,0x7b #APX_F OPC_EVEX_EVEX + sar BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sar WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sar DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sar QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sar WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sar DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sar QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sar r16b,1 #APX_F OPC_EVEX_EVEX + sar r18w,1 #APX_F OPC_EVEX_EVEX + sar r25d,1 #APX_F OPC_EVEX_EVEX + sar r31,1 #APX_F OPC_EVEX_EVEX + sar BYTE PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + sar WORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + sar DWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + sar QWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + sar WORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + sar DWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + sar QWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + sar r16b,cl #APX_F OPC_EVEX_EVEX + sar r18w,cl #APX_F OPC_EVEX_EVEX + sar r25d,cl #APX_F OPC_EVEX_EVEX + sar r31,cl #APX_F OPC_EVEX_EVEX + sar BYTE PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + sar WORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + sar DWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + sar QWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + sar WORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + sar DWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + sar QWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + sarx r10d,edx,r25d #APX_F OPC_EVEX_EVEX + sarx edx,DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + sarx r11,r15,r31 #APX_F OPC_EVEX_EVEX + sarx r15,QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + sbb r16b,0x7b #APX_F OPC_EVEX_EVEX + sbb r18w,0x7b #APX_F OPC_EVEX_EVEX + sbb r25d,0x7b #APX_F OPC_EVEX_EVEX + sbb r31,0x7b #APX_F OPC_EVEX_EVEX + sbb BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sbb WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sbb DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sbb QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sbb WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sbb DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sbb QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sbb dl,r16b #APX_F OPC_EVEX_EVEX + sbb BYTE PTR [r31+rax*4+0x123],r16b #APX_F OPC_EVEX_EVEX + sbb ax,r18w #APX_F OPC_EVEX_EVEX + sbb WORD PTR [r16+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + sbb WORD PTR [r31+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + sbb edx,r25d #APX_F OPC_EVEX_EVEX + sbb DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + sbb r15,r31 #APX_F OPC_EVEX_EVEX + sbb QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + sbb r16b,BYTE PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sbb r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sbb r18w,WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sbb r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sbb r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sha1msg1 xmm22,xmm23 #APX_F OPC_EVEX_EVEX + sha1msg1 xmm22,XMMWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sha1msg2 xmm22,xmm23 #APX_F OPC_EVEX_EVEX + sha1msg2 xmm22,XMMWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sha1nexte xmm22,xmm23 #APX_F OPC_EVEX_EVEX + sha1nexte xmm22,XMMWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sha1rnds4 xmm22,xmm23,0x7b #APX_F OPC_EVEX_EVEX + sha1rnds4 xmm22,XMMWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sha256msg1 xmm22,xmm23 #APX_F OPC_EVEX_EVEX + sha256msg1 xmm22,XMMWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sha256msg2 xmm22,xmm23 #APX_F OPC_EVEX_EVEX + sha256msg2 xmm22,XMMWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sha256rnds2 xmm12,XMMWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + shl r16b,0x7b #APX_F OPC_EVEX_EVEX + shl r18w,0x7b #APX_F OPC_EVEX_EVEX + shl r25d,0x7b #APX_F OPC_EVEX_EVEX + shl r31,0x7b #APX_F OPC_EVEX_EVEX + shl BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shl WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shl DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shl QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shl BYTE PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shl WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shl DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shl QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shl r16b,1 #APX_F OPC_EVEX_EVEX + shl r18w,1 #APX_F OPC_EVEX_EVEX + shl r25d,1 #APX_F OPC_EVEX_EVEX + shl r31,1 #APX_F OPC_EVEX_EVEX + shl BYTE PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shl WORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shl DWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shl QWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shl WORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shl DWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shl QWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shl r16b,cl #APX_F OPC_EVEX_EVEX + shl r18w,cl #APX_F OPC_EVEX_EVEX + shl r25d,cl #APX_F OPC_EVEX_EVEX + shl r31,cl #APX_F OPC_EVEX_EVEX + shl BYTE PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shl WORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shl DWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shl QWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shl BYTE PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shl WORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shl DWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shl QWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shld ax,r18w,0x7b #APX_F OPC_EVEX_EVEX + shld WORD PTR [r31+rax*4+0x123],r18w,0x7b #APX_F OPC_EVEX_EVEX + shld edx,r25d,0x7b #APX_F OPC_EVEX_EVEX + shld DWORD PTR [r31+rax*4+0x123],r25d,0x7b #APX_F OPC_EVEX_EVEX + shld r15,r31,0x7b #APX_F OPC_EVEX_EVEX + shld QWORD PTR [r16+rax*4+0x123],r31,0x7b #APX_F OPC_EVEX_EVEX + shld ax,r18w,cl #APX_F OPC_EVEX_EVEX + shld WORD PTR [r16+rax*4+0x123],r18w,cl #APX_F OPC_EVEX_EVEX + shld edx,r25d,cl #APX_F OPC_EVEX_EVEX + shld DWORD PTR [r16+rax*4+0x123],r25d,cl #APX_F OPC_EVEX_EVEX + shld DWORD PTR [r31+rax*4+0x123],r25d,cl #APX_F OPC_EVEX_EVEX + shld r15,r31,cl #APX_F OPC_EVEX_EVEX + shld QWORD PTR [r31+rax*4+0x123],r31,cl #APX_F OPC_EVEX_EVEX + shlx r10d,edx,r25d #APX_F OPC_EVEX_EVEX + shlx edx,DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + shlx r11,r15,r31 #APX_F OPC_EVEX_EVEX + shlx r15,QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + shr r16b,0x7b #APX_F OPC_EVEX_EVEX + shr r18w,0x7b #APX_F OPC_EVEX_EVEX + shr r25d,0x7b #APX_F OPC_EVEX_EVEX + shr r31,0x7b #APX_F OPC_EVEX_EVEX + shr BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shr WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shr DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shr QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shr WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shr DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shr QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + shr r16b,1 #APX_F OPC_EVEX_EVEX + shr r18w,1 #APX_F OPC_EVEX_EVEX + shr r25d,1 #APX_F OPC_EVEX_EVEX + shr r31,1 #APX_F OPC_EVEX_EVEX + shr BYTE PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shr WORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shr DWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shr QWORD PTR [r16+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shr WORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shr DWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shr QWORD PTR [r31+rax*4+0x123],1 #APX_F OPC_EVEX_EVEX + shr r16b,cl #APX_F OPC_EVEX_EVEX + shr r18w,cl #APX_F OPC_EVEX_EVEX + shr r25d,cl #APX_F OPC_EVEX_EVEX + shr r31,cl #APX_F OPC_EVEX_EVEX + shr BYTE PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shr WORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shr DWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shr QWORD PTR [r16+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shr WORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shr DWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shr QWORD PTR [r31+rax*4+0x123],cl #APX_F OPC_EVEX_EVEX + shrd ax,r18w,0x7b #APX_F OPC_EVEX_EVEX + shrd WORD PTR [r31+rax*4+0x123],r18w,0x7b #APX_F OPC_EVEX_EVEX + shrd edx,r25d,0x7b #APX_F OPC_EVEX_EVEX + shrd DWORD PTR [r31+rax*4+0x123],r25d,0x7b #APX_F OPC_EVEX_EVEX + shrd r15,r31,0x7b #APX_F OPC_EVEX_EVEX + shrd QWORD PTR [r16+rax*4+0x123],r31,0x7b #APX_F OPC_EVEX_EVEX + shrd ax,r18w,cl #APX_F OPC_EVEX_EVEX + shrd WORD PTR [r16+rax*4+0x123],r18w,cl #APX_F OPC_EVEX_EVEX + shrd edx,r25d,cl #APX_F OPC_EVEX_EVEX + shrd DWORD PTR [r16+rax*4+0x123],r25d,cl #APX_F OPC_EVEX_EVEX + shrd DWORD PTR [r31+rax*4+0x123],r25d,cl #APX_F OPC_EVEX_EVEX + shrd r15,r31,cl #APX_F OPC_EVEX_EVEX + shrd QWORD PTR [r31+rax*4+0x123],r31,cl #APX_F OPC_EVEX_EVEX + shrx r10d,edx,r25d #APX_F OPC_EVEX_EVEX + shrx edx,DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + shrx r11,r15,r31 #APX_F OPC_EVEX_EVEX + shrx r15,QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + sttilecfg [r31+rax*4+0x123] #APX_F + sub r16b,0x7b #APX_F OPC_EVEX_EVEX + sub r18w,0x7b #APX_F OPC_EVEX_EVEX + sub r25d,0x7b #APX_F OPC_EVEX_EVEX + sub r31,0x7b #APX_F OPC_EVEX_EVEX + sub BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sub WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sub DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sub QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sub WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sub DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sub QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + sub dl,r16b #APX_F OPC_EVEX_EVEX + sub BYTE PTR [r31+rax*4+0x123],r16b #APX_F OPC_EVEX_EVEX + sub ax,r18w #APX_F OPC_EVEX_EVEX + sub WORD PTR [r16+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + sub WORD PTR [r31+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + sub edx,r25d #APX_F OPC_EVEX_EVEX + sub DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + sub r15,r31 #APX_F OPC_EVEX_EVEX + sub QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + sub r16b,BYTE PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sub r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sub r18w,WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sub r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + sub r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + tileloadd tmm6,[r31+rax*4+0x123] #APX_F + tileloaddt1 tmm6,[r31+rax*4+0x123] #APX_F + tilestored [r31+rax*4+0x123],tmm6 #APX_F + tzcnt ax,r18w #APX_F OPC_EVEX_EVEX + tzcnt edx,r25d #APX_F OPC_EVEX_EVEX + tzcnt r15,r31 #APX_F OPC_EVEX_EVEX + tzcnt r18w,WORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + tzcnt r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + tzcnt r18w,WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + tzcnt r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + wrssd DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + wrssq QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + wrussd DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + wrussq QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + xor r16b,0x7b #APX_F OPC_EVEX_EVEX + xor r18w,0x7b #APX_F OPC_EVEX_EVEX + xor r25d,0x7b #APX_F OPC_EVEX_EVEX + xor r31,0x7b #APX_F OPC_EVEX_EVEX + xor BYTE PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + xor WORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + xor DWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + xor QWORD PTR [r16+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + xor WORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + xor DWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + xor QWORD PTR [r31+rax*4+0x123],0x7b #APX_F OPC_EVEX_EVEX + xor dl,r16b #APX_F OPC_EVEX_EVEX + xor BYTE PTR [r31+rax*4+0x123],r16b #APX_F OPC_EVEX_EVEX + xor ax,r18w #APX_F OPC_EVEX_EVEX + xor WORD PTR [r16+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + xor WORD PTR [r31+rax*4+0x123],r18w #APX_F OPC_EVEX_EVEX + xor edx,r25d #APX_F OPC_EVEX_EVEX + xor DWORD PTR [r31+rax*4+0x123],r25d #APX_F OPC_EVEX_EVEX + xor r15,r31 #APX_F OPC_EVEX_EVEX + xor QWORD PTR [r31+rax*4+0x123],r31 #APX_F OPC_EVEX_EVEX + xor r16b,BYTE PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + xor r31,QWORD PTR [r16+rax*4+0x123] #APX_F OPC_EVEX_EVEX + xor r18w,WORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + xor r25d,DWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX + xor r31,QWORD PTR [r31+rax*4+0x123] #APX_F OPC_EVEX_EVEX diff --git a/gas/testsuite/gas/i386/x86-64-evex.d b/gas/testsuite/gas/i386/x86-64-evex.d index 041747db892..5d974c312da 100644 --- a/gas/testsuite/gas/i386/x86-64-evex.d +++ b/gas/testsuite/gas/i386/x86-64-evex.d @@ -17,6 +17,6 @@ Disassembly of section .text: +[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ss %rax,\{rd-sae\},%xmm5,%xmm6 +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sd %eax,\{rd-bad\},%xmm5,%xmm6 +[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sd %rax,\{rd-sae\},%xmm5,%xmm6 - +[a-f0-9]+: 62 e1 7e 08 2d c0 vcvtss2si %xmm0,\(bad\) + +[a-f0-9]+: 62 e1 7e 08 2d c0 vcvtss2si %xmm0,%r16d +[a-f0-9]+: 62 e1 7c 08 c2 c0 00 vcmpeqps %xmm0,%xmm0,\(bad\) #pass diff --git a/gas/testsuite/gas/i386/x86-64-inval-movbe.l b/gas/testsuite/gas/i386/x86-64-inval-movbe.l index 1c8ceb55c11..44ddfe4f034 100644 --- a/gas/testsuite/gas/i386/x86-64-inval-movbe.l +++ b/gas/testsuite/gas/i386/x86-64-inval-movbe.l @@ -1,29 +1,30 @@ .*: Assembler messages: -.*:4: Error: .* .*:5: Error: .* .*:6: Error: .* .*:7: Error: .* .*:8: Error: .* -.*:11: Error: .* +.*:9: Error: .* .*:12: Error: .* .*:13: Error: .* .*:14: Error: .* .*:15: Error: .* +.*:16: Error: .* GAS LISTING .* [ ]*1[ ]+\# Check illegal movbe in 64bit mode\. [ ]*2[ ]+\.text -[ ]*3[ ]+foo: -[ ]*4[ ]+movbe \(%rcx\),%bl -[ ]*5[ ]+movbe %ecx,%ebx -[ ]*6[ ]+movbe %bx,%rcx -[ ]*7[ ]+movbe %rbx,%rcx -[ ]*8[ ]+movbe %bl,\(%rcx\) -[ ]*9[ ]+ -[ ]*10[ ]+\.intel_syntax noprefix -[ ]*11[ ]+movbe bl, byte ptr \[rcx\] -[ ]*12[ ]+movbe ebx, ecx -[ ]*13[ ]+movbe rcx, bx -[ ]*14[ ]+movbe rcx, rbx -[ ]*15[ ]+movbe byte ptr \[rcx\], bl +[ ]*3[ ]+\.arch \.noapx_f +[ ]*4[ ]+foo: +[ ]*5[ ]+movbe \(%rcx\),%bl +[ ]*6[ ]+movbe %ecx,%ebx +[ ]*7[ ]+movbe %bx,%rcx +[ ]*8[ ]+movbe %rbx,%rcx +[ ]*9[ ]+movbe %bl,\(%rcx\) +[ ]*10[ ]+ +[ ]*11[ ]+\.intel_syntax noprefix +[ ]*12[ ]+movbe bl, byte ptr \[rcx\] +[ ]*13[ ]+movbe ebx, ecx +[ ]*14[ ]+movbe rcx, bx +[ ]*15[ ]+movbe rcx, rbx +[ ]*16[ ]+movbe byte ptr \[rcx\], bl diff --git a/gas/testsuite/gas/i386/x86-64-inval-movbe.s b/gas/testsuite/gas/i386/x86-64-inval-movbe.s index 38f09b14d64..380a9191b6a 100644 --- a/gas/testsuite/gas/i386/x86-64-inval-movbe.s +++ b/gas/testsuite/gas/i386/x86-64-inval-movbe.s @@ -1,5 +1,6 @@ # Check illegal movbe in 64bit mode. .text + .arch .noapx_f foo: movbe (%rcx),%bl movbe %ecx,%ebx diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 07df89ba0cc..46fb3681528 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -361,8 +361,12 @@ run_dump_test "x86-64-avx512f-rcigrne" run_dump_test "x86-64-avx512f-rcigru-intel" run_dump_test "x86-64-avx512f-rcigru" run_list_test "x86-64-apx-egpr-inval" "-al" +run_list_test "x86-64-apx-egpr-promote-inval" "-al" run_dump_test "x86-64-apx-rex2" run_dump_test "x86-64-apx-rex2-inval" +run_dump_test "x86-64-apx-evex-promoted" +run_dump_test "x86-64-apx-evex-promoted-intel" +run_dump_test "x86-64-apx-evex-egpr" run_dump_test "x86-64-avx512f-rcigrz-intel" run_dump_test "x86-64-avx512f-rcigrz" run_dump_test "x86-64-clwb" From patchwork Tue Sep 19 15:25:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Frager, Neal via Binutils" X-Patchwork-Id: 76391 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A2E73383C998 for ; Tue, 19 Sep 2023 15:30:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A2E73383C998 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1695137400; bh=XxAo4nSnYqNbKryatXfEhI+Yl+oJMrjvA15bMfcDcIs=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=MuL7D3qK90hKBGfRPY91VYXZZzyWWvJFzt7SyjbPN1osHo3WE+oqwmh5Ud6ksO+ix BzYflzbQoV0MrsLbj/odpyLM6A77LbzWJkmu6+S6RUw49f1EfaUSiO47uDmJE9T1YA AiBy2qo1Fx9u0n7Pi6CC8ryfYf0HeMbb1bTWc6s0= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 6C04C385703F for ; Tue, 19 Sep 2023 15:25:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6C04C385703F X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="444057977" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="444057977" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 08:25:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="775599170" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="775599170" Received: from scymds03.sc.intel.com ([10.148.94.166]) by orsmga008.jf.intel.com with ESMTP; 19 Sep 2023 08:25:36 -0700 Received: from shgcc101.sh.intel.com (shgcc101.sh.intel.com [10.239.85.97]) by scymds03.sc.intel.com (Postfix) with ESMTP id E51696A; Tue, 19 Sep 2023 08:25:34 -0700 (PDT) To: binutils@sourceware.org Cc: jbeulich@suse.com, hongjiu.lu@intel.com, konglin1 Subject: [PATCH 4/8] Support APX NDD Date: Tue, 19 Sep 2023 15:25:23 +0000 Message-Id: <20230919152527.497773-5-lili.cui@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230919152527.497773-1-lili.cui@intel.com> References: <20230919152527.497773-1-lili.cui@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_FILL_THIS_FORM_SHORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Cui, Lili via Binutils" From: "Frager, Neal via Binutils" Reply-To: "Cui, Lili" Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" From: konglin1 opcodes/ChangeLog: * opcodes/i386-dis-evex-prefix.h: Add NDD decode for adox/adcx. * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_C0, REG_EVEX_MAP4_C1, REG_EVEX_MAP4_D0, REG_EVEX_MAP4_D1, REG_EVEX_MAP4_D2, REG_EVEX_MAP4_D3, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (VexGb): Add new define. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (print_register): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (Opcode_APX_NDDD): New macro. * opcodes/i386-opc.tbl: Add APX NDD instructions. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (is_any_apx_encoding): Add legacy insn promote to SPACE_EVEXMAP4. (build_legacy_insns_with_apx_encoding): Add ndd bit encode. (md_assemble): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (operand_size_match): Support APX NDD that the number of operands is 3. (match_template): Support swap the first two operands for APX NDD that the number of operands is 3. * gas/testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * gas/testsuite/gas/i386/x86-64-apx-ndd.d: New test. * gas/testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. --- gas/config/tc-i386.c | 80 ++++++++---- gas/testsuite/gas/i386/x86-64-apx-ndd.d | 165 ++++++++++++++++++++++++ gas/testsuite/gas/i386/x86-64-apx-ndd.s | 156 ++++++++++++++++++++++ gas/testsuite/gas/i386/x86-64-pseudos.d | 42 ++++++ gas/testsuite/gas/i386/x86-64-pseudos.s | 43 ++++++ gas/testsuite/gas/i386/x86-64.exp | 1 + opcodes/i386-dis-evex-prefix.h | 4 +- opcodes/i386-dis-evex-reg.h | 123 ++++++++++++++++++ opcodes/i386-dis-evex.h | 124 +++++++++--------- opcodes/i386-dis.c | 47 ++++++- opcodes/i386-opc.h | 1 + opcodes/i386-opc.tbl | 67 ++++++++++ 12 files changed, 762 insertions(+), 91 deletions(-) create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ndd.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ndd.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 48916bc3846..381e389bb04 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2261,8 +2261,9 @@ operand_size_match (const insn_template *t) unsigned int given = i.operands - j - 1; /* For FMA4 and XOP insns VEX.W controls just the first two - register operands. */ - if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP)) + register operands. And APX insns just swap the first operands. */ + if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP) + || (is_cpu (t,CpuAPX_F) && i.operands == 3)) given = j < 2 ? 1 - j : j; if (t->operand_types[j].bitfield.class == Reg @@ -3876,6 +3877,7 @@ is_any_apx_encoding (void) { return i.rex2 || i.rex2_encoding + || i.tm.opcode_space == SPACE_EVEXMAP4 || (i.vex.register_specifier && i.vex.register_specifier->reg_flags & RegRex2); } @@ -4204,6 +4206,10 @@ build_legacy_insns_with_apx_encoding (void) } build_evex_insns_with_extend_evex_prefix (); + + /* Encode the NDD bit. */ + if (i.vex.register_specifier) + i.vex.bytes[3] |= 0x10; } static void @@ -7383,26 +7389,31 @@ match_template (char mnem_suffix) overlap1 = operand_type_and (operand_types[0], operand_types[1]); if (t->opcode_modifier.d && i.reg_operands == i.operands && !operand_type_all_zero (&overlap1)) - switch (i.dir_encoding) - { - case dir_encoding_load: - if (operand_type_check (operand_types[i.operands - 1], anymem) - || t->opcode_modifier.regmem) - goto check_reverse; - break; + { + int isMemOperand = (t->opcode_modifier.vexvvvv + && t->opcode_space == SPACE_EVEXMAP4) + ? i.operands - 2 : i.operands - 1; + switch (i.dir_encoding) + { + case dir_encoding_load: + if (operand_type_check (operand_types[isMemOperand], anymem) + || t->opcode_modifier.regmem) + goto check_reverse; + break; - case dir_encoding_store: - if (!operand_type_check (operand_types[i.operands - 1], anymem) - && !t->opcode_modifier.regmem) - goto check_reverse; - break; + case dir_encoding_store: + if (!operand_type_check (operand_types[isMemOperand], anymem) + && !t->opcode_modifier.regmem) + goto check_reverse; + break; - case dir_encoding_swap: - goto check_reverse; + case dir_encoding_swap: + goto check_reverse; - case dir_encoding_default: - break; - } + case dir_encoding_default: + break; + } + } /* If we want store form, we skip the current load. */ if ((i.dir_encoding == dir_encoding_store || i.dir_encoding == dir_encoding_swap) @@ -7432,11 +7443,13 @@ match_template (char mnem_suffix) continue; /* Try reversing direction of operands. */ j = is_cpu (t, CpuFMA4) - || is_cpu (t, CpuXOP) ? 1 : i.operands - 1; + || is_cpu (t, CpuXOP) + || is_cpu (t, CpuAPX_F) ? 1 : i.operands - 1; overlap0 = operand_type_and (i.types[0], operand_types[j]); overlap1 = operand_type_and (i.types[j], operand_types[0]); overlap2 = operand_type_and (i.types[1], operand_types[1]); - gas_assert (t->operands != 3 || !check_register); + gas_assert (t->operands != 3 || !check_register + || is_cpu (t,CpuAPX_F)); if (!operand_type_match (overlap0, i.types[0]) || !operand_type_match (overlap1, i.types[j]) || (t->operands == 3 @@ -7471,6 +7484,12 @@ match_template (char mnem_suffix) found_reverse_match = Opcode_VexW; goto check_operands_345; } + else if (is_cpu (t,CpuAPX_F) + && i.operands == 3) + { + found_reverse_match = Opcode_APX_NDDD; + goto check_operands_345; + } else if (t->opcode_space != SPACE_BASE && (t->opcode_space != SPACE_0F /* MOV to/from CR/DR/TR, as an exception, follow @@ -7636,6 +7655,15 @@ match_template (char mnem_suffix) flipping VEX.W. */ i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1; + j = i.tm.operand_types[0].bitfield.imm8; + i.tm.operand_types[j] = operand_types[j + 1]; + i.tm.operand_types[j + 1] = operand_types[j]; + break; + + case Opcode_APX_NDDD: + /* Only the first two register operands need reversing. */ + i.tm.base_opcode ^= 0x2; + j = i.tm.operand_types[0].bitfield.imm8; i.tm.operand_types[j] = operand_types[j + 1]; i.tm.operand_types[j + 1] = operand_types[j]; @@ -8462,8 +8490,8 @@ process_operands (void) const reg_entry *default_seg = NULL; /* We only need to check those implicit registers for instructions - with 3 operands or less. */ - if (i.operands <= 3) + with 4 operands or less. */ + if (i.operands <= 4) for (unsigned int j = 0; j < i.operands; j++) if (i.types[j].bitfield.instance != InstanceNone) i.reg_operands--; @@ -8825,6 +8853,9 @@ build_modrm_byte (void) break; if (v >= dest) v = ~0; + if (i.tm.opcode_space == SPACE_EVEXMAP4 + && i.tm.opcode_modifier.vexvvvv) + v = dest; if (i.tm.extension_opcode != None) { if (dest != source) @@ -9088,6 +9119,9 @@ build_modrm_byte (void) set_rex_vrex (i.op[op].regs, REX_B, false); } + if (i.tm.opcode_space == SPACE_EVEXMAP4 + && i.tm.opcode_modifier.vexvvvv) + dest--; if (op == dest) dest = ~0; if (op == source) diff --git a/gas/testsuite/gas/i386/x86-64-apx-ndd.d b/gas/testsuite/gas/i386/x86-64-apx-ndd.d new file mode 100644 index 00000000000..debb99f2ff9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-ndd.d @@ -0,0 +1,165 @@ +#as: +#objdump: -dw +#name: x86-64 APX NDD instructions with evex prefix encoding +#source: x86-64-apx-ndd.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 f4 e4 18 ff c0\s+inc %rax,%rbx +\s*[a-f0-9]+:\s*62 dc bc 18 ff c7\s+inc %r31,%r8 +\s*[a-f0-9]+:\s*62 dc fc 10 ff c7\s+inc %r31,%r16 +\s*[a-f0-9]+:\s*62 44 7c 10 00 f8\s+add %r31b,%r8b,%r16b +\s*[a-f0-9]+:\s*62 44 7c 10 00 f8\s+add %r31b,%r8b,%r16b +\s*[a-f0-9]+:\s*62 44 fc 10 01 f8\s+add %r31,%r8,%r16 +\s*[a-f0-9]+:\s*62 44 fc 10 01 f8\s+add %r31,%r8,%r16 +\s*[a-f0-9]+:\s*62 44 7c 10 01 f8\s+add %r31d,%r8d,%r16d +\s*[a-f0-9]+:\s*62 44 7c 10 01 f8\s+add %r31d,%r8d,%r16d +\s*[a-f0-9]+:\s*62 44 7d 10 01 f8\s+add %r31w,%r8w,%r16w +\s*[a-f0-9]+:\s*62 44 7d 10 01 f8\s+add %r31w,%r8w,%r16w +\s*[a-f0-9]+:\s*62 44 fc 10 01 f8\s+add %r31,%r8,%r16 +\s*[a-f0-9]+:\s*62 5c fc 10 03 c7\s+add %r31,%r8,%r16 +\s*[a-f0-9]+:\s*62 44 fc 10 01 38\s+add %r31,\(%r8\),%r16 +\s*[a-f0-9]+:\s*62 5c fc 10 03 07\s+add \(%r31\),%r8,%r16 +\s*[a-f0-9]+:\s*62 5c f8 10 03 84 07 90 90 00 00\s+add\s+0x9090\(%r31,%r16,1\),%r8,%r16 +\s*[a-f0-9]+:\s*62 44 f8 10 01 3c c0\s+add %r31,\(%r8,%r16,8\),%r16 +\s*[a-f0-9]+:\s*62 d4 74 10 80 c5 34\s+add \$0x34,%r13b,%r17b +\s*[a-f0-9]+:\s*62 fc 5c 10 83 04 83 11\s+addl \$0x11,\(%r19,%rax,4\),%r20d +\s*[a-f0-9]+:\s*62 f4 0d 10 81 c0 34 12\s+add \$0x1234,%ax,%r30w +\s*[a-f0-9]+:\s*62 d4 fc 10 81 c7 33 44 34 12\s+add \$0x12344433,%r15,%r16 +\s*[a-f0-9]+:\s*62 d4 fc 10 81 04 8f 33 44 34 12\s+addq \$0x12344433,\(%r15,%rcx,4\),%r16 +\s*[a-f0-9]+:\s*62 f4 bc 18 81 c0 11 22 33 f4\s+add \$0xfffffffff4332211,%rax,%r8 +\s*[a-f0-9]+:\s*62 f4 f4 10 ff c8 dec %rax,%r17 +\s*[a-f0-9]+:\s*62 9c 3c 18 fe 0c 27 decb \(%r31,%r12,1\),%r8b +\s*[a-f0-9]+:\s*62 f4 f4 10 f7 d0 not %rax,%r17 +\s*[a-f0-9]+:\s*62 9c 3c 18 f6 14 27 notb \(%r31,%r12,1\),%r8b +\s*[a-f0-9]+:\s*62 f4 f4 10 f7 d8 neg %rax,%r17 +\s*[a-f0-9]+:\s*62 9c 3c 18 f6 1c 27 negb \(%r31,%r12,1\),%r8b +\s*[a-f0-9]+:\s*62 7c 6c 10 28 f9 sub %r15b,%r17b,%r18b +\s*[a-f0-9]+:\s*62 54 6c 10 29 38 sub %r15d,\(%r8\),%r18d +\s*[a-f0-9]+:\s*62 c4 3c 18 2a 04 07 sub \(%r15,%rax,1\),%r16b,%r8b +\s*[a-f0-9]+:\s*62 c4 3d 18 2b 04 07 sub \(%r15,%rax,1\),%r16w,%r8w +\s*[a-f0-9]+:\s*62 fc 5c 10 83 2c 83 11 subl \$0x11,\(%r19,%rax,4\),%r20d +\s*[a-f0-9]+:\s*62 f4 0d 10 81 e8 34 12 sub \$0x1234,%ax,%r30w +\s*[a-f0-9]+:\s*62 7c 6c 10 18 f9 sbb %r15b,%r17b,%r18b +\s*[a-f0-9]+:\s*62 54 6c 10 19 38 sbb %r15d,\(%r8\),%r18d +\s*[a-f0-9]+:\s*62 c4 3c 18 1a 04 07 sbb \(%r15,%rax,1\),%r16b,%r8b +\s*[a-f0-9]+:\s*62 c4 3d 18 1b 04 07 sbb \(%r15,%rax,1\),%r16w,%r8w +\s*[a-f0-9]+:\s*62 fc 5c 10 83 1c 83 11 sbbl \$0x11,\(%r19,%rax,4\),%r20d +\s*[a-f0-9]+:\s*62 f4 0d 10 81 d8 34 12 sbb \$0x1234,%ax,%r30w +\s*[a-f0-9]+:\s*62 7c 6c 10 10 f9 adc %r15b,%r17b,%r18b +\s*[a-f0-9]+:\s*62 54 6c 10 11 38 adc %r15d,\(%r8\),%r18d +\s*[a-f0-9]+:\s*62 c4 3c 18 12 04 07 adc \(%r15,%rax,1\),%r16b,%r8b +\s*[a-f0-9]+:\s*62 c4 3d 18 13 04 07 adc \(%r15,%rax,1\),%r16w,%r8w +\s*[a-f0-9]+:\s*62 fc 5c 10 83 14 83 11 adcl \$0x11,\(%r19,%rax,4\),%r20d +\s*[a-f0-9]+:\s*62 f4 0d 10 81 d0 34 12 adc \$0x1234,%ax,%r30w +\s*[a-f0-9]+:\s*62 7c 6c 10 08 f9 or %r15b,%r17b,%r18b +\s*[a-f0-9]+:\s*62 54 6c 10 09 38 or %r15d,\(%r8\),%r18d +\s*[a-f0-9]+:\s*62 c4 3c 18 0a 04 07 or \(%r15,%rax,1\),%r16b,%r8b +\s*[a-f0-9]+:\s*62 c4 3d 18 0b 04 07 or \(%r15,%rax,1\),%r16w,%r8w +\s*[a-f0-9]+:\s*62 fc 5c 10 83 0c 83 11 orl \$0x11,\(%r19,%rax,4\),%r20d +\s*[a-f0-9]+:\s*62 f4 0d 10 81 c8 34 12 or \$0x1234,%ax,%r30w +\s*[a-f0-9]+:\s*62 7c 6c 10 30 f9 xor %r15b,%r17b,%r18b +\s*[a-f0-9]+:\s*62 54 6c 10 31 38 xor %r15d,\(%r8\),%r18d +\s*[a-f0-9]+:\s*62 c4 3c 18 32 04 07 xor \(%r15,%rax,1\),%r16b,%r8b +\s*[a-f0-9]+:\s*62 c4 3d 18 33 04 07 xor \(%r15,%rax,1\),%r16w,%r8w +\s*[a-f0-9]+:\s*62 fc 5c 10 83 34 83 11 xorl \$0x11,\(%r19,%rax,4\),%r20d +\s*[a-f0-9]+:\s*62 f4 0d 10 81 f0 34 12 xor \$0x1234,%ax,%r30w +\s*[a-f0-9]+:\s*62 7c 6c 10 20 f9 and %r15b,%r17b,%r18b +\s*[a-f0-9]+:\s*62 54 6c 10 21 38 and %r15d,\(%r8\),%r18d +\s*[a-f0-9]+:\s*62 c4 3c 18 22 04 07 and \(%r15,%rax,1\),%r16b,%r8b +\s*[a-f0-9]+:\s*62 c4 3d 18 23 04 07 and \(%r15,%rax,1\),%r16w,%r8w +\s*[a-f0-9]+:\s*62 fc 5c 10 83 24 83 11 andl \$0x11,\(%r19,%rax,4\),%r20d +\s*[a-f0-9]+:\s*62 f4 0d 10 81 e0 34 12 and \$0x1234,%ax,%r30w +\s*[a-f0-9]+:\s*62 f4 04 10 d0 08 rorb \(%rax\),%r31b +\s*[a-f0-9]+:\s*62 d4 04 10 c0 cc 02 ror \$0x2,%r12b,%r31b +\s*[a-f0-9]+:\s*62 f4 04 10 c1 08 02 rorl \$0x2,\(%rax\),%r31d +\s*[a-f0-9]+:\s*62 f4 05 10 d1 08 rorw \(%rax\),%r31w +\s*[a-f0-9]+:\s*62 fc 3c 18 d2 c8 ror %cl,%r16b,%r8b +\s*[a-f0-9]+:\s*62 fc 05 10 d3 0c 83 rorw %cl,\(%r19,%rax,4\),%r31w +\s*[a-f0-9]+:\s*62 f4 04 10 d0 00 rolb \(%rax\),%r31b +\s*[a-f0-9]+:\s*62 d4 04 10 c0 c4 02 rol \$0x2,%r12b,%r31b +\s*[a-f0-9]+:\s*62 f4 04 10 c1 00 02 roll \$0x2,\(%rax\),%r31d +\s*[a-f0-9]+:\s*62 f4 05 10 d1 00 rolw \(%rax\),%r31w +\s*[a-f0-9]+:\s*62 fc 3c 18 d2 c0 rol %cl,%r16b,%r8b +\s*[a-f0-9]+:\s*62 fc 05 10 d3 04 83 rolw %cl,\(%r19,%rax,4\),%r31w +\s*[a-f0-9]+:\s*62 f4 04 10 d0 18 rcrb \(%rax\),%r31b +\s*[a-f0-9]+:\s*62 d4 04 10 c0 dc 02 rcr \$0x2,%r12b,%r31b +\s*[a-f0-9]+:\s*62 f4 04 10 c1 18 02 rcrl \$0x2,\(%rax\),%r31d +\s*[a-f0-9]+:\s*62 f4 05 10 d1 18 rcrw \(%rax\),%r31w +\s*[a-f0-9]+:\s*62 fc 3c 18 d2 d8 rcr %cl,%r16b,%r8b +\s*[a-f0-9]+:\s*62 fc 05 10 d3 1c 83 rcrw %cl,\(%r19,%rax,4\),%r31w +\s*[a-f0-9]+:\s*62 f4 04 10 d0 10 rclb \(%rax\),%r31b +\s*[a-f0-9]+:\s*62 d4 04 10 c0 d4 02 rcl \$0x2,%r12b,%r31b +\s*[a-f0-9]+:\s*62 f4 04 10 c1 10 02 rcll \$0x2,\(%rax\),%r31d +\s*[a-f0-9]+:\s*62 f4 05 10 d1 10 rclw \(%rax\),%r31w +\s*[a-f0-9]+:\s*62 fc 3c 18 d2 d0 rcl %cl,%r16b,%r8b +\s*[a-f0-9]+:\s*62 fc 05 10 d3 14 83 rclw %cl,\(%r19,%rax,4\),%r31w +\s*[a-f0-9]+:\s*62 f4 04 10 d0 20 shlb \(%rax\),%r31b +\s*[a-f0-9]+:\s*62 d4 04 10 c0 e4 02 shl \$0x2,%r12b,%r31b +\s*[a-f0-9]+:\s*62 f4 04 10 c1 20 02 shll \$0x2,\(%rax\),%r31d +\s*[a-f0-9]+:\s*62 f4 05 10 d1 20 shlw \(%rax\),%r31w +\s*[a-f0-9]+:\s*62 fc 3c 18 d2 e0 shl %cl,%r16b,%r8b +\s*[a-f0-9]+:\s*62 fc 05 10 d3 24 83 shlw %cl,\(%r19,%rax,4\),%r31w +\s*[a-f0-9]+:\s*62 f4 04 10 d0 38 sarb \(%rax\),%r31b +\s*[a-f0-9]+:\s*62 d4 04 10 c0 fc 02 sar \$0x2,%r12b,%r31b +\s*[a-f0-9]+:\s*62 f4 04 10 c1 38 02 sarl \$0x2,\(%rax\),%r31d +\s*[a-f0-9]+:\s*62 f4 05 10 d1 38 sarw \(%rax\),%r31w +\s*[a-f0-9]+:\s*62 fc 3c 18 d2 f8 sar %cl,%r16b,%r8b +\s*[a-f0-9]+:\s*62 fc 05 10 d3 3c 83 sarw %cl,\(%r19,%rax,4\),%r31w +\s*[a-f0-9]+:\s*62 f4 04 10 d0 20 shlb \(%rax\),%r31b +\s*[a-f0-9]+:\s*62 d4 04 10 c0 e4 02 shl \$0x2,%r12b,%r31b +\s*[a-f0-9]+:\s*62 f4 04 10 c1 20 02 shll \$0x2,\(%rax\),%r31d +\s*[a-f0-9]+:\s*62 f4 05 10 d1 20 shlw \(%rax\),%r31w +\s*[a-f0-9]+:\s*62 fc 3c 18 d2 e0 shl %cl,%r16b,%r8b +\s*[a-f0-9]+:\s*62 fc 05 10 d3 24 83 shlw %cl,\(%r19,%rax,4\),%r31w +\s*[a-f0-9]+:\s*62 f4 04 10 d0 28 shrb \(%rax\),%r31b +\s*[a-f0-9]+:\s*62 d4 04 10 c0 ec 02 shr \$0x2,%r12b,%r31b +\s*[a-f0-9]+:\s*62 f4 04 10 c1 28 02 shrl \$0x2,\(%rax\),%r31d +\s*[a-f0-9]+:\s*62 f4 05 10 d1 28 shrw \(%rax\),%r31w +\s*[a-f0-9]+:\s*62 fc 3c 18 d2 e8 shr %cl,%r16b,%r8b +\s*[a-f0-9]+:\s*62 fc 05 10 d3 2c 83 shrw %cl,\(%r19,%rax,4\),%r31w +\s*[a-f0-9]+:\s*62 74 84 10 24 20 01 shld \$0x1,%r12,\(%rax\),%r31 +\s*[a-f0-9]+:\s*62 54 05 10 24 c4 02 shld \$0x2,%r8w,%r12w,%r31w +\s*[a-f0-9]+:\s*62 74 04 10 24 38 02 shld \$0x2,%r15d,\(%rax\),%r31d +\s*[a-f0-9]+:\s*62 74 05 10 a5 08 shld %cl,%r9w,\(%rax\),%r31w +\s*[a-f0-9]+:\s*62 7c bc 18 a5 e0\s+shld %cl,%r12,%r16,%r8 +\s*[a-f0-9]+:\s*62 7c 05 10 a5 2c 83\s+shld %cl,%r13w,\(%r19,%rax,4\),%r31w +\s*[a-f0-9]+:\s*62 74 84 10 2c 20 01 shrd \$0x1,%r12,\(%rax\),%r31 +\s*[a-f0-9]+:\s*62 54 05 10 2c c4 02 shrd \$0x2,%r8w,%r12w,%r31w +\s*[a-f0-9]+:\s*62 74 04 10 2c 38 02 shrd \$0x2,%r15d,\(%rax\),%r31d +\s*[a-f0-9]+:\s*62 74 05 10 ad 08\s+shrd %cl,%r9w,\(%rax\),%r31w +\s*[a-f0-9]+:\s*62 7c bc 18 ad e0\s+shrd %cl,%r12,%r16,%r8 +\s*[a-f0-9]+:\s*62 7c 05 10 ad 2c 83\s+shrd %cl,%r13w,\(%r19,%rax,4\),%r31w +\s*[a-f0-9]+:\s*62 54 6d 10 66 c7 adcx %r15d,%r8d,%r18d +\s*[a-f0-9]+:\s*62 14 69 10 66 04 3f adcx \(%r15,%r31,1\),%r8d,%r18d +\s*[a-f0-9]+:\s*62 14 f9 08 66 04 3f adcx \(%r15,%r31,1\),%r8 +\s*[a-f0-9]+:\s*62 54 6e 10 66 c7 adox %r15d,%r8d,%r18d +\s*[a-f0-9]+:\s*62 14 6a 10 66 04 3f adox \(%r15,%r31,1\),%r8d,%r18d +\s*[a-f0-9]+:\s*62 14 fa 08 66 04 3f adox \(%r15,%r31,1\),%r8 +\s*[a-f0-9]+:\s*67 62 f4 3c 18 40 90 90 90 90 90 cmovo -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 41 90 90 90 90 90 cmovno -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 42 90 90 90 90 90 cmovb -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 43 90 90 90 90 90 cmovae -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 44 90 90 90 90 90 cmove -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 45 90 90 90 90 90 cmovne -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 46 90 90 90 90 90 cmovbe -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 47 90 90 90 90 90 cmova -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 48 90 90 90 90 90 cmovs -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 49 90 90 90 90 90 cmovns -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 4c 90 90 90 90 90 cmovl -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 4d 90 90 90 90 90 cmovge -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 4e 90 90 90 90 90 cmovle -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 4f 90 90 90 90 90 cmovg -0x6f6f6f70\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*67 62 f4 3c 18 af 90 09 09 09 00 imul 0x90909\(%eax\),%edx,%r8d +\s*[a-f0-9]+:\s*62 b4 b0 10 af 94 f8 09 09 00 00 imul 0x909\(%rax,%r31,8\),%rdx,%r25 +\s*[a-f0-9]+:\s*62 f4 fc 08 ff c0\s+inc %rax +\s*[a-f0-9]+:\s*62 f4 ec\s+\(bad\) +\s*[a-f0-9]+:\s*08 ff\s+or %bh,%bh +\s*[a-f0-9]+:\s*c0\s+\.byte 0xc0 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-apx-ndd.s b/gas/testsuite/gas/i386/x86-64-apx-ndd.s new file mode 100644 index 00000000000..8c86989ffe5 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-ndd.s @@ -0,0 +1,156 @@ +# Check 64bit APX NDD instructions with evex prefix encoding + + .allow_index_reg + .text +_start: +inc %rax,%rbx +inc %r31,%r8 +inc %r31,%r16 +add %r31b,%r8b,%r16b +addb %r31b,%r8b,%r16b +add %r31,%r8,%r16 +addq %r31,%r8,%r16 +add %r31d,%r8d,%r16d +addl %r31d,%r8d,%r16d +add %r31w,%r8w,%r16w +addw %r31w,%r8w,%r16w +{store} add %r31,%r8,%r16 +{load} add %r31,%r8,%r16 +add %r31,(%r8),%r16 +add (%r31),%r8,%r16 +add 0x9090(%r31,%r16,1),%r8,%r16 +add %r31,(%r8,%r16,8),%r16 +add $0x34,%r13b,%r17b +addl $0x11,(%r19,%rax,4),%r20d +add $0x1234,%ax,%r30w +add $0x12344433,%r15,%r16 +addq $0x12344433,(%r15,%rcx,4),%r16 +add $0xfffffffff4332211,%rax,%r8 +dec %rax,%r17 +decb (%r31,%r12,1),%r8b +not %rax,%r17 +notb (%r31,%r12,1),%r8b +neg %rax,%r17 +negb (%r31,%r12,1),%r8b +sub %r15b,%r17b,%r18b +sub %r15d,(%r8),%r18d +sub (%r15,%rax,1),%r16b,%r8b +sub (%r15,%rax,1),%r16w,%r8w +subl $0x11,(%r19,%rax,4),%r20d +sub $0x1234,%ax,%r30w +sbb %r15b,%r17b,%r18b +sbb %r15d,(%r8),%r18d +sbb (%r15,%rax,1),%r16b,%r8b +sbb (%r15,%rax,1),%r16w,%r8w +sbbl $0x11,(%r19,%rax,4),%r20d +sbb $0x1234,%ax,%r30w +adc %r15b,%r17b,%r18b +adc %r15d,(%r8),%r18d +adc (%r15,%rax,1),%r16b,%r8b +adc (%r15,%rax,1),%r16w,%r8w +adcl $0x11,(%r19,%rax,4),%r20d +adc $0x1234,%ax,%r30w +or %r15b,%r17b,%r18b +or %r15d,(%r8),%r18d +or (%r15,%rax,1),%r16b,%r8b +or (%r15,%rax,1),%r16w,%r8w +orl $0x11,(%r19,%rax,4),%r20d +or $0x1234,%ax,%r30w +xor %r15b,%r17b,%r18b +xor %r15d,(%r8),%r18d +xor (%r15,%rax,1),%r16b,%r8b +xor (%r15,%rax,1),%r16w,%r8w +xorl $0x11,(%r19,%rax,4),%r20d +xor $0x1234,%ax,%r30w +and %r15b,%r17b,%r18b +and %r15d,(%r8),%r18d +and (%r15,%rax,1),%r16b,%r8b +and (%r15,%rax,1),%r16w,%r8w +andl $0x11,(%r19,%rax,4),%r20d +and $0x1234,%ax,%r30w +rorb (%rax),%r31b +ror $0x2,%r12b,%r31b +rorl $0x2,(%rax),%r31d +rorw (%rax),%r31w +ror %cl,%r16b,%r8b +rorw %cl,(%r19,%rax,4),%r31w +rolb (%rax),%r31b +rol $0x2,%r12b,%r31b +roll $0x2,(%rax),%r31d +rolw (%rax),%r31w +rol %cl,%r16b,%r8b +rolw %cl,(%r19,%rax,4),%r31w +rcrb (%rax),%r31b +rcr $0x2,%r12b,%r31b +rcrl $0x2,(%rax),%r31d +rcrw (%rax),%r31w +rcr %cl,%r16b,%r8b +rcrw %cl,(%r19,%rax,4),%r31w +rclb (%rax),%r31b +rcl $0x2,%r12b,%r31b +rcll $0x2,(%rax),%r31d +rclw (%rax),%r31w +rcl %cl,%r16b,%r8b +rclw %cl,(%r19,%rax,4),%r31w +shlb (%rax),%r31b +shl $0x2,%r12b,%r31b +shll $0x2,(%rax),%r31d +shlw (%rax),%r31w +shl %cl,%r16b,%r8b +shlw %cl,(%r19,%rax,4),%r31w +sarb (%rax),%r31b +sar $0x2,%r12b,%r31b +sarl $0x2,(%rax),%r31d +sarw (%rax),%r31w +sar %cl,%r16b,%r8b +sarw %cl,(%r19,%rax,4),%r31w +shlb (%rax),%r31b +shl $0x2,%r12b,%r31b +shll $0x2,(%rax),%r31d +shlw (%rax),%r31w +shl %cl,%r16b,%r8b +shlw %cl,(%r19,%rax,4),%r31w +shrb (%rax),%r31b +shr $0x2,%r12b,%r31b +shrl $0x2,(%rax),%r31d +shrw (%rax),%r31w +shr %cl,%r16b,%r8b +shrw %cl,(%r19,%rax,4),%r31w +shld $0x1,%r12,(%rax),%r31 +shld $0x2,%r8w,%r12w,%r31w +shld $0x2,%r15d,(%rax),%r31d +shld %cl,%r9w,(%rax),%r31w +shld %cl,%r12,%r16,%r8 +shld %cl,%r13w,(%r19,%rax,4),%r31w +shrd $0x1,%r12,(%rax),%r31 +shrd $0x2,%r8w,%r12w,%r31w +shrd $0x2,%r15d,(%rax),%r31d +shrd %cl,%r9w,(%rax),%r31w +shrd %cl,%r12,%r16,%r8 +shrd %cl,%r13w,(%r19,%rax,4),%r31w +adcx %r15d,%r8d,%r18d +adcx (%r15,%r31,1),%r8d,%r18d +adcx (%r15,%r31,1),%r8 +adox %r15d,%r8d,%r18d +adox (%r15,%r31,1),%r8d,%r18d +adox (%r15,%r31,1),%r8 +cmovo 0x90909090(%eax),%edx,%r8d +cmovno 0x90909090(%eax),%edx,%r8d +cmovb 0x90909090(%eax),%edx,%r8d +cmovae 0x90909090(%eax),%edx,%r8d +cmove 0x90909090(%eax),%edx,%r8d +cmovne 0x90909090(%eax),%edx,%r8d +cmovbe 0x90909090(%eax),%edx,%r8d +cmova 0x90909090(%eax),%edx,%r8d +cmovs 0x90909090(%eax),%edx,%r8d +cmovns 0x90909090(%eax),%edx,%r8d +cmovp 0x90909090(%eax),%edx,%r8d +cmovnp 0x90909090(%eax),%edx,%r8d +cmovl 0x90909090(%eax),%edx,%r8d +cmovge 0x90909090(%eax),%edx,%r8d +cmovle 0x90909090(%eax),%edx,%r8d +cmovg 0x90909090(%eax),%edx,%r8d +imul 0x90909(%eax),%edx,%r8d +imul 0x909(%rax,%r31,8),%rdx,%r25 +.byte 0x62,0xf4,0xfc,0x08,0xff,0xc0 #inc %rax +.byte 0x62,0xf4,0xec,0x08,0xff,0xc0 #bad diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.d b/gas/testsuite/gas/i386/x86-64-pseudos.d index 8cc4040cb77..f6257c01792 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.d +++ b/gas/testsuite/gas/i386/x86-64-pseudos.d @@ -137,6 +137,48 @@ Disassembly of section .text: +[a-f0-9]+: 33 07 xor \(%rdi\),%eax +[a-f0-9]+: 31 07 xor %eax,\(%rdi\) +[a-f0-9]+: 33 07 xor \(%rdi\),%eax + +[a-f0-9]+: 62 44 fc 10 01 38 add %r31,\(%r8\),%r16 + +[a-f0-9]+: 62 44 fc 10 03 38 add \(%r8\),%r31,%r16 + +[a-f0-9]+: 62 44 fc 10 01 38 add %r31,\(%r8\),%r16 + +[a-f0-9]+: 62 44 fc 10 03 38 add \(%r8\),%r31,%r16 + +[a-f0-9]+: 62 54 6c 10 29 38 sub %r15d,\(%r8\),%r18d + +[a-f0-9]+: 62 54 6c 10 2b 38 sub \(%r8\),%r15d,%r18d + +[a-f0-9]+: 62 54 6c 10 29 38 sub %r15d,\(%r8\),%r18d + +[a-f0-9]+: 62 54 6c 10 2b 38 sub \(%r8\),%r15d,%r18d + +[a-f0-9]+: 62 54 6c 10 19 38 sbb %r15d,\(%r8\),%r18d + +[a-f0-9]+: 62 54 6c 10 1b 38 sbb \(%r8\),%r15d,%r18d + +[a-f0-9]+: 62 54 6c 10 19 38 sbb %r15d,\(%r8\),%r18d + +[a-f0-9]+: 62 54 6c 10 1b 38 sbb \(%r8\),%r15d,%r18d + +[a-f0-9]+: 62 54 6c 10 21 38 and %r15d,\(%r8\),%r18d + +[a-f0-9]+: 62 54 6c 10 23 38 and \(%r8\),%r15d,%r18d + +[a-f0-9]+: 62 54 6c 10 21 38 and %r15d,\(%r8\),%r18d + +[a-f0-9]+: 62 54 6c 10 23 38 and \(%r8\),%r15d,%r18d + +[a-f0-9]+: 62 54 6c 10 09 38 or %r15d,\(%r8\),%r18d + +[a-f0-9]+: 62 54 6c 10 0b 38 or \(%r8\),%r15d,%r18d + +[a-f0-9]+: 62 54 6c 10 09 38 or %r15d,\(%r8\),%r18d + +[a-f0-9]+: 62 54 6c 10 0b 38 or \(%r8\),%r15d,%r18d + +[a-f0-9]+: 62 54 6c 10 31 38 xor %r15d,\(%r8\),%r18d + +[a-f0-9]+: 62 54 6c 10 33 38 xor \(%r8\),%r15d,%r18d + +[a-f0-9]+: 62 54 6c 10 31 38 xor %r15d,\(%r8\),%r18d + +[a-f0-9]+: 62 54 6c 10 33 38 xor \(%r8\),%r15d,%r18d + +[a-f0-9]+: 62 54 6c 10 11 38 adc %r15d,\(%r8\),%r18d + +[a-f0-9]+: 62 54 6c 10 13 38 adc \(%r8\),%r15d,%r18d + +[a-f0-9]+: 62 54 6c 10 11 38 adc %r15d,\(%r8\),%r18d + +[a-f0-9]+: 62 54 6c 10 13 38 adc \(%r8\),%r15d,%r18d + +[a-f0-9]+: 62 44 fc 10 01 f8 add %r31,%r8,%r16 + +[a-f0-9]+: 62 5c fc 10 03 c7 add %r31,%r8,%r16 + +[a-f0-9]+: 62 7c 6c 10 28 f9 sub %r15b,%r17b,%r18b + +[a-f0-9]+: 62 c4 6c 10 2a cf sub %r15b,%r17b,%r18b + +[a-f0-9]+: 62 7c 6c 10 18 f9 sbb %r15b,%r17b,%r18b + +[a-f0-9]+: 62 c4 6c 10 1a cf sbb %r15b,%r17b,%r18b + +[a-f0-9]+: 62 7c 6c 10 20 f9 and %r15b,%r17b,%r18b + +[a-f0-9]+: 62 c4 6c 10 22 cf and %r15b,%r17b,%r18b + +[a-f0-9]+: 62 7c 6c 10 08 f9 or %r15b,%r17b,%r18b + +[a-f0-9]+: 62 c4 6c 10 0a cf or %r15b,%r17b,%r18b + +[a-f0-9]+: 62 7c 6c 10 30 f9 xor %r15b,%r17b,%r18b + +[a-f0-9]+: 62 c4 6c 10 32 cf xor %r15b,%r17b,%r18b + +[a-f0-9]+: 62 7c 6c 10 10 f9 adc %r15b,%r17b,%r18b + +[a-f0-9]+: 62 c4 6c 10 12 cf adc %r15b,%r17b,%r18b +[a-f0-9]+: b0 12 mov \$0x12,%al +[a-f0-9]+: b8 45 03 00 00 mov \$0x345,%eax +[a-f0-9]+: b0 12 mov \$0x12,%al diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.s b/gas/testsuite/gas/i386/x86-64-pseudos.s index eb25f2a8fbf..9f756e5ba04 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.s +++ b/gas/testsuite/gas/i386/x86-64-pseudos.s @@ -134,6 +134,49 @@ _start: {load} xor (%rdi), %eax {store} xor %eax, (%rdi) {store} xor (%rdi), %eax + {load} add %r31,(%r8),%r16 + {load} add (%r8),%r31,%r16 + {store} add %r31,(%r8),%r16 + {store} add (%r8),%r31,%r16 + {load} sub %r15d,(%r8),%r18d + {load} sub (%r8),%r15d,%r18d + {store} sub %r15d,(%r8),%r18d + {store} sub (%r8),%r15d,%r18d + {load} sbb %r15d,(%r8),%r18d + {load} sbb (%r8),%r15d,%r18d + {store} sbb %r15d,(%r8),%r18d + {store} sbb (%r8),%r15d,%r18d + {load} and %r15d,(%r8),%r18d + {load} and (%r8),%r15d,%r18d + {store} and %r15d,(%r8),%r18d + {store} and (%r8),%r15d,%r18d + {load} or %r15d,(%r8),%r18d + {load} or (%r8),%r15d,%r18d + {store} or %r15d,(%r8),%r18d + {store} or (%r8),%r15d,%r18d + {load} xor %r15d,(%r8),%r18d + {load} xor (%r8),%r15d,%r18d + {store} xor %r15d,(%r8),%r18d + {store} xor (%r8),%r15d,%r18d + {load} adc %r15d,(%r8),%r18d + {load} adc (%r8),%r15d,%r18d + {store} adc %r15d,(%r8),%r18d + {store} adc (%r8),%r15d,%r18d + + {store} add %r31,%r8,%r16 + {load} add %r31,%r8,%r16 + {store} sub %r15b,%r17b,%r18b + {load} sub %r15b,%r17b,%r18b + {store} sbb %r15b,%r17b,%r18b + {load} sbb %r15b,%r17b,%r18b + {store} and %r15b,%r17b,%r18b + {load} and %r15b,%r17b,%r18b + {store} or %r15b,%r17b,%r18b + {load} or %r15b,%r17b,%r18b + {store} xor %r15b,%r17b,%r18b + {load} xor %r15b,%r17b,%r18b + {store} adc %r15b,%r17b,%r18b + {load} adc %r15b,%r17b,%r18b .irp m, mov, adc, add, and, cmp, or, sbb, sub, test, xor \m $0x12, %al diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 46fb3681528..ca1583c6f88 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -367,6 +367,7 @@ run_dump_test "x86-64-apx-rex2-inval" run_dump_test "x86-64-apx-evex-promoted" run_dump_test "x86-64-apx-evex-promoted-intel" run_dump_test "x86-64-apx-evex-egpr" +run_dump_test "x86-64-apx-ndd" run_dump_test "x86-64-avx512f-rcigrz-intel" run_dump_test "x86-64-avx512f-rcigrz" run_dump_test "x86-64-clwb" diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h index f6f02de6c47..210783d7e88 100644 --- a/opcodes/i386-dis-evex-prefix.h +++ b/opcodes/i386-dis-evex-prefix.h @@ -353,8 +353,8 @@ /* PREFIX_EVEX_MAP4_66 */ { { MOD_TABLE (MOD_EVEX_MAP4_66_PREFIX_0) }, - { "adoxS", { Gdq, Edq }, 0 }, - { "adcxS", { Gdq, Edq }, 0 }, + { "adoxS", { VexGdq, Gdq, Edq }, 0 }, + { "adcxS", { VexGdq, Gdq, Edq }, 0 }, }, /* PREFIX_EVEX_MAP4_D8 */ { diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h index c3b4f083346..d00c2843e12 100644 --- a/opcodes/i386-dis-evex-reg.h +++ b/opcodes/i386-dis-evex-reg.h @@ -56,6 +56,105 @@ { "blsmskS", { VexGdq, Edq }, 0 }, { "blsiS", { VexGdq, Edq }, 0 }, }, + /* REG_EVEX_MAP4_80 */ + { + { "addA", { VexGb, Eb, Ib }, 0 }, + { "orA", { VexGb, Eb, Ib }, 0 }, + { "adcA", { VexGb, Eb, Ib }, 0 }, + { "sbbA", { VexGb, Eb, Ib }, 0 }, + { "andA", { VexGb, Eb, Ib }, 0 }, + { "subA", { VexGb, Eb, Ib }, 0 }, + { "xorA", { VexGb, Eb, Ib }, 0 }, + { Bad_Opcode }, + }, + /* REG_EVEX_MAP4_81 */ + { + { "addQ", { VexGv, Ev, Iv }, 0 }, + { "orQ", { VexGv, Ev, Iv }, 0 }, + { "adcQ", { VexGv, Ev, Iv }, 0 }, + { "sbbQ", { VexGv, Ev, Iv }, 0 }, + { "andQ", { VexGv, Ev, Iv }, 0 }, + { "subQ", { VexGv, Ev, Iv }, 0 }, + { "xorQ", { VexGv, Ev, Iv }, 0 }, + { Bad_Opcode }, + }, + /* REG_EVEX_MAP4_83 */ + { + { "addQ", { VexGv, Ev, sIb }, 0 }, + { "orQ", { VexGv, Ev, sIb }, 0 }, + { "adcQ", { VexGv, Ev, sIb }, 0 }, + { "sbbQ", { VexGv, Ev, sIb }, 0 }, + { "andQ", { VexGv, Ev, sIb }, 0 }, + { "subQ", { VexGv, Ev, sIb }, 0 }, + { "xorQ", { VexGv, Ev, sIb }, 0 }, + { Bad_Opcode }, + }, + /* REG_EVEX_MAP4_C0 */ + { + { "rolA", { VexGb, Eb, Ib }, 0 }, + { "rorA", { VexGb, Eb, Ib }, 0 }, + { "rclA", { VexGb, Eb, Ib }, 0 }, + { "rcrA", { VexGb, Eb, Ib }, 0 }, + { "shlA", { VexGb, Eb, Ib }, 0 }, + { "shrA", { VexGb, Eb, Ib }, 0 }, + { "shlA", { VexGb, Eb, Ib }, 0 }, + { "sarA", { VexGb, Eb, Ib }, 0 }, + }, + /* REG_EVEX_MAP4_C1 */ + { + { "rolQ", { VexGv, Ev, Ib }, 0 }, + { "rorQ", { VexGv, Ev, Ib }, 0 }, + { "rclQ", { VexGv, Ev, Ib }, 0 }, + { "rcrQ", { VexGv, Ev, Ib }, 0 }, + { "shlQ", { VexGv, Ev, Ib }, 0 }, + { "shrQ", { VexGv, Ev, Ib }, 0 }, + { "shlQ", { VexGv, Ev, Ib }, 0 }, + { "sarQ", { VexGv, Ev, Ib }, 0 }, + }, + /* REG_EVEX_MAP4_D0 */ + { + { "rolA", { VexGb, Eb, I1 }, 0 }, + { "rorA", { VexGb, Eb, I1 }, 0 }, + { "rclA", { VexGb, Eb, I1 }, 0 }, + { "rcrA", { VexGb, Eb, I1 }, 0 }, + { "shlA", { VexGb, Eb, I1 }, 0 }, + { "shrA", { VexGb, Eb, I1 }, 0 }, + { "shlA", { VexGb, Eb, I1 }, 0 }, + { "sarA", { VexGb, Eb, I1 }, 0 }, + }, + /* REG_EVEX_MAP4_D1 */ + { + { "rolQ", { VexGv, Ev, I1 }, 0 }, + { "rorQ", { VexGv, Ev, I1 }, 0 }, + { "rclQ", { VexGv, Ev, I1 }, 0 }, + { "rcrQ", { VexGv, Ev, I1 }, 0 }, + { "shlQ", { VexGv, Ev, I1 }, 0 }, + { "shrQ", { VexGv, Ev, I1 }, 0 }, + { "shlQ", { VexGv, Ev, I1 }, 0 }, + { "sarQ", { VexGv, Ev, I1 }, 0 }, + }, + /* REG_EVEX_MAP4_D2 */ + { + { "rolA", { VexGb, Eb, CL }, 0 }, + { "rorA", { VexGb, Eb, CL }, 0 }, + { "rclA", { VexGb, Eb, CL }, 0 }, + { "rcrA", { VexGb, Eb, CL }, 0 }, + { "shlA", { VexGb, Eb, CL }, 0 }, + { "shrA", { VexGb, Eb, CL }, 0 }, + { "shlA", { VexGb, Eb, CL }, 0 }, + { "sarA", { VexGb, Eb, CL }, 0 }, + }, + /* REG_EVEX_MAP4_D3 */ + { + { "rolQ", { VexGv, Ev, CL }, 0 }, + { "rorQ", { VexGv, Ev, CL }, 0 }, + { "rclQ", { VexGv, Ev, CL }, 0 }, + { "rcrQ", { VexGv, Ev, CL }, 0 }, + { "shlQ", { VexGv, Ev, CL }, 0 }, + { "shrQ", { VexGv, Ev, CL }, 0 }, + { "shlQ", { VexGv, Ev, CL }, 0 }, + { "sarQ", { VexGv, Ev, CL }, 0 }, + }, /* REG_EVEX_MAP4_D8_PREFIX_1 */ { { "aesencwide128kl", { M }, 0 }, @@ -63,3 +162,27 @@ { "aesencwide256kl", { M }, 0 }, { "aesdecwide256kl", { M }, 0 }, }, + /* REG_EVEX_MAP4_F6 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "notA", { VexGb, Eb }, 0 }, + { "negA", { VexGb, Eb }, 0 }, + }, + /* REG_EVEX_MAP4_F7 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "notQ", { VexGv, Ev }, 0 }, + { "negQ", { VexGv, Ev }, 0 }, + }, + /* REG_EVEX_MAP4_FE */ + { + { "incA", { VexGb ,Eb }, 0 }, + { "decA", { VexGb ,Eb }, 0 }, + }, + /* REG_EVEX_MAP4_FF */ + { + { "incQ", { VexGv ,Ev }, 0 }, + { "decQ", { VexGv ,Ev }, 0 }, + }, diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index 2a8c80c5200..1787be6dbf0 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -875,64 +875,64 @@ static const struct dis386 evex_table[][256] = { /* EVEX_MAP4_ */ { /* 00 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "addB", { VexGb, Eb, Gb }, 0 }, + { "addS", { VexGv, Ev, Gv }, 0 }, + { "addB", { VexGb, Gb, EbS }, 0 }, + { "addS", { VexGv, Gv, EvS }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 08 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "orB", { VexGb, Eb, Gb }, 0 }, + { "orS", { VexGv, Ev, Gv }, 0 }, + { "orB", { VexGb, Gb, EbS }, 0 }, + { "orS", { VexGv, Gv, EvS }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 10 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "adcB", { VexGb, Eb, Gb }, 0 }, + { "adcS", { VexGv, Ev, Gv }, 0 }, + { "adcB", { VexGb, Gb, EbS }, 0 }, + { "adcS", { VexGv, Gv, EvS }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 18 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "sbbB", { VexGb, Eb, Gb }, 0 }, + { "sbbS", { VexGv, Ev, Gv }, 0 }, + { "sbbB", { VexGb, Gb, EbS }, 0 }, + { "sbbS", { VexGv, Gv, EvS }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 20 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "andB", { VexGb, Eb, Gb }, 0 }, + { "andS", { VexGv, Ev, Gv }, 0 }, + { "andB", { VexGb, Gb, EbS }, 0 }, + { "andS", { VexGv, Gv, EvS }, 0 }, + { "shldS", { VexGv, Ev, Gv, Ib }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 28 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "subB", { VexGb, Eb, Gb }, 0 }, + { "subS", { VexGv, Ev, Gv }, 0 }, + { "subB", { VexGb, Gb, EbS }, 0 }, + { "subS", { VexGv, Gv, EvS }, 0 }, + { "shrdS", { VexGv, Ev, Gv, Ib }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 30 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "xorB", { VexGb, Eb, Gb }, 0 }, + { "xorS", { VexGv, Ev, Gv }, 0 }, + { "xorB", { VexGb, Gb, EbS }, 0 }, + { "xorS", { VexGv, Gv, EvS }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -947,23 +947,23 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 40 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "cmovoS", { VexGv, Gv, Ev }, 0 }, + { "cmovnoS", { VexGv, Gv, Ev }, 0 }, + { "cmovbS", { VexGv, Gv, Ev }, 0 }, + { "cmovaeS", { VexGv, Gv, Ev }, 0 }, + { "cmoveS", { VexGv, Gv, Ev }, 0 }, + { "cmovneS", { VexGv, Gv, Ev }, 0 }, + { "cmovbeS", { VexGv, Gv, Ev }, 0 }, + { "cmovaS", { VexGv, Gv, Ev }, 0 }, /* 48 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "cmovsS", { VexGv, Gv, Ev }, 0 }, + { "cmovnsS", { VexGv, Gv, Ev }, 0 }, + { "cmovpS", { VexGv, Gv, Ev }, 0 }, + { "cmovnpS", { VexGv, Gv, Ev }, 0 }, + { "cmovlS", { VexGv, Gv, Ev }, 0 }, + { "cmovgeS", { VexGv, Gv, Ev }, 0 }, + { "cmovleS", { VexGv, Gv, Ev }, 0 }, + { "cmovgS", { VexGv, Gv, Ev }, 0 }, /* 50 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1019,10 +1019,10 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 80 */ + { REG_TABLE (REG_EVEX_MAP4_80) }, + { REG_TABLE (REG_EVEX_MAP4_81) }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { REG_TABLE (REG_EVEX_MAP4_83) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -1060,7 +1060,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { "shldS", { VexGv, Ev, Gv, CL }, 0 }, { Bad_Opcode }, { Bad_Opcode }, /* A8 */ @@ -1069,9 +1069,9 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { "shrdS", { VexGv, Ev, Gv, CL }, 0 }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "imulS", { VexGv, Gv, Ev }, 0 }, /* B0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1091,8 +1091,8 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* C0 */ - { Bad_Opcode }, - { Bad_Opcode }, + { REG_TABLE (REG_EVEX_MAP4_C0) }, + { REG_TABLE (REG_EVEX_MAP4_C1) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -1109,10 +1109,10 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* D0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { REG_TABLE (REG_EVEX_MAP4_D0) }, + { REG_TABLE (REG_EVEX_MAP4_D1) }, + { REG_TABLE (REG_EVEX_MAP4_D2) }, + { REG_TABLE (REG_EVEX_MAP4_D3) }, { "sha1rnds4", { XM, EXxmm, Ib }, 0 }, { Bad_Opcode }, { Bad_Opcode }, @@ -1151,8 +1151,8 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { REG_TABLE (REG_EVEX_MAP4_F6) }, + { REG_TABLE (REG_EVEX_MAP4_F7) }, /* F8 */ { PREFIX_TABLE (PREFIX_EVEX_MAP4_F8) }, { MOD_TABLE (MOD_EVEX_MAP4_F9) }, @@ -1160,8 +1160,8 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { PREFIX_TABLE (PREFIX_EVEX_MAP4_FC) }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { REG_TABLE (REG_EVEX_MAP4_FE) }, + { REG_TABLE (REG_EVEX_MAP4_FF) }, }, /* EVEX_MAP5_ */ { diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index c8f3cfb8149..c702fd9e756 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -571,6 +571,8 @@ fetch_error (const instr_info *ins) #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode } #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } #define VexGdq { OP_VEX, dq_mode } +#define VexGb { OP_VEX, b_mode } +#define VexGv { OP_VEX, v_mode } #define VexTmm { OP_VEX, tmm_mode } #define XMVexI4 { OP_REG_VexI4, x_mode } #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode } @@ -883,7 +885,20 @@ enum REG_EVEX_0F38C6_L_2, REG_EVEX_0F38C7_L_2, REG_EVEX_0F38F3_L_0, - REG_EVEX_MAP4_D8_PREFIX_1 + REG_EVEX_MAP4_80, + REG_EVEX_MAP4_81, + REG_EVEX_MAP4_83, + REG_EVEX_MAP4_C0, + REG_EVEX_MAP4_C1, + REG_EVEX_MAP4_D0, + REG_EVEX_MAP4_D1, + REG_EVEX_MAP4_D2, + REG_EVEX_MAP4_D3, + REG_EVEX_MAP4_D8_PREFIX_1, + REG_EVEX_MAP4_F6, + REG_EVEX_MAP4_F7, + REG_EVEX_MAP4_FE, + REG_EVEX_MAP4_FF, }; enum @@ -9070,6 +9085,14 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) ins->rex &= ~REX_B; ins->rex2 &= ~REX_R; } + if (ins->evex_type == evex_from_legacy) + { + if (ins->vex.ll || ins->vex.zeroing + || (!ins->vex.b && (ins->vex.register_specifier + || !ins->vex.v))) + return &bad_opcode; + ins->rex |= REX_OPCODE; + } ins->need_vex = 4; ins->codep++; @@ -9080,7 +9103,7 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) return &err_opcode; /* Set vector length. */ - if (ins->modrm.mod == 3 && ins->vex.b) + if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type == evex_default) ins->vex.length = 512; else { @@ -10994,7 +11017,7 @@ print_displacement (instr_info *ins, bfd_signed_vma val) static void intel_operand_size (instr_info *ins, int bytemode, int sizeflag) { - if (ins->vex.b) + if (ins->vex.b && ins->evex_type != evex_from_legacy) { if (!ins->vex.no_broadcast) switch (bytemode) @@ -11928,7 +11951,8 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag) ins->vex.no_broadcast = true; if (!ins->vex.no_broadcast - && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used))) + && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)) + && ins->evex_type == evex_default) { if (bytemode == xh_mode) { @@ -13280,6 +13304,14 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) if (!ins->need_vex) return true; + if (ins->evex_type == evex_from_legacy) + { + if (ins->vex.b) + ins->evex_used |= EVEX_b_used; + else + return true; + } + reg = ins->vex.register_specifier; ins->vex.register_specifier = 0; if (ins->address_mode != mode_64bit) @@ -13371,12 +13403,19 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) names = att_names_xmm; ins->evex_used |= EVEX_len_used; break; + case v_mode: case dq_mode: if (ins->rex & REX_W) names = att_names64; + else if (bytemode == v_mode + && !(sizeflag & DFLAG)) + names = att_names16; else names = att_names32; break; + case b_mode: + names = att_names8rex; + break; case mask_bd_mode: case mask_mode: if (reg > 0x7) diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 9dd5625f54d..f36a8da5cbe 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -960,6 +960,7 @@ typedef struct insn_template /* The next value is arbitrary, as long as it's non-zero and distinct from all other values above. */ #define Opcode_VexW 0xf /* Operand order controlled by VEX.W. */ +#define Opcode_APX_NDDD 0x11 /* Direction bit for APX NDD insns. */ /* how many operands */ unsigned int operands:3; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 791a9fe0177..4bb0c9f4906 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -286,17 +286,25 @@ add, 0x0, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg3 add, 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } add, 0x80/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +add, 0x0, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +add, 0x83/0, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +add, 0x80/0, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64} inc, 0x40, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +inc, 0xfe/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, {Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64} sub, 0x28, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sub, 0x83/5, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } sub, 0x2c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } sub, 0x80/5, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sub, 0x28, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64, } +sub, 0x83/5, APX_F|x64, Modrm|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +sub, 0x80/5, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } dec, 0x48, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } dec, 0xfe/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +dec, 0xfe/1, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } sbb, 0x18, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sbb, 0x83/3, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } @@ -305,6 +313,9 @@ sbb, 0x80/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|R sbb, 0x18, APX_F|x64, D|W|CheckOperandSize|Modrm|EVex128|EVexMap4|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sbb, 0x83/3, APX_F|x64, Modrm|EVex128|EVexMap4|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } sbb, 0x80/3, APX_F|x64, W|Modrm|EVex128|EVexMap4|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sbb, 0x18, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +sbb, 0x83/3, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +sbb, 0x80/3, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } cmp, 0x38, 0, D|W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } cmp, 0x83/7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } @@ -319,16 +330,25 @@ and, 0x20, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8| and, 0x83/4, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } and, 0x24, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } and, 0x80/4, 0, W|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +and, 0x20, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +and, 0x83/4, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +and, 0x80/4, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } or, 0x8, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } or, 0x83/1, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } or, 0xc, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } or, 0x80/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +or, 0x8, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +or, 0x83/1, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +or, 0x80/1, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } xor, 0x30, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } xor, 0x83/6, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } xor, 0x34, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } xor, 0x80/6, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +xor, 0x30, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +xor, 0x83/6, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +xor, 0x80/6, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } // clr with 1 operand is really xor with 2 operands. clr, 0x30, 0, W|Modrm|No_sSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 } @@ -340,11 +360,16 @@ adc, 0x80/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|R adc, 0x10, APX_F|x64, D|W|CheckOperandSize|Modrm|EVex128|EVexMap4|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } adc, 0x83/2, APX_F|x64, Modrm|EVex128|EVexMap4|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } adc, 0x80/2, APX_F|x64, W|Modrm|EVex128|EVexMap4|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +adc, 0x10, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +adc, 0x83/2, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +adc, 0x80/2, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } neg, 0xf6/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +neg, 0xf6/3, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } not, 0xf6/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } not, 0xf6/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +not, 0xf6/2, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } aaa, 0x37, No64, NoSuf, {} aas, 0x3f, No64, NoSuf, {} @@ -378,6 +403,7 @@ cqto, 0x99, x64, Size64|NoSuf, {} mul, 0xf6/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } imul, 0xf6/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } imul, 0xfaf, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 } +imul, 0xaf, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } imul, 0x6b, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } imul, 0x69, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // imul with 2 operands mimics imul with 3 by putting the register in @@ -395,11 +421,19 @@ rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword| rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +rol, 0xc0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +rol, 0xd2/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ror, 0xc0/1, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +ror, 0xc0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +ror, 0xd2/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcl, 0xc0/2, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } @@ -409,6 +443,10 @@ rcl, 0xd0/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg rcl, 0xc0/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcl, 0xd2/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcl, 0xd0/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcl, 0xd0/2, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +rcl, 0xc0/2, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +rcl, 0xd2/2, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +rcl, 0xd0/2, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xc0/3, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } @@ -418,34 +456,60 @@ rcr, 0xd0/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg rcr, 0xc0/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xd2/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xd0/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcr, 0xd0/3, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +rcr, 0xc0/3, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +rcr, 0xd2/3, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +rcr, 0xd0/3, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sal, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sal, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sal, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +sal, 0xc0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +sal, 0xd2/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +sal, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shl, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shl, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +shl, 0xc0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +shl, 0xd2/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shr, 0xc0/5, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shr, 0xd2/5, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +shr, 0xc0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +shr, 0xd2/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sar, 0xc0/7, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sar, 0xd2/7, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +sar, 0xc0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +sar, 0xd2/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } shld, 0xfa4, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } shld, 0xfa5, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } shld, 0xfa5, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shld, 0x24, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } shrd, 0xfac, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } shrd, 0xfad, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } shrd, 0xfad, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shrd, 0x2c, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // Control transfer instructions. call, 0xe8, No64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 } @@ -951,6 +1015,7 @@ ud2b, 0xfb9, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|U ud0, 0xfff, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } cmov, 0xf4, CMOV, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +cmov, 0x4, CMOV|APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } fcmovb, 0xda/0, i687, Modrm|NoSuf, { FloatReg, FloatAcc } fcmovnae, 0xda/0, i687, Modrm|NoSuf, { FloatReg, FloatAcc } @@ -2044,8 +2109,10 @@ xstore, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {} // Multy-precision Add Carry, rdseed instructions. adcx, 0x660f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } adcx, 0x6666, ADX|APX_F|x64, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|EVex128|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +adcx, 0x6666, ADX|APX_F|x64, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } adox, 0xf30f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } adox, 0xf366, ADX|APX_F|x64, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|EVex128|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +adox, 0xf366, ADX|APX_F|x64, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } rdseed, 0xfc7/7, RdSeed, Modrm|NoSuf, { Reg16|Reg32|Reg64 } // SMAP instructions. From patchwork Tue Sep 19 15:25:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Frager, Neal via Binutils" X-Patchwork-Id: 76386 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0F0273856DE8 for ; Tue, 19 Sep 2023 15:26:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0F0273856DE8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1695137203; bh=DHXKtbj4qUMg/y3AgtVjo/7XO/xPbxivG6zI/8gSRZ8=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=oCx3VzJlneJhEsBtK0EnFJxStpJAxz+0hyD62FT9t21xq1vVZ77/V3bO0+7I+CNLM lD56KmhG4iCMsXREiTBIDLQIxgfDbo7LU6ZPDKLTw2E9YH8xCPc6RrdGNUv+WpORON U11vYdUR0HwlKb6ANe04s1BSfQpB4gqs4E8r2klE= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id DD4113857728 for ; Tue, 19 Sep 2023 15:25:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DD4113857728 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="377286218" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="377286218" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 08:25:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="695950272" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="695950272" Received: from scymds03.sc.intel.com ([10.148.94.166]) by orsmga003.jf.intel.com with ESMTP; 19 Sep 2023 08:25:37 -0700 Received: from shgcc101.sh.intel.com (shgcc101.sh.intel.com [10.239.85.97]) by scymds03.sc.intel.com (Postfix) with ESMTP id 6BA206A; Tue, 19 Sep 2023 08:25:36 -0700 (PDT) To: binutils@sourceware.org Cc: jbeulich@suse.com, hongjiu.lu@intel.com, "Hu, Lin1" Subject: [PATCH 5/8] Support APX NDD optimized encoding. Date: Tue, 19 Sep 2023 15:25:24 +0000 Message-Id: <20230919152527.497773-6-lili.cui@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230919152527.497773-1-lili.cui@intel.com> References: <20230919152527.497773-1-lili.cui@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Cui, Lili via Binutils" From: "Frager, Neal via Binutils" Reply-To: "Cui, Lili" Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" From: "Hu, Lin1" This patch aims to optimize: add %r16, %r15, %r15 -> add %r16, %r15 gas/ChangeLog: * config/tc-i386.c (optimize_NDD_to_nonNDD): New function. (match_template): If we can optimzie APX NDD insns, so rematch template. * testsuite/gas/i386/x86-64.exp: Add test. * testsuite/gas/i386/x86-64-apx-ndd-optimize.d: New test. * testsuite/gas/i386/x86-64-apx-ndd-optimize.s: Ditto. --- gas/config/tc-i386.c | 49 +++++++ .../gas/i386/x86-64-apx-ndd-optimize.d | 120 ++++++++++++++++++ .../gas/i386/x86-64-apx-ndd-optimize.s | 115 +++++++++++++++++ gas/testsuite/gas/i386/x86-64.exp | 1 + 4 files changed, 285 insertions(+) create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 381e389bb04..fba97ae37d8 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -7091,6 +7091,46 @@ check_EgprOperands (const insn_template *t) return 0; } +/* Optimize APX NDD insns to non-NDD insns. */ + +static int +optimize_NDD_to_nonNDD (const insn_template *t) +{ + if (t->opcode_modifier.vexvvvv + && t->opcode_space == SPACE_EVEXMAP4 + && i.reg_operands >= 2 + && (i.types[i.operands - 1].bitfield.dword + || i.types[i.operands - 1].bitfield.qword)) + { + int tmp_flag = -1; + int dest = i.operands - 1; + int src1 = (i.operands > 2) ? i.operands - 2 : 0; + int src2 = (i.operands > 3) ? i.operands - 3 : 0; + + if (i.op[src1].regs == i.op[dest].regs) + tmp_flag = src2; + /* adcx and adox don't have D bit. */ + else if (i.op[src2].regs == i.op[dest].regs + && (t->opcode_modifier.d + || t->mnem_off == MN_adcx + || t->mnem_off == MN_adox) + && (t->mnem_off != MN_sub) + && (t->mnem_off != MN_sbb)) + tmp_flag = src1; + if (tmp_flag != -1) + { + --i.operands; + --i.reg_operands; + --i.tm.operands; + + if (tmp_flag != src2) + swap_2_operands (tmp_flag, src2); + return 1; + } + } + return 0; +} + /* Helper function for the progress() macro in match_template(). */ static INLINE enum i386_error progress (enum i386_error new, enum i386_error last, @@ -7562,6 +7602,15 @@ match_template (char mnem_suffix) slip through to break. */ } + /* If we can optimize a NDD insn to non-NDD insn, like + add %r16, %r8, %r8 -> add %r16, %r8, then rematch template. */ + if (optimize_NDD_to_nonNDD (t)) + { + t = current_templates->start; + --t; + continue; + } + /* Check if VEX/EVEX encoding requirements can be satisfied. */ if (VEX_check_encoding (t)) { diff --git a/gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.d b/gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.d new file mode 100644 index 00000000000..173b368da71 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.d @@ -0,0 +1,120 @@ +#objdump: -drw +#name: x86-64 APX NDD optimized encoding +#source: x86-64-apx-ndd-optimize.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 f4 7d 18 ff c0\s+inc\s+%ax,%ax +\s*[a-f0-9]+:\s*ff c0\s+inc\s+%eax +\s*[a-f0-9]+:\s*48 ff c0\s+inc\s+%rax +\s*[a-f0-9]+:\s*d5 18 ff c0\s+inc\s+%r16 +\s*[a-f0-9]+:\s*62 44 3c 18 00 f8\s+add\s+%r31b,%r8b,%r8b +\s*[a-f0-9]+:\s*62 44 04 10 00 f8\s+add\s+%r31b,%r8b,%r31b +\s*[a-f0-9]+:\s*62 44 3c 18 00 f8\s+add\s+%r31b,%r8b,%r8b +\s*[a-f0-9]+:\s*d5 4d 01 f8\s+add\s+%r31,%r8 +\s*[a-f0-9]+:\s*d5 4d 01 f8\s+add\s+%r31,%r8 +\s*[a-f0-9]+:\s*d5 45 01 f8\s+add\s+%r31d,%r8d +\s*[a-f0-9]+:\s*d5 45 01 f8\s+add\s+%r31d,%r8d +\s*[a-f0-9]+:\s*62 44 3d 18 01 f8\s+add\s+%r31w,%r8w,%r8w +\s*[a-f0-9]+:\s*62 44 3d 18 01 f8\s+add\s+%r31w,%r8w,%r8w +\s*[a-f0-9]+:\s*d5 4d 01 f8\s+add\s+%r31,%r8 +\s*[a-f0-9]+:\s*d5 1d 03 c7\s+add\s+%r31,%r8 +\s*[a-f0-9]+:\s*d5 4d 03 38\s+add\s+\(%r8\),%r31 +\s*[a-f0-9]+:\s*d5 1d 03 07\s+add\s+\(%r31\),%r8 +\s*[a-f0-9]+:\s*49 81 c7 33 44 34 12\s+add\s+\$0x12344433,%r15 +\s*[a-f0-9]+:\s*49 81 c0 11 22 33 f4\s+add\s+\$0xfffffffff4332211,%r8 +\s*[a-f0-9]+:\s*d5 18 ff c9\s+dec\s+%r17 +\s*[a-f0-9]+:\s*d5 18 f7 d1\s+not\s+%r17 +\s*[a-f0-9]+:\s*d5 18 f7 d9\s+neg\s+%r17 +\s*[a-f0-9]+:\s*d5 1c 29 f9\s+sub\s+%r15,%r17 +\s*[a-f0-9]+:\s*62 54 04 18 29 38\s+sub\s+%r15d,\(%r8\),%r15d +\s*[a-f0-9]+:\s*d5 49 2b 04 07\s+sub\s+\(%r15,%rax,1\),%r16 +\s*[a-f0-9]+:\s*d5 19 81 ee 34 12 00 00\s+sub\s+\$0x1234,%r30 +\s*[a-f0-9]+:\s*d5 1c 19 f9\s+sbb\s+%r15,%r17 +\s*[a-f0-9]+:\s*62 54 84 18 19 38\s+sbb\s+%r15,\(%r8\),%r15 +\s*[a-f0-9]+:\s*d5 49 1b 04 07\s+sbb\s+\(%r15,%rax,1\),%r16 +\s*[a-f0-9]+:\s*d5 19 81 de 34 12 00 00\s+sbb\s+\$0x1234,%r30 +\s*[a-f0-9]+:\s*d5 1c 11 f9\s+adc\s+%r15,%r17 +\s*[a-f0-9]+:\s*45 13 38\s+adc\s+\(%r8\),%r15d +\s*[a-f0-9]+:\s*d5 49 13 04 07\s+adc\s+\(%r15,%rax,1\),%r16 +\s*[a-f0-9]+:\s*d5 19 81 d6 34 12 00 00\s+adc\s+\$0x1234,%r30 +\s*[a-f0-9]+:\s*d5 1c 09 f9\s+or\s+ %r15,%r17 +\s*[a-f0-9]+:\s*45 0b 38\s+or\s+ \(%r8\),%r15d +\s*[a-f0-9]+:\s*d5 49 0b 04 07\s+or\s+\(%r15,%rax,1\),%r16 +\s*[a-f0-9]+:\s*d5 19 81 ce 34 12 00 00\s+or\s+\$0x1234,%r30 +\s*[a-f0-9]+:\s*d5 1c 31 f9\s+xor\s+%r15,%r17 +\s*[a-f0-9]+:\s*45 33 38\s+xor\s+\(%r8\),%r15d +\s*[a-f0-9]+:\s*d5 49 33 04 07\s+xor\s+\(%r15,%rax,1\),%r16 +\s*[a-f0-9]+:\s*d5 19 81 f6 34 12 00 00\s+xor\s+\$0x1234,%r30 +\s*[a-f0-9]+:\s*d5 1c 21 f9\s+and\s+%r15,%r17 +\s*[a-f0-9]+:\s*45 23 38\s+and\s+\(%r8\),%r15d +\s*[a-f0-9]+:\s*d5 49 23 04 07\s+and\s+\(%r15,%rax,1\),%r16 +\s*[a-f0-9]+:\s*d5 19 81 e6 34 12 00 00\s+and\s+\$0x1234,%r30 +\s*[a-f0-9]+:\s*d5 19 81 e6 34 12 00 00\s+and\s+\$0x1234,%r30 +\s*[a-f0-9]+:\s*d5 19 d1 cf\s+ror\s+%r31 +\s*[a-f0-9]+:\s*62 dc 04 10 d0 cf\s+ror\s+%r31b,%r31b +\s*[a-f0-9]+:\s*49 c1 cc 02\s+ror\s+\$0x2,%r12 +\s*[a-f0-9]+:\s*d5 19 d1 c7\s+rol\s+%r31 +\s*[a-f0-9]+:\s*62 dc 04 10 d0 c7\s+rol\s+%r31b,%r31b +\s*[a-f0-9]+:\s*49 c1 c4 02\s+rol\s+\$0x2,%r12 +\s*[a-f0-9]+:\s*d5 19 d1 df\s+rcr\s+%r31 +\s*[a-f0-9]+:\s*62 dc 04 10 d0 df\s+rcr\s+%r31b,%r31b +\s*[a-f0-9]+:\s*62 d4 1c 18 c0 dc 02\s+rcr\s+\$0x2,%r12b,%r12b +\s*[a-f0-9]+:\s*49 c1 dc 02\s+rcr\s+\$0x2,%r12 +\s*[a-f0-9]+:\s*d5 19 d1 d7\s+rcl\s+%r31 +\s*[a-f0-9]+:\s*62 dc 04 10 d0 d7\s+rcl\s+%r31b,%r31b +\s*[a-f0-9]+:\s*62 d4 1c 18 c0 d4 02\s+rcl\s+\$0x2,%r12b,%r12b +\s*[a-f0-9]+:\s*49 c1 d4 02\s+rcl\s+\$0x2,%r12 +\s*[a-f0-9]+:\s*d5 19 d1 e7\s+shl\s+%r31 +\s*[a-f0-9]+:\s*62 dc 04 10 d0 e7 \s+shl\s+%r31b,%r31b +\s*[a-f0-9]+:\s*62 d4 1c 18 c0 e4 02\s+shl\s+\$0x2,%r12b,%r12b +\s*[a-f0-9]+:\s*49 c1 e4 02\s+shl\s+\$0x2,%r12 +\s*[a-f0-9]+:\s*d5 19 d1 ff\s+sar\s+%r31 +\s*[a-f0-9]+:\s*62 dc 04 10 d0 ff\s+sar\s+%r31b,%r31b +\s*[a-f0-9]+:\s*62 d4 1c 18 c0 fc 02\s+sar\s+\$0x2,%r12b,%r12b +\s*[a-f0-9]+:\s*49 c1 fc 02\s+sar\s+\$0x2,%r12 +\s*[a-f0-9]+:\s*d5 19 d1 e7\s+shl\s+%r31 +\s*[a-f0-9]+:\s*62 dc 04 10 d0 e7\s+shl\s+%r31b,%r31b +\s*[a-f0-9]+:\s*62 d4 1c 18 c0 e4 02\s+shl\s+\$0x2,%r12b,%r12b +\s*[a-f0-9]+:\s*49 c1 e4 02\s+shl\s+\$0x2,%r12 +\s*[a-f0-9]+:\s*d5 19 d1 ef\s+shr\s+%r31 +\s*[a-f0-9]+:\s*62 dc 04 10 d0 ef\s+shr\s+%r31b,%r31b +\s*[a-f0-9]+:\s*62 d4 1c 18 c0 ec 02\s+shr\s+\$0x2,%r12b,%r12b +\s*[a-f0-9]+:\s*49 c1 ec 02\s+shr\s+\$0x2,%r12 +\s*[a-f0-9]+:\s*62 74 9c 18 24 20 01\s+shld\s+\$0x1,%r12,\(%rax\),%r12 +\s*[a-f0-9]+:\s*62 54 1d 18 24 c4 02\s+shld\s+\$0x2,%r8w,%r12w,%r12w +\s*[a-f0-9]+:\s*62 74 35 18 a5 08\s+shld\s+ %cl,%r9w,\(%rax\),%r9w +\s*[a-f0-9]+:\s*d5 9c a5 e0\s+shld\s+%cl,%r12,%r16 +\s*[a-f0-9]+:\s*62 7c 15 18 a5 2c 83\s+shld\s+%cl,%r13w,\(%r19,%rax,4\),%r13w +\s*[a-f0-9]+:\s*62 74 9c 18 2c 20 01\s+shrd\s+\$0x1,%r12,\(%rax\),%r12 +\s*[a-f0-9]+:\s*4d 0f ac ec 01\s+shrd\s+\$0x1,%r13,%r12 +\s*[a-f0-9]+:\s*62 54 1d 18 2c c4 02\s+shrd\s+\$0x2,%r8w,%r12w,%r12w +\s*[a-f0-9]+:\s*62 74 35 18 ad 08\s+shrd\s+%cl,%r9w,\(%rax\),%r9w +\s*[a-f0-9]+:\s*d5 9c ad e0\s+shrd\s+%cl,%r12,%r16 +\s*[a-f0-9]+:\s*62 7c 15 18 ad 2c 83\s+shrd\s+%cl,%r13w,\(%r19,%rax,4\),%r13w +\s*[a-f0-9]+:\s*66 45 0f 38 f6 c7\s+adcx\s+%r15d,%r8d +\s*[a-f0-9]+:\s*62 14 79 08 66 04 3f\s+adcx\s+\(%r15,%r31,1\),%r8d +\s*[a-f0-9]+:\s*f3 45 0f 38 f6 c7\s+adox\s+%r15d,%r8d +\s*[a-f0-9]+:\s*62 14 7a 08 66 04 3f\s+adox\s+\(%r15,%r31,1\),%r8d +\s*[a-f0-9]+:\s*67 0f 40 90 90 90 90 90\s+cmovo\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 41 90 90 90 90 90\s+cmovno\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 42 90 90 90 90 90\s+cmovb\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 43 90 90 90 90 90\s+cmovae\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 44 90 90 90 90 90\s+cmove\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 45 90 90 90 90 90\s+cmovne\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 46 90 90 90 90 90\s+cmovbe\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 47 90 90 90 90 90\s+cmova\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 48 90 90 90 90 90\s+cmovs\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 49 90 90 90 90 90\s+cmovns\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 4a 90 90 90 90 90\s+cmovp\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 4b 90 90 90 90 90\s+cmovnp\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 4c 90 90 90 90 90\s+cmovl\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 4d 90 90 90 90 90\s+cmovge\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 4e 90 90 90 90 90\s+cmovle\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 4f 90 90 90 90 90\s+cmovg\s+-0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f af 90 09 09 09 00\s+imul\s+0x90909\(%eax\),%edx +\s*[a-f0-9]+:\s*d5 aa af 94 f8 09 09 00 00\s+imul\s+0x909\(%rax,%r31,8\),%rdx diff --git a/gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.s b/gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.s new file mode 100644 index 00000000000..139d875d5a7 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.s @@ -0,0 +1,115 @@ +# Check 64bit APX NDD instructions with optimized encoding + + .allow_index_reg + .text +_start: +inc %ax,%ax +inc %eax,%eax +inc %rax,%rax +inc %r16,%r16 +add %r31b,%r8b,%r8b +add %r31b,%r8b,%r31b +addb %r31b,%r8b,%r8b +add %r31,%r8,%r8 +addq %r31,%r8,%r8 +add %r31d,%r8d,%r8d +addl %r31d,%r8d,%r8d +add %r31w,%r8w,%r8w +addw %r31w,%r8w,%r8w +{store} add %r31,%r8,%r8 +{load} add %r31,%r8,%r8 +add %r31,(%r8),%r31 +add (%r31),%r8,%r8 +add $0x12344433,%r15,%r15 +add $0xfffffffff4332211,%r8,%r8 +dec %r17,%r17 +not %r17,%r17 +neg %r17,%r17 +sub %r15,%r17,%r17 +sub %r15d,(%r8),%r15d +sub (%r15,%rax,1),%r16,%r16 +sub $0x1234,%r30,%r30 +sbb %r15,%r17,%r17 +sbb %r15,(%r8),%r15 +sbb (%r15,%rax,1),%r16,%r16 +sbb $0x1234,%r30,%r30 +adc %r15,%r17,%r17 +adc %r15d,(%r8),%r15d +adc (%r15,%rax,1),%r16,%r16 +adc $0x1234,%r30,%r30 +or %r15,%r17,%r17 +or %r15d,(%r8),%r15d +or (%r15,%rax,1),%r16,%r16 +or $0x1234,%r30,%r30 +xor %r15,%r17,%r17 +xor %r15d,(%r8),%r15d +xor (%r15,%rax,1),%r16,%r16 +xor $0x1234,%r30,%r30 +and %r15,%r17,%r17 +and %r15d,(%r8),%r15d +and (%r15,%rax,1),%r16,%r16 +and $0x1234,%r30,%r30 +and $0x1234,%r30 +ror %r31,%r31 +rorb %r31b,%r31b +ror $0x2,%r12,%r12 +rol %r31,%r31 +rolb %r31b,%r31b +rol $0x2,%r12,%r12 +rcr %r31,%r31 +rcrb %r31b,%r31b +rcr $0x2,%r12b,%r12b +rcr $0x2,%r12,%r12 +rcl %r31,%r31 +rclb %r31b,%r31b +rcl $0x2,%r12b,%r12b +rcl $0x2,%r12,%r12 +shl %r31,%r31 +shlb %r31b,%r31b +shl $0x2,%r12b,%r12b +shl $0x2,%r12,%r12 +sar %r31,%r31 +sarb %r31b,%r31b +sar $0x2,%r12b,%r12b +sar $0x2,%r12,%r12 +shl %r31,%r31 +shlb %r31b,%r31b +shl $0x2,%r12b,%r12b +shl $0x2,%r12,%r12 +shr %r31,%r31 +shrb %r31b,%r31b +shr $0x2,%r12b,%r12b +shr $0x2,%r12,%r12 +shld $0x1,%r12,(%rax),%r12 +shld $0x2,%r8w,%r12w,%r12w +shld %cl,%r9w,(%rax),%r9w +shld %cl,%r12,%r16,%r16 +shld %cl,%r13w,(%r19,%rax,4),%r13w +shrd $0x1,%r12,(%rax),%r12 +shrd $0x1,%r13,%r12,%r12 +shrd $0x2,%r8w,%r12w,%r12w +shrd %cl,%r9w,(%rax),%r9w +shrd %cl,%r12,%r16,%r16 +shrd %cl,%r13w,(%r19,%rax,4),%r13w +adcx %r15d,%r8d,%r8d +adcx (%r15,%r31,1),%r8d,%r8d +adox %r15d,%r8d,%r8d +adox (%r15,%r31,1),%r8d,%r8d +cmovo 0x90909090(%eax),%edx,%edx +cmovno 0x90909090(%eax),%edx,%edx +cmovb 0x90909090(%eax),%edx,%edx +cmovae 0x90909090(%eax),%edx,%edx +cmove 0x90909090(%eax),%edx,%edx +cmovne 0x90909090(%eax),%edx,%edx +cmovbe 0x90909090(%eax),%edx,%edx +cmova 0x90909090(%eax),%edx,%edx +cmovs 0x90909090(%eax),%edx,%edx +cmovns 0x90909090(%eax),%edx,%edx +cmovp 0x90909090(%eax),%edx,%edx +cmovnp 0x90909090(%eax),%edx,%edx +cmovl 0x90909090(%eax),%edx,%edx +cmovge 0x90909090(%eax),%edx,%edx +cmovle 0x90909090(%eax),%edx,%edx +cmovg 0x90909090(%eax),%edx,%edx +imul 0x90909(%eax),%edx,%edx +imul 0x909(%rax,%r31,8),%rdx,%rdx diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index ca1583c6f88..c48430ca7cb 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -549,6 +549,7 @@ run_dump_test "x86-64-optimize-6" run_list_test "x86-64-optimize-7a" "-I${srcdir}/$subdir -march=+noavx -al" run_dump_test "x86-64-optimize-7b" run_list_test "x86-64-optimize-8" "-I${srcdir}/$subdir -march=+noavx2 -al" +run_dump_test "x86-64-apx-ndd-optimize" run_dump_test "x86-64-align-branch-1a" run_dump_test "x86-64-align-branch-1b" run_dump_test "x86-64-align-branch-1c" From patchwork Tue Sep 19 15:25:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Frager, Neal via Binutils" X-Patchwork-Id: 76389 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D00E93847EE9 for ; Tue, 19 Sep 2023 15:28:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D00E93847EE9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1695137334; bh=4ZxqXZYiYUu4AyPeWnjY5yPIFRJfxsNRndV2XEdceIs=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=uyJidwyjsuOR91J8F5Aykh33QMIz+YJ/88mi4MpUwYoYSLBkFDw4u2ZgX7Oq6bQ94 gwvQ+IbGADZ6m7d/p0UMJ9vMosV56nelSipkn3pFKVheb0bNsMuyvHbkEMljIAfBRl O/8E/3AgIsjM4AWXXWFQIMsmUjKaSaAL3/dJrBk8= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id D3E983857C44 for ; Tue, 19 Sep 2023 15:25:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D3E983857C44 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="377286231" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="377286231" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 08:25:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="695950279" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="695950279" Received: from scymds03.sc.intel.com ([10.148.94.166]) by orsmga003.jf.intel.com with ESMTP; 19 Sep 2023 08:25:39 -0700 Received: from shgcc101.sh.intel.com (shgcc101.sh.intel.com [10.239.85.97]) by scymds03.sc.intel.com (Postfix) with ESMTP id E642E6A; Tue, 19 Sep 2023 08:25:37 -0700 (PDT) To: binutils@sourceware.org Cc: jbeulich@suse.com, hongjiu.lu@intel.com, "Mo, Zewei" Subject: [PATCH 6/8] Support APX Push2/Pop2 Date: Tue, 19 Sep 2023 15:25:25 +0000 Message-Id: <20230919152527.497773-7-lili.cui@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230919152527.497773-1-lili.cui@intel.com> References: <20230919152527.497773-1-lili.cui@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Cui, Lili via Binutils" From: "Frager, Neal via Binutils" Reply-To: "Cui, Lili" Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" From: "Mo, Zewei" gas/ChangeLog: * config/tc-i386.c: (is_any_apx_encoding): Add handler for APX-Push2/Pop2 when no EGPR32 is used, (md_assemble): Add handler for APX-Push2/Pop2. (build_modrm_byte): Add handler for operands order, vvvv encoding and modrm encoding of APX-Push2/Pop2. * testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests. * testsuite/gas/i386/x86-64-apx-push2pop2.d: New test. * testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-decode-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-decode-inval.d: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.d: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add EVEX_MAP4_8F. * i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_X86_64_L_0_M_1_R_0_P_0, EVEX_W_MAP4_FF_R_6_X86_64_L_0_M_1_P_0. * i386-dis-evex-len.h: Add EVEX_LEN_MAP4_8F_X86_64, EVEX_LEN_MAP4_FF_R_6_X86_64. * i386-dis-evex-mod.h: Add MOD_EVEX_MAP4_8F_X86_64_L_0, MOD_EVEX_MAP4_FF_R_6_X86_64_L_0. * i386-dis-evex-prefix.h: Add PREFIX_EVEX_MAP4_8F_X86_64_L_0_M_1_R_0, PREFIX_EVEX_MAP4_FF_R_6_X86_64_L_0_M_1. * i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F_X86_64_L_0_M_1. * i386-dis-evex-x86.h: Add X86_64_EVEX_MAP4_8F_X86_64, X86_64_EVEX_MAP4_FF_R_6_X86_64. * i386-dis.c: (OP) Add VexGq. (MOD_EVEX_MAP4_8F_X86_64_L_0): New. (MOD_EVEX_MAP4_FF_R_6_X86_64_L_0): Ditto. (PREFIX_EVEX_MAP4_8F_X86_64_L_0_M_1_R_0): Ditto. (PREFIX_EVEX_MAP4_FF_R_6_X86_64_L_0_M_1): Ditto. (EVEX_LEN_MAP4_8F_X86_64): Ditto. (EVEX_LEN_MAP4_FF_R_6_X86_64): Ditto. (EVEX_W_MAP4_8F_X86_64_L_0_M_1_R_0_P_0): Ditto. (EVEX_W_MAP4_FF_R_6_X86_64_L_0_M_1_P_0): Ditto. (REG_EVEX_MAP4_8F_X86_64_L_0_M_1): Ditto. (X86_64_EVEX_MAP4_8F): Ditto. (X86_64_EVEX_MAP4_FF_R_6): Ditto. (get_valid_dis386): Add handler of setting vector length for APX-Push2/Pop2 insn. (print_insn): Add handler of rounding control and cleaning vex.mask_register_specifier for APX-Push2/Pop2. (OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn. * i386-opc.tbl: Add APX-Push2/Pop2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated. --- gas/config/tc-i386.c | 30 ++++++++++++- gas/testsuite/gas/i386/apx-push2pop2-inval.l | 5 +++ gas/testsuite/gas/i386/apx-push2pop2-inval.s | 9 ++++ gas/testsuite/gas/i386/i386.exp | 1 + .../i386/x86-64-apx-push2pop2-decode-inval.d | 29 ++++++++++++ .../i386/x86-64-apx-push2pop2-decode-inval.s | 19 ++++++++ .../gas/i386/x86-64-apx-push2pop2-intel.d | 42 ++++++++++++++++++ .../gas/i386/x86-64-apx-push2pop2-inval.l | 9 ++++ .../gas/i386/x86-64-apx-push2pop2-inval.s | 13 ++++++ gas/testsuite/gas/i386/x86-64-apx-push2pop2.d | 42 ++++++++++++++++++ gas/testsuite/gas/i386/x86-64-apx-push2pop2.s | 39 ++++++++++++++++ gas/testsuite/gas/i386/x86-64.exp | 4 ++ opcodes/i386-dis-evex-len.h | 10 +++++ opcodes/i386-dis-evex-mod.h | 10 +++++ opcodes/i386-dis-evex-prefix.h | 8 ++++ opcodes/i386-dis-evex-reg.h | 9 ++++ opcodes/i386-dis-evex-w.h | 10 +++++ opcodes/i386-dis-evex-x86.h | 10 +++++ opcodes/i386-dis-evex.h | 2 +- opcodes/i386-dis.c | 44 ++++++++++++++++++- opcodes/i386-gen.c | 1 + opcodes/i386-opc.h | 4 ++ opcodes/i386-opc.tbl | 6 +++ 23 files changed, 351 insertions(+), 5 deletions(-) create mode 100644 gas/testsuite/gas/i386/apx-push2pop2-inval.l create mode 100644 gas/testsuite/gas/i386/apx-push2pop2-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-decode-inval.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-decode-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index fba97ae37d8..dd3af5dd2d5 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -5667,6 +5667,22 @@ md_assemble (char *line) i.rex &= REX_OPCODE; } + if (i.tm.opcode_modifier.push2pop2) + { + i.imm_operands = 0; + unsigned int reg1 = register_number (i.op[0].regs); + unsigned int reg2 = register_number (i.op[1].regs); + + /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers. */ + if (reg1 == 0x4 || reg2 == 0x4) + as_bad (_("%s for `%s'"), _("invalid register operand"), + insn_name (current_templates->start)); + + if ((i.tm.mnem_off == MN_pop2 || i.tm.mnem_off == MN_pop2p) && reg1 == reg2) + as_bad (_("%s for `%s'"), _("invalid register operand"), + insn_name (current_templates->start)); + } + /* Handle conversion of 'int $3' --> special int3 insn. */ if (i.tm.mnem_off == MN_int && i.op[0].imms->X_add_number == 3) @@ -7100,7 +7116,11 @@ optimize_NDD_to_nonNDD (const insn_template *t) && t->opcode_space == SPACE_EVEXMAP4 && i.reg_operands >= 2 && (i.types[i.operands - 1].bitfield.dword - || i.types[i.operands - 1].bitfield.qword)) + || i.types[i.operands - 1].bitfield.qword) + && (t->mnem_off != MN_pop2 + && t->mnem_off != MN_pop2p + && t->mnem_off != MN_push2 + && t->mnem_off != MN_push2p)) { int tmp_flag = -1; int dest = i.operands - 1; @@ -8912,7 +8932,13 @@ build_modrm_byte (void) dest = ~0; } gas_assert (source < dest); - if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCES + if (i.tm.opcode_modifier.push2pop2) + { + v = 1; + dest = (unsigned int) ~0; + source = 0; + } + else if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCES && source != op) { unsigned int tmp = source; diff --git a/gas/testsuite/gas/i386/apx-push2pop2-inval.l b/gas/testsuite/gas/i386/apx-push2pop2-inval.l new file mode 100644 index 00000000000..a55a71520c8 --- /dev/null +++ b/gas/testsuite/gas/i386/apx-push2pop2-inval.l @@ -0,0 +1,5 @@ +.* Assembler messages: +.*:6: Error: `push2' is only supported in 64-bit mode +.*:7: Error: `push2p' is only supported in 64-bit mode +.*:8: Error: `pop2' is only supported in 64-bit mode +.*:9: Error: `pop2p' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/apx-push2pop2-inval.s b/gas/testsuite/gas/i386/apx-push2pop2-inval.s new file mode 100644 index 00000000000..77166327ed1 --- /dev/null +++ b/gas/testsuite/gas/i386/apx-push2pop2-inval.s @@ -0,0 +1,9 @@ +# Check 32bit APX-PUSH2/POP2 instructions + + .allow_index_reg + .text +_start: + push2 %rax, %rbx + push2p %rax, %rbx + pop2 %rax, %rbx + pop2p %rax, %rbx diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index d16eb888f24..7e0ad339141 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -507,6 +507,7 @@ if [gas_32_check] then { run_dump_test "sm4" run_dump_test "sm4-intel" run_list_test "pbndkb-inval" + run_list_test "apx-push2pop2-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2-decode-inval.d b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-decode-inval.d new file mode 100644 index 00000000000..e63a44554a0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-decode-inval.d @@ -0,0 +1,29 @@ +#as: --64 +#objdump: -dw +#name: illegal decoding of APX-push2pop2 insns +#source: x86-64-apx-push2pop2-decode-inval.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ : +[ ]*[a-f0-9]+: 62 f4 64 \(bad\) +[ ]*[a-f0-9]+: 08 .byte 0x8 +[ ]*[a-f0-9]+: 8f c0 pop %rax + +0+6 : +[ ]*[a-f0-9]+: 62 f4 5c 18 8f \(bad\) +[ ]*[a-f0-9]+: c0 .byte 0xc0 + +0+c : +[ ]*[a-f0-9]+: 62 f4 74 10 ff \(bad\) +[ ]*[a-f0-9]+: f4 hlt + +0+12 : +[ ]*[a-f0-9]+: 62 d4 1c 18 8f \(bad\) +[ ]*[a-f0-9]+: c4 .byte 0xc4 + +0+18 : +[ ]*[a-f0-9]+: 62 dc 04 10 8f \(bad\) +[ ]*[a-f0-9]+: c7 .byte 0xc7 diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2-decode-inval.s b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-decode-inval.s new file mode 100644 index 00000000000..ac7296bc94d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-decode-inval.s @@ -0,0 +1,19 @@ +# Check illegal bytecode of APX-Push2Pop2 instructions +# pop2 %rax, %rbx +# pop2 %rax, %rsp +# push2 %rsp, %r17 +# pop2 %r12, %r12 +# pop2 %r31, %r31 + + .allow_index_reg + .text +popnd0: + .byte 0x62,0xF4,0x64,0x08,0x8F,0xC0 +poprspvvvv: + .byte 0x62,0xF4,0x5C,0x18,0x8F,0xC0 +pushrsprm: + .byte 0x62,0xF4,0x74,0x10,0xFF,0xF4 +popsamereg: + .byte 0x62,0xD4,0x1C,0x18,0x8F,0xC4 +popsameegpr32: + .byte 0x62,0xDC,0x04,0x10,0x8F,0xC7 diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d new file mode 100644 index 00000000000..46b21219582 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d @@ -0,0 +1,42 @@ +#as: --64 +#objdump: -dw -Mintel +#name: i386 APX-push2pop2 insns (Intel disassembly) +#source: x86-64-apx-push2pop2.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+rax,rbx +\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+r8,r17 +\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+r31,r9 +\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+r24,r31 +\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+rax,rbx +\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+r8,r17 +\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+r31,r9 +\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+r24,r31 +\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+rbx,rax +\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+r17,r8 +\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+r9,r31 +\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+r31,r24 +\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+rbx,rax +\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+r17,r8 +\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+r9,r31 +\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+r31,r24 +\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+rax,rbx +\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+r8,r17 +\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+r31,r9 +\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+r24,r31 +\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+rax,rbx +\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+r8,r17 +\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+r31,r9 +\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+r24,r31 +\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+rbx,rax +\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+r17,r8 +\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+r9,r31 +\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+r31,r24 +\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+rbx,rax +\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+r17,r8 +\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+r9,r31 +\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+r31,r24 diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l new file mode 100644 index 00000000000..61a9672edcd --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l @@ -0,0 +1,9 @@ +.* Assembler messages: +.*:6: Error: operand size mismatch for `push2' +.*:7: Error: invalid register operand for `pop2' +.*:8: Error: invalid register operand for `push2' +.*:9: Error: invalid register operand for `pop2' +.*:10: Error: operand size mismatch for `push2p' +.*:11: Error: invalid register operand for `pop2p' +.*:12: Error: invalid register operand for `push2p' +.*:13: Error: invalid register operand for `pop2p' diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s new file mode 100644 index 00000000000..c36bd5df88b --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s @@ -0,0 +1,13 @@ +# Check illegal APX-Push2Pop2 instructions + + .allow_index_reg + .text +_start: + push2 %eax, %ebx + pop2 %rax, %rsp + push2 %rsp, %r17 + pop2 %r12, %r12 + push2p %eax, %ebx + pop2p %rax, %rsp + push2p %rsp, %r17 + pop2p %r12, %r12 diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2.d b/gas/testsuite/gas/i386/x86-64-apx-push2pop2.d new file mode 100644 index 00000000000..54f22a7f94e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2.d @@ -0,0 +1,42 @@ +#as: --64 +#objdump: -dw +#name: x86_64 APX-push2pop2 insns +#source: x86-64-apx-push2pop2.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+%rbx,%rax +\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+%r17,%r8 +\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+%r9,%r31 +\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+%r31,%r24 +\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+%rbx,%rax +\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+%r17,%r8 +\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+%r9,%r31 +\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+%r31,%r24 +\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+%rax,%rbx +\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+%r8,%r17 +\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+%r31,%r9 +\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+%r24,%r31 +\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+%rax,%rbx +\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+%r8,%r17 +\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+%r31,%r9 +\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+%r24,%r31 +\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+%rbx,%rax +\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+%r17,%r8 +\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+%r9,%r31 +\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+%r31,%r24 +\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+%rbx,%rax +\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+%r17,%r8 +\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+%r9,%r31 +\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+%r31,%r24 +\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+%rax,%rbx +\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+%r8,%r17 +\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+%r31,%r9 +\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+%r24,%r31 +\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+%rax,%rbx +\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+%r8,%r17 +\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+%r31,%r9 +\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+%r24,%r31 diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2.s b/gas/testsuite/gas/i386/x86-64-apx-push2pop2.s new file mode 100644 index 00000000000..4cfc0a2185f --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2.s @@ -0,0 +1,39 @@ +# Check 64bit APX-Push2Pop2 instructions + + .allow_index_reg + .text +_start: + push2 %rbx, %rax + push2 %r17, %r8 + push2 %r9, %r31 + push2 %r31, %r24 + push2p %rbx, %rax + push2p %r17, %r8 + push2p %r9, %r31 + push2p %r31, %r24 + pop2 %rax, %rbx + pop2 %r8, %r17 + pop2 %r31, %r9 + pop2 %r24, %r31 + pop2p %rax, %rbx + pop2p %r8, %r17 + pop2p %r31, %r9 + pop2p %r24, %r31 + +.intel_syntax noprefix + push2 rax, rbx + push2 r8, r17 + push2 r31, r9 + push2 r24, r31 + push2p rax, rbx + push2p r8, r17 + push2p r31, r9 + push2p r24, r31 + pop2 rbx, rax + pop2 r17, r8 + pop2 r9, r31 + pop2 r31, r24 + pop2p rbx, rax + pop2p r17, r8 + pop2p r9, r31 + pop2p r31, r24 diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index c48430ca7cb..2d3a0387497 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -342,6 +342,10 @@ run_dump_test "x86-64-avx512dq-rcigrd-intel" run_dump_test "x86-64-avx512dq-rcigrd" run_dump_test "x86-64-avx512dq-rcigrne-intel" run_dump_test "x86-64-avx512dq-rcigrne" +run_dump_test "x86-64-apx-push2pop2" +run_dump_test "x86-64-apx-push2pop2-intel" +run_list_test "x86-64-apx-push2pop2-inval" +run_dump_test "x86-64-apx-push2pop2-decode-inval" run_dump_test "x86-64-avx512dq-rcigru-intel" run_dump_test "x86-64-avx512dq-rcigru" run_dump_test "x86-64-avx512dq-rcigrz-intel" diff --git a/opcodes/i386-dis-evex-len.h b/opcodes/i386-dis-evex-len.h index 1933a045822..7c9b921bf6b 100644 --- a/opcodes/i386-dis-evex-len.h +++ b/opcodes/i386-dis-evex-len.h @@ -155,4 +155,14 @@ static const struct dis386 evex_len_table[][3] = { { VEX_W_TABLE (EVEX_W_0F3A43_L_n) }, { VEX_W_TABLE (EVEX_W_0F3A43_L_n) }, }, + + /* EVEX_LEN_MAP4_8F_X86_64 */ + { + { MOD_TABLE (MOD_EVEX_MAP4_8F_X86_64_L_0) }, + }, + + /* EVEX_LEN_MAP4_FF_R_6_X86_64 */ + { + { MOD_TABLE (MOD_EVEX_MAP4_FF_R_6_X86_64_L_0) }, + }, }; diff --git a/opcodes/i386-dis-evex-mod.h b/opcodes/i386-dis-evex-mod.h index 5a1326a1b73..ad7b0514720 100644 --- a/opcodes/i386-dis-evex-mod.h +++ b/opcodes/i386-dis-evex-mod.h @@ -7,6 +7,11 @@ { { "wrssK", { M, Gdq }, 0 }, }, + /* MOD_EVEX_MAP4_8F_X86_64_L_0 */ + { + { Bad_Opcode }, + { REG_TABLE (REG_EVEX_MAP4_8F_X86_64_L_0_M_1) }, + }, /* MOD_EVEX_MAP4_DA_PREFIX_1 */ { { Bad_Opcode }, @@ -49,3 +54,8 @@ { { "movdiri", { Edq, Gdq }, 0 }, }, + /* MOD_EVEX_MAP4_FF_R_6_X86_64_L_0 */ + { + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_FF_R_6_X86_64_L_0_M_1) }, + }, diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h index 210783d7e88..5b2dff379bd 100644 --- a/opcodes/i386-dis-evex-prefix.h +++ b/opcodes/i386-dis-evex-prefix.h @@ -356,6 +356,10 @@ { "adoxS", { VexGdq, Gdq, Edq }, 0 }, { "adcxS", { VexGdq, Gdq, Edq }, 0 }, }, + /* PREFIX_EVEX_MAP4_8F_X86_64_L_0_M_1_R_0 */ + { + { VEX_W_TABLE (EVEX_W_MAP4_8F_X86_64_L_0_M_1_R_0_P_0) } + }, /* PREFIX_EVEX_MAP4_D8 */ { { "sha1nexte", { XM, EXxmm }, 0 }, @@ -421,6 +425,10 @@ { "aand", { Mdq, Gdq }, 0 }, { "aor", { Mdq, Gdq }, 0 }, }, + /* PREFIX_EVEX_MAP4_FF_R_6_X86_64_L_0_M_1 */ + { + { VEX_W_TABLE (EVEX_W_MAP4_FF_R_6_X86_64_L_0_M_1_P_0) }, + }, /* PREFIX_EVEX_MAP5_10 */ { { Bad_Opcode }, diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h index d00c2843e12..f9d313a78e1 100644 --- a/opcodes/i386-dis-evex-reg.h +++ b/opcodes/i386-dis-evex-reg.h @@ -89,6 +89,10 @@ { "xorQ", { VexGv, Ev, sIb }, 0 }, { Bad_Opcode }, }, + /* REG_EVEX_MAP4_8F_X86_64_L_0_M_1 */ + { + { PREFIX_TABLE (PREFIX_EVEX_MAP4_8F_X86_64_L_0_M_1_R_0) }, + }, /* REG_EVEX_MAP4_C0 */ { { "rolA", { VexGb, Eb, Ib }, 0 }, @@ -185,4 +189,9 @@ { { "incQ", { VexGv ,Ev }, 0 }, { "decQ", { VexGv ,Ev }, 0 }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { X86_64_EVEX_PUSH2_TABLE (X86_64_EVEX_MAP4_FF_R_6) }, }, diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h index b828277d413..da238764d59 100644 --- a/opcodes/i386-dis-evex-w.h +++ b/opcodes/i386-dis-evex-w.h @@ -442,6 +442,16 @@ { Bad_Opcode }, { "vpshrdw", { XM, Vex, EXx, Ib }, 0 }, }, + /* EVEX_W_MAP4_8F_X86_64_L_0_M_1_R_0_P_0 */ + { + { "pop2", { VexGq, Eq }, 0 }, + { "pop2p", { VexGq, Eq }, 0 }, + }, + /* EVEX_W_MAP4_FF_R_6_X86_64_L_0_M_1_P_0 */ + { + { "push2", { VexGq, Eq }, 0 }, + { "push2p", { VexGq, Eq }, 0 }, + }, /* EVEX_W_MAP5_5B_P_0 */ { { "vcvtdq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, diff --git a/opcodes/i386-dis-evex-x86.h b/opcodes/i386-dis-evex-x86.h index 1121223d877..b603f1af882 100644 --- a/opcodes/i386-dis-evex-x86.h +++ b/opcodes/i386-dis-evex-x86.h @@ -138,3 +138,13 @@ { Bad_Opcode }, { VEX_LEN_TABLE (VEX_LEN_0F3AF0) }, }, + /* X86_64_EVEX_MAP4_8F*/ + { + { Bad_Opcode }, + { EVEX_LEN_TABLE (EVEX_LEN_MAP4_8F_X86_64) }, + }, + /* X86_64_EVEX_MAP4_FF_R_6*/ + { + { Bad_Opcode }, + { EVEX_LEN_TABLE (EVEX_LEN_MAP4_FF_R_6_X86_64) }, + }, diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index 1787be6dbf0..22fa9b2b067 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -1035,7 +1035,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_EVEX_POP2_TABLE (X86_64_EVEX_MAP4_8F) }, /* 90 */ { Bad_Opcode }, { Bad_Opcode }, diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index c702fd9e756..4671d2e4b0e 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -137,6 +137,7 @@ enum evex_type evex_default = 0, evex_from_legacy, evex_from_vex, + evex_push2_pop2, }; struct instr_info @@ -571,6 +572,7 @@ fetch_error (const instr_info *ins) #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode } #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } #define VexGdq { OP_VEX, dq_mode } +#define VexGq { OP_VEX, q_mode } #define VexGb { OP_VEX, b_mode } #define VexGv { OP_VEX, v_mode } #define VexTmm { OP_VEX, tmm_mode } @@ -804,6 +806,8 @@ enum USE_PREFIX_TABLE, USE_X86_64_TABLE, USE_X86_64_EVEX_FROM_VEX_TABLE, + USE_X86_64_EVEX_PUSH2_TABLE, + USE_X86_64_EVEX_POP2_TABLE, USE_3BYTE_TABLE, USE_XOP_8F_TABLE, USE_VEX_C4_TABLE, @@ -824,6 +828,10 @@ enum #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) #define X86_64_EVEX_FROM_VEX_TABLE(I) \ DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I)) +#define X86_64_EVEX_PUSH2_TABLE(I) \ + DIS386 (USE_X86_64_EVEX_PUSH2_TABLE, (I)) +#define X86_64_EVEX_POP2_TABLE(I) \ + DIS386 (USE_X86_64_EVEX_POP2_TABLE, (I)) #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) #define XOP_8F_TABLE() DIS386 (USE_XOP_8F_TABLE, 0) #define VEX_C4_TABLE() DIS386 (USE_VEX_C4_TABLE, 0) @@ -888,6 +896,7 @@ enum REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, + REG_EVEX_MAP4_8F_X86_64_L_0_M_1, REG_EVEX_MAP4_C0, REG_EVEX_MAP4_C1, REG_EVEX_MAP4_D0, @@ -941,6 +950,7 @@ enum MOD_EVEX_MAP4_65, MOD_EVEX_MAP4_66_PREFIX_0, + MOD_EVEX_MAP4_8F_X86_64_L_0, MOD_EVEX_MAP4_DA_PREFIX_1, MOD_EVEX_MAP4_DB_PREFIX_1, MOD_EVEX_MAP4_DC_PREFIX_1, @@ -951,6 +961,7 @@ enum MOD_EVEX_MAP4_F8_PREFIX_2, MOD_EVEX_MAP4_F8_PREFIX_3, MOD_EVEX_MAP4_F9, + MOD_EVEX_MAP4_FF_R_6_X86_64_L_0, }; enum @@ -1189,6 +1200,7 @@ enum PREFIX_EVEX_MAP4_60, PREFIX_EVEX_MAP4_61, PREFIX_EVEX_MAP4_66, + PREFIX_EVEX_MAP4_8F_X86_64_L_0_M_1_R_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, @@ -1201,6 +1213,7 @@ enum PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8, PREFIX_EVEX_MAP4_FC, + PREFIX_EVEX_MAP4_FF_R_6_X86_64_L_0_M_1, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, @@ -1341,6 +1354,9 @@ enum X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, + + X86_64_EVEX_MAP4_8F, + X86_64_EVEX_MAP4_FF_R_6, }; enum @@ -1537,7 +1553,10 @@ enum EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B, - EVEX_LEN_0F3A43 + EVEX_LEN_0F3A43, + + EVEX_LEN_MAP4_8F_X86_64, + EVEX_LEN_MAP4_FF_R_6_X86_64, }; enum @@ -1761,6 +1780,9 @@ enum EVEX_W_0F3A70, EVEX_W_0F3A72, + EVEX_W_MAP4_8F_X86_64_L_0_M_1_R_0_P_0, + EVEX_W_MAP4_FF_R_6_X86_64_L_0_M_1_P_0, + EVEX_W_MAP5_5B_P_0, EVEX_W_MAP5_7A_P_3, }; @@ -8757,10 +8779,24 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) dp = &prefix_table[dp->op[1].bytemode][vindex]; break; + case USE_X86_64_EVEX_PUSH2_TABLE: + case USE_X86_64_EVEX_POP2_TABLE: + ins->evex_type = evex_push2_pop2; + unsigned int vvvv_reg = ins->vex.register_specifier + | !ins->vex.v << 4; + unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0) + + (ins->rex2 & REX_B ? 16 : 0); + if (!ins->vex.b || vvvv_reg == 0x4 || rm_reg == 0x4 + || (dp->op[0].bytemode == USE_X86_64_EVEX_POP2_TABLE + && vvvv_reg == rm_reg)) + return &bad_opcode; + goto use_x86_64_table; + case USE_X86_64_EVEX_FROM_VEX_TABLE: ins->evex_type = evex_from_vex; /* Fall through. */ case USE_X86_64_TABLE: +use_x86_64_table: vindex = ins->address_mode == mode_64bit ? 1 : 0; dp = &x86_64_table[dp->op[1].bytemode][vindex]; break; @@ -9570,7 +9606,8 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) /* Check whether rounding control was enabled for an insn not supporting it. */ if (ins.modrm.mod == 3 && ins.vex.b - && !(ins.evex_used & EVEX_b_used)) + && !(ins.evex_used & EVEX_b_used) + && ins.evex_type != evex_push2_pop2) { for (i = 0; i < MAX_OPERANDS; ++i) { @@ -13416,6 +13453,9 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) case b_mode: names = att_names8rex; break; + case q_mode: + names = att_names64; + break; case mask_bd_mode: case mask_mode: if (reg > 0x7) diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index f43cb1ecf7c..f951c452cc3 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -471,6 +471,7 @@ static bitfield opcode_modifiers[] = BITFIELD (IntelSyntax), BITFIELD (ISA64), BITFIELD (No_egpr), + BITFIELD (Push2Pop2), }; #define CLASS(n) #n, n diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index f36a8da5cbe..1663cc74937 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -749,6 +749,9 @@ enum /* egprs (r16-r31) on instruction illegal. */ No_egpr, + /* APX Push2Pop2 bit */ + Push2Pop2, + /* The last bitfield in i386_opcode_modifier. */ Opcode_Modifier_Num }; @@ -797,6 +800,7 @@ typedef struct i386_opcode_modifier unsigned int intelsyntax:1; unsigned int isa64:2; unsigned int no_egpr:1; + unsigned int push2pop2:1; } i386_opcode_modifier; /* Operand classes. */ diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 4bb0c9f4906..583b6676b0e 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3555,3 +3555,9 @@ eretu, 0xf30f01ca, FRED|x64, NoSuf, {} // FRED instructions end. +// APX Push2/Pop2 instruction. + +push2, 0xff/6, APX_F|x64, Modrm|VexW0|EVex128|Push2Pop2|EVexMap4|VexVVVV|No_bSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } +push2p, 0xff/6, APX_F|x64, Modrm|VexW1|EVex128|Push2Pop2|EVexMap4|VexVVVV|No_bSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } +pop2, 0x8f/0, APX_F|x64, Modrm|VexW0|EVex128|Push2Pop2|SwapSources|EVexMap4|VexVVVV|No_bSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } +pop2p, 0x8f/0, APX_F|x64, Modrm|VexW1|EVex128|Push2Pop2|SwapSources|EVexMap4|VexVVVV|No_bSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } From patchwork Tue Sep 19 15:25:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Frager, Neal via Binutils" X-Patchwork-Id: 76392 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 18C0D3851ABA for ; Tue, 19 Sep 2023 15:30:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 18C0D3851ABA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1695137412; bh=bNLpVVfh6I+yhF/1TrLkWvvhy8pcg29odHGSmh/HeSU=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: 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d="scan'208";a="695950284" Received: from scymds03.sc.intel.com ([10.148.94.166]) by orsmga003.jf.intel.com with ESMTP; 19 Sep 2023 08:25:40 -0700 Received: from shgcc101.sh.intel.com (shgcc101.sh.intel.com [10.239.85.97]) by scymds03.sc.intel.com (Postfix) with ESMTP id 72A9F6A; Tue, 19 Sep 2023 08:25:39 -0700 (PDT) To: binutils@sourceware.org Cc: jbeulich@suse.com, hongjiu.lu@intel.com Subject: [PATCH 7/8] Support APX NF Date: Tue, 19 Sep 2023 15:25:26 +0000 Message-Id: <20230919152527.497773-8-lili.cui@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230919152527.497773-1-lili.cui@intel.com> References: <20230919152527.497773-1-lili.cui@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Cui, Lili via Binutils" From: "Frager, Neal via Binutils" Reply-To: "Cui, Lili" Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" gas/ChangeLog: * config/tc-i386.c (is_any_apx_encoding): Add has_nf and i.has_zero_upper for apx encoding. (build_evex_insns_with_extend_evex_prefix): Encode the NF bit. (build_legacy_insns_with_apx_encoding): Likewise. (parse_insn): Handle Prefix_NF. (check_NfPrefix): New. (match_template): Handle check_NfPrefix and add nf check for D. * testsuite/gas/i386/x86-64.exp: Add apx-nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Likewise. * testsuite/gas/i386/x86-64-apx_nf.s: Likewise. opcodes/ChangeLog: * i386-dis-evex-len.h: Add %XN to the instructions that support APX NF. * i386-dis-evex-reg.h: Likewise. * i386-dis-evex.h: Add %XN to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "XN" for EVEX.NF. (print_insn): Use EVEX.a2 bit as appropriate (putop): Handle "%XN". * i386-gen.c: Add BITFIELD for NF. * i386-mnem.h: Regenerated. * i386-opc.h (Prefix_NoOptimize): Add Prefix_NF. (Prefix_NF): New. * i386-opc.tbl: Add new entries for the instructions that support APX NF. * i386-tbl.h: Regenerated. --- gas/config/tc-i386.c | 39 +- gas/testsuite/gas/i386/x86-64-apx-ndd.d | 2 +- gas/testsuite/gas/i386/x86-64-apx-nf-intel.d | 633 +++++++++ gas/testsuite/gas/i386/x86-64-apx-nf.d | 633 +++++++++ gas/testsuite/gas/i386/x86-64-apx-nf.s | 1256 ++++++++++++++++++ gas/testsuite/gas/i386/x86-64.exp | 2 + opcodes/i386-dis-evex-len.h | 2 +- opcodes/i386-dis-evex-reg.h | 133 +- opcodes/i386-dis-evex.h | 60 +- opcodes/i386-dis.c | 49 +- opcodes/i386-gen.c | 1 + opcodes/i386-opc.h | 9 +- opcodes/i386-opc.tbl | 192 ++- 13 files changed, 2855 insertions(+), 156 deletions(-) create mode 100644 gas/testsuite/gas/i386/x86-64-apx-nf-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-nf.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-nf.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index dd3af5dd2d5..1fe4980f26a 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -3863,7 +3863,7 @@ is_evex_encoding (const insn_template *t) { return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift || t->opcode_modifier.broadcast || t->opcode_modifier.masking - || t->opcode_modifier.sae; + || t->opcode_modifier.sae || t->opcode_modifier.nf; } static INLINE bool @@ -3878,6 +3878,8 @@ is_any_apx_encoding (void) return i.rex2 || i.rex2_encoding || i.tm.opcode_space == SPACE_EVEXMAP4 + || i.has_nf + || i.has_zero_upper || (i.vex.register_specifier && i.vex.register_specifier->reg_flags & RegRex2); } @@ -4178,11 +4180,15 @@ build_evex_insns_with_extend_evex_prefix (void) i.vex.bytes[1] &= 0xef; if (i.vex.register_specifier && register_number (i.vex.register_specifier) > 0xf) - i.vex.bytes[3] &=0xf7; + i.vex.bytes[3] &= 0xf7; if (i.rex2 & REX_B) i.vex.bytes[1] |= 0x08; if (i.rex2 & REX_X) i.vex.bytes[2] &= 0xfb; + + /* Encode the NF bit. */ + if (i.has_nf) + i.vex.bytes[3] |= 0x04; } /* Build the EVEX prefix (4-byte) for legacy insn @@ -4210,6 +4216,10 @@ build_legacy_insns_with_apx_encoding (void) /* Encode the NDD bit. */ if (i.vex.register_specifier) i.vex.bytes[3] |= 0x10; + + /* Encode the NF bit. */ + if (i.has_nf) + i.vex.bytes[3] |= 0x04; } static void @@ -5944,6 +5954,10 @@ parse_insn (const char *line, char *mnemonic, bool prefix_only) /* {rex2} */ i.rex2_encoding = true; break; + case Prefix_NF: + /* {NF} */ + i.has_nf = true; + break; case Prefix_NoOptimize: /* {nooptimize} */ i.no_optimize = true; @@ -7151,6 +7165,19 @@ optimize_NDD_to_nonNDD (const insn_template *t) return 0; } +/* Check if NF prefix requirements are met by the instruction. */ +static int +check_NfPrefix (const insn_template *t) +{ + if (i.has_nf && !t->opcode_modifier.nf) + { + /* This instruction should support nf prefix. */ + i.error = unsupported; + return 1; + } + return 0; +} + /* Helper function for the progress() macro in match_template(). */ static INLINE enum i386_error progress (enum i386_error new, enum i386_error last, @@ -7551,6 +7578,7 @@ match_template (char mnem_suffix) goto check_operands_345; } else if (t->opcode_space != SPACE_BASE + && !t->opcode_modifier.nf && (t->opcode_space != SPACE_0F /* MOV to/from CR/DR/TR, as an exception, follow the base opcode space encoding model. */ @@ -7652,6 +7680,13 @@ match_template (char mnem_suffix) continue; } + /* Check if nf prefix are valid. */ + if (check_NfPrefix (t)) + { + specific_error = progress (i.error); + continue; + } + /* We've found a match; break out of loop. */ break; } diff --git a/gas/testsuite/gas/i386/x86-64-apx-ndd.d b/gas/testsuite/gas/i386/x86-64-apx-ndd.d index debb99f2ff9..080c0cbd784 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-ndd.d +++ b/gas/testsuite/gas/i386/x86-64-apx-ndd.d @@ -158,7 +158,7 @@ Disassembly of section .text: \s*[a-f0-9]+:\s*67 62 f4 3c 18 4f 90 90 90 90 90 cmovg -0x6f6f6f70\(%eax\),%edx,%r8d \s*[a-f0-9]+:\s*67 62 f4 3c 18 af 90 09 09 09 00 imul 0x90909\(%eax\),%edx,%r8d \s*[a-f0-9]+:\s*62 b4 b0 10 af 94 f8 09 09 00 00 imul 0x909\(%rax,%r31,8\),%rdx,%r25 -\s*[a-f0-9]+:\s*62 f4 fc 08 ff c0\s+inc %rax +\s*[a-f0-9]+:\s*62 f4 fc 08 ff c0\s+\{evex\} inc %rax \s*[a-f0-9]+:\s*62 f4 ec\s+\(bad\) \s*[a-f0-9]+:\s*08 ff\s+or %bh,%bh \s*[a-f0-9]+:\s*c0\s+\.byte 0xc0 diff --git a/gas/testsuite/gas/i386/x86-64-apx-nf-intel.d b/gas/testsuite/gas/i386/x86-64-apx-nf-intel.d new file mode 100644 index 00000000000..240c9ba6150 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-nf-intel.d @@ -0,0 +1,633 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 APX_F insns (Intel disassembly) +#source: x86-64-apx-nf.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 f4 7c 0c 80 c3 7b\s+\{nf\} add bl,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c 80 c3 7b\s+\{nf\} add dl,bl,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 0c 83 c2 7b\s+\{nf\} add dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 1c 83 c2 7b\s+\{nf\} add ax,dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c1 7b\s+\{nf\} add ecx,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c1 7b\s+\{nf\} add edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c1 7b\s+\{nf\} add r9,0x7b +\s*[a-f0-9]+:\s*62 d4 84 14 83 c1 7b\s+\{nf\} add r31,r9,0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c 80 84 80 23 01 00 00 7b\s+\{nf\} add BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 64 1c 80 84 80 23 01 00 00 7b\s+\{nf\} add bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7d 0c 83 84 80 23 01 00 00 7b\s+\{nf\} add WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 6d 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c 83 84 80 23 01 00 00 7b\s+\{nf\} add DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 74 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 84 80 23 01 00 00 7b\s+\{nf\} add QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 b4 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c 00 da\s+\{nf\} add dl,bl +\s*[a-f0-9]+:\s*62 f4 3c 1c 00 da\s+\{nf\} add r8b,dl,bl +\s*[a-f0-9]+:\s*62 d4 7c 0c 00 9c 80 23 01 00 00\s+\{nf\} add BYTE PTR \[r8\+rax\*4\+0x123\],bl +\s*[a-f0-9]+:\s*62 d4 6c 1c 00 9c 80 23 01 00 00\s+\{nf\} add dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl +\s*[a-f0-9]+:\s*62 f4 7d 0c 01 d0\s+\{nf\} add ax,dx +\s*[a-f0-9]+:\s*62 f4 35 1c 01 d0\s+\{nf\} add r9w,ax,dx +\s*[a-f0-9]+:\s*62 d4 7d 0c 01 94 80 23 01 00 00\s+\{nf\} add WORD PTR \[r8\+rax\*4\+0x123\],dx +\s*[a-f0-9]+:\s*62 d4 7d 1c 01 94 80 23 01 00 00\s+\{nf\} add ax,WORD PTR \[r8\+rax\*4\+0x123\],dx +\s*[a-f0-9]+:\s*62 f4 7c 0c 01 ca\s+\{nf\} add edx,ecx +\s*[a-f0-9]+:\s*62 f4 2c 1c 01 ca\s+\{nf\} add r10d,edx,ecx +\s*[a-f0-9]+:\s*62 d4 7c 0c 01 8c 80 23 01 00 00\s+\{nf\} add DWORD PTR \[r8\+rax\*4\+0x123\],ecx +\s*[a-f0-9]+:\s*62 d4 6c 1c 01 8c 80 23 01 00 00\s+\{nf\} add edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx +\s*[a-f0-9]+:\s*62 5c fc 0c 01 cf\s+\{nf\} add r31,r9 +\s*[a-f0-9]+:\s*62 5c a4 1c 01 cf\s+\{nf\} add r11,r31,r9 +\s*[a-f0-9]+:\s*62 54 fc 0c 01 8c 80 23 01 00 00\s+\{nf\} add QWORD PTR \[r8\+rax\*4\+0x123\],r9 +\s*[a-f0-9]+:\s*62 54 84 14 01 8c 80 23 01 00 00\s+\{nf\} add r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c 02 9c 80 23 01 00 00\s+\{nf\} add bl,BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6c 1c 02 9c 80 23 01 00 00\s+\{nf\} add dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 0c 03 94 80 23 01 00 00\s+\{nf\} add dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 1c 03 94 80 23 01 00 00\s+\{nf\} add ax,dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c 03 8c 80 23 01 00 00\s+\{nf\} add ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6c 1c 03 8c 80 23 01 00 00\s+\{nf\} add edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 fc 0c 03 8c 80 23 01 00 00\s+\{nf\} add r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 84 14 03 8c 80 23 01 00 00\s+\{nf\} add r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f4 7c 0c 80 e3 7b\s+\{nf\} and bl,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c 80 e3 7b\s+\{nf\} and dl,bl,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 0c 83 e2 7b\s+\{nf\} and dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 1c 83 e2 7b\s+\{nf\} and ax,dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e1 7b\s+\{nf\} and ecx,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e1 7b\s+\{nf\} and edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e1 7b\s+\{nf\} and r9,0x7b +\s*[a-f0-9]+:\s*62 d4 84 14 83 e1 7b\s+\{nf\} and r31,r9,0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c 80 a4 80 23 01 00 00 7b\s+\{nf\} and BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 64 1c 80 a4 80 23 01 00 00 7b\s+\{nf\} and bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7d 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} and WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 6d 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} and DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 74 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} and QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 b4 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c 20 da\s+\{nf\} and dl,bl +\s*[a-f0-9]+:\s*62 f4 3c 1c 20 da\s+\{nf\} and r8b,dl,bl +\s*[a-f0-9]+:\s*62 d4 7c 0c 20 9c 80 23 01 00 00\s+\{nf\} and BYTE PTR \[r8\+rax\*4\+0x123\],bl +\s*[a-f0-9]+:\s*62 d4 6c 1c 20 9c 80 23 01 00 00\s+\{nf\} and dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl +\s*[a-f0-9]+:\s*62 f4 7d 0c 21 d0\s+\{nf\} and ax,dx +\s*[a-f0-9]+:\s*62 f4 35 1c 21 d0\s+\{nf\} and r9w,ax,dx +\s*[a-f0-9]+:\s*62 d4 7d 0c 21 94 80 23 01 00 00\s+\{nf\} and WORD PTR \[r8\+rax\*4\+0x123\],dx +\s*[a-f0-9]+:\s*62 d4 7d 1c 21 94 80 23 01 00 00\s+\{nf\} and ax,WORD PTR \[r8\+rax\*4\+0x123\],dx +\s*[a-f0-9]+:\s*62 f4 7c 0c 21 ca\s+\{nf\} and edx,ecx +\s*[a-f0-9]+:\s*62 f4 2c 1c 21 ca\s+\{nf\} and r10d,edx,ecx +\s*[a-f0-9]+:\s*62 d4 7c 0c 21 8c 80 23 01 00 00\s+\{nf\} and DWORD PTR \[r8\+rax\*4\+0x123\],ecx +\s*[a-f0-9]+:\s*62 d4 6c 1c 21 8c 80 23 01 00 00\s+\{nf\} and edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx +\s*[a-f0-9]+:\s*62 5c fc 0c 21 cf\s+\{nf\} and r31,r9 +\s*[a-f0-9]+:\s*62 5c a4 1c 21 cf\s+\{nf\} and r11,r31,r9 +\s*[a-f0-9]+:\s*62 54 fc 0c 21 8c 80 23 01 00 00\s+\{nf\} and QWORD PTR \[r8\+rax\*4\+0x123\],r9 +\s*[a-f0-9]+:\s*62 54 84 14 21 8c 80 23 01 00 00\s+\{nf\} and r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c 22 9c 80 23 01 00 00\s+\{nf\} and bl,BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6c 1c 22 9c 80 23 01 00 00\s+\{nf\} and dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 0c 23 94 80 23 01 00 00\s+\{nf\} and dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 1c 23 94 80 23 01 00 00\s+\{nf\} and ax,dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c 23 8c 80 23 01 00 00\s+\{nf\} and ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6c 1c 23 8c 80 23 01 00 00\s+\{nf\} and edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 fc 0c 23 8c 80 23 01 00 00\s+\{nf\} and r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 84 14 23 8c 80 23 01 00 00\s+\{nf\} and r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 72 6c 0c f2 d1\s+\{nf\} andn r10d,edx,ecx +\s*[a-f0-9]+:\s*62 52 84 04 f2 d9\s+\{nf\} andn r11,r31,r9 +\s*[a-f0-9]+:\s*62 d2 74 0c f2 94 80 23 01 00 00\s+\{nf\} andn edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 42 b4 0c f2 bc 80 23 01 00 00\s+\{nf\} andn r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 72 74 0c f7 d2\s+\{nf\} bextr r10d,edx,ecx +\s*[a-f0-9]+:\s*62 d2 74 0c f7 94 80 23 01 00 00\s+\{nf\} bextr edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx +\s*[a-f0-9]+:\s*62 5a b4 0c f7 df\s+\{nf\} bextr r11,r31,r9 +\s*[a-f0-9]+:\s*62 42 b4 0c f7 bc 80 23 01 00 00\s+\{nf\} bextr r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9 +\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d9\s+\{nf\} blsi edx,ecx +\s*[a-f0-9]+:\s*62 d2 84 04 f3 d9\s+\{nf\} blsi r31,r9 +\s*[a-f0-9]+:\s*62 d2 74 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d2 b4 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d1\s+\{nf\} blsmsk edx,ecx +\s*[a-f0-9]+:\s*62 d2 84 04 f3 d1\s+\{nf\} blsmsk r31,r9 +\s*[a-f0-9]+:\s*62 d2 74 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d2 b4 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f2 6c 0c f3 c9\s+\{nf\} blsr edx,ecx +\s*[a-f0-9]+:\s*62 d2 84 04 f3 c9\s+\{nf\} blsr r31,r9 +\s*[a-f0-9]+:\s*62 d2 74 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d2 b4 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 72 74 0c f5 d2\s+\{nf\} bzhi r10d,edx,ecx +\s*[a-f0-9]+:\s*62 d2 74 0c f5 94 80 23 01 00 00\s+\{nf\} bzhi edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx +\s*[a-f0-9]+:\s*62 5a b4 0c f5 df\s+\{nf\} bzhi r11,r31,r9 +\s*[a-f0-9]+:\s*62 42 b4 0c f5 bc 80 23 01 00 00\s+\{nf\} bzhi r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c fe cb\s+\{nf\} dec bl +\s*[a-f0-9]+:\s*62 f4 6c 1c fe cb\s+\{nf\} dec dl,bl +\s*[a-f0-9]+:\s*62 f4 7d 0c ff ca\s+\{nf\} dec dx +\s*[a-f0-9]+:\s*62 f4 7d 1c ff ca\s+\{nf\} dec ax,dx +\s*[a-f0-9]+:\s*62 f4 7c 0c ff c9\s+\{nf\} dec ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c ff c9\s+\{nf\} dec edx,ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c ff c9\s+\{nf\} dec r9 +\s*[a-f0-9]+:\s*62 d4 84 14 ff c9\s+\{nf\} dec r31,r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c fe 8c 80 23 01 00 00\s+\{nf\} dec BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 64 1c fe 8c 80 23 01 00 00\s+\{nf\} dec bl,BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 0c ff 8c 80 23 01 00 00\s+\{nf\} dec WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6d 1c ff 8c 80 23 01 00 00\s+\{nf\} dec dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c ff 8c 80 23 01 00 00\s+\{nf\} dec DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 74 1c ff 8c 80 23 01 00 00\s+\{nf\} dec ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 fc 0c ff 8c 80 23 01 00 00\s+\{nf\} dec QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 b4 1c ff 8c 80 23 01 00 00\s+\{nf\} dec r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f4 7c 0c f6 f3\s+\{nf\} div bl +\s*[a-f0-9]+:\s*62 f4 7d 0c f7 f2\s+\{nf\} div dx +\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f1\s+\{nf\} div ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f1\s+\{nf\} div r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c f6 b4 80 23 01 00 00\s+\{nf\} div BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 0c f7 b4 80 23 01 00 00\s+\{nf\} div WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c f7 b4 80 23 01 00 00\s+\{nf\} div DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 b4 80 23 01 00 00\s+\{nf\} div QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f4 7c 0c f6 fb\s+\{nf\} idiv bl +\s*[a-f0-9]+:\s*62 f4 7d 0c f7 fa\s+\{nf\} idiv dx +\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f9\s+\{nf\} idiv ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f9\s+\{nf\} idiv r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c f6 bc 80 23 01 00 00\s+\{nf\} idiv BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 0c f7 bc 80 23 01 00 00\s+\{nf\} idiv WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c f7 bc 80 23 01 00 00\s+\{nf\} idiv DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 bc 80 23 01 00 00\s+\{nf\} idiv QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f4 7c 0c f6 eb\s+\{nf\} imul bl +\s*[a-f0-9]+:\s*62 f4 7d 0c f7 ea\s+\{nf\} imul dx +\s*[a-f0-9]+:\s*62 f4 7d 0c af c2\s+\{nf\} imul ax,dx +\s*[a-f0-9]+:\s*62 f4 35 1c af c2\s+\{nf\} imul r9w,ax,dx +\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e9\s+\{nf\} imul ecx +\s*[a-f0-9]+:\s*62 f4 7c 0c af d1\s+\{nf\} imul edx,ecx +\s*[a-f0-9]+:\s*62 f4 2c 1c af d1\s+\{nf\} imul r10d,edx,ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e9\s+\{nf\} imul r9 +\s*[a-f0-9]+:\s*62 44 fc 0c af f9\s+\{nf\} imul r31,r9 +\s*[a-f0-9]+:\s*62 44 a4 1c af f9\s+\{nf\} imul r11,r31,r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c f6 ac 80 23 01 00 00\s+\{nf\} imul BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 0c f7 ac 80 23 01 00 00\s+\{nf\} imul WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 0c af 94 80 23 01 00 00\s+\{nf\} imul dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 1c af 94 80 23 01 00 00\s+\{nf\} imul ax,dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c f7 ac 80 23 01 00 00\s+\{nf\} imul DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c af 8c 80 23 01 00 00\s+\{nf\} imul ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6c 1c af 8c 80 23 01 00 00\s+\{nf\} imul edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 ac 80 23 01 00 00\s+\{nf\} imul QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 fc 0c af 8c 80 23 01 00 00\s+\{nf\} imul r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 84 14 af 8c 80 23 01 00 00\s+\{nf\} imul r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f4 7c 0c fe c3\s+\{nf\} inc bl +\s*[a-f0-9]+:\s*62 f4 6c 1c fe c3\s+\{nf\} inc dl,bl +\s*[a-f0-9]+:\s*62 f4 7d 0c ff c2\s+\{nf\} inc dx +\s*[a-f0-9]+:\s*62 f4 7d 1c ff c2\s+\{nf\} inc ax,dx +\s*[a-f0-9]+:\s*62 f4 7c 0c ff c1\s+\{nf\} inc ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c ff c1\s+\{nf\} inc edx,ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c ff c1\s+\{nf\} inc r9 +\s*[a-f0-9]+:\s*62 d4 84 14 ff c1\s+\{nf\} inc r31,r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c fe 84 80 23 01 00 00\s+\{nf\} inc BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 64 1c fe 84 80 23 01 00 00\s+\{nf\} inc bl,BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 0c ff 84 80 23 01 00 00\s+\{nf\} inc WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6d 1c ff 84 80 23 01 00 00\s+\{nf\} inc dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c ff 84 80 23 01 00 00\s+\{nf\} inc DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 74 1c ff 84 80 23 01 00 00\s+\{nf\} inc ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 fc 0c ff 84 80 23 01 00 00\s+\{nf\} inc QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 b4 1c ff 84 80 23 01 00 00\s+\{nf\} inc r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f4 7d 0c f5 c2\s+\{nf\} lzcnt ax,dx +\s*[a-f0-9]+:\s*62 f4 7c 0c f5 d1\s+\{nf\} lzcnt edx,ecx +\s*[a-f0-9]+:\s*62 44 fc 0c f5 f9\s+\{nf\} lzcnt r31,r9 +\s*[a-f0-9]+:\s*62 d4 7d 0c f5 94 80 23 01 00 00\s+\{nf\} lzcnt dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 fc 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f4 7c 0c f6 e3\s+\{nf\} mul bl +\s*[a-f0-9]+:\s*62 f4 7d 0c f7 e2\s+\{nf\} mul dx +\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e1\s+\{nf\} mul ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e1\s+\{nf\} mul r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c f6 a4 80 23 01 00 00\s+\{nf\} mul BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 0c f7 a4 80 23 01 00 00\s+\{nf\} mul WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c f7 a4 80 23 01 00 00\s+\{nf\} mul DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 a4 80 23 01 00 00\s+\{nf\} mul QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f4 7c 0c f6 db\s+\{nf\} neg bl +\s*[a-f0-9]+:\s*62 f4 6c 1c f6 db\s+\{nf\} neg dl,bl +\s*[a-f0-9]+:\s*62 f4 7d 0c f7 da\s+\{nf\} neg dx +\s*[a-f0-9]+:\s*62 f4 7d 1c f7 da\s+\{nf\} neg ax,dx +\s*[a-f0-9]+:\s*62 f4 7c 0c f7 d9\s+\{nf\} neg ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c f7 d9\s+\{nf\} neg edx,ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 d9\s+\{nf\} neg r9 +\s*[a-f0-9]+:\s*62 d4 84 14 f7 d9\s+\{nf\} neg r31,r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c f6 9c 80 23 01 00 00\s+\{nf\} neg BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 64 1c f6 9c 80 23 01 00 00\s+\{nf\} neg bl,BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 0c f7 9c 80 23 01 00 00\s+\{nf\} neg WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6d 1c f7 9c 80 23 01 00 00\s+\{nf\} neg dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c f7 9c 80 23 01 00 00\s+\{nf\} neg DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 74 1c f7 9c 80 23 01 00 00\s+\{nf\} neg ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 9c 80 23 01 00 00\s+\{nf\} neg QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 b4 1c f7 9c 80 23 01 00 00\s+\{nf\} neg r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f4 7c 0c 80 cb 7b\s+\{nf\} or bl,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c 80 cb 7b\s+\{nf\} or dl,bl,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ca 7b\s+\{nf\} or dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ca 7b\s+\{nf\} or ax,dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c9 7b\s+\{nf\} or ecx,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c9 7b\s+\{nf\} or edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c9 7b\s+\{nf\} or r9,0x7b +\s*[a-f0-9]+:\s*62 d4 84 14 83 c9 7b\s+\{nf\} or r31,r9,0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c 80 8c 80 23 01 00 00 7b\s+\{nf\} or BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 64 1c 80 8c 80 23 01 00 00 7b\s+\{nf\} or bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7d 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} or WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 6d 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} or DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 74 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} or QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 b4 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c 08 da\s+\{nf\} or dl,bl +\s*[a-f0-9]+:\s*62 f4 3c 1c 08 da\s+\{nf\} or r8b,dl,bl +\s*[a-f0-9]+:\s*62 d4 7c 0c 08 9c 80 23 01 00 00\s+\{nf\} or BYTE PTR \[r8\+rax\*4\+0x123\],bl +\s*[a-f0-9]+:\s*62 d4 6c 1c 08 9c 80 23 01 00 00\s+\{nf\} or dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl +\s*[a-f0-9]+:\s*62 f4 7d 0c 09 d0\s+\{nf\} or ax,dx +\s*[a-f0-9]+:\s*62 f4 35 1c 09 d0\s+\{nf\} or r9w,ax,dx +\s*[a-f0-9]+:\s*62 d4 7d 0c 09 94 80 23 01 00 00\s+\{nf\} or WORD PTR \[r8\+rax\*4\+0x123\],dx +\s*[a-f0-9]+:\s*62 d4 7d 1c 09 94 80 23 01 00 00\s+\{nf\} or ax,WORD PTR \[r8\+rax\*4\+0x123\],dx +\s*[a-f0-9]+:\s*62 f4 7c 0c 09 ca\s+\{nf\} or edx,ecx +\s*[a-f0-9]+:\s*62 f4 2c 1c 09 ca\s+\{nf\} or r10d,edx,ecx +\s*[a-f0-9]+:\s*62 d4 7c 0c 09 8c 80 23 01 00 00\s+\{nf\} or DWORD PTR \[r8\+rax\*4\+0x123\],ecx +\s*[a-f0-9]+:\s*62 d4 6c 1c 09 8c 80 23 01 00 00\s+\{nf\} or edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx +\s*[a-f0-9]+:\s*62 5c fc 0c 09 cf\s+\{nf\} or r31,r9 +\s*[a-f0-9]+:\s*62 5c a4 1c 09 cf\s+\{nf\} or r11,r31,r9 +\s*[a-f0-9]+:\s*62 54 fc 0c 09 8c 80 23 01 00 00\s+\{nf\} or QWORD PTR \[r8\+rax\*4\+0x123\],r9 +\s*[a-f0-9]+:\s*62 54 84 14 09 8c 80 23 01 00 00\s+\{nf\} or r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c 0a 9c 80 23 01 00 00\s+\{nf\} or bl,BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6c 1c 0a 9c 80 23 01 00 00\s+\{nf\} or dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 0c 0b 94 80 23 01 00 00\s+\{nf\} or dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 1c 0b 94 80 23 01 00 00\s+\{nf\} or ax,dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c 0b 8c 80 23 01 00 00\s+\{nf\} or ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6c 1c 0b 8c 80 23 01 00 00\s+\{nf\} or edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 fc 0c 0b 8c 80 23 01 00 00\s+\{nf\} or r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 84 14 0b 8c 80 23 01 00 00\s+\{nf\} or r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f4 7d 0c 88 c2\s+\{nf\} popcnt ax,dx +\s*[a-f0-9]+:\s*62 f4 7c 0c 88 d1\s+\{nf\} popcnt edx,ecx +\s*[a-f0-9]+:\s*62 44 fc 0c 88 f9\s+\{nf\} popcnt r31,r9 +\s*[a-f0-9]+:\s*62 d4 7d 0c 88 94 80 23 01 00 00\s+\{nf\} popcnt dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 fc 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f4 7c 0c d0 c3\s+\{nf\} rol bl,1 +\s*[a-f0-9]+:\s*62 f4 6c 1c d0 c3\s+\{nf\} rol dl,bl,1 +\s*[a-f0-9]+:\s*62 f4 7d 0c d1 c2\s+\{nf\} rol dx,1 +\s*[a-f0-9]+:\s*62 f4 7d 1c d1 c2\s+\{nf\} rol ax,dx,1 +\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c1\s+\{nf\} rol ecx,1 +\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c1\s+\{nf\} rol edx,ecx,1 +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c1\s+\{nf\} rol r9,1 +\s*[a-f0-9]+:\s*62 d4 84 14 d1 c1\s+\{nf\} rol r31,r9,1 +\s*[a-f0-9]+:\s*62 d4 7c 0c d0 84 80 23 01 00 00\s+\{nf\} rol BYTE PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 64 1c d0 84 80 23 01 00 00\s+\{nf\} rol bl,BYTE PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 7d 0c d1 84 80 23 01 00 00\s+\{nf\} rol WORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 6d 1c d1 84 80 23 01 00 00\s+\{nf\} rol dx,WORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 7c 0c d1 84 80 23 01 00 00\s+\{nf\} rol DWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 74 1c d1 84 80 23 01 00 00\s+\{nf\} rol ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 84 80 23 01 00 00\s+\{nf\} rol QWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 b4 1c d1 84 80 23 01 00 00\s+\{nf\} rol r9,QWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 f4 7c 0c c0 c3 7b\s+\{nf\} rol bl,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c c0 c3 7b\s+\{nf\} rol dl,bl,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 0c c1 c2 7b\s+\{nf\} rol dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 1c c1 c2 7b\s+\{nf\} rol ax,dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c1 7b\s+\{nf\} rol ecx,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c1 7b\s+\{nf\} rol edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c1 7b\s+\{nf\} rol r9,0x7b +\s*[a-f0-9]+:\s*62 d4 84 14 c1 c1 7b\s+\{nf\} rol r31,r9,0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c c0 84 80 23 01 00 00 7b\s+\{nf\} rol BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 64 1c c0 84 80 23 01 00 00 7b\s+\{nf\} rol bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7d 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rol WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 6d 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rol DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 74 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rol QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 b4 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c d2 c3\s+\{nf\} rol bl,cl +\s*[a-f0-9]+:\s*62 f4 6c 1c d2 c3\s+\{nf\} rol dl,bl,cl +\s*[a-f0-9]+:\s*62 f4 7d 0c d3 c2\s+\{nf\} rol dx,cl +\s*[a-f0-9]+:\s*62 f4 7d 1c d3 c2\s+\{nf\} rol ax,dx,cl +\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c1\s+\{nf\} rol ecx,cl +\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c1\s+\{nf\} rol edx,ecx,cl +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c1\s+\{nf\} rol r9,cl +\s*[a-f0-9]+:\s*62 d4 84 14 d3 c1\s+\{nf\} rol r31,r9,cl +\s*[a-f0-9]+:\s*62 d4 7c 0c d2 84 80 23 01 00 00\s+\{nf\} rol BYTE PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 64 1c d2 84 80 23 01 00 00\s+\{nf\} rol bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 7d 0c d3 84 80 23 01 00 00\s+\{nf\} rol WORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 6d 1c d3 84 80 23 01 00 00\s+\{nf\} rol dx,WORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 7c 0c d3 84 80 23 01 00 00\s+\{nf\} rol DWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 74 1c d3 84 80 23 01 00 00\s+\{nf\} rol ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 84 80 23 01 00 00\s+\{nf\} rol QWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 b4 1c d3 84 80 23 01 00 00\s+\{nf\} rol r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 f4 7c 0c d0 cb\s+\{nf\} ror bl,1 +\s*[a-f0-9]+:\s*62 f4 6c 1c d0 cb\s+\{nf\} ror dl,bl,1 +\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ca\s+\{nf\} ror dx,1 +\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ca\s+\{nf\} ror ax,dx,1 +\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c9\s+\{nf\} ror ecx,1 +\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c9\s+\{nf\} ror edx,ecx,1 +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c9\s+\{nf\} ror r9,1 +\s*[a-f0-9]+:\s*62 d4 84 14 d1 c9\s+\{nf\} ror r31,r9,1 +\s*[a-f0-9]+:\s*62 d4 7c 0c d0 8c 80 23 01 00 00\s+\{nf\} ror BYTE PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 64 1c d0 8c 80 23 01 00 00\s+\{nf\} ror bl,BYTE PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 7d 0c d1 8c 80 23 01 00 00\s+\{nf\} ror WORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 6d 1c d1 8c 80 23 01 00 00\s+\{nf\} ror dx,WORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 7c 0c d1 8c 80 23 01 00 00\s+\{nf\} ror DWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 74 1c d1 8c 80 23 01 00 00\s+\{nf\} ror ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 8c 80 23 01 00 00\s+\{nf\} ror QWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 b4 1c d1 8c 80 23 01 00 00\s+\{nf\} ror r9,QWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 f4 7c 0c c0 cb 7b\s+\{nf\} ror bl,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c c0 cb 7b\s+\{nf\} ror dl,bl,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ca 7b\s+\{nf\} ror dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ca 7b\s+\{nf\} ror ax,dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c9 7b\s+\{nf\} ror ecx,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c9 7b\s+\{nf\} ror edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c9 7b\s+\{nf\} ror r9,0x7b +\s*[a-f0-9]+:\s*62 d4 84 14 c1 c9 7b\s+\{nf\} ror r31,r9,0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c c0 8c 80 23 01 00 00 7b\s+\{nf\} ror BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 64 1c c0 8c 80 23 01 00 00 7b\s+\{nf\} ror bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7d 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 6d 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 74 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 b4 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c d2 cb\s+\{nf\} ror bl,cl +\s*[a-f0-9]+:\s*62 f4 6c 1c d2 cb\s+\{nf\} ror dl,bl,cl +\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ca\s+\{nf\} ror dx,cl +\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ca\s+\{nf\} ror ax,dx,cl +\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c9\s+\{nf\} ror ecx,cl +\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c9\s+\{nf\} ror edx,ecx,cl +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c9\s+\{nf\} ror r9,cl +\s*[a-f0-9]+:\s*62 d4 84 14 d3 c9\s+\{nf\} ror r31,r9,cl +\s*[a-f0-9]+:\s*62 d4 7c 0c d2 8c 80 23 01 00 00\s+\{nf\} ror BYTE PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 64 1c d2 8c 80 23 01 00 00\s+\{nf\} ror bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 7d 0c d3 8c 80 23 01 00 00\s+\{nf\} ror WORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 6d 1c d3 8c 80 23 01 00 00\s+\{nf\} ror dx,WORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 7c 0c d3 8c 80 23 01 00 00\s+\{nf\} ror DWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 74 1c d3 8c 80 23 01 00 00\s+\{nf\} ror ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 8c 80 23 01 00 00\s+\{nf\} ror QWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 b4 1c d3 8c 80 23 01 00 00\s+\{nf\} ror r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 f4 7c 0c d0 fb\s+\{nf\} sar bl,1 +\s*[a-f0-9]+:\s*62 f4 6c 1c d0 fb\s+\{nf\} sar dl,bl,1 +\s*[a-f0-9]+:\s*62 f4 7d 0c d1 fa\s+\{nf\} sar dx,1 +\s*[a-f0-9]+:\s*62 f4 7d 1c d1 fa\s+\{nf\} sar ax,dx,1 +\s*[a-f0-9]+:\s*62 f4 7c 0c d1 f9\s+\{nf\} sar ecx,1 +\s*[a-f0-9]+:\s*62 f4 6c 1c d1 f9\s+\{nf\} sar edx,ecx,1 +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 f9\s+\{nf\} sar r9,1 +\s*[a-f0-9]+:\s*62 d4 84 14 d1 f9\s+\{nf\} sar r31,r9,1 +\s*[a-f0-9]+:\s*62 d4 7c 0c d0 bc 80 23 01 00 00\s+\{nf\} sar BYTE PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 64 1c d0 bc 80 23 01 00 00\s+\{nf\} sar bl,BYTE PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 7d 0c d1 bc 80 23 01 00 00\s+\{nf\} sar WORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 6d 1c d1 bc 80 23 01 00 00\s+\{nf\} sar dx,WORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 7c 0c d1 bc 80 23 01 00 00\s+\{nf\} sar DWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 74 1c d1 bc 80 23 01 00 00\s+\{nf\} sar ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 bc 80 23 01 00 00\s+\{nf\} sar QWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 b4 1c d1 bc 80 23 01 00 00\s+\{nf\} sar r9,QWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 f4 7c 0c c0 fb 7b\s+\{nf\} sar bl,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c c0 fb 7b\s+\{nf\} sar dl,bl,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 0c c1 fa 7b\s+\{nf\} sar dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 1c c1 fa 7b\s+\{nf\} sar ax,dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c c1 f9 7b\s+\{nf\} sar ecx,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c c1 f9 7b\s+\{nf\} sar edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 f9 7b\s+\{nf\} sar r9,0x7b +\s*[a-f0-9]+:\s*62 d4 84 14 c1 f9 7b\s+\{nf\} sar r31,r9,0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c c0 bc 80 23 01 00 00 7b\s+\{nf\} sar BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 64 1c c0 bc 80 23 01 00 00 7b\s+\{nf\} sar bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7d 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 6d 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 74 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 b4 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c d2 fb\s+\{nf\} sar bl,cl +\s*[a-f0-9]+:\s*62 f4 6c 1c d2 fb\s+\{nf\} sar dl,bl,cl +\s*[a-f0-9]+:\s*62 f4 7d 0c d3 fa\s+\{nf\} sar dx,cl +\s*[a-f0-9]+:\s*62 f4 7d 1c d3 fa\s+\{nf\} sar ax,dx,cl +\s*[a-f0-9]+:\s*62 f4 7c 0c d3 f9\s+\{nf\} sar ecx,cl +\s*[a-f0-9]+:\s*62 f4 6c 1c d3 f9\s+\{nf\} sar edx,ecx,cl +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 f9\s+\{nf\} sar r9,cl +\s*[a-f0-9]+:\s*62 d4 84 14 d3 f9\s+\{nf\} sar r31,r9,cl +\s*[a-f0-9]+:\s*62 d4 7c 0c d2 bc 80 23 01 00 00\s+\{nf\} sar BYTE PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 64 1c d2 bc 80 23 01 00 00\s+\{nf\} sar bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 7d 0c d3 bc 80 23 01 00 00\s+\{nf\} sar WORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 6d 1c d3 bc 80 23 01 00 00\s+\{nf\} sar dx,WORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 7c 0c d3 bc 80 23 01 00 00\s+\{nf\} sar DWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 74 1c d3 bc 80 23 01 00 00\s+\{nf\} sar ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 bc 80 23 01 00 00\s+\{nf\} sar QWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 b4 1c d3 bc 80 23 01 00 00\s+\{nf\} sar r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 f4 7c 0c d0 e3\s+\{nf\} shl bl,1 +\s*[a-f0-9]+:\s*62 f4 6c 1c d0 e3\s+\{nf\} shl dl,bl,1 +\s*[a-f0-9]+:\s*62 f4 7d 0c d1 e2\s+\{nf\} shl dx,1 +\s*[a-f0-9]+:\s*62 f4 7d 1c d1 e2\s+\{nf\} shl ax,dx,1 +\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e1\s+\{nf\} shl ecx,1 +\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e1\s+\{nf\} shl edx,ecx,1 +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e1\s+\{nf\} shl r9,1 +\s*[a-f0-9]+:\s*62 d4 84 14 d1 e1\s+\{nf\} shl r31,r9,1 +\s*[a-f0-9]+:\s*62 d4 7c 0c d0 a4 80 23 01 00 00\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 64 1c d0 a4 80 23 01 00 00\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 7d 0c d1 a4 80 23 01 00 00\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 6d 1c d1 a4 80 23 01 00 00\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 7c 0c d1 a4 80 23 01 00 00\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 74 1c d1 a4 80 23 01 00 00\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 a4 80 23 01 00 00\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 b4 1c d1 a4 80 23 01 00 00\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 f4 7c 0c c0 e3 7b\s+\{nf\} shl bl,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c c0 e3 7b\s+\{nf\} shl dl,bl,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 0c c1 e2 7b\s+\{nf\} shl dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 1c c1 e2 7b\s+\{nf\} shl ax,dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e1 7b\s+\{nf\} shl ecx,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e1 7b\s+\{nf\} shl edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e1 7b\s+\{nf\} shl r9,0x7b +\s*[a-f0-9]+:\s*62 d4 84 14 c1 e1 7b\s+\{nf\} shl r31,r9,0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c c0 a4 80 23 01 00 00 7b\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 64 1c c0 a4 80 23 01 00 00 7b\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7d 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 6d 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 74 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 b4 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c d2 e3\s+\{nf\} shl bl,cl +\s*[a-f0-9]+:\s*62 f4 6c 1c d2 e3\s+\{nf\} shl dl,bl,cl +\s*[a-f0-9]+:\s*62 f4 7d 0c d3 e2\s+\{nf\} shl dx,cl +\s*[a-f0-9]+:\s*62 f4 7d 1c d3 e2\s+\{nf\} shl ax,dx,cl +\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e1\s+\{nf\} shl ecx,cl +\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e1\s+\{nf\} shl edx,ecx,cl +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e1\s+\{nf\} shl r9,cl +\s*[a-f0-9]+:\s*62 d4 84 14 d3 e1\s+\{nf\} shl r31,r9,cl +\s*[a-f0-9]+:\s*62 d4 7c 0c d2 a4 80 23 01 00 00\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 64 1c d2 a4 80 23 01 00 00\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 7d 0c d3 a4 80 23 01 00 00\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 6d 1c d3 a4 80 23 01 00 00\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 7c 0c d3 a4 80 23 01 00 00\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 74 1c d3 a4 80 23 01 00 00\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 a4 80 23 01 00 00\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 b4 1c d3 a4 80 23 01 00 00\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 f4 7d 0c 24 d0 7b\s+\{nf\} shld ax,dx,0x7b +\s*[a-f0-9]+:\s*62 f4 35 1c 24 d0 7b\s+\{nf\} shld r9w,ax,dx,0x7b +\s*[a-f0-9]+:\s*62 d4 7d 0c 24 94 80 23 01 00 00 7b\s+\{nf\} shld WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b +\s*[a-f0-9]+:\s*62 d4 7d 1c 24 94 80 23 01 00 00 7b\s+\{nf\} shld ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c 24 ca 7b\s+\{nf\} shld edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 f4 2c 1c 24 ca 7b\s+\{nf\} shld r10d,edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 6c 1c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b +\s*[a-f0-9]+:\s*62 5c fc 0c 24 cf 7b\s+\{nf\} shld r31,r9,0x7b +\s*[a-f0-9]+:\s*62 5c a4 1c 24 cf 7b\s+\{nf\} shld r11,r31,r9,0x7b +\s*[a-f0-9]+:\s*62 54 fc 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b +\s*[a-f0-9]+:\s*62 54 84 14 24 8c 80 23 01 00 00 7b\s+\{nf\} shld r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 0c a5 d0\s+\{nf\} shld ax,dx,cl +\s*[a-f0-9]+:\s*62 f4 35 1c a5 d0\s+\{nf\} shld r9w,ax,dx,cl +\s*[a-f0-9]+:\s*62 d4 7d 0c a5 94 80 23 01 00 00\s+\{nf\} shld WORD PTR \[r8\+rax\*4\+0x123\],dx,cl +\s*[a-f0-9]+:\s*62 d4 7d 1c a5 94 80 23 01 00 00\s+\{nf\} shld ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,cl +\s*[a-f0-9]+:\s*62 f4 7c 0c a5 ca\s+\{nf\} shld edx,ecx,cl +\s*[a-f0-9]+:\s*62 f4 2c 1c a5 ca\s+\{nf\} shld r10d,edx,ecx,cl +\s*[a-f0-9]+:\s*62 d4 7c 0c a5 8c 80 23 01 00 00\s+\{nf\} shld DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl +\s*[a-f0-9]+:\s*62 d4 6c 1c a5 8c 80 23 01 00 00\s+\{nf\} shld edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl +\s*[a-f0-9]+:\s*62 5c fc 0c a5 cf\s+\{nf\} shld r31,r9,cl +\s*[a-f0-9]+:\s*62 5c a4 1c a5 cf\s+\{nf\} shld r11,r31,r9,cl +\s*[a-f0-9]+:\s*62 54 fc 0c a5 8c 80 23 01 00 00\s+\{nf\} shld QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl +\s*[a-f0-9]+:\s*62 54 84 14 a5 8c 80 23 01 00 00\s+\{nf\} shld r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl +\s*[a-f0-9]+:\s*62 f4 7c 0c d0 eb\s+\{nf\} shr bl,1 +\s*[a-f0-9]+:\s*62 f4 6c 1c d0 eb\s+\{nf\} shr dl,bl,1 +\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ea\s+\{nf\} shr dx,1 +\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ea\s+\{nf\} shr ax,dx,1 +\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e9\s+\{nf\} shr ecx,1 +\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e9\s+\{nf\} shr edx,ecx,1 +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e9\s+\{nf\} shr r9,1 +\s*[a-f0-9]+:\s*62 d4 84 14 d1 e9\s+\{nf\} shr r31,r9,1 +\s*[a-f0-9]+:\s*62 d4 7c 0c d0 ac 80 23 01 00 00\s+\{nf\} shr BYTE PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 64 1c d0 ac 80 23 01 00 00\s+\{nf\} shr bl,BYTE PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 7d 0c d1 ac 80 23 01 00 00\s+\{nf\} shr WORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 6d 1c d1 ac 80 23 01 00 00\s+\{nf\} shr dx,WORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 7c 0c d1 ac 80 23 01 00 00\s+\{nf\} shr DWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 74 1c d1 ac 80 23 01 00 00\s+\{nf\} shr ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 ac 80 23 01 00 00\s+\{nf\} shr QWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 d4 b4 1c d1 ac 80 23 01 00 00\s+\{nf\} shr r9,QWORD PTR \[r8\+rax\*4\+0x123\],1 +\s*[a-f0-9]+:\s*62 f4 7c 0c c0 eb 7b\s+\{nf\} shr bl,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c c0 eb 7b\s+\{nf\} shr dl,bl,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ea 7b\s+\{nf\} shr dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ea 7b\s+\{nf\} shr ax,dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e9 7b\s+\{nf\} shr ecx,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e9 7b\s+\{nf\} shr edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e9 7b\s+\{nf\} shr r9,0x7b +\s*[a-f0-9]+:\s*62 d4 84 14 c1 e9 7b\s+\{nf\} shr r31,r9,0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c c0 ac 80 23 01 00 00 7b\s+\{nf\} shr BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 64 1c c0 ac 80 23 01 00 00 7b\s+\{nf\} shr bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7d 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 6d 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 74 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 b4 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c d2 eb\s+\{nf\} shr bl,cl +\s*[a-f0-9]+:\s*62 f4 6c 1c d2 eb\s+\{nf\} shr dl,bl,cl +\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ea\s+\{nf\} shr dx,cl +\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ea\s+\{nf\} shr ax,dx,cl +\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e9\s+\{nf\} shr ecx,cl +\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e9\s+\{nf\} shr edx,ecx,cl +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e9\s+\{nf\} shr r9,cl +\s*[a-f0-9]+:\s*62 d4 84 14 d3 e9\s+\{nf\} shr r31,r9,cl +\s*[a-f0-9]+:\s*62 d4 7c 0c d2 ac 80 23 01 00 00\s+\{nf\} shr BYTE PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 64 1c d2 ac 80 23 01 00 00\s+\{nf\} shr bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 7d 0c d3 ac 80 23 01 00 00\s+\{nf\} shr WORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 6d 1c d3 ac 80 23 01 00 00\s+\{nf\} shr dx,WORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 7c 0c d3 ac 80 23 01 00 00\s+\{nf\} shr DWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 74 1c d3 ac 80 23 01 00 00\s+\{nf\} shr ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 ac 80 23 01 00 00\s+\{nf\} shr QWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 d4 b4 1c d3 ac 80 23 01 00 00\s+\{nf\} shr r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl +\s*[a-f0-9]+:\s*62 f4 7d 0c 2c d0 7b\s+\{nf\} shrd ax,dx,0x7b +\s*[a-f0-9]+:\s*62 f4 35 1c 2c d0 7b\s+\{nf\} shrd r9w,ax,dx,0x7b +\s*[a-f0-9]+:\s*62 d4 7d 0c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b +\s*[a-f0-9]+:\s*62 d4 7d 1c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c 2c ca 7b\s+\{nf\} shrd edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 f4 2c 1c 2c ca 7b\s+\{nf\} shrd r10d,edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 6c 1c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b +\s*[a-f0-9]+:\s*62 5c fc 0c 2c cf 7b\s+\{nf\} shrd r31,r9,0x7b +\s*[a-f0-9]+:\s*62 5c a4 1c 2c cf 7b\s+\{nf\} shrd r11,r31,r9,0x7b +\s*[a-f0-9]+:\s*62 54 fc 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b +\s*[a-f0-9]+:\s*62 54 84 14 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 0c ad d0\s+\{nf\} shrd ax,dx,cl +\s*[a-f0-9]+:\s*62 f4 35 1c ad d0\s+\{nf\} shrd r9w,ax,dx,cl +\s*[a-f0-9]+:\s*62 d4 7d 0c ad 94 80 23 01 00 00\s+\{nf\} shrd WORD PTR \[r8\+rax\*4\+0x123\],dx,cl +\s*[a-f0-9]+:\s*62 d4 7d 1c ad 94 80 23 01 00 00\s+\{nf\} shrd ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,cl +\s*[a-f0-9]+:\s*62 f4 7c 0c ad ca\s+\{nf\} shrd edx,ecx,cl +\s*[a-f0-9]+:\s*62 f4 2c 1c ad ca\s+\{nf\} shrd r10d,edx,ecx,cl +\s*[a-f0-9]+:\s*62 d4 7c 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl +\s*[a-f0-9]+:\s*62 d4 6c 1c ad 8c 80 23 01 00 00\s+\{nf\} shrd edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl +\s*[a-f0-9]+:\s*62 5c fc 0c ad cf\s+\{nf\} shrd r31,r9,cl +\s*[a-f0-9]+:\s*62 5c a4 1c ad cf\s+\{nf\} shrd r11,r31,r9,cl +\s*[a-f0-9]+:\s*62 54 fc 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl +\s*[a-f0-9]+:\s*62 54 84 14 ad 8c 80 23 01 00 00\s+\{nf\} shrd r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl +\s*[a-f0-9]+:\s*62 f4 7c 0c 80 eb 7b\s+\{nf\} sub bl,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c 80 eb 7b\s+\{nf\} sub dl,bl,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ea 7b\s+\{nf\} sub dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ea 7b\s+\{nf\} sub ax,dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e9 7b\s+\{nf\} sub ecx,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e9 7b\s+\{nf\} sub edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e9 7b\s+\{nf\} sub r9,0x7b +\s*[a-f0-9]+:\s*62 d4 84 14 83 e9 7b\s+\{nf\} sub r31,r9,0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c 80 ac 80 23 01 00 00 7b\s+\{nf\} sub BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 64 1c 80 ac 80 23 01 00 00 7b\s+\{nf\} sub bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7d 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 6d 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 74 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 b4 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c 28 da\s+\{nf\} sub dl,bl +\s*[a-f0-9]+:\s*62 f4 3c 1c 28 da\s+\{nf\} sub r8b,dl,bl +\s*[a-f0-9]+:\s*62 d4 7c 0c 28 9c 80 23 01 00 00\s+\{nf\} sub BYTE PTR \[r8\+rax\*4\+0x123\],bl +\s*[a-f0-9]+:\s*62 d4 6c 1c 28 9c 80 23 01 00 00\s+\{nf\} sub dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl +\s*[a-f0-9]+:\s*62 f4 7d 0c 29 d0\s+\{nf\} sub ax,dx +\s*[a-f0-9]+:\s*62 f4 35 1c 29 d0\s+\{nf\} sub r9w,ax,dx +\s*[a-f0-9]+:\s*62 d4 7d 0c 29 94 80 23 01 00 00\s+\{nf\} sub WORD PTR \[r8\+rax\*4\+0x123\],dx +\s*[a-f0-9]+:\s*62 d4 7d 1c 29 94 80 23 01 00 00\s+\{nf\} sub ax,WORD PTR \[r8\+rax\*4\+0x123\],dx +\s*[a-f0-9]+:\s*62 f4 7c 0c 29 ca\s+\{nf\} sub edx,ecx +\s*[a-f0-9]+:\s*62 f4 2c 1c 29 ca\s+\{nf\} sub r10d,edx,ecx +\s*[a-f0-9]+:\s*62 d4 7c 0c 29 8c 80 23 01 00 00\s+\{nf\} sub DWORD PTR \[r8\+rax\*4\+0x123\],ecx +\s*[a-f0-9]+:\s*62 d4 6c 1c 29 8c 80 23 01 00 00\s+\{nf\} sub edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx +\s*[a-f0-9]+:\s*62 5c fc 0c 29 cf\s+\{nf\} sub r31,r9 +\s*[a-f0-9]+:\s*62 5c a4 1c 29 cf\s+\{nf\} sub r11,r31,r9 +\s*[a-f0-9]+:\s*62 54 fc 0c 29 8c 80 23 01 00 00\s+\{nf\} sub QWORD PTR \[r8\+rax\*4\+0x123\],r9 +\s*[a-f0-9]+:\s*62 54 84 14 29 8c 80 23 01 00 00\s+\{nf\} sub r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c 2a 9c 80 23 01 00 00\s+\{nf\} sub bl,BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6c 1c 2a 9c 80 23 01 00 00\s+\{nf\} sub dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 0c 2b 94 80 23 01 00 00\s+\{nf\} sub dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 1c 2b 94 80 23 01 00 00\s+\{nf\} sub ax,dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6c 1c 2b 8c 80 23 01 00 00\s+\{nf\} sub edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 fc 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 84 14 2b 8c 80 23 01 00 00\s+\{nf\} sub r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f4 7d 0c f4 c2\s+\{nf\} tzcnt ax,dx +\s*[a-f0-9]+:\s*62 f4 7c 0c f4 d1\s+\{nf\} tzcnt edx,ecx +\s*[a-f0-9]+:\s*62 44 fc 0c f4 f9\s+\{nf\} tzcnt r31,r9 +\s*[a-f0-9]+:\s*62 d4 7d 0c f4 94 80 23 01 00 00\s+\{nf\} tzcnt dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 fc 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 f4 7c 0c 80 f3 7b\s+\{nf\} xor bl,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c 80 f3 7b\s+\{nf\} xor dl,bl,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 0c 83 f2 7b\s+\{nf\} xor dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7d 1c 83 f2 7b\s+\{nf\} xor ax,dx,0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c 83 f1 7b\s+\{nf\} xor ecx,0x7b +\s*[a-f0-9]+:\s*62 f4 6c 1c 83 f1 7b\s+\{nf\} xor edx,ecx,0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 f1 7b\s+\{nf\} xor r9,0x7b +\s*[a-f0-9]+:\s*62 d4 84 14 83 f1 7b\s+\{nf\} xor r31,r9,0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c 80 b4 80 23 01 00 00 7b\s+\{nf\} xor BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 64 1c 80 b4 80 23 01 00 00 7b\s+\{nf\} xor bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7d 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 6d 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 7c 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 74 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 d4 b4 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b +\s*[a-f0-9]+:\s*62 f4 7c 0c 30 da\s+\{nf\} xor dl,bl +\s*[a-f0-9]+:\s*62 f4 3c 1c 30 da\s+\{nf\} xor r8b,dl,bl +\s*[a-f0-9]+:\s*62 d4 7c 0c 30 9c 80 23 01 00 00\s+\{nf\} xor BYTE PTR \[r8\+rax\*4\+0x123\],bl +\s*[a-f0-9]+:\s*62 d4 6c 1c 30 9c 80 23 01 00 00\s+\{nf\} xor dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl +\s*[a-f0-9]+:\s*62 f4 7d 0c 31 d0\s+\{nf\} xor ax,dx +\s*[a-f0-9]+:\s*62 f4 35 1c 31 d0\s+\{nf\} xor r9w,ax,dx +\s*[a-f0-9]+:\s*62 d4 7d 0c 31 94 80 23 01 00 00\s+\{nf\} xor WORD PTR \[r8\+rax\*4\+0x123\],dx +\s*[a-f0-9]+:\s*62 d4 7d 1c 31 94 80 23 01 00 00\s+\{nf\} xor ax,WORD PTR \[r8\+rax\*4\+0x123\],dx +\s*[a-f0-9]+:\s*62 f4 7c 0c 31 ca\s+\{nf\} xor edx,ecx +\s*[a-f0-9]+:\s*62 f4 2c 1c 31 ca\s+\{nf\} xor r10d,edx,ecx +\s*[a-f0-9]+:\s*62 d4 7c 0c 31 8c 80 23 01 00 00\s+\{nf\} xor DWORD PTR \[r8\+rax\*4\+0x123\],ecx +\s*[a-f0-9]+:\s*62 d4 6c 1c 31 8c 80 23 01 00 00\s+\{nf\} xor edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx +\s*[a-f0-9]+:\s*62 5c fc 0c 31 cf\s+\{nf\} xor r31,r9 +\s*[a-f0-9]+:\s*62 5c a4 1c 31 cf\s+\{nf\} xor r11,r31,r9 +\s*[a-f0-9]+:\s*62 54 fc 0c 31 8c 80 23 01 00 00\s+\{nf\} xor QWORD PTR \[r8\+rax\*4\+0x123\],r9 +\s*[a-f0-9]+:\s*62 54 84 14 31 8c 80 23 01 00 00\s+\{nf\} xor r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c 32 9c 80 23 01 00 00\s+\{nf\} xor bl,BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6c 1c 32 9c 80 23 01 00 00\s+\{nf\} xor dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 0c 33 94 80 23 01 00 00\s+\{nf\} xor dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7d 1c 33 94 80 23 01 00 00\s+\{nf\} xor ax,dx,WORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 7c 0c 33 8c 80 23 01 00 00\s+\{nf\} xor ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 d4 6c 1c 33 8c 80 23 01 00 00\s+\{nf\} xor edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 fc 0c 33 8c 80 23 01 00 00\s+\{nf\} xor r9,QWORD PTR \[r8\+rax\*4\+0x123\] +\s*[a-f0-9]+:\s*62 54 84 14 33 8c 80 23 01 00 00\s+\{nf\} xor r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-apx-nf.d b/gas/testsuite/gas/i386/x86-64-apx-nf.d new file mode 100644 index 00000000000..ba166e9a98f --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-nf.d @@ -0,0 +1,633 @@ +#as: +#objdump: -dw +#name: x86_64 APX_F insns +#source: x86-64-apx-nf.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 f4 7c 0c 80 c3 7b\s+\{nf\} add \$0x7b,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c 80 c3 7b\s+\{nf\} add \$0x7b,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c 83 c2 7b\s+\{nf\} add \$0x7b,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c 83 c2 7b\s+\{nf\} add \$0x7b,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c1 7b\s+\{nf\} add \$0x7b,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c1 7b\s+\{nf\} add \$0x7b,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c1 7b\s+\{nf\} add \$0x7b,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 83 c1 7b\s+\{nf\} add \$0x7b,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c 80 84 80 23 01 00 00 7b\s+\{nf\} addb \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c 80 84 80 23 01 00 00 7b\s+\{nf\} addb \$0x7b,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c 83 84 80 23 01 00 00 7b\s+\{nf\} addw \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c 83 84 80 23 01 00 00 7b\s+\{nf\} addw \$0x7b,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c 83 84 80 23 01 00 00 7b\s+\{nf\} addl \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c 83 84 80 23 01 00 00 7b\s+\{nf\} addl \$0x7b,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 84 80 23 01 00 00 7b\s+\{nf\} addq \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c 83 84 80 23 01 00 00 7b\s+\{nf\} addq \$0x7b,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c 00 da\s+\{nf\} add %bl,%dl +\s*[a-f0-9]+:\s*62 f4 3c 1c 00 da\s+\{nf\} add %bl,%dl,%r8b +\s*[a-f0-9]+:\s*62 d4 7c 0c 00 9c 80 23 01 00 00\s+\{nf\} add %bl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c 00 9c 80 23 01 00 00\s+\{nf\} add %bl,0x123\(%r8,%rax,4\),%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c 01 d0\s+\{nf\} add %dx,%ax +\s*[a-f0-9]+:\s*62 f4 35 1c 01 d0\s+\{nf\} add %dx,%ax,%r9w +\s*[a-f0-9]+:\s*62 d4 7d 0c 01 94 80 23 01 00 00\s+\{nf\} add %dx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 1c 01 94 80 23 01 00 00\s+\{nf\} add %dx,0x123\(%r8,%rax,4\),%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c 01 ca\s+\{nf\} add %ecx,%edx +\s*[a-f0-9]+:\s*62 f4 2c 1c 01 ca\s+\{nf\} add %ecx,%edx,%r10d +\s*[a-f0-9]+:\s*62 d4 7c 0c 01 8c 80 23 01 00 00\s+\{nf\} add %ecx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c 01 8c 80 23 01 00 00\s+\{nf\} add %ecx,0x123\(%r8,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 5c fc 0c 01 cf\s+\{nf\} add %r9,%r31 +\s*[a-f0-9]+:\s*62 5c a4 1c 01 cf\s+\{nf\} add %r9,%r31,%r11 +\s*[a-f0-9]+:\s*62 54 fc 0c 01 8c 80 23 01 00 00\s+\{nf\} add %r9,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 54 84 14 01 8c 80 23 01 00 00\s+\{nf\} add %r9,0x123\(%r8,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c 02 9c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 6c 1c 02 9c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%bl,%dl +\s*[a-f0-9]+:\s*62 d4 7d 0c 03 94 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7d 1c 03 94 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%dx,%ax +\s*[a-f0-9]+:\s*62 d4 7c 0c 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 6c 1c 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%ecx,%edx +\s*[a-f0-9]+:\s*62 54 fc 0c 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 54 84 14 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%r9,%r31 +\s*[a-f0-9]+:\s*62 f4 7c 0c 80 e3 7b\s+\{nf\} and \$0x7b,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c 80 e3 7b\s+\{nf\} and \$0x7b,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c 83 e2 7b\s+\{nf\} and \$0x7b,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c 83 e2 7b\s+\{nf\} and \$0x7b,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e1 7b\s+\{nf\} and \$0x7b,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e1 7b\s+\{nf\} and \$0x7b,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e1 7b\s+\{nf\} and \$0x7b,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 83 e1 7b\s+\{nf\} and \$0x7b,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c 80 a4 80 23 01 00 00 7b\s+\{nf\} andb \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c 80 a4 80 23 01 00 00 7b\s+\{nf\} andb \$0x7b,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} andw \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} andw \$0x7b,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} andl \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} andl \$0x7b,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} andq \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} andq \$0x7b,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c 20 da\s+\{nf\} and %bl,%dl +\s*[a-f0-9]+:\s*62 f4 3c 1c 20 da\s+\{nf\} and %bl,%dl,%r8b +\s*[a-f0-9]+:\s*62 d4 7c 0c 20 9c 80 23 01 00 00\s+\{nf\} and %bl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c 20 9c 80 23 01 00 00\s+\{nf\} and %bl,0x123\(%r8,%rax,4\),%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c 21 d0\s+\{nf\} and %dx,%ax +\s*[a-f0-9]+:\s*62 f4 35 1c 21 d0\s+\{nf\} and %dx,%ax,%r9w +\s*[a-f0-9]+:\s*62 d4 7d 0c 21 94 80 23 01 00 00\s+\{nf\} and %dx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 1c 21 94 80 23 01 00 00\s+\{nf\} and %dx,0x123\(%r8,%rax,4\),%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c 21 ca\s+\{nf\} and %ecx,%edx +\s*[a-f0-9]+:\s*62 f4 2c 1c 21 ca\s+\{nf\} and %ecx,%edx,%r10d +\s*[a-f0-9]+:\s*62 d4 7c 0c 21 8c 80 23 01 00 00\s+\{nf\} and %ecx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c 21 8c 80 23 01 00 00\s+\{nf\} and %ecx,0x123\(%r8,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 5c fc 0c 21 cf\s+\{nf\} and %r9,%r31 +\s*[a-f0-9]+:\s*62 5c a4 1c 21 cf\s+\{nf\} and %r9,%r31,%r11 +\s*[a-f0-9]+:\s*62 54 fc 0c 21 8c 80 23 01 00 00\s+\{nf\} and %r9,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 54 84 14 21 8c 80 23 01 00 00\s+\{nf\} and %r9,0x123\(%r8,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c 22 9c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 6c 1c 22 9c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%bl,%dl +\s*[a-f0-9]+:\s*62 d4 7d 0c 23 94 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7d 1c 23 94 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%dx,%ax +\s*[a-f0-9]+:\s*62 d4 7c 0c 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 6c 1c 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%ecx,%edx +\s*[a-f0-9]+:\s*62 54 fc 0c 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 54 84 14 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%r9,%r31 +\s*[a-f0-9]+:\s*62 72 6c 0c f2 d1\s+\{nf\} andn %ecx,%edx,%r10d +\s*[a-f0-9]+:\s*62 52 84 04 f2 d9\s+\{nf\} andn %r9,%r31,%r11 +\s*[a-f0-9]+:\s*62 d2 74 0c f2 94 80 23 01 00 00\s+\{nf\} andn 0x123\(%r8,%rax,4\),%ecx,%edx +\s*[a-f0-9]+:\s*62 42 b4 0c f2 bc 80 23 01 00 00\s+\{nf\} andn 0x123\(%r8,%rax,4\),%r9,%r31 +\s*[a-f0-9]+:\s*62 72 74 0c f7 d2\s+\{nf\} bextr %ecx,%edx,%r10d +\s*[a-f0-9]+:\s*62 d2 74 0c f7 94 80 23 01 00 00\s+\{nf\} bextr %ecx,0x123\(%r8,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 5a b4 0c f7 df\s+\{nf\} bextr %r9,%r31,%r11 +\s*[a-f0-9]+:\s*62 42 b4 0c f7 bc 80 23 01 00 00\s+\{nf\} bextr %r9,0x123\(%r8,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d9\s+\{nf\} blsi %ecx,%edx +\s*[a-f0-9]+:\s*62 d2 84 04 f3 d9\s+\{nf\} blsi %r9,%r31 +\s*[a-f0-9]+:\s*62 d2 74 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d2 b4 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d1\s+\{nf\} blsmsk %ecx,%edx +\s*[a-f0-9]+:\s*62 d2 84 04 f3 d1\s+\{nf\} blsmsk %r9,%r31 +\s*[a-f0-9]+:\s*62 d2 74 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d2 b4 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f2 6c 0c f3 c9\s+\{nf\} blsr %ecx,%edx +\s*[a-f0-9]+:\s*62 d2 84 04 f3 c9\s+\{nf\} blsr %r9,%r31 +\s*[a-f0-9]+:\s*62 d2 74 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d2 b4 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 72 74 0c f5 d2\s+\{nf\} bzhi %ecx,%edx,%r10d +\s*[a-f0-9]+:\s*62 d2 74 0c f5 94 80 23 01 00 00\s+\{nf\} bzhi %ecx,0x123\(%r8,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 5a b4 0c f5 df\s+\{nf\} bzhi %r9,%r31,%r11 +\s*[a-f0-9]+:\s*62 42 b4 0c f5 bc 80 23 01 00 00\s+\{nf\} bzhi %r9,0x123\(%r8,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 f4 7c 0c fe cb\s+\{nf\} dec %bl +\s*[a-f0-9]+:\s*62 f4 6c 1c fe cb\s+\{nf\} dec %bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c ff ca\s+\{nf\} dec %dx +\s*[a-f0-9]+:\s*62 f4 7d 1c ff ca\s+\{nf\} dec %dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c ff c9\s+\{nf\} dec %ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c ff c9\s+\{nf\} dec %ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c ff c9\s+\{nf\} dec %r9 +\s*[a-f0-9]+:\s*62 d4 84 14 ff c9\s+\{nf\} dec %r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c fe 8c 80 23 01 00 00\s+\{nf\} decb 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c fe 8c 80 23 01 00 00\s+\{nf\} decb 0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c ff 8c 80 23 01 00 00\s+\{nf\} decw 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c ff 8c 80 23 01 00 00\s+\{nf\} decw 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c ff 8c 80 23 01 00 00\s+\{nf\} decl 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c ff 8c 80 23 01 00 00\s+\{nf\} decl 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c ff 8c 80 23 01 00 00\s+\{nf\} decq 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c ff 8c 80 23 01 00 00\s+\{nf\} decq 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c f6 f3\s+\{nf\} div %bl +\s*[a-f0-9]+:\s*62 f4 7d 0c f7 f2\s+\{nf\} div %dx +\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f1\s+\{nf\} div %ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f1\s+\{nf\} div %r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c f6 b4 80 23 01 00 00\s+\{nf\} divb 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 0c f7 b4 80 23 01 00 00\s+\{nf\} divw 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7c 0c f7 b4 80 23 01 00 00\s+\{nf\} divl 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 b4 80 23 01 00 00\s+\{nf\} divq 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 f4 7c 0c f6 fb\s+\{nf\} idiv %bl +\s*[a-f0-9]+:\s*62 f4 7d 0c f7 fa\s+\{nf\} idiv %dx +\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f9\s+\{nf\} idiv %ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f9\s+\{nf\} idiv %r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c f6 bc 80 23 01 00 00\s+\{nf\} idivb 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 0c f7 bc 80 23 01 00 00\s+\{nf\} idivw 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7c 0c f7 bc 80 23 01 00 00\s+\{nf\} idivl 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 bc 80 23 01 00 00\s+\{nf\} idivq 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 f4 7c 0c f6 eb\s+\{nf\} imul %bl +\s*[a-f0-9]+:\s*62 f4 7d 0c f7 ea\s+\{nf\} imul %dx +\s*[a-f0-9]+:\s*62 f4 7d 0c af c2\s+\{nf\} imul %dx,%ax +\s*[a-f0-9]+:\s*62 f4 35 1c af c2\s+\{nf\} imul %dx,%ax,%r9w +\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e9\s+\{nf\} imul %ecx +\s*[a-f0-9]+:\s*62 f4 7c 0c af d1\s+\{nf\} imul %ecx,%edx +\s*[a-f0-9]+:\s*62 f4 2c 1c af d1\s+\{nf\} imul %ecx,%edx,%r10d +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e9\s+\{nf\} imul %r9 +\s*[a-f0-9]+:\s*62 44 fc 0c af f9\s+\{nf\} imul %r9,%r31 +\s*[a-f0-9]+:\s*62 44 a4 1c af f9\s+\{nf\} imul %r9,%r31,%r11 +\s*[a-f0-9]+:\s*62 d4 7c 0c f6 ac 80 23 01 00 00\s+\{nf\} imulb 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 0c f7 ac 80 23 01 00 00\s+\{nf\} imulw 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 0c af 94 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7d 1c af 94 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%dx,%ax +\s*[a-f0-9]+:\s*62 d4 7c 0c f7 ac 80 23 01 00 00\s+\{nf\} imull 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7c 0c af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 6c 1c af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 ac 80 23 01 00 00\s+\{nf\} imulq 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 54 fc 0c af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 54 84 14 af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%r9,%r31 +\s*[a-f0-9]+:\s*62 f4 7c 0c fe c3\s+\{nf\} inc %bl +\s*[a-f0-9]+:\s*62 f4 6c 1c fe c3\s+\{nf\} inc %bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c ff c2\s+\{nf\} inc %dx +\s*[a-f0-9]+:\s*62 f4 7d 1c ff c2\s+\{nf\} inc %dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c ff c1\s+\{nf\} inc %ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c ff c1\s+\{nf\} inc %ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c ff c1\s+\{nf\} inc %r9 +\s*[a-f0-9]+:\s*62 d4 84 14 ff c1\s+\{nf\} inc %r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c fe 84 80 23 01 00 00\s+\{nf\} incb 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c fe 84 80 23 01 00 00\s+\{nf\} incb 0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c ff 84 80 23 01 00 00\s+\{nf\} incw 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c ff 84 80 23 01 00 00\s+\{nf\} incw 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c ff 84 80 23 01 00 00\s+\{nf\} incl 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c ff 84 80 23 01 00 00\s+\{nf\} incl 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c ff 84 80 23 01 00 00\s+\{nf\} incq 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c ff 84 80 23 01 00 00\s+\{nf\} incq 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7d 0c f5 c2\s+\{nf\} lzcnt %dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c f5 d1\s+\{nf\} lzcnt %ecx,%edx +\s*[a-f0-9]+:\s*62 44 fc 0c f5 f9\s+\{nf\} lzcnt %r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7d 0c f5 94 80 23 01 00 00\s+\{nf\} lzcnt 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 54 fc 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c f6 e3\s+\{nf\} mul %bl +\s*[a-f0-9]+:\s*62 f4 7d 0c f7 e2\s+\{nf\} mul %dx +\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e1\s+\{nf\} mul %ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e1\s+\{nf\} mul %r9 +\s*[a-f0-9]+:\s*62 d4 7c 0c f6 a4 80 23 01 00 00\s+\{nf\} mulb 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 0c f7 a4 80 23 01 00 00\s+\{nf\} mulw 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7c 0c f7 a4 80 23 01 00 00\s+\{nf\} mull 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 a4 80 23 01 00 00\s+\{nf\} mulq 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 f4 7c 0c f6 db\s+\{nf\} neg %bl +\s*[a-f0-9]+:\s*62 f4 6c 1c f6 db\s+\{nf\} neg %bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c f7 da\s+\{nf\} neg %dx +\s*[a-f0-9]+:\s*62 f4 7d 1c f7 da\s+\{nf\} neg %dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c f7 d9\s+\{nf\} neg %ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c f7 d9\s+\{nf\} neg %ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 d9\s+\{nf\} neg %r9 +\s*[a-f0-9]+:\s*62 d4 84 14 f7 d9\s+\{nf\} neg %r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c f6 9c 80 23 01 00 00\s+\{nf\} negb 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c f6 9c 80 23 01 00 00\s+\{nf\} negb 0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c f7 9c 80 23 01 00 00\s+\{nf\} negw 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c f7 9c 80 23 01 00 00\s+\{nf\} negw 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c f7 9c 80 23 01 00 00\s+\{nf\} negl 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c f7 9c 80 23 01 00 00\s+\{nf\} negl 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c f7 9c 80 23 01 00 00\s+\{nf\} negq 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c f7 9c 80 23 01 00 00\s+\{nf\} negq 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c 80 cb 7b\s+\{nf\} or \$0x7b,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c 80 cb 7b\s+\{nf\} or \$0x7b,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ca 7b\s+\{nf\} or \$0x7b,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ca 7b\s+\{nf\} or \$0x7b,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c9 7b\s+\{nf\} or \$0x7b,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c9 7b\s+\{nf\} or \$0x7b,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c9 7b\s+\{nf\} or \$0x7b,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 83 c9 7b\s+\{nf\} or \$0x7b,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c 80 8c 80 23 01 00 00 7b\s+\{nf\} orb \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c 80 8c 80 23 01 00 00 7b\s+\{nf\} orb \$0x7b,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} orw \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} orw \$0x7b,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} orl \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} orl \$0x7b,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} orq \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} orq \$0x7b,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c 08 da\s+\{nf\} or %bl,%dl +\s*[a-f0-9]+:\s*62 f4 3c 1c 08 da\s+\{nf\} or %bl,%dl,%r8b +\s*[a-f0-9]+:\s*62 d4 7c 0c 08 9c 80 23 01 00 00\s+\{nf\} or %bl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c 08 9c 80 23 01 00 00\s+\{nf\} or %bl,0x123\(%r8,%rax,4\),%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c 09 d0\s+\{nf\} or %dx,%ax +\s*[a-f0-9]+:\s*62 f4 35 1c 09 d0\s+\{nf\} or %dx,%ax,%r9w +\s*[a-f0-9]+:\s*62 d4 7d 0c 09 94 80 23 01 00 00\s+\{nf\} or %dx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 1c 09 94 80 23 01 00 00\s+\{nf\} or %dx,0x123\(%r8,%rax,4\),%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c 09 ca\s+\{nf\} or %ecx,%edx +\s*[a-f0-9]+:\s*62 f4 2c 1c 09 ca\s+\{nf\} or %ecx,%edx,%r10d +\s*[a-f0-9]+:\s*62 d4 7c 0c 09 8c 80 23 01 00 00\s+\{nf\} or %ecx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c 09 8c 80 23 01 00 00\s+\{nf\} or %ecx,0x123\(%r8,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 5c fc 0c 09 cf\s+\{nf\} or %r9,%r31 +\s*[a-f0-9]+:\s*62 5c a4 1c 09 cf\s+\{nf\} or %r9,%r31,%r11 +\s*[a-f0-9]+:\s*62 54 fc 0c 09 8c 80 23 01 00 00\s+\{nf\} or %r9,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 54 84 14 09 8c 80 23 01 00 00\s+\{nf\} or %r9,0x123\(%r8,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c 0a 9c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 6c 1c 0a 9c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%bl,%dl +\s*[a-f0-9]+:\s*62 d4 7d 0c 0b 94 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7d 1c 0b 94 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%dx,%ax +\s*[a-f0-9]+:\s*62 d4 7c 0c 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 6c 1c 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%ecx,%edx +\s*[a-f0-9]+:\s*62 54 fc 0c 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 54 84 14 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%r9,%r31 +\s*[a-f0-9]+:\s*62 f4 7d 0c 88 c2\s+\{nf\} popcnt %dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c 88 d1\s+\{nf\} popcnt %ecx,%edx +\s*[a-f0-9]+:\s*62 44 fc 0c 88 f9\s+\{nf\} popcnt %r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7d 0c 88 94 80 23 01 00 00\s+\{nf\} popcnt 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 54 fc 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c d0 c3\s+\{nf\} rol %bl +\s*[a-f0-9]+:\s*62 f4 6c 1c d0 c3\s+\{nf\} rol %bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c d1 c2\s+\{nf\} rol %dx +\s*[a-f0-9]+:\s*62 f4 7d 1c d1 c2\s+\{nf\} rol %dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c1\s+\{nf\} rol %ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c1\s+\{nf\} rol %ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c1\s+\{nf\} rol %r9 +\s*[a-f0-9]+:\s*62 d4 84 14 d1 c1\s+\{nf\} rol %r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c d0 84 80 23 01 00 00\s+\{nf\} rolb 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c d0 84 80 23 01 00 00\s+\{nf\} rolb 0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c d1 84 80 23 01 00 00\s+\{nf\} rolw 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c d1 84 80 23 01 00 00\s+\{nf\} rolw 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c d1 84 80 23 01 00 00\s+\{nf\} roll 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c d1 84 80 23 01 00 00\s+\{nf\} roll 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 84 80 23 01 00 00\s+\{nf\} rolq 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c d1 84 80 23 01 00 00\s+\{nf\} rolq 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c c0 c3 7b\s+\{nf\} rol \$0x7b,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c c0 c3 7b\s+\{nf\} rol \$0x7b,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c c1 c2 7b\s+\{nf\} rol \$0x7b,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c c1 c2 7b\s+\{nf\} rol \$0x7b,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c1 7b\s+\{nf\} rol \$0x7b,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c1 7b\s+\{nf\} rol \$0x7b,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c1 7b\s+\{nf\} rol \$0x7b,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 c1 c1 7b\s+\{nf\} rol \$0x7b,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c c0 84 80 23 01 00 00 7b\s+\{nf\} rolb \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c c0 84 80 23 01 00 00 7b\s+\{nf\} rolb \$0x7b,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rolw \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rolw \$0x7b,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c c1 84 80 23 01 00 00 7b\s+\{nf\} roll \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c c1 84 80 23 01 00 00 7b\s+\{nf\} roll \$0x7b,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rolq \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rolq \$0x7b,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c d2 c3\s+\{nf\} rol %cl,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c d2 c3\s+\{nf\} rol %cl,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c d3 c2\s+\{nf\} rol %cl,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c d3 c2\s+\{nf\} rol %cl,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c1\s+\{nf\} rol %cl,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c1\s+\{nf\} rol %cl,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c1\s+\{nf\} rol %cl,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 d3 c1\s+\{nf\} rol %cl,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c d2 84 80 23 01 00 00\s+\{nf\} rolb %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c d2 84 80 23 01 00 00\s+\{nf\} rolb %cl,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c d3 84 80 23 01 00 00\s+\{nf\} rolw %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c d3 84 80 23 01 00 00\s+\{nf\} rolw %cl,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c d3 84 80 23 01 00 00\s+\{nf\} roll %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c d3 84 80 23 01 00 00\s+\{nf\} roll %cl,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 84 80 23 01 00 00\s+\{nf\} rolq %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c d3 84 80 23 01 00 00\s+\{nf\} rolq %cl,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c d0 cb\s+\{nf\} ror %bl +\s*[a-f0-9]+:\s*62 f4 6c 1c d0 cb\s+\{nf\} ror %bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ca\s+\{nf\} ror %dx +\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ca\s+\{nf\} ror %dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c9\s+\{nf\} ror %ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c9\s+\{nf\} ror %ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c9\s+\{nf\} ror %r9 +\s*[a-f0-9]+:\s*62 d4 84 14 d1 c9\s+\{nf\} ror %r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c d0 8c 80 23 01 00 00\s+\{nf\} rorb 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c d0 8c 80 23 01 00 00\s+\{nf\} rorb 0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c d1 8c 80 23 01 00 00\s+\{nf\} rorw 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c d1 8c 80 23 01 00 00\s+\{nf\} rorw 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c d1 8c 80 23 01 00 00\s+\{nf\} rorl 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c d1 8c 80 23 01 00 00\s+\{nf\} rorl 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 8c 80 23 01 00 00\s+\{nf\} rorq 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c d1 8c 80 23 01 00 00\s+\{nf\} rorq 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c c0 cb 7b\s+\{nf\} ror \$0x7b,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c c0 cb 7b\s+\{nf\} ror \$0x7b,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ca 7b\s+\{nf\} ror \$0x7b,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ca 7b\s+\{nf\} ror \$0x7b,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c9 7b\s+\{nf\} ror \$0x7b,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c9 7b\s+\{nf\} ror \$0x7b,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c9 7b\s+\{nf\} ror \$0x7b,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 c1 c9 7b\s+\{nf\} ror \$0x7b,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c c0 8c 80 23 01 00 00 7b\s+\{nf\} rorb \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c c0 8c 80 23 01 00 00 7b\s+\{nf\} rorb \$0x7b,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorw \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorw \$0x7b,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorl \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorl \$0x7b,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorq \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorq \$0x7b,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c d2 cb\s+\{nf\} ror %cl,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c d2 cb\s+\{nf\} ror %cl,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ca\s+\{nf\} ror %cl,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ca\s+\{nf\} ror %cl,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c9\s+\{nf\} ror %cl,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c9\s+\{nf\} ror %cl,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c9\s+\{nf\} ror %cl,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 d3 c9\s+\{nf\} ror %cl,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c d2 8c 80 23 01 00 00\s+\{nf\} rorb %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c d2 8c 80 23 01 00 00\s+\{nf\} rorb %cl,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c d3 8c 80 23 01 00 00\s+\{nf\} rorw %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c d3 8c 80 23 01 00 00\s+\{nf\} rorw %cl,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c d3 8c 80 23 01 00 00\s+\{nf\} rorl %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c d3 8c 80 23 01 00 00\s+\{nf\} rorl %cl,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 8c 80 23 01 00 00\s+\{nf\} rorq %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c d3 8c 80 23 01 00 00\s+\{nf\} rorq %cl,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c d0 fb\s+\{nf\} sar %bl +\s*[a-f0-9]+:\s*62 f4 6c 1c d0 fb\s+\{nf\} sar %bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c d1 fa\s+\{nf\} sar %dx +\s*[a-f0-9]+:\s*62 f4 7d 1c d1 fa\s+\{nf\} sar %dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c d1 f9\s+\{nf\} sar %ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c d1 f9\s+\{nf\} sar %ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 f9\s+\{nf\} sar %r9 +\s*[a-f0-9]+:\s*62 d4 84 14 d1 f9\s+\{nf\} sar %r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c d0 bc 80 23 01 00 00\s+\{nf\} sarb 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c d0 bc 80 23 01 00 00\s+\{nf\} sarb 0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c d1 bc 80 23 01 00 00\s+\{nf\} sarw 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c d1 bc 80 23 01 00 00\s+\{nf\} sarw 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c d1 bc 80 23 01 00 00\s+\{nf\} sarl 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c d1 bc 80 23 01 00 00\s+\{nf\} sarl 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 bc 80 23 01 00 00\s+\{nf\} sarq 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c d1 bc 80 23 01 00 00\s+\{nf\} sarq 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c c0 fb 7b\s+\{nf\} sar \$0x7b,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c c0 fb 7b\s+\{nf\} sar \$0x7b,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c c1 fa 7b\s+\{nf\} sar \$0x7b,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c c1 fa 7b\s+\{nf\} sar \$0x7b,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c c1 f9 7b\s+\{nf\} sar \$0x7b,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c c1 f9 7b\s+\{nf\} sar \$0x7b,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 f9 7b\s+\{nf\} sar \$0x7b,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 c1 f9 7b\s+\{nf\} sar \$0x7b,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c c0 bc 80 23 01 00 00 7b\s+\{nf\} sarb \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c c0 bc 80 23 01 00 00 7b\s+\{nf\} sarb \$0x7b,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarw \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarw \$0x7b,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarl \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarl \$0x7b,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarq \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarq \$0x7b,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c d2 fb\s+\{nf\} sar %cl,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c d2 fb\s+\{nf\} sar %cl,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c d3 fa\s+\{nf\} sar %cl,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c d3 fa\s+\{nf\} sar %cl,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c d3 f9\s+\{nf\} sar %cl,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c d3 f9\s+\{nf\} sar %cl,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 f9\s+\{nf\} sar %cl,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 d3 f9\s+\{nf\} sar %cl,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c d2 bc 80 23 01 00 00\s+\{nf\} sarb %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c d2 bc 80 23 01 00 00\s+\{nf\} sarb %cl,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c d3 bc 80 23 01 00 00\s+\{nf\} sarw %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c d3 bc 80 23 01 00 00\s+\{nf\} sarw %cl,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c d3 bc 80 23 01 00 00\s+\{nf\} sarl %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c d3 bc 80 23 01 00 00\s+\{nf\} sarl %cl,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 bc 80 23 01 00 00\s+\{nf\} sarq %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c d3 bc 80 23 01 00 00\s+\{nf\} sarq %cl,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c d0 e3\s+\{nf\} shl %bl +\s*[a-f0-9]+:\s*62 f4 6c 1c d0 e3\s+\{nf\} shl %bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c d1 e2\s+\{nf\} shl %dx +\s*[a-f0-9]+:\s*62 f4 7d 1c d1 e2\s+\{nf\} shl %dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e1\s+\{nf\} shl %ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e1\s+\{nf\} shl %ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e1\s+\{nf\} shl %r9 +\s*[a-f0-9]+:\s*62 d4 84 14 d1 e1\s+\{nf\} shl %r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c d0 a4 80 23 01 00 00\s+\{nf\} shlb 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c d0 a4 80 23 01 00 00\s+\{nf\} shlb 0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c d1 a4 80 23 01 00 00\s+\{nf\} shlw 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c d1 a4 80 23 01 00 00\s+\{nf\} shlw 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c d1 a4 80 23 01 00 00\s+\{nf\} shll 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c d1 a4 80 23 01 00 00\s+\{nf\} shll 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 a4 80 23 01 00 00\s+\{nf\} shlq 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c d1 a4 80 23 01 00 00\s+\{nf\} shlq 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c c0 e3 7b\s+\{nf\} shl \$0x7b,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c c0 e3 7b\s+\{nf\} shl \$0x7b,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c c1 e2 7b\s+\{nf\} shl \$0x7b,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c c1 e2 7b\s+\{nf\} shl \$0x7b,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e1 7b\s+\{nf\} shl \$0x7b,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e1 7b\s+\{nf\} shl \$0x7b,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e1 7b\s+\{nf\} shl \$0x7b,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 c1 e1 7b\s+\{nf\} shl \$0x7b,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c c0 a4 80 23 01 00 00 7b\s+\{nf\} shlb \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c c0 a4 80 23 01 00 00 7b\s+\{nf\} shlb \$0x7b,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlw \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlw \$0x7b,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shll \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shll \$0x7b,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlq \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlq \$0x7b,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c d2 e3\s+\{nf\} shl %cl,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c d2 e3\s+\{nf\} shl %cl,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c d3 e2\s+\{nf\} shl %cl,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c d3 e2\s+\{nf\} shl %cl,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e1\s+\{nf\} shl %cl,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e1\s+\{nf\} shl %cl,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e1\s+\{nf\} shl %cl,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 d3 e1\s+\{nf\} shl %cl,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c d2 a4 80 23 01 00 00\s+\{nf\} shlb %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c d2 a4 80 23 01 00 00\s+\{nf\} shlb %cl,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c d3 a4 80 23 01 00 00\s+\{nf\} shlw %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c d3 a4 80 23 01 00 00\s+\{nf\} shlw %cl,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c d3 a4 80 23 01 00 00\s+\{nf\} shll %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c d3 a4 80 23 01 00 00\s+\{nf\} shll %cl,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 a4 80 23 01 00 00\s+\{nf\} shlq %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c d3 a4 80 23 01 00 00\s+\{nf\} shlq %cl,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7d 0c 24 d0 7b\s+\{nf\} shld \$0x7b,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 35 1c 24 d0 7b\s+\{nf\} shld \$0x7b,%dx,%ax,%r9w +\s*[a-f0-9]+:\s*62 d4 7d 0c 24 94 80 23 01 00 00 7b\s+\{nf\} shld \$0x7b,%dx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 1c 24 94 80 23 01 00 00 7b\s+\{nf\} shld \$0x7b,%dx,0x123\(%r8,%rax,4\),%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c 24 ca 7b\s+\{nf\} shld \$0x7b,%ecx,%edx +\s*[a-f0-9]+:\s*62 f4 2c 1c 24 ca 7b\s+\{nf\} shld \$0x7b,%ecx,%edx,%r10d +\s*[a-f0-9]+:\s*62 d4 7c 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld \$0x7b,%ecx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld \$0x7b,%ecx,0x123\(%r8,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 5c fc 0c 24 cf 7b\s+\{nf\} shld \$0x7b,%r9,%r31 +\s*[a-f0-9]+:\s*62 5c a4 1c 24 cf 7b\s+\{nf\} shld \$0x7b,%r9,%r31,%r11 +\s*[a-f0-9]+:\s*62 54 fc 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld \$0x7b,%r9,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 54 84 14 24 8c 80 23 01 00 00 7b\s+\{nf\} shld \$0x7b,%r9,0x123\(%r8,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 f4 7d 0c a5 d0\s+\{nf\} shld %cl,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 35 1c a5 d0\s+\{nf\} shld %cl,%dx,%ax,%r9w +\s*[a-f0-9]+:\s*62 d4 7d 0c a5 94 80 23 01 00 00\s+\{nf\} shld %cl,%dx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 1c a5 94 80 23 01 00 00\s+\{nf\} shld %cl,%dx,0x123\(%r8,%rax,4\),%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c a5 ca\s+\{nf\} shld %cl,%ecx,%edx +\s*[a-f0-9]+:\s*62 f4 2c 1c a5 ca\s+\{nf\} shld %cl,%ecx,%edx,%r10d +\s*[a-f0-9]+:\s*62 d4 7c 0c a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%ecx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%ecx,0x123\(%r8,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 5c fc 0c a5 cf\s+\{nf\} shld %cl,%r9,%r31 +\s*[a-f0-9]+:\s*62 5c a4 1c a5 cf\s+\{nf\} shld %cl,%r9,%r31,%r11 +\s*[a-f0-9]+:\s*62 54 fc 0c a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%r9,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 54 84 14 a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%r9,0x123\(%r8,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 f4 7c 0c d0 eb\s+\{nf\} shr %bl +\s*[a-f0-9]+:\s*62 f4 6c 1c d0 eb\s+\{nf\} shr %bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ea\s+\{nf\} shr %dx +\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ea\s+\{nf\} shr %dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e9\s+\{nf\} shr %ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e9\s+\{nf\} shr %ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e9\s+\{nf\} shr %r9 +\s*[a-f0-9]+:\s*62 d4 84 14 d1 e9\s+\{nf\} shr %r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c d0 ac 80 23 01 00 00\s+\{nf\} shrb 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c d0 ac 80 23 01 00 00\s+\{nf\} shrb 0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c d1 ac 80 23 01 00 00\s+\{nf\} shrw 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c d1 ac 80 23 01 00 00\s+\{nf\} shrw 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c d1 ac 80 23 01 00 00\s+\{nf\} shrl 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c d1 ac 80 23 01 00 00\s+\{nf\} shrl 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c d1 ac 80 23 01 00 00\s+\{nf\} shrq 0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c d1 ac 80 23 01 00 00\s+\{nf\} shrq 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c c0 eb 7b\s+\{nf\} shr \$0x7b,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c c0 eb 7b\s+\{nf\} shr \$0x7b,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ea 7b\s+\{nf\} shr \$0x7b,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ea 7b\s+\{nf\} shr \$0x7b,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e9 7b\s+\{nf\} shr \$0x7b,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e9 7b\s+\{nf\} shr \$0x7b,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e9 7b\s+\{nf\} shr \$0x7b,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 c1 e9 7b\s+\{nf\} shr \$0x7b,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c c0 ac 80 23 01 00 00 7b\s+\{nf\} shrb \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c c0 ac 80 23 01 00 00 7b\s+\{nf\} shrb \$0x7b,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrw \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrw \$0x7b,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrl \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrl \$0x7b,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrq \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrq \$0x7b,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c d2 eb\s+\{nf\} shr %cl,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c d2 eb\s+\{nf\} shr %cl,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ea\s+\{nf\} shr %cl,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ea\s+\{nf\} shr %cl,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e9\s+\{nf\} shr %cl,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e9\s+\{nf\} shr %cl,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e9\s+\{nf\} shr %cl,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 d3 e9\s+\{nf\} shr %cl,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c d2 ac 80 23 01 00 00\s+\{nf\} shrb %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c d2 ac 80 23 01 00 00\s+\{nf\} shrb %cl,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c d3 ac 80 23 01 00 00\s+\{nf\} shrw %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c d3 ac 80 23 01 00 00\s+\{nf\} shrw %cl,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c d3 ac 80 23 01 00 00\s+\{nf\} shrl %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c d3 ac 80 23 01 00 00\s+\{nf\} shrl %cl,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c d3 ac 80 23 01 00 00\s+\{nf\} shrq %cl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c d3 ac 80 23 01 00 00\s+\{nf\} shrq %cl,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7d 0c 2c d0 7b\s+\{nf\} shrd \$0x7b,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 35 1c 2c d0 7b\s+\{nf\} shrd \$0x7b,%dx,%ax,%r9w +\s*[a-f0-9]+:\s*62 d4 7d 0c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd \$0x7b,%dx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 1c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd \$0x7b,%dx,0x123\(%r8,%rax,4\),%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c 2c ca 7b\s+\{nf\} shrd \$0x7b,%ecx,%edx +\s*[a-f0-9]+:\s*62 f4 2c 1c 2c ca 7b\s+\{nf\} shrd \$0x7b,%ecx,%edx,%r10d +\s*[a-f0-9]+:\s*62 d4 7c 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd \$0x7b,%ecx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd \$0x7b,%ecx,0x123\(%r8,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 5c fc 0c 2c cf 7b\s+\{nf\} shrd \$0x7b,%r9,%r31 +\s*[a-f0-9]+:\s*62 5c a4 1c 2c cf 7b\s+\{nf\} shrd \$0x7b,%r9,%r31,%r11 +\s*[a-f0-9]+:\s*62 54 fc 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd \$0x7b,%r9,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 54 84 14 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd \$0x7b,%r9,0x123\(%r8,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 f4 7d 0c ad d0\s+\{nf\} shrd %cl,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 35 1c ad d0\s+\{nf\} shrd %cl,%dx,%ax,%r9w +\s*[a-f0-9]+:\s*62 d4 7d 0c ad 94 80 23 01 00 00\s+\{nf\} shrd %cl,%dx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 1c ad 94 80 23 01 00 00\s+\{nf\} shrd %cl,%dx,0x123\(%r8,%rax,4\),%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c ad ca\s+\{nf\} shrd %cl,%ecx,%edx +\s*[a-f0-9]+:\s*62 f4 2c 1c ad ca\s+\{nf\} shrd %cl,%ecx,%edx,%r10d +\s*[a-f0-9]+:\s*62 d4 7c 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%ecx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%ecx,0x123\(%r8,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 5c fc 0c ad cf\s+\{nf\} shrd %cl,%r9,%r31 +\s*[a-f0-9]+:\s*62 5c a4 1c ad cf\s+\{nf\} shrd %cl,%r9,%r31,%r11 +\s*[a-f0-9]+:\s*62 54 fc 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%r9,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 54 84 14 ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%r9,0x123\(%r8,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 f4 7c 0c 80 eb 7b\s+\{nf\} sub \$0x7b,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c 80 eb 7b\s+\{nf\} sub \$0x7b,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ea 7b\s+\{nf\} sub \$0x7b,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ea 7b\s+\{nf\} sub \$0x7b,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e9 7b\s+\{nf\} sub \$0x7b,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e9 7b\s+\{nf\} sub \$0x7b,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e9 7b\s+\{nf\} sub \$0x7b,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 83 e9 7b\s+\{nf\} sub \$0x7b,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c 80 ac 80 23 01 00 00 7b\s+\{nf\} subb \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c 80 ac 80 23 01 00 00 7b\s+\{nf\} subb \$0x7b,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} subw \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} subw \$0x7b,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} subl \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} subl \$0x7b,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} subq \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} subq \$0x7b,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c 28 da\s+\{nf\} sub %bl,%dl +\s*[a-f0-9]+:\s*62 f4 3c 1c 28 da\s+\{nf\} sub %bl,%dl,%r8b +\s*[a-f0-9]+:\s*62 d4 7c 0c 28 9c 80 23 01 00 00\s+\{nf\} sub %bl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c 28 9c 80 23 01 00 00\s+\{nf\} sub %bl,0x123\(%r8,%rax,4\),%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c 29 d0\s+\{nf\} sub %dx,%ax +\s*[a-f0-9]+:\s*62 f4 35 1c 29 d0\s+\{nf\} sub %dx,%ax,%r9w +\s*[a-f0-9]+:\s*62 d4 7d 0c 29 94 80 23 01 00 00\s+\{nf\} sub %dx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 1c 29 94 80 23 01 00 00\s+\{nf\} sub %dx,0x123\(%r8,%rax,4\),%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c 29 ca\s+\{nf\} sub %ecx,%edx +\s*[a-f0-9]+:\s*62 f4 2c 1c 29 ca\s+\{nf\} sub %ecx,%edx,%r10d +\s*[a-f0-9]+:\s*62 d4 7c 0c 29 8c 80 23 01 00 00\s+\{nf\} sub %ecx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c 29 8c 80 23 01 00 00\s+\{nf\} sub %ecx,0x123\(%r8,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 5c fc 0c 29 cf\s+\{nf\} sub %r9,%r31 +\s*[a-f0-9]+:\s*62 5c a4 1c 29 cf\s+\{nf\} sub %r9,%r31,%r11 +\s*[a-f0-9]+:\s*62 54 fc 0c 29 8c 80 23 01 00 00\s+\{nf\} sub %r9,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 54 84 14 29 8c 80 23 01 00 00\s+\{nf\} sub %r9,0x123\(%r8,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c 2a 9c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 6c 1c 2a 9c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%bl,%dl +\s*[a-f0-9]+:\s*62 d4 7d 0c 2b 94 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7d 1c 2b 94 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%dx,%ax +\s*[a-f0-9]+:\s*62 d4 7c 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 6c 1c 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%ecx,%edx +\s*[a-f0-9]+:\s*62 54 fc 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 54 84 14 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%r9,%r31 +\s*[a-f0-9]+:\s*62 f4 7d 0c f4 c2\s+\{nf\} tzcnt %dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c f4 d1\s+\{nf\} tzcnt %ecx,%edx +\s*[a-f0-9]+:\s*62 44 fc 0c f4 f9\s+\{nf\} tzcnt %r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7d 0c f4 94 80 23 01 00 00\s+\{nf\} tzcnt 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 54 fc 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c 80 f3 7b\s+\{nf\} xor \$0x7b,%bl +\s*[a-f0-9]+:\s*62 f4 6c 1c 80 f3 7b\s+\{nf\} xor \$0x7b,%bl,%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c 83 f2 7b\s+\{nf\} xor \$0x7b,%dx +\s*[a-f0-9]+:\s*62 f4 7d 1c 83 f2 7b\s+\{nf\} xor \$0x7b,%dx,%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c 83 f1 7b\s+\{nf\} xor \$0x7b,%ecx +\s*[a-f0-9]+:\s*62 f4 6c 1c 83 f1 7b\s+\{nf\} xor \$0x7b,%ecx,%edx +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 f1 7b\s+\{nf\} xor \$0x7b,%r9 +\s*[a-f0-9]+:\s*62 d4 84 14 83 f1 7b\s+\{nf\} xor \$0x7b,%r9,%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c 80 b4 80 23 01 00 00 7b\s+\{nf\} xorb \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 64 1c 80 b4 80 23 01 00 00 7b\s+\{nf\} xorb \$0x7b,0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 7d 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorw \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6d 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorw \$0x7b,0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7c 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorl \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 74 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorl \$0x7b,0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 fc 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorq \$0x7b,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 b4 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorq \$0x7b,0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 f4 7c 0c 30 da\s+\{nf\} xor %bl,%dl +\s*[a-f0-9]+:\s*62 f4 3c 1c 30 da\s+\{nf\} xor %bl,%dl,%r8b +\s*[a-f0-9]+:\s*62 d4 7c 0c 30 9c 80 23 01 00 00\s+\{nf\} xor %bl,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c 30 9c 80 23 01 00 00\s+\{nf\} xor %bl,0x123\(%r8,%rax,4\),%dl +\s*[a-f0-9]+:\s*62 f4 7d 0c 31 d0\s+\{nf\} xor %dx,%ax +\s*[a-f0-9]+:\s*62 f4 35 1c 31 d0\s+\{nf\} xor %dx,%ax,%r9w +\s*[a-f0-9]+:\s*62 d4 7d 0c 31 94 80 23 01 00 00\s+\{nf\} xor %dx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 7d 1c 31 94 80 23 01 00 00\s+\{nf\} xor %dx,0x123\(%r8,%rax,4\),%ax +\s*[a-f0-9]+:\s*62 f4 7c 0c 31 ca\s+\{nf\} xor %ecx,%edx +\s*[a-f0-9]+:\s*62 f4 2c 1c 31 ca\s+\{nf\} xor %ecx,%edx,%r10d +\s*[a-f0-9]+:\s*62 d4 7c 0c 31 8c 80 23 01 00 00\s+\{nf\} xor %ecx,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 d4 6c 1c 31 8c 80 23 01 00 00\s+\{nf\} xor %ecx,0x123\(%r8,%rax,4\),%edx +\s*[a-f0-9]+:\s*62 5c fc 0c 31 cf\s+\{nf\} xor %r9,%r31 +\s*[a-f0-9]+:\s*62 5c a4 1c 31 cf\s+\{nf\} xor %r9,%r31,%r11 +\s*[a-f0-9]+:\s*62 54 fc 0c 31 8c 80 23 01 00 00\s+\{nf\} xor %r9,0x123\(%r8,%rax,4\) +\s*[a-f0-9]+:\s*62 54 84 14 31 8c 80 23 01 00 00\s+\{nf\} xor %r9,0x123\(%r8,%rax,4\),%r31 +\s*[a-f0-9]+:\s*62 d4 7c 0c 32 9c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%bl +\s*[a-f0-9]+:\s*62 d4 6c 1c 32 9c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%bl,%dl +\s*[a-f0-9]+:\s*62 d4 7d 0c 33 94 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%dx +\s*[a-f0-9]+:\s*62 d4 7d 1c 33 94 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%dx,%ax +\s*[a-f0-9]+:\s*62 d4 7c 0c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%ecx +\s*[a-f0-9]+:\s*62 d4 6c 1c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%ecx,%edx +\s*[a-f0-9]+:\s*62 54 fc 0c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%r9 +\s*[a-f0-9]+:\s*62 54 84 14 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%r9,%r31 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-apx-nf.s b/gas/testsuite/gas/i386/x86-64-apx-nf.s new file mode 100644 index 00000000000..1016dcfdd27 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-nf.s @@ -0,0 +1,1256 @@ +# Check 64bit APX_F instructions + + .text +_start: + {nf} add $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} addb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} addb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} addw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} addw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} addl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} addl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} addq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} addq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add %bl, %dl, %r8b #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add %bl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add %bl, 291(%r8, %rax, 4), %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add 291(%r8, %rax, 4), %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add 291(%r8, %rax, 4), %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} andb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} andb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} andw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} andw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} andl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} andl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} andq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} andq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and %bl, %dl, %r8b #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and %bl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and %bl, 291(%r8, %rax, 4), %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and 291(%r8, %rax, 4), %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and 291(%r8, %rax, 4), %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} andn %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} andn %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} andn 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} andn 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bextr %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bextr %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bextr %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bextr %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsi %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsi %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsi 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsi 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsmsk %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsmsk %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsmsk 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsmsk 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsr %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsr %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsr 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsr 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bzhi %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bzhi %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bzhi %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bzhi %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} dec %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} dec %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} dec %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} decb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} decb 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} decw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} decw 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} decl 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} decl 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} decq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} decq 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} div %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} div %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} div %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} div %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} divb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} divw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} divl 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} divq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idiv %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idiv %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idiv %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idiv %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idivb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idivw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idivl 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idivq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} imul %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} imul %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} imulb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imulw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul 291(%r8, %rax, 4), %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} imull 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} imulq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} inc %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} inc %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} inc %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} inc %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} inc %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} inc %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} inc %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} inc %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} incb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} incb 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} incw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} incw 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} incl 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} incl 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} incq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} incq 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} lzcnt %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} lzcnt %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} lzcnt %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} lzcnt 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} lzcnt 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} lzcnt 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mul %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mul %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mul %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mul %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mulb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mulw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mull 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mulq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} neg %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} neg %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} neg %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} negb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} negb 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} negw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} negw 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} negl 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} negl 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} negq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} negq 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} orb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} orb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} orw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} orw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} orl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} orl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} orq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} orq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or %bl, %dl, %r8b #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or %bl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or %bl, 291(%r8, %rax, 4), %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or 291(%r8, %rax, 4), %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or 291(%r8, %rax, 4), %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} popcnt %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} popcnt %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} popcnt %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} popcnt 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} popcnt 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} popcnt 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol $1, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol $1, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol $1, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol $1, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol $1, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol $1, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol $1, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol $1, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rolb $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rolb $1, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rolw $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rolw $1, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} roll $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} roll $1, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rolq $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rolq $1, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rolb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rolb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rolw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rolw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} roll $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} roll $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rolq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rolq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol %cl, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol %cl, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol %cl, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol %cl, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol %cl, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rolb %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rolb %cl, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rolw %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rolw %cl, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} roll %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} roll %cl, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rolq %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rolq %cl, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror $1, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror $1, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror $1, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror $1, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror $1, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror $1, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror $1, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror $1, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rorb $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rorb $1, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rorw $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rorw $1, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rorl $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rorl $1, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rorq $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rorq $1, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rorb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rorb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rorw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rorw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rorl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rorl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rorq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rorq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror %cl, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror %cl, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror %cl, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror %cl, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror %cl, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rorb %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rorb %cl, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rorw %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rorw %cl, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rorl %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rorl %cl, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rorq %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rorq %cl, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar $1, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar $1, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar $1, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar $1, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar $1, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar $1, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar $1, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar $1, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sarb $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sarb $1, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sarw $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sarw $1, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sarl $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sarl $1, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sarq $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sarq $1, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sarb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sarb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sarw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sarw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sarl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sarl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sarq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sarq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar %cl, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar %cl, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar %cl, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar %cl, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar %cl, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sarb %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sarb %cl, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sarw %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sarw %cl, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sarl %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sarl %cl, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sarq %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sarq %cl, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl $1, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl $1, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl $1, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl $1, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl $1, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl $1, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl $1, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl $1, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shlb $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shlb $1, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shlw $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shlw $1, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shll $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shll $1, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shlq $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shlq $1, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shlb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shlb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shlw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shlw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shll $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shll $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shlq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shlq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl %cl, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl %cl, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl %cl, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl %cl, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl %cl, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shlb %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shlb %cl, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shlw %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shlw %cl, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shll %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shll %cl, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shlq %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shlq %cl, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld $123, %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld $123, %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld $123, %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld $123, %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld $123, %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld $123, %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld $123, %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld $123, %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld $123, %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld %cl, %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld %cl, %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld %cl, %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld %cl, %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld %cl, %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld %cl, %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld %cl, %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld %cl, %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld %cl, %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr $1, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr $1, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr $1, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr $1, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr $1, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr $1, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr $1, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr $1, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrb $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrb $1, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrw $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrw $1, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrl $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrl $1, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrq $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrq $1, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr %cl, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr %cl, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr %cl, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr %cl, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr %cl, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrb %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrb %cl, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrw %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrw %cl, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrl %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrl %cl, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrq %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrq %cl, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd $123, %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd $123, %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd $123, %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd $123, %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd $123, %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd $123, %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd $123, %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd $123, %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd $123, %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd %cl, %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd %cl, %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd %cl, %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd %cl, %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd %cl, %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd %cl, %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd %cl, %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd %cl, %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd %cl, %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} subb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} subb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} subw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} subw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} subl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} subl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} subq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} subq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub %bl, %dl, %r8b #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub %bl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub %bl, 291(%r8, %rax, 4), %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub 291(%r8, %rax, 4), %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub 291(%r8, %rax, 4), %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} tzcnt %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} tzcnt %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} tzcnt %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} tzcnt 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} tzcnt 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} tzcnt 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xorb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xorb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xorw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xorw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xorl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xorl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xorq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xorq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor %bl, %dl, %r8b #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor %bl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor %bl, 291(%r8, %rax, 4), %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor 291(%r8, %rax, 4), %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor 291(%r8, %rax, 4), %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND + +.intel_syntax noprefix + {nf} add bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add r8b, dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add dl, BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add r9w, ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add ax, WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add dl, bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add ax, dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} add r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} add r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and r8b, dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and dl, BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and r9w, ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and ax, WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and dl, bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and ax, dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} and r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} and r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} andn r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} andn r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} andn edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} andn r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bextr r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bextr edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bextr r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bextr r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsi edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsi r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsi ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsi r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsmsk edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsmsk r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsmsk ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsmsk r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsr edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsr r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsr ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} blsr r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bzhi r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bzhi edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bzhi r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} bzhi r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} dec dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} dec ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} dec r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} dec BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} dec WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} dec DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} dec QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} dec r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} div bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} div dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} div ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} div r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} div BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} div WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} div DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} div QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idiv bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idiv dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idiv ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idiv r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idiv BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idiv WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idiv DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} idiv QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul ax, dx, 123 #APX_F OPC_EVEX_NF + {nf} imul edx, ecx, 123 #APX_F OPC_EVEX_NF + {nf} imul r31, r9, 123 #APX_F OPC_EVEX_NF + {nf} imul dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF + {nf} imul ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF + {nf} imul r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF + {nf} imul bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul r9w, ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} imul ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} imul r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} imul BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul ax, dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} imul DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} imul QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} imul r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} inc bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} inc dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} inc dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} inc ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} inc ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} inc edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} inc r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} inc r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} inc BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} inc bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} inc WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} inc dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} inc DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} inc ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} inc QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} inc r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} lzcnt ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} lzcnt edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} lzcnt r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} lzcnt dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} lzcnt ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} lzcnt r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mul bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mul dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mul ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mul r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mul BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mul WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mul DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} mul QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} neg dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} neg ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} neg r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} neg BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} neg WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} neg DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} neg QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} neg r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or r8b, dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or dl, BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or r9w, ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or ax, WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or dl, bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or ax, dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} or r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} or r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} popcnt ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} popcnt edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} popcnt r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} popcnt dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} popcnt ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} popcnt r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol dl, bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol ax, dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol edx, ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol r31, r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol bl, BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol dx, WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol ecx, DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol r9, QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol dl, bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol bl, BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol dx, WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol ecx, DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} rol QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} rol r9, QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror dl, bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror ax, dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror edx, ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror r31, r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror bl, BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror dx, WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror ecx, DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror r9, QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror dl, bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror bl, BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror dx, WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror ecx, DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} ror QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} ror r9, QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar dl, bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar ax, dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar edx, ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar r31, r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar bl, BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar dx, WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar ecx, DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar r9, QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar dl, bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar bl, BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar dx, WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar ecx, DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sar QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sar r9, QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl dl, bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl ax, dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl edx, ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl r31, r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl bl, BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl dx, WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl ecx, DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl r9, QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl dl, bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl bl, BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl dx, WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl ecx, DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shl QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shl r9, QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld r9w, ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld WORD PTR [r8+rax*4+291], dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld ax, WORD PTR [r8+rax*4+291], dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld r10d, edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld DWORD PTR [r8+rax*4+291], ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld edx, DWORD PTR [r8+rax*4+291], ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld r11, r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld QWORD PTR [r8+rax*4+291], r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld r31, QWORD PTR [r8+rax*4+291], r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld r9w, ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld WORD PTR [r8+rax*4+291], dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld ax, WORD PTR [r8+rax*4+291], dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld r10d, edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld DWORD PTR [r8+rax*4+291], ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld edx, DWORD PTR [r8+rax*4+291], ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld r11, r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shld QWORD PTR [r8+rax*4+291], r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shld r31, QWORD PTR [r8+rax*4+291], r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr dl, bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr ax, dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr edx, ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr r31, r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr bl, BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr dx, WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr ecx, DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr r9, QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr dl, bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr bl, BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr dx, WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr ecx, DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shr QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shr r9, QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd r9w, ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd WORD PTR [r8+rax*4+291], dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd ax, WORD PTR [r8+rax*4+291], dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd r10d, edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd DWORD PTR [r8+rax*4+291], ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd edx, DWORD PTR [r8+rax*4+291], ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd r11, r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd QWORD PTR [r8+rax*4+291], r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd r31, QWORD PTR [r8+rax*4+291], r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd r9w, ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd WORD PTR [r8+rax*4+291], dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd ax, WORD PTR [r8+rax*4+291], dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd r10d, edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd DWORD PTR [r8+rax*4+291], ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd edx, DWORD PTR [r8+rax*4+291], ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd r11, r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} shrd QWORD PTR [r8+rax*4+291], r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} shrd r31, QWORD PTR [r8+rax*4+291], r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub r8b, dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub dl, BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub r9w, ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub ax, WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub dl, bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub ax, dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} sub r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} sub r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} tzcnt ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} tzcnt edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} tzcnt r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} tzcnt dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} tzcnt ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} tzcnt r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor r8b, dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor dl, BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor r9w, ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor ax, WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor dl, bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor ax, dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND + {nf} xor r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX + {nf} xor r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 2d3a0387497..9aaa905393b 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -372,6 +372,8 @@ run_dump_test "x86-64-apx-evex-promoted" run_dump_test "x86-64-apx-evex-promoted-intel" run_dump_test "x86-64-apx-evex-egpr" run_dump_test "x86-64-apx-ndd" +run_dump_test "x86-64-apx-nf" +run_dump_test "x86-64-apx-nf-intel" run_dump_test "x86-64-avx512f-rcigrz-intel" run_dump_test "x86-64-avx512f-rcigrz" run_dump_test "x86-64-clwb" diff --git a/opcodes/i386-dis-evex-len.h b/opcodes/i386-dis-evex-len.h index 7c9b921bf6b..060ba3afb6c 100644 --- a/opcodes/i386-dis-evex-len.h +++ b/opcodes/i386-dis-evex-len.h @@ -64,7 +64,7 @@ static const struct dis386 evex_len_table[][3] = { /* EVEX_LEN_0F38F2 */ { - { "andnS", { Gdq, VexGdq, Edq }, 0 }, + { "%XNandnS", { Gdq, VexGdq, Edq }, 0 }, }, /* EVEX_LEN_0F38F3 */ diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h index f9d313a78e1..109b43334ad 100644 --- a/opcodes/i386-dis-evex-reg.h +++ b/opcodes/i386-dis-evex-reg.h @@ -52,41 +52,41 @@ /* REG_EVEX_0F38F3_L_0 */ { { Bad_Opcode }, - { "blsrS", { VexGdq, Edq }, 0 }, - { "blsmskS", { VexGdq, Edq }, 0 }, - { "blsiS", { VexGdq, Edq }, 0 }, + { "%XNblsrS", { VexGdq, Edq }, 0 }, + { "%XNblsmskS", { VexGdq, Edq }, 0 }, + { "%XNblsiS", { VexGdq, Edq }, 0 }, }, /* REG_EVEX_MAP4_80 */ { - { "addA", { VexGb, Eb, Ib }, 0 }, - { "orA", { VexGb, Eb, Ib }, 0 }, + { "%XNaddA", { VexGb, Eb, Ib }, 0 }, + { "%XNorA", { VexGb, Eb, Ib }, 0 }, { "adcA", { VexGb, Eb, Ib }, 0 }, { "sbbA", { VexGb, Eb, Ib }, 0 }, - { "andA", { VexGb, Eb, Ib }, 0 }, - { "subA", { VexGb, Eb, Ib }, 0 }, - { "xorA", { VexGb, Eb, Ib }, 0 }, + { "%XNandA", { VexGb, Eb, Ib }, 0 }, + { "%XNsubA", { VexGb, Eb, Ib }, 0 }, + { "%XNxorA", {VexGb, Eb, Ib }, 0 }, { Bad_Opcode }, }, /* REG_EVEX_MAP4_81 */ { - { "addQ", { VexGv, Ev, Iv }, 0 }, - { "orQ", { VexGv, Ev, Iv }, 0 }, + { "%XNaddQ", { VexGv, Ev, Iv }, 0 }, + { "%XNorQ", { VexGv, Ev, Iv }, 0 }, { "adcQ", { VexGv, Ev, Iv }, 0 }, { "sbbQ", { VexGv, Ev, Iv }, 0 }, - { "andQ", { VexGv, Ev, Iv }, 0 }, - { "subQ", { VexGv, Ev, Iv }, 0 }, - { "xorQ", { VexGv, Ev, Iv }, 0 }, + { "%XNandQ", { VexGv, Ev, Iv }, 0 }, + { "%XNsubQ", { VexGv, Ev, Iv }, 0 }, + { "%XNxorQ", { VexGv, Ev, Iv }, 0 }, { Bad_Opcode }, }, /* REG_EVEX_MAP4_83 */ { - { "addQ", { VexGv, Ev, sIb }, 0 }, - { "orQ", { VexGv, Ev, sIb }, 0 }, + { "%XNaddQ", { VexGv, Ev, sIb }, 0 }, + { "%XNorQ", { VexGv, Ev, sIb }, 0 }, { "adcQ", { VexGv, Ev, sIb }, 0 }, { "sbbQ", { VexGv, Ev, sIb }, 0 }, - { "andQ", { VexGv, Ev, sIb }, 0 }, - { "subQ", { VexGv, Ev, sIb }, 0 }, - { "xorQ", { VexGv, Ev, sIb }, 0 }, + { "%XNandQ", { VexGv, Ev, sIb }, 0 }, + { "%XNsubQ", { VexGv, Ev, sIb }, 0 }, + { "%XNxorQ", { VexGv, Ev, sIb }, 0 }, { Bad_Opcode }, }, /* REG_EVEX_MAP4_8F_X86_64_L_0_M_1 */ @@ -95,69 +95,69 @@ }, /* REG_EVEX_MAP4_C0 */ { - { "rolA", { VexGb, Eb, Ib }, 0 }, - { "rorA", { VexGb, Eb, Ib }, 0 }, + { "%XNrolA", { VexGb, Eb, Ib }, 0 }, + { "%XNrorA", { VexGb, Eb, Ib }, 0 }, { "rclA", { VexGb, Eb, Ib }, 0 }, { "rcrA", { VexGb, Eb, Ib }, 0 }, - { "shlA", { VexGb, Eb, Ib }, 0 }, - { "shrA", { VexGb, Eb, Ib }, 0 }, - { "shlA", { VexGb, Eb, Ib }, 0 }, - { "sarA", { VexGb, Eb, Ib }, 0 }, + { "%XNshlA", { VexGb, Eb, Ib }, 0 }, + { "%XNshrA", { VexGb, Eb, Ib }, 0 }, + { "%XNshlA", { VexGb, Eb, Ib }, 0 }, + { "%XNsarA", { VexGb, Eb, Ib }, 0 }, }, /* REG_EVEX_MAP4_C1 */ { - { "rolQ", { VexGv, Ev, Ib }, 0 }, - { "rorQ", { VexGv, Ev, Ib }, 0 }, + { "%XNrolQ", { VexGv, Ev, Ib }, 0 }, + { "%XNrorQ", { VexGv, Ev, Ib }, 0 }, { "rclQ", { VexGv, Ev, Ib }, 0 }, { "rcrQ", { VexGv, Ev, Ib }, 0 }, - { "shlQ", { VexGv, Ev, Ib }, 0 }, - { "shrQ", { VexGv, Ev, Ib }, 0 }, - { "shlQ", { VexGv, Ev, Ib }, 0 }, - { "sarQ", { VexGv, Ev, Ib }, 0 }, + { "%XNshlQ", { VexGv, Ev, Ib }, 0 }, + { "%XNshrQ", { VexGv, Ev, Ib }, 0 }, + { "%XNshlQ", { VexGv, Ev, Ib }, 0 }, + { "%XNsarQ", { VexGv, Ev, Ib }, 0 }, }, /* REG_EVEX_MAP4_D0 */ { - { "rolA", { VexGb, Eb, I1 }, 0 }, - { "rorA", { VexGb, Eb, I1 }, 0 }, + { "%XNrolA", { VexGb, Eb, I1 }, 0 }, + { "%XNrorA", { VexGb, Eb, I1 }, 0 }, { "rclA", { VexGb, Eb, I1 }, 0 }, { "rcrA", { VexGb, Eb, I1 }, 0 }, - { "shlA", { VexGb, Eb, I1 }, 0 }, - { "shrA", { VexGb, Eb, I1 }, 0 }, - { "shlA", { VexGb, Eb, I1 }, 0 }, - { "sarA", { VexGb, Eb, I1 }, 0 }, + { "%XNshlA", { VexGb, Eb, I1 }, 0 }, + { "%XNshrA", { VexGb, Eb, I1 }, 0 }, + { "%XNshlA", { VexGb, Eb, I1 }, 0 }, + { "%XNsarA", { VexGb, Eb, I1 }, 0 }, }, /* REG_EVEX_MAP4_D1 */ { - { "rolQ", { VexGv, Ev, I1 }, 0 }, - { "rorQ", { VexGv, Ev, I1 }, 0 }, + { "%XNrolQ", { VexGv, Ev, I1 }, 0 }, + { "%XNrorQ", { VexGv, Ev, I1 }, 0 }, { "rclQ", { VexGv, Ev, I1 }, 0 }, { "rcrQ", { VexGv, Ev, I1 }, 0 }, - { "shlQ", { VexGv, Ev, I1 }, 0 }, - { "shrQ", { VexGv, Ev, I1 }, 0 }, - { "shlQ", { VexGv, Ev, I1 }, 0 }, - { "sarQ", { VexGv, Ev, I1 }, 0 }, + { "%XNshlQ", { VexGv, Ev, I1 }, 0 }, + { "%XNshrQ", { VexGv, Ev, I1 }, 0 }, + { "%XNshlQ", { VexGv, Ev, I1 }, 0 }, + { "%XNsarQ", { VexGv, Ev, I1 }, 0 }, }, /* REG_EVEX_MAP4_D2 */ { - { "rolA", { VexGb, Eb, CL }, 0 }, - { "rorA", { VexGb, Eb, CL }, 0 }, + { "%XNrolA", { VexGb, Eb, CL }, 0 }, + { "%XNrorA", { VexGb, Eb, CL }, 0 }, { "rclA", { VexGb, Eb, CL }, 0 }, { "rcrA", { VexGb, Eb, CL }, 0 }, - { "shlA", { VexGb, Eb, CL }, 0 }, - { "shrA", { VexGb, Eb, CL }, 0 }, - { "shlA", { VexGb, Eb, CL }, 0 }, - { "sarA", { VexGb, Eb, CL }, 0 }, + { "%XNshlA", { VexGb, Eb, CL }, 0 }, + { "%XNshrA", { VexGb, Eb, CL }, 0 }, + { "%XNshlA", { VexGb, Eb, CL }, 0 }, + { "%XNsarA", { VexGb, Eb, CL }, 0 }, }, /* REG_EVEX_MAP4_D3 */ { - { "rolQ", { VexGv, Ev, CL }, 0 }, - { "rorQ", { VexGv, Ev, CL }, 0 }, + { "%XNrolQ", { VexGv, Ev, CL }, 0 }, + { "%XNrorQ", { VexGv, Ev, CL }, 0 }, { "rclQ", { VexGv, Ev, CL }, 0 }, { "rcrQ", { VexGv, Ev, CL }, 0 }, - { "shlQ", { VexGv, Ev, CL }, 0 }, - { "shrQ", { VexGv, Ev, CL }, 0 }, - { "shlQ", { VexGv, Ev, CL }, 0 }, - { "sarQ", { VexGv, Ev, CL }, 0 }, + { "%XNshlQ", { VexGv, Ev, CL }, 0 }, + { "%XNshrQ", { VexGv, Ev, CL }, 0 }, + { "%XNshlQ", { VexGv, Ev, CL }, 0 }, + { "%XNsarQ", { VexGv, Ev, CL }, 0 }, }, /* REG_EVEX_MAP4_D8_PREFIX_1 */ { @@ -170,25 +170,34 @@ { { Bad_Opcode }, { Bad_Opcode }, - { "notA", { VexGb, Eb }, 0 }, - { "negA", { VexGb, Eb }, 0 }, + { "%XNnotA", { VexGb, Eb }, 0 }, + { "%XNnegA", { VexGb, Eb }, 0 }, + { "%XNmulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ + { "%XNimulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ + { "%XNdivA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ + { "%XNidivA", { Eb }, 0 }, /* and idiv for consistency. */ + }, /* REG_EVEX_MAP4_F7 */ { { Bad_Opcode }, { Bad_Opcode }, - { "notQ", { VexGv, Ev }, 0 }, - { "negQ", { VexGv, Ev }, 0 }, + { "%XNnotQ", { VexGv, Ev }, 0 }, + { "%XNnegQ", { VexGv, Ev }, 0 }, + { "%XNmulQ", { Ev }, 0 }, /* Don't print the implicit %al register, */ + { "%XNimulQ", { Ev }, 0 }, /* to distinguish these opcodes from other */ + { "%XNdivQ", { Ev }, 0 }, /* mul/imul opcodes. Do the same for div */ + { "%XNidivQ", { Ev }, 0 }, /* and idiv for consistency. */ }, /* REG_EVEX_MAP4_FE */ { - { "incA", { VexGb ,Eb }, 0 }, - { "decA", { VexGb ,Eb }, 0 }, + { "%XNincA", { VexGb ,Eb }, 0 }, + { "%XNdecA", { VexGb ,Eb }, 0 }, }, /* REG_EVEX_MAP4_FF */ { - { "incQ", { VexGv ,Ev }, 0 }, - { "decQ", { VexGv ,Ev }, 0 }, + { "%XNincQ", { VexGv ,Ev }, 0 }, + { "%XNdecQ", { VexGv ,Ev }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index 22fa9b2b067..0f196155054 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -875,19 +875,19 @@ static const struct dis386 evex_table[][256] = { /* EVEX_MAP4_ */ { /* 00 */ - { "addB", { VexGb, Eb, Gb }, 0 }, - { "addS", { VexGv, Ev, Gv }, 0 }, - { "addB", { VexGb, Gb, EbS }, 0 }, - { "addS", { VexGv, Gv, EvS }, 0 }, + { "%XNaddB", { VexGb, Eb, Gb }, 0 }, + { "%XNaddS", { VexGv, Ev, Gv }, 0 }, + { "%XNaddB", { VexGb, Gb, EbS }, 0 }, + { "%XNaddS", { VexGv, Gv, EvS }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 08 */ - { "orB", { VexGb, Eb, Gb }, 0 }, - { "orS", { VexGv, Ev, Gv }, 0 }, - { "orB", { VexGb, Gb, EbS }, 0 }, - { "orS", { VexGv, Gv, EvS }, 0 }, + { "%XNorB", { VexGb, Eb, Gb }, 0 }, + { "%XNorS", { VexGv, Ev, Gv }, 0 }, + { "%XNorB", { VexGb, Gb, EbS }, 0 }, + { "%XNorS", { VexGv, Gv, EvS }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -911,28 +911,28 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 20 */ - { "andB", { VexGb, Eb, Gb }, 0 }, - { "andS", { VexGv, Ev, Gv }, 0 }, - { "andB", { VexGb, Gb, EbS }, 0 }, - { "andS", { VexGv, Gv, EvS }, 0 }, - { "shldS", { VexGv, Ev, Gv, Ib }, 0 }, + { "%XNandB", { VexGb, Eb, Gb }, 0 }, + { "%XNandS", { VexGv, Ev, Gv }, 0 }, + { "%XNandB", { VexGb, Gb, EbS }, 0 }, + { "%XNandS", { VexGv, Gv, EvS }, 0 }, + { "%XNshldS", { VexGv, Ev, Gv, Ib }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 28 */ - { "subB", { VexGb, Eb, Gb }, 0 }, - { "subS", { VexGv, Ev, Gv }, 0 }, - { "subB", { VexGb, Gb, EbS }, 0 }, - { "subS", { VexGv, Gv, EvS }, 0 }, - { "shrdS", { VexGv, Ev, Gv, Ib }, 0 }, + { "%XNsubB", { VexGb, Eb, Gb }, 0 }, + { "%XNsubS", { VexGv, Ev, Gv }, 0 }, + { "%XNsubB", { VexGb, Gb, EbS }, 0 }, + { "%XNsubS", { VexGv, Gv, EvS }, 0 }, + { "%XNshrdS", { VexGv, Ev, Gv, Ib }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 30 */ - { "xorB", { VexGb, Eb, Gb }, 0 }, - { "xorS", { VexGv, Ev, Gv }, 0 }, - { "xorB", { VexGb, Gb, EbS }, 0 }, - { "xorS", { VexGv, Gv, EvS }, 0 }, + { "%XNxorB", { VexGb, Eb, Gb }, 0 }, + { "%XNxorS", { VexGv, Ev, Gv }, 0 }, + { "%XNxorB", { VexGb, Gb, EbS }, 0 }, + { "%XNxorS", { VexGv, Gv, EvS }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -993,9 +993,9 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, /* 68 */ { Bad_Opcode }, + { "%XNimulS", { VexGv, Ev, Iv }, 0 }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "%XNimulS", { VexGv, Ev, sIb }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -1028,7 +1028,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 88 */ - { Bad_Opcode }, + { "%XNpopcntS", { Gv, Ev }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -1060,7 +1060,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "shldS", { VexGv, Ev, Gv, CL }, 0 }, + { "%XNshldS", { VexGv, Ev, Gv, CL }, 0 }, { Bad_Opcode }, { Bad_Opcode }, /* A8 */ @@ -1069,9 +1069,9 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "shrdS", { VexGv, Ev, Gv, CL }, 0 }, + { "%XNshrdS", { VexGv, Ev, Gv, CL }, 0 }, { Bad_Opcode }, - { "imulS", { VexGv, Gv, Ev }, 0 }, + { "%XNimulS", { VexGv, Gv, Ev }, 0 }, /* B0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1149,8 +1149,8 @@ static const struct dis386 evex_table[][256] = { { PREFIX_TABLE (PREFIX_EVEX_MAP4_F1) }, { PREFIX_TABLE (PREFIX_EVEX_MAP4_F2) }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "%XNtzcntS", { Gv, Ev }, 0 }, + { "%XNlzcntS", { Gv, Ev }, 0 }, { REG_TABLE (REG_EVEX_MAP4_F6) }, { REG_TABLE (REG_EVEX_MAP4_F7) }, /* F8 */ diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 4671d2e4b0e..b3ede02df06 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -224,6 +224,7 @@ struct instr_info bool zeroing; bool b; bool no_broadcast; + bool nf; } vex; @@ -1851,6 +1852,8 @@ struct dis386 { "XV" => print "{vex} " pseudo prefix "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is is used by an EVEX-encoded (AVX512VL) instruction. + "XN" => print "{nf} " pseudo prefix when EVEX.NF = 1. + a valid encoding. "YK" keep unused, to avoid ambiguity with the combined use of Y and K. "YX" keep unused, to avoid ambiguity with the combined use of Y and X. "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond @@ -4119,7 +4122,7 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F38F5_L_0 */ { - { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, + { "%XNbzhiS", { Gdq, Edq, VexGdq }, 0 }, { "pextS", { Gdq, VexGdq, Edq }, 0 }, { Bad_Opcode }, { "pdepS", { Gdq, VexGdq, Edq }, 0 }, @@ -4135,7 +4138,7 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F38F7_L_0 */ { - { "bextrS", { Gdq, Edq, VexGdq }, 0 }, + { "%XNbextrS", { Gdq, Edq, VexGdq }, 0 }, { "sarxS", { Gdq, Edq, VexGdq }, 0 }, { "shlxS", { Gdq, Edq, VexGdq }, 0 }, { "shrxS", { Gdq, Edq, VexGdq }, 0 }, @@ -9111,6 +9114,10 @@ use_x86_64_table: ins->vex.v = *ins->codep & 0x8; ins->vex.mask_register_specifier = *ins->codep & 0x7; ins->vex.zeroing = *ins->codep & 0x80; + /* Set the NF bit for the EVEX instruction extended from the legacy or + vex instruction, this bit will be cleared when it can be confirmed + that its defaut type is evex. */ + ins->vex.nf = *ins->codep & 0x4; if (ins->address_mode != mode_64bit) { @@ -9550,6 +9557,11 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) && ins.vex.prefix == DATA_PREFIX_OPCODE) sizeflag ^= DFLAG; + if(ins.evex_type == evex_default) + ins.vex.nf = false; + else + ins.vex.mask_register_specifier = 0; + if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0) { if (!get_sib (&ins, sizeflag)) @@ -10553,11 +10565,36 @@ putop (instr_info *ins, const char *in_template, int sizeflag) *ins->obufp++ = 'r'; break; case 'N': - if ((ins->prefixes & PREFIX_FWAIT) == 0) - *ins->obufp++ = 'n'; + if (l == 1 && last[0] == 'X') + { + if (ins->vex.nf == true) + { + *ins->obufp++ = '{'; + *ins->obufp++ = 'n'; + *ins->obufp++ = 'f'; + *ins->obufp++ = '}'; + *ins->obufp++ = ' '; + } + else if (ins->evex_type == evex_from_legacy && !ins->vex.b) + { + *ins->obufp++ = '{'; + *ins->obufp++ = 'e'; + *ins->obufp++ = 'v'; + *ins->obufp++ = 'e'; + *ins->obufp++ = 'x'; + *ins->obufp++ = '}'; + *ins->obufp++ = ' '; + } + break; + } else - ins->used_prefixes |= PREFIX_FWAIT; - break; + { + if ((ins->prefixes & PREFIX_FWAIT) == 0) + *ins->obufp++ = 'n'; + else + ins->used_prefixes |= PREFIX_FWAIT; + break; + } case 'O': USED_REX (REX_W); if (ins->rex & REX_W) diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index f951c452cc3..a472fba6254 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -472,6 +472,7 @@ static bitfield opcode_modifiers[] = BITFIELD (ISA64), BITFIELD (No_egpr), BITFIELD (Push2Pop2), + BITFIELD (NF), }; #define CLASS(n) #n, n diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 1663cc74937..05f69d4a584 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -752,6 +752,9 @@ enum /* APX Push2Pop2 bit */ Push2Pop2, + /* No CSPAZO flags update indication. */ + NF, + /* The last bitfield in i386_opcode_modifier. */ Opcode_Modifier_Num }; @@ -801,6 +804,7 @@ typedef struct i386_opcode_modifier unsigned int isa64:2; unsigned int no_egpr:1; unsigned int push2pop2:1; + unsigned int nf:1; } i386_opcode_modifier; /* Operand classes. */ @@ -1003,7 +1007,7 @@ typedef struct insn_template AMD 3DNow! instructions. If this template has no extension opcode (the usual case) use None Instructions */ - signed int extension_opcode:0xA; + signed int extension_opcode:0xB; #define None (-1) /* If no extension_opcode is possible. */ /* Pseudo prefixes. */ @@ -1017,7 +1021,8 @@ typedef struct insn_template #define Prefix_EVEX 7 /* {evex} */ #define Prefix_REX 8 /* {rex} */ #define Prefix_REX2 9 /* {rex2} */ -#define Prefix_NoOptimize 0xA /* {nooptimize} */ +#define Prefix_NF 0xA /* {nf} */ +#define Prefix_NoOptimize 0xB /* {nooptimize} */ /* the bits in opcode_modifier are used to generate the final opcode from the base_opcode. These bits also are used to detect alternate forms of diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 583b6676b0e..4e8ef15c28b 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -286,25 +286,41 @@ add, 0x0, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg3 add, 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } add, 0x80/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -add, 0x0, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -add, 0x83/0, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -add, 0x80/0, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64} + +add, 0x0, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +add, 0x83/0, APX_F|x64, Modrm|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +add, 0x80/0, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +add, 0x0, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +add, 0x83/0, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +add, 0x80/0, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64} inc, 0x40, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -inc, 0xfe/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, {Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64} + +inc, 0xfe/0, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +inc, 0xfe/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, {Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64} sub, 0x28, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sub, 0x83/5, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } sub, 0x2c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } sub, 0x80/5, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -sub, 0x28, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64, } -sub, 0x83/5, APX_F|x64, Modrm|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -sub, 0x80/5, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } + +sub, 0x28, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|Optimize|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sub, 0x83/5, APX_F|x64, Modrm|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +sub, 0x80/5, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +sub, 0x28, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64, } +sub, 0x83/5, APX_F|x64, Modrm|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +sub, 0x80/5, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } dec, 0x48, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 } dec, 0xfe/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -dec, 0xfe/1, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } + +dec, 0xfe/1, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +dec, 0xfe/1, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } sbb, 0x18, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sbb, 0x83/3, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } @@ -330,25 +346,40 @@ and, 0x20, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8| and, 0x83/4, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } and, 0x24, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } and, 0x80/4, 0, W|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -and, 0x20, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -and, 0x83/4, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -and, 0x80/4, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } + +and, 0x20, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|Optimize|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +and, 0x83/4, APX_F|x64, Modrm|No_bSuf|No_sSuf|Optimize|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +and, 0x80/4, APX_F|x64, W|Modrm|No_sSuf|Optimize|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +and, 0x20, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +and, 0x83/4, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +and, 0x80/4, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } or, 0x8, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } or, 0x83/1, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } or, 0xc, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } or, 0x80/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -or, 0x8, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -or, 0x83/1, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -or, 0x80/1, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } + +or, 0x8, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|Optimize|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +or, 0x83/1, APX_F|x64, Modrm|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +or, 0x80/1, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +or, 0x8, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +or, 0x83/1, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +or, 0x80/1, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } xor, 0x30, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } xor, 0x83/6, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } xor, 0x34, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } xor, 0x80/6, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -xor, 0x30, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -xor, 0x83/6, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -xor, 0x80/6, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } + +xor, 0x30, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|EVex128|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +xor, 0x83/6, APX_F|x64, Modrm|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +xor, 0x80/6, 0, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +xor, 0x30, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +xor, 0x83/6, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +xor, 0x80/6, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } // clr with 1 operand is really xor with 2 operands. clr, 0x30, 0, W|Modrm|No_sSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 } @@ -365,7 +396,8 @@ adc, 0x83/2, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|E adc, 0x80/2, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } neg, 0xf6/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -neg, 0xf6/3, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +neg, 0xf6/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +neg, 0xf6/3, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } not, 0xf6/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } not, 0xf6/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } @@ -401,11 +433,21 @@ cqto, 0x99, x64, Size64|NoSuf, {} // 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) // These multiplies can only be selected with single operand forms. mul, 0xf6/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +mul, 0xf6/4, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + imul, 0xf6/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } imul, 0xfaf, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 } -imul, 0xaf, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } imul, 0x6b, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } imul, 0x69, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + +imul, 0xf6/5, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +imul, 0xaf, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 } + +imul, 0xaf, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } + +imul, 0x6b, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +imul, 0x69, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // imul with 2 operands mimics imul with 3 by putting the register in // both i.rm.reg & i.rm.regmem fields. RegKludge enables this // transformation. @@ -416,24 +458,38 @@ div, 0xf6/6, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword| div, 0xf6/6, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } idiv, 0xf6/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } idiv, 0xf6/7, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } +div, 0xf6/6, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +idiv, 0xf6/7, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -rol, 0xc0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -rol, 0xd2/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } + +rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rol, 0xc0/0, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rol, 0xd2/0, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +rol, 0xc0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +rol, 0xd2/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ror, 0xc0/1, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -ror, 0xc0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -ror, 0xd2/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } + +ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +ror, 0xc0/1, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +ror, 0xd2/1, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +ror, 0xc0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +ror, 0xd2/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcl, 0xc0/2, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } @@ -474,42 +530,70 @@ shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword| shl, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shl, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -shl, 0xc0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -shl, 0xd2/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } + +shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shl, 0xc0/4, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shl, 0xd2/4, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +shl, 0xc0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +shl, 0xd2/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shr, 0xc0/5, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shr, 0xd2/5, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -shr, 0xc0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -shr, 0xd2/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } + +shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shr, 0xc0/5, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shr, 0xd2/5, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +shr, 0xc0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +shr, 0xd2/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sar, 0xc0/7, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sar, 0xd2/7, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -sar, 0xc0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -sar, 0xd2/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } -sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } + +sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sar, 0xc0/7, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sar, 0xd2/7, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + +sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +sar, 0xc0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +sar, 0xd2/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } shld, 0xfa4, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } shld, 0xfa5, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } shld, 0xfa5, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -shld, 0x24, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + +shld, 0x24, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } + +shld, 0x24, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } shrd, 0xfac, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } shrd, 0xfad, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } shrd, 0xfad, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -shrd, 0x2c, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } -shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } + +shrd, 0x2c, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } + +shrd, 0x2c, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // Control transfer instructions. call, 0xe8, No64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 } @@ -971,7 +1055,8 @@ rex.wrxb, 0x4f, x64, NoSuf|IsPrefix, {} + rex:REX:x64, rex2:REX2:x64, nf:NF:x64, + + nooptimize:NoOptimize:0> {}, PSEUDO_PREFIX/Prefix_, , NoSuf|IsPrefix, {} @@ -1910,7 +1995,7 @@ xtest, 0xf01d6, HLE|RTM, NoSuf, {} // BMI2 instructions. bzhi, 0xf5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } -bzhi, 0xf5, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +bzhi, 0xf5, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|NF|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } mulx, 0xf2f6, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } mulx, 0xf2f6, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } pdep, 0xf2f5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } @@ -1995,16 +2080,17 @@ lwpins, 0x12/0, LWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV|Vex, { Imm32|Imm32S, Reg32|U // BMI instructions andn, 0xf2, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } -andn, 0xf2, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +andn, 0xf2, BMI|APX_F, Modrm|CheckOperandSize|EVex128|NF|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } bextr, 0xf7, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } -bextr, 0xf7, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +bextr, 0xf7, BMI|APX_F, Modrm|CheckOperandSize|EVex128|NF|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } blsi, 0xf3/3, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } -blsi, 0xf3/3, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +blsi, 0xf3/3, BMI|APX_F, Modrm|CheckOperandSize|EVex128|NF|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } blsmsk, 0xf3/2, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } -blsmsk, 0xf3/2, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +blsmsk, 0xf3/2, BMI|APX_F, Modrm|CheckOperandSize|EVex128|NF|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } blsr, 0xf3/1, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } -blsr, 0xf3/1, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +blsr, 0xf3/1, BMI|APX_F, Modrm|CheckOperandSize|EVex128|NF|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } tzcnt, 0xf30fbc, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +tzcnt, 0xf4, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // TBM instructions @@ -2082,9 +2168,11 @@ insertq, 0xf20f78, SSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM, RegXMM } // LZCNT instruction lzcnt, 0xf30fbd, LZCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +lzcnt, 0xf5, LZCNT|APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // POPCNT instruction popcnt, 0xf30fb8, POPCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +popcnt, 0x88, POPCNT|APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // VIA PadLock extensions. xstore-rng, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {} From patchwork Tue Sep 19 15:25:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Frager, Neal via Binutils" X-Patchwork-Id: 76390 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AB94B3853D3B for ; Tue, 19 Sep 2023 15:28:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AB94B3853D3B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1695137335; bh=vTD6Iq8S+tiN9aYAHpQjhNGmb2lo9f0nzEbdxbgqFFY=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=qFPo7gxnMBVQN2+IKytxJwjJ9HY2e2RGeoh4XcmCXsLbJaxEK7ALm6i/ol+P3pg5k buPGyS11gspd8nxJBNagkTi3FYR2A2vicRNmGaSauxWNeM0yDrpF7aK4N5i7gY+ZBP mYgVLL0b1ocwPqLqa5cZiQroaRl92GG9nKjxm2fM= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id A7E643857B9B for ; Tue, 19 Sep 2023 15:25:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A7E643857B9B X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="377286256" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="377286256" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 08:25:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="695950288" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="695950288" Received: from scymds03.sc.intel.com ([10.148.94.166]) by orsmga003.jf.intel.com with ESMTP; 19 Sep 2023 08:25:42 -0700 Received: from shgcc101.sh.intel.com (shgcc101.sh.intel.com [10.239.85.97]) by scymds03.sc.intel.com (Postfix) with ESMTP id ED3D46A; Tue, 19 Sep 2023 08:25:40 -0700 (PDT) To: binutils@sourceware.org Cc: jbeulich@suse.com, hongjiu.lu@intel.com, "Hu, Lin1" Subject: [PATCH 8/8] Support APX JMPABS Date: Tue, 19 Sep 2023 15:25:27 +0000 Message-Id: <20230919152527.497773-9-lili.cui@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230919152527.497773-1-lili.cui@intel.com> References: <20230919152527.497773-1-lili.cui@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Cui, Lili via Binutils" From: "Frager, Neal via Binutils" Reply-To: "Cui, Lili" Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" From: "Hu, Lin1" gas/ChangeLog: * config/tc-i386.c (is_any_apx_encoding): Add jmpabs. (is_any_apx_rex2_encoding): Ditto. * testsuite/gas/i386/i386.exp: Add tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/apx-jmpabs-inval.l: New test. * testsuite/gas/i386/apx-jmpabs-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-mov-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-mov-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs.s: Ditto. opcodes/ChangeLog: * i386-dis.c (JMPABS_Fixup): New Fixup function to disassemble jmpabs. (print_insn): Add #UD exception for jmpabs. (dis386): Modify a1 unit for support jmpabs. * i386-mnem.h: Regenerated. * i386-opc.tbl: New insns. * i386-tbl.h: Regenerated. --- gas/config/tc-i386.c | 6 +- gas/testsuite/gas/i386/apx-jmpabs-inval.l | 3 + gas/testsuite/gas/i386/apx-jmpabs-inval.s | 6 ++ gas/testsuite/gas/i386/apx-mov-inval.l | 2 + gas/testsuite/gas/i386/i386.exp | 1 + .../gas/i386/x86-64-apx-jmpabs-intel.d | 14 +++++ .../gas/i386/x86-64-apx-jmpabs-inval.d | 55 +++++++++++++++++++ .../gas/i386/x86-64-apx-jmpabs-inval.s | 18 ++++++ gas/testsuite/gas/i386/x86-64-apx-jmpabs.d | 14 +++++ gas/testsuite/gas/i386/x86-64-apx-jmpabs.s | 10 ++++ gas/testsuite/gas/i386/x86-64-apx-mov-inval.l | 2 + gas/testsuite/gas/i386/x86-64-apx-mov-inval.s | 5 ++ gas/testsuite/gas/i386/x86-64.exp | 4 ++ opcodes/i386-dis.c | 42 +++++++++++++- opcodes/i386-opc.tbl | 4 +- 15 files changed, 182 insertions(+), 4 deletions(-) create mode 100644 gas/testsuite/gas/i386/apx-jmpabs-inval.l create mode 100644 gas/testsuite/gas/i386/apx-jmpabs-inval.s create mode 100644 gas/testsuite/gas/i386/apx-mov-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-apx-jmpabs-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-jmpabs-inval.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-jmpabs-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-jmpabs.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-jmpabs.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-mov-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-apx-mov-inval.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 1fe4980f26a..36720d40eb0 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -3880,6 +3880,7 @@ is_any_apx_encoding (void) || i.tm.opcode_space == SPACE_EVEXMAP4 || i.has_nf || i.has_zero_upper + || i.tm.mnem_off == MN_jmpabs || (i.vex.register_specifier && i.vex.register_specifier->reg_flags & RegRex2); } @@ -3887,7 +3888,8 @@ is_any_apx_encoding (void) static INLINE bool is_any_apx_rex2_encoding (void) { - return (i.rex2 && i.vex.length == 2) || i.rex2_encoding; + return (i.rex2 && i.vex.length == 2) || i.rex2_encoding + || i.tm.mnem_off == MN_jmpabs; } static INLINE bool @@ -7703,7 +7705,7 @@ match_template (char mnem_suffix) if (!quiet_warnings) { if (!intel_syntax - && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) + && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE) && t->mnem_off != MN_jmpabs)) as_warn (_("indirect %s without `*'"), insn_name (t)); if (t->opcode_modifier.isprefix diff --git a/gas/testsuite/gas/i386/apx-jmpabs-inval.l b/gas/testsuite/gas/i386/apx-jmpabs-inval.l new file mode 100644 index 00000000000..87e7a800f1a --- /dev/null +++ b/gas/testsuite/gas/i386/apx-jmpabs-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:5: Error: `jmpabs' is only supported in 64-bit mode +.*:6: Error: `jmpabs' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/apx-jmpabs-inval.s b/gas/testsuite/gas/i386/apx-jmpabs-inval.s new file mode 100644 index 00000000000..1f9f1f80b72 --- /dev/null +++ b/gas/testsuite/gas/i386/apx-jmpabs-inval.s @@ -0,0 +1,6 @@ +# Check 32bit illegal APX_F JMPABS instructions + + .text + _start: + jmpabs $0x0202020202020202 + jmpabs $0x2 diff --git a/gas/testsuite/gas/i386/apx-mov-inval.l b/gas/testsuite/gas/i386/apx-mov-inval.l new file mode 100644 index 00000000000..b1aa91ae3c9 --- /dev/null +++ b/gas/testsuite/gas/i386/apx-mov-inval.l @@ -0,0 +1,2 @@ +.* Assembler messages: +.*:5: Error: unsupport rex2 pseudo prefix for `mov' diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 7e0ad339141..d842505a928 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -508,6 +508,7 @@ if [gas_32_check] then { run_dump_test "sm4-intel" run_list_test "pbndkb-inval" run_list_test "apx-push2pop2-inval" + run_list_test "apx-jmpabs-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/x86-64-apx-jmpabs-intel.d b/gas/testsuite/gas/i386/x86-64-apx-jmpabs-intel.d new file mode 100644 index 00000000000..d8407bdd92b --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-jmpabs-intel.d @@ -0,0 +1,14 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 APX_F JMPABS insns (Intel disassembly) +#source: x86-64-apx-jmpabs.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*d5 00 a1 02 02 02 02 02 02 02 02\s+jmpabs 0x202020202020202 +\s*[a-f0-9]+:\s*d5 00 a1 02 00 00 00 00 00 00 00\s+jmpabs 0x2 +\s*[a-f0-9]+:\s*d5 00 a1 02 02 02 02 02 02 02 02\s+jmpabs 0x202020202020202 +\s*[a-f0-9]+:\s*d5 00 a1 02 00 00 00 00 00 00 00\s+jmpabs 0x2 diff --git a/gas/testsuite/gas/i386/x86-64-apx-jmpabs-inval.d b/gas/testsuite/gas/i386/x86-64-apx-jmpabs-inval.d new file mode 100644 index 00000000000..5c887acfebc --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-jmpabs-inval.d @@ -0,0 +1,55 @@ +#as: --64 +#objdump: -dw +#name: illegal decoding of APX_F jmpabs insns +#source: x86-64-apx-jmpabs-inval.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <.text>: +\s*[a-f0-9]+: 66 64 d5 00 a1\s+\(bad\) +\s*[a-f0-9]+: 01 00\s+add %eax,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 66 d5 00 a1\s+\(bad\) +\s*[a-f0-9]+: 01 00\s+add %eax,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 67 64 d5 00 a1\s+\(bad\) +\s*[a-f0-9]+: 01 00\s+add %eax,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 67 d5 00 a1\s+\(bad\) +\s*[a-f0-9]+: 01 00\s+add %eax,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: f2 64 d5 00 a1\s+\(bad\) +\s*[a-f0-9]+: 01 00\s+add %eax,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: f2 d5 00 a1\s+\(bad\) +\s*[a-f0-9]+: 01 00\s+add %eax,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: f3 64 d5 00 a1\s+\(bad\) +\s*[a-f0-9]+: 01 00\s+add %eax,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: f3 d5 00 a1\s+\(bad\) +\s*[a-f0-9]+: 01 00\s+add %eax,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: d5 08 a1\s+\(bad\) +\s*[a-f0-9]+: 01 00\s+add %eax,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*[a-f0-9]+: 00 00\s+add %al,\(%rax\) +\s*... diff --git a/gas/testsuite/gas/i386/x86-64-apx-jmpabs-inval.s b/gas/testsuite/gas/i386/x86-64-apx-jmpabs-inval.s new file mode 100644 index 00000000000..3642d430546 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-jmpabs-inval.s @@ -0,0 +1,18 @@ +# Check bytecode of APX_F jmpabs instructions with illegal encode. + + .allow_index_reg + .text +# With 66 prefix + .byte 0x66,0x64,0xd5,0x00,0xa1,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x66,0xd5,0x00,0xa1,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +# With 67 prefix + .byte 0x67,0x64,0xd5,0x00,0xa1,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x67,0xd5,0x00,0xa1,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +# With F2 prefix + .byte 0xf2,0x64,0xd5,0x00,0xa1,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0xf2,0xd5,0x00,0xa1,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +# With F3 prefix + .byte 0xf3,0x64,0xd5,0x00,0xa1,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0xf3,0xd5,0x00,0xa1,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +# REX2.M0 = 0 REX2.W = 1 + .byte 0xd5,0x08,0xa1,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 diff --git a/gas/testsuite/gas/i386/x86-64-apx-jmpabs.d b/gas/testsuite/gas/i386/x86-64-apx-jmpabs.d new file mode 100644 index 00000000000..409943dd9b9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-jmpabs.d @@ -0,0 +1,14 @@ +#as: +#objdump: -dw +#name: x86_64 APX_F JMPABS insns +#source: x86-64-apx-jmpabs.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*d5 00 a1 02 02 02 02 02 02 02 02\s+jmpabs \$0x202020202020202 +\s*[a-f0-9]+:\s*d5 00 a1 02 00 00 00 00 00 00 00\s+jmpabs \$0x2 +\s*[a-f0-9]+:\s*d5 00 a1 02 02 02 02 02 02 02 02\s+jmpabs \$0x202020202020202 +\s*[a-f0-9]+:\s*d5 00 a1 02 00 00 00 00 00 00 00\s+jmpabs \$0x2 diff --git a/gas/testsuite/gas/i386/x86-64-apx-jmpabs.s b/gas/testsuite/gas/i386/x86-64-apx-jmpabs.s new file mode 100644 index 00000000000..beb722421bd --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-jmpabs.s @@ -0,0 +1,10 @@ +# Check 64bit APX_F JMPABS instructions + + .text + _start: + jmpabs $0x0202020202020202 + jmpabs $0x2 + +.intel_syntax noprefix + jmpabs 0x0202020202020202 + jmpabs 0x2 diff --git a/gas/testsuite/gas/i386/x86-64-apx-mov-inval.l b/gas/testsuite/gas/i386/x86-64-apx-mov-inval.l new file mode 100644 index 00000000000..b1aa91ae3c9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-mov-inval.l @@ -0,0 +1,2 @@ +.* Assembler messages: +.*:5: Error: unsupport rex2 pseudo prefix for `mov' diff --git a/gas/testsuite/gas/i386/x86-64-apx-mov-inval.s b/gas/testsuite/gas/i386/x86-64-apx-mov-inval.s new file mode 100644 index 00000000000..f0896da6b4d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-mov-inval.s @@ -0,0 +1,5 @@ +# Check 64bit illegal APX_F mov instructions with rex2 prefix + + .text + _start: + {rex2} mov %fs:0x0202020202020202, %rax diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 9aaa905393b..cf64b1f0000 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -374,6 +374,10 @@ run_dump_test "x86-64-apx-evex-egpr" run_dump_test "x86-64-apx-ndd" run_dump_test "x86-64-apx-nf" run_dump_test "x86-64-apx-nf-intel" +run_dump_test "x86-64-apx-jmpabs" +run_dump_test "x86-64-apx-jmpabs-intel" +run_dump_test "x86-64-apx-jmpabs-inval" +run_list_test "x86-64-apx-mov-inval" run_dump_test "x86-64-avx512f-rcigrz-intel" run_dump_test "x86-64-avx512f-rcigrz" run_dump_test "x86-64-clwb" diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index b3ede02df06..e2e903afde4 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -105,6 +105,7 @@ static bool FXSAVE_Fixup (instr_info *, int, int); static bool MOVSXD_Fixup (instr_info *, int, int); static bool DistinctDest_Fixup (instr_info *, int, int); static bool PREFETCHI_Fixup (instr_info *, int, int); +static bool JMPABS_Fixup (instr_info *, int, int); static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *, enum disassembler_style, @@ -260,6 +261,9 @@ struct instr_info char scale_char; enum x86_64_isa isa64; + + /* Remember if the current op is jmpabs instructions. */ + bool jmpabs; }; struct dis_private { @@ -2057,7 +2061,7 @@ static const struct dis386 dis386[] = { { "lahf", { XX }, 0 }, /* a0 */ { "mov%LB", { AL, Ob }, 0 }, - { "mov%LS", { eAX, Ov }, 0 }, + { "mov%LS", { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, 0 }, { "mov%LB", { Ob, AL }, 0 }, { "mov%LS", { Ov, eAX }, 0 }, { "movs{b|}", { Ybr, Xb }, 0 }, @@ -9690,6 +9694,15 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) goto out; } + if (ins.jmpabs + && ((ins.prefixes & (PREFIX_OPCODE | PREFIX_ADDR)) != 0x0 + || (ins.rex2_payload & 0x8) != 0x0)) + { + i386_dis_printf (info, dis_style_text, "(bad)"); + ret = ins.end_codep - priv.the_buffer; + goto out; + } + switch (dp->prefix_requirement) { case PREFIX_DATA: @@ -13877,3 +13890,30 @@ PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag) return OP_M (ins, bytemode, sizeflag); } + +static bool +JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag) +{ + if (ins->address_mode == mode_64bit + && ins->last_rex2_prefix >= 0 + && (ins->rex2_payload & 0x80) == 0x0) + { + uint64_t op; + + if (bytemode == eAX_reg) + return true; + + if (!get64 (ins, &op)) + return false; + + ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs"); + ins->all_prefixes[ins->last_rex2_prefix] = 0; + ins->jmpabs = true; + oappend_immediate (ins, op); + return true; + } + + if (bytemode == eAX_reg) + return OP_IMREG (ins, bytemode, sizeflag); + return OP_OFF64 (ins, v_mode, sizeflag); +} diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 4e8ef15c28b..4d1b6742060 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -161,7 +161,7 @@ // Move instructions. mov, 0xa0, No64, D|W|CheckOperandSize|No_sSuf|No_qSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword } -mov, 0xa0, x64, D|W|CheckOperandSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } +mov, 0xa0, x64, D|W|CheckOperandSize|No_sSuf|No_egpr, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } movabs, 0xa0, x64, D|W|CheckOperandSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } mov, 0x88, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } // In the 64bit mode the short form mov immediate is redefined to have @@ -623,6 +623,8 @@ ljmp, 0xea, No64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 ljmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex } ljmp, 0xff/5, x64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex } +jmpabs, 0xa1, APX_F|x64, JumpAbsolute|NoSuf, { Imm64 } + ret, 0xc3, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, {} ret, 0xc2, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, { Imm16 } ret, 0xc3, x64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {}