From patchwork Thu Aug 31 03:21:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 75006 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C29F63857359 for ; Thu, 31 Aug 2023 03:23:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C29F63857359 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1693452196; bh=xGy7XI9RihsO29RLsAFpF5CVVRKP2kyz8QLeeq7VXU0=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=KNKxO5Sa+kvL3cG5cQsvxgI3bOJg8UpL/Z4K+gXjYT7XzBxWf7Bf1pfUpdw7kqQoW 8bjZCo0wFfZRhyYa2dWnz9UxLXVpkd3iYZ8sqk4xCk6u+Xw6ZO2v8JLPuvkzCu1EEE 38XqVcfHFrz6c0a7cgvp4DXLsTU6RR+rs1cBCRvo= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 047013858419; Thu, 31 Aug 2023 03:22:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 047013858419 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 3F7BE300089; Thu, 31 Aug 2023 03:22:20 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH v2 1/3] RISC-V: Remove RV64E conflict Date: Thu, 31 Aug 2023 03:21:54 +0000 Message-ID: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" From: Tsukasa OI Since RV32E *and* RV64E are ratified, RV64E is no longer invalid. This commit removes a restriction that prevents making base ISA with reduced GPRs with XLEN > 32. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Remove RV64E conflict since the ratified 'E' base ISAs include RV64E. gas/ChangeLog: * testsuite/gas/riscv/march-fail-base-02.d: Removed. * testsuite/gas/riscv/march-fail-base-02.l: Removed. --- bfd/elfxx-riscv.c | 7 ------- gas/testsuite/gas/riscv/march-fail-base-02.d | 3 --- gas/testsuite/gas/riscv/march-fail-base-02.l | 2 -- 3 files changed, 12 deletions(-) delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.l diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index cb65024beaff..9a397c5a8d1c 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1942,13 +1942,6 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps) int xlen = *rps->xlen; bool no_conflict = true; - if (riscv_lookup_subset (rps->subset_list, "e", &subset) - && xlen > 32) - { - rps->error_handler - (_("rv%d does not support the `e' extension"), xlen); - no_conflict = false; - } if (riscv_lookup_subset (rps->subset_list, "q", &subset) && (subset->major_version < 2 || (subset->major_version == 2 && subset->minor_version < 2)) diff --git a/gas/testsuite/gas/riscv/march-fail-base-02.d b/gas/testsuite/gas/riscv/march-fail-base-02.d deleted file mode 100644 index cfe085ab21aa..000000000000 --- a/gas/testsuite/gas/riscv/march-fail-base-02.d +++ /dev/null @@ -1,3 +0,0 @@ -#as: -march=rv64e -#source: empty.s -#error_output: march-fail-base-02.l diff --git a/gas/testsuite/gas/riscv/march-fail-base-02.l b/gas/testsuite/gas/riscv/march-fail-base-02.l deleted file mode 100644 index 52fee96af368..000000000000 --- a/gas/testsuite/gas/riscv/march-fail-base-02.l +++ /dev/null @@ -1,2 +0,0 @@ -.*Assembler messages: -.*Error: rv64 does not support the `e' extension From patchwork Thu Aug 31 03:21:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 75008 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 22A7E385C6E7 for ; Thu, 31 Aug 2023 03:24:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 22A7E385C6E7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1693452261; bh=2izWNIfiF3zih1BlzNx3BEKgn50yTWc1KBnG5Yzij3Q=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=RsLYBKGhMW47wvIcugP1v/jwzuHwYw5GWy6zUyLICfA0sN2LRZ6cQnI1cg230N3vY jZvSGbK20WhleA2nZSTF8vhSnrB0y61kTeH6Gf1ixA6/UYJOVNNAAZVqT21jD7syNb U15Pd+eiJfSIdQ3qxQBLUXUwqgugdlyGz5nEjWZg= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id CE0F53858D32; Thu, 31 Aug 2023 03:22:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CE0F53858D32 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 155CA300089; Thu, 31 Aug 2023 03:22:31 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH v2 2/3] RISC-V: Add "lp64e" ABI support Date: Thu, 31 Aug 2023 03:21:55 +0000 Message-ID: <00ee23325647b98524c2600b00041601e459d03d.1693452083.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" From: Tsukasa OI Since RV32E and RV64E are now ratified, this commit prepares the ABI support for LP64E (LP64 with reduced GPRs). gas/ChangeLog: * config/tc-riscv.c (riscv_set_abi_by_arch): Update the error message. (md_parse_option): Accept "lp64e". * doc/c-riscv.texi: Update the documentation to allow "lp64e". * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Change error message. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l: Likewise. --- gas/config/tc-riscv.c | 4 +++- gas/doc/c-riscv.texi | 5 ++--- gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l | 2 +- gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l | 2 +- gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l | 2 +- 5 files changed, 8 insertions(+), 7 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 959cbbc32a5e..d0caf691fc65 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -384,7 +384,7 @@ riscv_set_abi_by_arch (void) as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); if (riscv_subset_supports (&riscv_rps_as, "e") && !rve_abi) - as_bad ("only the ilp32e ABI is supported for e extension"); + as_bad ("only ilp32e/lp64e ABI are supported for e extension"); if (float_abi == FLOAT_ABI_SINGLE && !riscv_subset_supports (&riscv_rps_as, "f")) @@ -3897,6 +3897,8 @@ md_parse_option (int c, const char *arg) riscv_set_abi (32, FLOAT_ABI_QUAD, false); else if (strcmp (arg, "lp64") == 0) riscv_set_abi (64, FLOAT_ABI_SOFT, false); + else if (strcmp (arg, "lp64e") == 0) + riscv_set_abi (64, FLOAT_ABI_SOFT, true); else if (strcmp (arg, "lp64f") == 0) riscv_set_abi (64, FLOAT_ABI_SINGLE, false); else if (strcmp (arg, "lp64d") == 0) diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index b175ba0a7293..e7fdbfa22afb 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -65,9 +65,8 @@ aren't set, then assembler will check the default configure setting @item -mabi=ABI Selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or -quad-precision floating-point calling convention, or none to indicate -the soft-float calling convention. Also, "ilp32" can optionally be followed -by "e" to indicate the RVE ABI, which is always soft-float. +quad-precision floating-point calling convention, or none or "e" to indicate +the soft-float calling convention ("e" indicates a soft-float RVE ABI). @cindex @samp{-mrelax} option, RISC-V @item -mrelax diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l index f7306cb24d20..419a01d5d53a 100644 --- a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l +++ b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l @@ -1,4 +1,4 @@ .*Assembler messages: .*Error: can't have 64-bit ABI on 32-bit ISA -.*Error: only the ilp32e ABI is supported for e extension +.*Error: only ilp32e/lp64e ABI are supported for e extension .*Error: ilp32d/lp64d ABI can't be used when d extension isn't supported diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l index 706690ac9c64..7b2fcda8d685 100644 --- a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l +++ b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l @@ -1,4 +1,4 @@ .*Assembler messages: .*Error: can't have 64-bit ABI on 32-bit ISA -.*Error: only the ilp32e ABI is supported for e extension +.*Error: only ilp32e/lp64e ABI are supported for e extension .*Error: ilp32f/lp64f ABI can't be used when f extension isn't supported diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l index ab64b1546f63..a06e9ea1aa93 100644 --- a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l +++ b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l @@ -1,4 +1,4 @@ .*Assembler messages: .*Error: can't have 64-bit ABI on 32-bit ISA -.*Error: only the ilp32e ABI is supported for e extension +.*Error: only ilp32e/lp64e ABI are supported for e extension .*Error: ilp32q/lp64q ABI can't be used when q extension isn't supported From patchwork Thu Aug 31 03:21:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 75009 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3CFC93857359 for ; Thu, 31 Aug 2023 03:24:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3CFC93857359 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1693452263; bh=VnWs0K+9KHEZ9cbflpgDfs4aNi3zzC0VfrZ0dj1yqCw=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=jJ+ZmCoQ0CkUoAMo4xUZBCXUuZb0X6Drv8IGS4bFXsRcLmZkRM/jvXucW458digZz HcPvhaQlfy0Dzj1RtyjBHax3zGJ05ayulhiTm1XHdN7hfPq3+RJJ2MXQMBkaQI86uK 6nKlzboYJHH3Q+kTC5NM6HebmqfzRADsVv0sHfrA= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 597343858D20; Thu, 31 Aug 2023 03:22:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 597343858D20 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id DB326300089; Thu, 31 Aug 2023 03:22:41 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH v2 3/3] RISC-V: Add RV64E support to GDB Date: Thu, 31 Aug 2023 03:21:56 +0000 Message-ID: <25f7d27892de6e905300c7fadf15226bc9a5dbe5.1693452083.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" From: Tsukasa OI Since RV32E and RV64E are ratified, RV64E is no longer invalid. So, this commit adds RV64E support for various parts. --- gdb/arch/riscv.c | 15 +++++++++++++-- gdb/arch/riscv.h | 2 +- gdb/features/Makefile | 1 + gdb/features/riscv/rv64e-xregs.c | 30 +++++++++++++++++++++++++++++ gdb/features/riscv/rv64e-xregs.xml | 31 ++++++++++++++++++++++++++++++ gdb/riscv-tdep.c | 9 +-------- 6 files changed, 77 insertions(+), 11 deletions(-) create mode 100644 gdb/features/riscv/rv64e-xregs.c create mode 100644 gdb/features/riscv/rv64e-xregs.xml diff --git a/gdb/arch/riscv.c b/gdb/arch/riscv.c index 6f6fcb081e81..346fc1d0230d 100644 --- a/gdb/arch/riscv.c +++ b/gdb/arch/riscv.c @@ -25,6 +25,7 @@ #include "../features/riscv/32bit-fpu.c" #include "../features/riscv/64bit-fpu.c" #include "../features/riscv/rv32e-xregs.c" +#include "../features/riscv/rv64e-xregs.c" #ifndef GDBSERVER #define STATIC_IN_GDB static @@ -51,7 +52,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features) arch_name.append (":rv32i"); } else if (features.xlen == 8) - arch_name.append (":rv64i"); + { + if (features.embedded) + arch_name.append (":rv64e"); + else + arch_name.append (":rv64i"); + } else if (features.xlen == 16) arch_name.append (":rv128i"); @@ -76,7 +82,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features) regnum = create_feature_riscv_32bit_cpu (tdesc.get (), regnum); } else if (features.xlen == 8) - regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum); + { + if (features.embedded) + regnum = create_feature_riscv_rv64e_xregs (tdesc.get (), regnum); + else + regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum); + } /* For now we only support creating 32-bit or 64-bit f-registers. */ if (features.flen == 4) diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h index e1965da69ebb..abbac59aa09b 100644 --- a/gdb/arch/riscv.h +++ b/gdb/arch/riscv.h @@ -53,7 +53,7 @@ struct riscv_gdbarch_features vector size. */ int vlen = 0; - /* When true this target is RV32E. */ + /* When true this target is RV32E or RV64E. */ bool embedded = false; /* Track if the target description has an fcsr, fflags, and frm diff --git a/gdb/features/Makefile b/gdb/features/Makefile index 32341f718156..a2719d0cd813 100644 --- a/gdb/features/Makefile +++ b/gdb/features/Makefile @@ -238,6 +238,7 @@ FEATURE_XMLFILES = aarch64-core.xml \ loongarch/base64.xml \ loongarch/fpu.xml \ riscv/rv32e-xregs.xml \ + riscv/rv64e-xregs.xml \ riscv/32bit-cpu.xml \ riscv/32bit-fpu.xml \ riscv/64bit-cpu.xml \ diff --git a/gdb/features/riscv/rv64e-xregs.c b/gdb/features/riscv/rv64e-xregs.c new file mode 100644 index 000000000000..4346c3004ba8 --- /dev/null +++ b/gdb/features/riscv/rv64e-xregs.c @@ -0,0 +1,30 @@ +/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: + Original: rv64e-xregs.xml */ + +#include "gdbsupport/tdesc.h" + +static int +create_feature_riscv_rv64e_xregs (struct target_desc *result, long regnum) +{ + struct tdesc_feature *feature; + + feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.cpu"); + tdesc_create_reg (feature, "zero", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "ra", regnum++, 1, NULL, 64, "code_ptr"); + tdesc_create_reg (feature, "sp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "gp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "tp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "t0", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "t1", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "t2", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "fp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "s1", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a0", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a1", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a2", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a3", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a4", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a5", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "pc", regnum++, 1, NULL, 64, "code_ptr"); + return regnum; +} diff --git a/gdb/features/riscv/rv64e-xregs.xml b/gdb/features/riscv/rv64e-xregs.xml new file mode 100644 index 000000000000..103588fd7f2d --- /dev/null +++ b/gdb/features/riscv/rv64e-xregs.xml @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index ae18eb644527..b230ba634147 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -3847,14 +3847,7 @@ riscv_features_from_bfd (const bfd *abfd) features.flen = 4; if (e_flags & EF_RISCV_RVE) - { - if (features.xlen == 8) - { - warning (_("64-bit ELF with RV32E flag set! Assuming 32-bit")); - features.xlen = 4; - } - features.embedded = true; - } + features.embedded = true; } return features;