From patchwork Wed Aug 30 01:38:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 74937 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CE18538582B0 for ; Wed, 30 Aug 2023 01:39:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CE18538582B0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1693359564; bh=wunbAHerI411bLnhOAcb71fKGT18IUF0/KdOmiwxG+4=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=U3kptUvxT4ppkQZV9+MYR9wi4RADsE63Lxrr070+Va0rXjBbMJNE+ZOkLBtBf6xpc FEdqF7jDhXuCIcquq3hjDu0C6PCLit56iBaCRzZyK1qX4cX1o7lLM3cKcG0qS8z6fN IdxRA+6SKUW2VePiSSk0PrLO6SBTeivJ/fBYxrz8= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id DA9C7385841B for ; Wed, 30 Aug 2023 01:38:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DA9C7385841B Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 87A32300089; Wed, 30 Aug 2023 01:38:49 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng , Jeff Law , Greg Favor Cc: binutils@sourceware.org Subject: [PATCH 1/1] RISC-V: Make XVentanaCondOps RV64 only Date: Wed, 30 Aug 2023 01:38:34 +0000 Message-ID: <0af2c2372b816ba128cef7165227d905e419357a.1693359513.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org Sender: "Binutils" From: Tsukasa OI Although XVentanaCondOps instructions are XLEN-agonistic, Ventana's manual only defines them only for RV64 (because all Ventana's processors implement RV64). This commit limits XVentanaCondOps instructions RV64-only to match the behavior of the manual and LLVM. Note that this commit alone will not make XVentanaCondOps extension with RV32 invalid (it just makes XVentanaCondOps on RV32 empty). opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Restrict "vt.maskc" and "vt.maskcn" to XLEN=64. gas/ChangeLog: * testsuite/gas/riscv/x-ventana-condops-32.d: New failure test. * testsuite/gas/riscv/x-ventana-condops-32.l: Likewise. --- gas/testsuite/gas/riscv/x-ventana-condops-32.d | 3 +++ gas/testsuite/gas/riscv/x-ventana-condops-32.l | 3 +++ opcodes/riscv-opc.c | 4 ++-- 3 files changed, 8 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops-32.d create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops-32.l diff --git a/gas/testsuite/gas/riscv/x-ventana-condops-32.d b/gas/testsuite/gas/riscv/x-ventana-condops-32.d new file mode 100644 index 000000000000..ea67515da0e3 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-ventana-condops-32.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xventanacondops +#source: x-ventana-condops.s +#error_output: x-ventana-condops-32.l diff --git a/gas/testsuite/gas/riscv/x-ventana-condops-32.l b/gas/testsuite/gas/riscv/x-ventana-condops-32.l new file mode 100644 index 000000000000..e434caf15f60 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-ventana-condops-32.l @@ -0,0 +1,3 @@ +.*Assembler messages: +.*Error: unrecognized opcode `vt.maskc a0,a1,a2' +.*Error: unrecognized opcode `vt.maskcn a0,a3,a4' diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 067e9fdb611f..f5416605dcc3 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2174,8 +2174,8 @@ const struct riscv_opcode riscv_opcodes[] = {"th.sync.s", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_S, MASK_TH_SYNC_S, match_opcode, 0}, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ -{"vt.maskc", 0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, -{"vt.maskcn", 0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 }, +{"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, +{"vt.maskcn", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 }, /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}