From patchwork Wed Jun 14 07:57:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 71075 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8AEE5385841B for ; Wed, 14 Jun 2023 07:58:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8AEE5385841B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686729529; bh=M8556CRgyb35fpSZwH61s/bPaCgmbEjNs92bnXekikU=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=asrxFu60PvERk5YHASpSW3D3EYGMKS/5yb77E3m8M7JWJtCJhMblQmlTE0cHtGTIG Rzn10xwlSLHvm3Sm3OTTJTF5JJQSXja3POVPRIzS4NI3qvxYRsveJIWdhiy6rC5Mrp c3qlDeu9TxFbK1SmOGNGViqmZ0WB0XULoOaS1jcM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-124.freemail.mail.aliyun.com (out30-124.freemail.mail.aliyun.com [115.124.30.124]) by sourceware.org (Postfix) with ESMTPS id 492093858D38 for ; Wed, 14 Jun 2023 07:58:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 492093858D38 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R731e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046056; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0Vl5dKBf_1686729489; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vl5dKBf_1686729489) by smtp.aliyun-inc.com; Wed, 14 Jun 2023 15:58:14 +0800 To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, palmer@dabbelt.com, richard.sandiford@arm.com, kito.cheng@gmail.com, christoph.muellner@vrull.eu, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH v2] RISC-V: Save and restore FCSR in interrupt functions to avoid program errors. Date: Wed, 14 Jun 2023 15:57:45 +0800 Message-Id: <20230614075746.3918-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20230613064126.1323-1-jinma@linux.alibaba.com> References: <20230613064126.1323-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.7 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jin Ma via Gcc-patches From: Jin Ma Reply-To: Jin Ma Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" In order to avoid interrupt functions to change the FCSR, it needs to be saved and restored at the beginning and end of the function. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_compute_frame_info): Allocate frame for FCSR. (riscv_for_each_saved_reg): Save and restore FCSR in interrupt functions. * config/riscv/riscv.md (riscv_frcsr): New patterns. (riscv_fscsr): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/interrupt-fcsr-1.c: New test. * gcc.target/riscv/interrupt-fcsr-2.c: New test. * gcc.target/riscv/interrupt-fcsr-3.c: New test. --- gcc/config/riscv/riscv.cc | 48 +++++++++++++++++-- gcc/config/riscv/riscv.md | 13 +++++ .../gcc.target/riscv/interrupt-fcsr-1.c | 15 ++++++ .../gcc.target/riscv/interrupt-fcsr-2.c | 15 ++++++ .../gcc.target/riscv/interrupt-fcsr-3.c | 14 ++++++ 5 files changed, 102 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/interrupt-fcsr-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/interrupt-fcsr-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/interrupt-fcsr-3.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index dd5361c2bd2..9d71e5c9f72 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5095,12 +5095,15 @@ riscv_compute_frame_info (void) frame = &cfun->machine->frame; - /* In an interrupt function, if we have a large frame, then we need to - save/restore t0. We check for this before clearing the frame struct. */ + /* In an interrupt function, there are two cases in which t0 needs to be used: + 1, If we have a large frame, then we need to save/restore t0. We check for + this before clearing the frame struct. + 2, Need to save and restore some CSRs in the frame. */ if (cfun->machine->interrupt_handler_p) { HOST_WIDE_INT step1 = riscv_first_stack_step (frame, frame->total_size); - if (! POLY_SMALL_OPERAND_P ((frame->total_size - step1))) + if (! POLY_SMALL_OPERAND_P ((frame->total_size - step1)) + || (TARGET_HARD_FLOAT || TARGET_ZFINX)) interrupt_save_prologue_temp = true; } @@ -5147,6 +5150,17 @@ riscv_compute_frame_info (void) } } + /* In an interrupt function, we need extra space for the initial saves of CSRs. */ + if (cfun->machine->interrupt_handler_p + && ((TARGET_HARD_FLOAT && frame->fmask) + || (TARGET_ZFINX + /* Except for RISCV_PROLOGUE_TEMP_REGNUM. */ + && (frame->mask & ~(1 << RISCV_PROLOGUE_TEMP_REGNUM))))) + /* Save and restore FCSR. */ + /* TODO: When P or V extensions support interrupts, some of their CSRs + may also need to be saved and restored. */ + x_save_size += riscv_stack_align (1 * UNITS_PER_WORD); + /* At the bottom of the frame are any outgoing stack arguments. */ offset = riscv_stack_align (crtl->outgoing_args_size); /* Next are local stack variables. */ @@ -5392,6 +5406,34 @@ riscv_for_each_saved_reg (poly_int64 sp_offset, riscv_save_restore_fn fn, } } + /* In an interrupt function, save and restore some necessary CSRs in the stack + to avoid changes in CSRs. */ + if (regno == RISCV_PROLOGUE_TEMP_REGNUM + && cfun->machine->interrupt_handler_p + && ((TARGET_HARD_FLOAT && cfun->machine->frame.fmask) + || (TARGET_ZFINX + && (cfun->machine->frame.mask & ~(1 << RISCV_PROLOGUE_TEMP_REGNUM))))) + { + unsigned int fcsr_size = GET_MODE_SIZE (SImode); + if (!epilogue) + { + riscv_save_restore_reg (word_mode, regno, offset, fn); + offset -= fcsr_size; + emit_insn (gen_riscv_frcsr (RISCV_PROLOGUE_TEMP (SImode))); + riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGNUM, + offset, riscv_save_reg); + } + else + { + riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGNUM, + offset - fcsr_size, riscv_restore_reg); + emit_insn (gen_riscv_fscsr (RISCV_PROLOGUE_TEMP (SImode))); + riscv_save_restore_reg (word_mode, regno, offset, fn); + offset -= fcsr_size; + } + continue; + } + riscv_save_restore_reg (word_mode, regno, offset, fn); } diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d8e935cb934..565e8cd27cd 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -78,6 +78,8 @@ (define_c_enum "unspecv" [ UNSPECV_GPR_RESTORE ;; Floating-point unspecs. + UNSPECV_FRCSR + UNSPECV_FSCSR UNSPECV_FRFLAGS UNSPECV_FSFLAGS UNSPECV_FSNVSNAN @@ -3056,6 +3058,17 @@ (define_insn "gpr_restore_return" "" "") +(define_insn "riscv_frcsr" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec_volatile [(const_int 0)] UNSPECV_FRCSR))] + "TARGET_HARD_FLOAT || TARGET_ZFINX" + "frcsr\t%0") + +(define_insn "riscv_fscsr" + [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSCSR)] + "TARGET_HARD_FLOAT || TARGET_ZFINX" + "fscsr\t%0") + (define_insn "riscv_frflags" [(set (match_operand:SI 0 "register_operand" "=r") (unspec_volatile [(const_int 0)] UNSPECV_FRFLAGS))] diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-1.c b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-1.c new file mode 100644 index 00000000000..aaafb08a674 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-1.c @@ -0,0 +1,15 @@ +/* Verify that fcsr instructions emitted. */ +/* { dg-do compile } */ +/* { dg-require-effective-target hard_float } */ +/* { dg-options "-O" } */ + +extern int foo (void); + +void __attribute__ ((interrupt)) +sub (void) +{ + foo (); +} + +/* { dg-final { scan-assembler-times "frcsr\t" 1 } } */ +/* { dg-final { scan-assembler-times "fscsr\t" 1 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-2.c b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-2.c new file mode 100644 index 00000000000..ea22e6a2be4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-2.c @@ -0,0 +1,15 @@ +/* Verify that fcsr instructions emitted. */ +/* { dg-do compile } */ +/* { dg-require-effective-target hard_float } */ +/* { dg-options "-O" } */ + +extern int foo (void); +extern float interrupt_count; +void __attribute__ ((interrupt)) +sub (void) +{ + interrupt_count++; +} + +/* { dg-final { scan-assembler-times "frcsr\t" 1 } } */ +/* { dg-final { scan-assembler-times "fscsr\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-3.c b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-3.c new file mode 100644 index 00000000000..5e7eac4b770 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-3.c @@ -0,0 +1,14 @@ +/* Verify that fcsr instructions are not emitted. */ +/* { dg-do compile } */ +/* { dg-require-effective-target hard_float } */ +/* { dg-options "-O" } */ + +extern int foo (void); + +void __attribute__ ((interrupt)) +sub (void) +{ +} + +/* { dg-final { scan-assembler-not "frcsr\t" } } */ +/* { dg-final { scan-assembler-not "fscsr\t" } } */