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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT025.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6118 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alex Coplan via Gcc-patches From: Alex Coplan Reply-To: Alex Coplan Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The ls64 builtin code was using incorrect GNU style with eight spaces where there should be a tab. Fixed thusly. gcc/ChangeLog: PR target/110100 * config/aarch64/aarch64-builtins.cc (aarch64_init_ls64_builtins_types): Replace eight consecutive spaces with tabs. (aarch64_init_ls64_builtins): Likewise. (aarch64_expand_builtin_ls64): Likewise. * config/aarch64/aarch64.md (ld64b): Likewise. (st64b): Likewise. (st64bv): Likewise (st64bv0): Likewise. --- gcc/config/aarch64/aarch64-builtins.cc | 64 +++++++++++++------------- gcc/config/aarch64/aarch64.md | 22 ++++----- 2 files changed, 43 insertions(+), 43 deletions(-) diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index e0bb2128e02..a3ae1a8e99e 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -1862,11 +1862,11 @@ aarch64_init_ls64_builtins_types (void) gcc_assert (TYPE_ALIGN (array_type) == 64); tree field = build_decl (input_location, FIELD_DECL, - get_identifier ("val"), array_type); + get_identifier ("val"), array_type); ls64_arm_data_t = lang_hooks.types.simulate_record_decl (input_location, - tuple_type_name, - make_array_slice (&field, 1)); + tuple_type_name, + make_array_slice (&field, 1)); gcc_assert (TYPE_MODE (ls64_arm_data_t) == V8DImode); gcc_assert (TYPE_MODE_RAW (ls64_arm_data_t) == TYPE_MODE (ls64_arm_data_t)); @@ -1881,16 +1881,16 @@ aarch64_init_ls64_builtins (void) ls64_builtins_data data[4] = { {"__builtin_aarch64_ld64b", AARCH64_LS64_BUILTIN_LD64B, build_function_type_list (ls64_arm_data_t, - const_ptr_type_node, NULL_TREE)}, + const_ptr_type_node, NULL_TREE)}, {"__builtin_aarch64_st64b", AARCH64_LS64_BUILTIN_ST64B, build_function_type_list (void_type_node, ptr_type_node, - ls64_arm_data_t, NULL_TREE)}, + ls64_arm_data_t, NULL_TREE)}, {"__builtin_aarch64_st64bv", AARCH64_LS64_BUILTIN_ST64BV, build_function_type_list (uint64_type_node, ptr_type_node, - ls64_arm_data_t, NULL_TREE)}, + ls64_arm_data_t, NULL_TREE)}, {"__builtin_aarch64_st64bv0", AARCH64_LS64_BUILTIN_ST64BV0, build_function_type_list (uint64_type_node, ptr_type_node, - ls64_arm_data_t, NULL_TREE)}, + ls64_arm_data_t, NULL_TREE)}, }; for (size_t i = 0; i < ARRAY_SIZE (data); ++i) @@ -2509,40 +2509,40 @@ aarch64_expand_builtin_ls64 (int fcode, tree exp, rtx target) { case AARCH64_LS64_BUILTIN_LD64B: { - rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); - create_output_operand (&ops[0], target, V8DImode); - create_input_operand (&ops[1], op0, DImode); - expand_insn (CODE_FOR_ld64b, 2, ops); - return ops[0].value; + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + create_output_operand (&ops[0], target, V8DImode); + create_input_operand (&ops[1], op0, DImode); + expand_insn (CODE_FOR_ld64b, 2, ops); + return ops[0].value; } case AARCH64_LS64_BUILTIN_ST64B: { - rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); - rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); - create_output_operand (&ops[0], op0, DImode); - create_input_operand (&ops[1], op1, V8DImode); - expand_insn (CODE_FOR_st64b, 2, ops); - return const0_rtx; + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); + create_output_operand (&ops[0], op0, DImode); + create_input_operand (&ops[1], op1, V8DImode); + expand_insn (CODE_FOR_st64b, 2, ops); + return const0_rtx; } case AARCH64_LS64_BUILTIN_ST64BV: { - rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); - rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); - create_output_operand (&ops[0], target, DImode); - create_input_operand (&ops[1], op0, DImode); - create_input_operand (&ops[2], op1, V8DImode); - expand_insn (CODE_FOR_st64bv, 3, ops); - return ops[0].value; + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); + create_output_operand (&ops[0], target, DImode); + create_input_operand (&ops[1], op0, DImode); + create_input_operand (&ops[2], op1, V8DImode); + expand_insn (CODE_FOR_st64bv, 3, ops); + return ops[0].value; } case AARCH64_LS64_BUILTIN_ST64BV0: { - rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); - rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); - create_output_operand (&ops[0], target, DImode); - create_input_operand (&ops[1], op0, DImode); - create_input_operand (&ops[2], op1, V8DImode); - expand_insn (CODE_FOR_st64bv0, 3, ops); - return ops[0].value; + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); + create_output_operand (&ops[0], target, DImode); + create_input_operand (&ops[1], op0, DImode); + create_input_operand (&ops[2], op1, V8DImode); + expand_insn (CODE_FOR_st64bv0, 3, ops); + return ops[0].value; } } diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c2ba726f8a0..11d0d9c8eb6 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -7918,9 +7918,9 @@ (define_insn "stg" ;; Load/Store 64-bit (LS64) instructions. (define_insn "ld64b" [(set (match_operand:V8DI 0 "register_operand" "=r") - (unspec_volatile:V8DI - [(mem:V8DI (match_operand:DI 1 "register_operand" "r"))] - UNSPEC_LD64B) + (unspec_volatile:V8DI + [(mem:V8DI (match_operand:DI 1 "register_operand" "r"))] + UNSPEC_LD64B) )] "TARGET_LS64" "ld64b\\t%0, [%1]" @@ -7929,8 +7929,8 @@ (define_insn "ld64b" (define_insn "st64b" [(set (mem:V8DI (match_operand:DI 0 "register_operand" "=r")) - (unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")] - UNSPEC_ST64B) + (unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")] + UNSPEC_ST64B) )] "TARGET_LS64" "st64b\\t%1, [%0]" @@ -7939,10 +7939,10 @@ (define_insn "st64b" (define_insn "st64bv" [(set (match_operand:DI 0 "register_operand" "=r") - (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV_RET)) + (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV_RET)) (set (mem:V8DI (match_operand:DI 1 "register_operand" "r")) - (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] - UNSPEC_ST64BV) + (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] + UNSPEC_ST64BV) )] "TARGET_LS64" "st64bv\\t%0, %2, [%1]" @@ -7951,10 +7951,10 @@ (define_insn "st64bv" (define_insn "st64bv0" [(set (match_operand:DI 0 "register_operand" "=r") - (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV0_RET)) + (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV0_RET)) (set (mem:V8DI (match_operand:DI 1 "register_operand" "r")) - (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] - UNSPEC_ST64BV0) + (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] + UNSPEC_ST64BV0) )] "TARGET_LS64" "st64bv0\\t%0, %2, [%1]" From patchwork Wed Jun 7 14:00:49 2023 Content-Type: text/plain; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT064.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9917 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alex Coplan via Gcc-patches From: Alex Coplan Reply-To: Alex Coplan Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The st64b pattern incorrectly had an output constraint on the register operand containing the destination address for the store, leading to wrong code. This patch fixes that. gcc/ChangeLog: PR target/110100 * config/aarch64/aarch64-builtins.cc (aarch64_expand_builtin_ls64): Use input operand for the destination address. * config/aarch64/aarch64.md: Fix constraint on address operand. gcc/testsuite/ChangeLog: PR target/110100 * gcc.target/aarch64/acle/pr110100.c: New test. --- gcc/config/aarch64/aarch64-builtins.cc | 2 +- gcc/config/aarch64/aarch64.md | 2 +- gcc/testsuite/gcc.target/aarch64/acle/pr110100.c | 7 +++++++ 3 files changed, 9 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/pr110100.c diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index a3ae1a8e99e..cb5828a70f4 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -2519,7 +2519,7 @@ aarch64_expand_builtin_ls64 (int fcode, tree exp, rtx target) { rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); - create_output_operand (&ops[0], op0, DImode); + create_input_operand (&ops[0], op0, DImode); create_input_operand (&ops[1], op1, V8DImode); expand_insn (CODE_FOR_st64b, 2, ops); return const0_rtx; diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 11d0d9c8eb6..ac39a4d683e 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -7928,7 +7928,7 @@ (define_insn "ld64b" ) (define_insn "st64b" - [(set (mem:V8DI (match_operand:DI 0 "register_operand" "=r")) + [(set (mem:V8DI (match_operand:DI 0 "register_operand" "r")) (unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")] UNSPEC_ST64B) )] diff --git a/gcc/testsuite/gcc.target/aarch64/acle/pr110100.c b/gcc/testsuite/gcc.target/aarch64/acle/pr110100.c new file mode 100644 index 00000000000..f56d5e619e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/pr110100.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8.7-a -O2" } */ +#include +void do_st64b(data512_t data) { + __arm_st64b((void*)0x10000000, data); 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT054.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB7882 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alex Coplan via Gcc-patches From: Alex Coplan Reply-To: Alex Coplan Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch refactors the ls64 builtins to allow the compiler to define them directly instead of having wrapper functions in arm_acle.h. This should be not only easier to maintain, but it makes two important correctness fixes: - It fixes PR110132, where the builtins ended up getting declared with invisible bindings in the C FE, so the FE ended up synthesizing incompatible implicit definitions for these builtins. - It allows the builtins to be used with LTO, which didn't work previously. We also take the opportunity to add test coverage from C++ for these builtins. gcc/ChangeLog: PR target/110132 * config/aarch64/aarch64-builtins.cc (aarch64_general_simulate_builtin): New. Use it ... (aarch64_init_ls64_builtins): ... here. Switch to declaring public ACLE names for builtins. (aarch64_general_init_builtins): Ensure we invoke the arm_acle.h setup if in_lto_p, just like we do for SVE. * config/aarch64/arm_acle.h: (__arm_ld64b): Delete. (__arm_st64b): Delete. (__arm_st64bv): Delete. (__arm_st64bv0): Delete. gcc/testsuite/ChangeLog: PR target/110132 * lib/target-supports.exp (check_effective_target_aarch64_asm_FUNC_ok): Extend to ls64. * g++.target/aarch64/acle/acle.exp: New. * g++.target/aarch64/acle/ls64.C: New test. * g++.target/aarch64/acle/ls64_lto.C: New test. * gcc.target/aarch64/acle/ls64_lto.c: New test. * gcc.target/aarch64/acle/pr110132.c: New test. --- gcc/config/aarch64/aarch64-builtins.cc | 24 ++++++++++--- gcc/config/aarch64/arm_acle.h | 33 ----------------- .../g++.target/aarch64/acle/acle.exp | 35 +++++++++++++++++++ gcc/testsuite/g++.target/aarch64/acle/ls64.C | 10 ++++++ .../g++.target/aarch64/acle/ls64_lto.C | 10 ++++++ .../gcc.target/aarch64/acle/ls64_lto.c | 10 ++++++ .../gcc.target/aarch64/acle/pr110132.c | 15 ++++++++ gcc/testsuite/lib/target-supports.exp | 2 +- 8 files changed, 100 insertions(+), 39 deletions(-) create mode 100644 gcc/testsuite/g++.target/aarch64/acle/acle.exp create mode 100644 gcc/testsuite/g++.target/aarch64/acle/ls64.C create mode 100644 gcc/testsuite/g++.target/aarch64/acle/ls64_lto.C create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_lto.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/pr110132.c diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index cb5828a70f4..fce95c34a7c 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -956,6 +956,16 @@ aarch64_general_add_builtin (const char *name, tree type, unsigned int code, NULL, attrs); } +static tree +aarch64_general_simulate_builtin (const char *name, tree fntype, + unsigned int code, + tree attrs = NULL_TREE) +{ + code = (code << AARCH64_BUILTIN_SHIFT) | AARCH64_BUILTIN_GENERAL; + return simulate_builtin_function_decl (input_location, name, fntype, + code, NULL, attrs); +} + static const char * aarch64_mangle_builtin_scalar_type (const_tree type) { @@ -1879,23 +1889,24 @@ aarch64_init_ls64_builtins (void) aarch64_init_ls64_builtins_types (); ls64_builtins_data data[4] = { - {"__builtin_aarch64_ld64b", AARCH64_LS64_BUILTIN_LD64B, + {"__arm_ld64b", AARCH64_LS64_BUILTIN_LD64B, build_function_type_list (ls64_arm_data_t, const_ptr_type_node, NULL_TREE)}, - {"__builtin_aarch64_st64b", AARCH64_LS64_BUILTIN_ST64B, + {"__arm_st64b", AARCH64_LS64_BUILTIN_ST64B, build_function_type_list (void_type_node, ptr_type_node, ls64_arm_data_t, NULL_TREE)}, - {"__builtin_aarch64_st64bv", AARCH64_LS64_BUILTIN_ST64BV, + {"__arm_st64bv", AARCH64_LS64_BUILTIN_ST64BV, build_function_type_list (uint64_type_node, ptr_type_node, ls64_arm_data_t, NULL_TREE)}, - {"__builtin_aarch64_st64bv0", AARCH64_LS64_BUILTIN_ST64BV0, + {"__arm_st64bv0", AARCH64_LS64_BUILTIN_ST64BV0, build_function_type_list (uint64_type_node, ptr_type_node, ls64_arm_data_t, NULL_TREE)}, }; for (size_t i = 0; i < ARRAY_SIZE (data); ++i) aarch64_builtin_decls[data[i].code] - = aarch64_general_add_builtin (data[i].name, data[i].type, data[i].code); + = aarch64_general_simulate_builtin (data[i].name, data[i].type, + data[i].code); } static void @@ -2028,6 +2039,9 @@ aarch64_general_init_builtins (void) if (TARGET_MEMTAG) aarch64_init_memtag_builtins (); + + if (in_lto_p) + handle_arm_acle_h (); } /* Implement TARGET_BUILTIN_DECL for the AARCH64_BUILTIN_GENERAL group. */ diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h index e0ac591d2c8..3b6b63e6805 100644 --- a/gcc/config/aarch64/arm_acle.h +++ b/gcc/config/aarch64/arm_acle.h @@ -270,40 +270,7 @@ __ttest (void) #endif #ifdef __ARM_FEATURE_LS64 -#pragma GCC push_options -#pragma GCC target ("+nothing+ls64") - typedef __arm_data512_t data512_t; - -__extension__ extern __inline data512_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_ld64b (const void *__addr) -{ - return __builtin_aarch64_ld64b (__addr); -} - -__extension__ extern __inline void -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_st64b (void *__addr, data512_t __value) -{ - __builtin_aarch64_st64b (__addr, __value); -} - -__extension__ extern __inline uint64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_st64bv (void *__addr, data512_t __value) -{ - return __builtin_aarch64_st64bv (__addr, __value); -} - -__extension__ extern __inline uint64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_st64bv0 (void *__addr, data512_t __value) -{ - return __builtin_aarch64_st64bv0 (__addr, __value); -} - -#pragma GCC pop_options #endif #pragma GCC push_options diff --git a/gcc/testsuite/g++.target/aarch64/acle/acle.exp b/gcc/testsuite/g++.target/aarch64/acle/acle.exp new file mode 100644 index 00000000000..9e1cbf4a0c6 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/acle/acle.exp @@ -0,0 +1,35 @@ +# Copyright (C) 2014-2023 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an AArch64 target. +if ![istarget aarch64*-*-*] then { + return +} + +# Load support procs. +load_lib g++-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/g++.target/aarch64/acle/ls64.C b/gcc/testsuite/g++.target/aarch64/acle/ls64.C new file mode 100644 index 00000000000..d9002785b57 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/acle/ls64.C @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.7-a" } */ +#include +int main() +{ + data512_t d = __arm_ld64b ((const void *)0x1000); + __arm_st64b ((void *)0x2000, d); + uint64_t x = __arm_st64bv ((void *)0x3000, d); + x += __arm_st64bv0 ((void *)0x4000, d); +} diff --git a/gcc/testsuite/g++.target/aarch64/acle/ls64_lto.C b/gcc/testsuite/g++.target/aarch64/acle/ls64_lto.C new file mode 100644 index 00000000000..274a4771e1c --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/acle/ls64_lto.C @@ -0,0 +1,10 @@ +/* { dg-do link { target aarch64_asm_ls64_ok } } */ +/* { dg-additional-options "-march=armv8.7-a -flto" } */ +#include +int main() +{ + data512_t d = __arm_ld64b ((const void *)0x1000); + __arm_st64b ((void *)0x2000, d); + uint64_t x = __arm_st64bv ((void *)0x3000, d); + x += __arm_st64bv0 ((void *)0x4000, d); +} diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_lto.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_lto.c new file mode 100644 index 00000000000..8b4f2427771 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_lto.c @@ -0,0 +1,10 @@ +/* { dg-do link { target aarch64_asm_ls64_ok } } */ +/* { dg-additional-options "-march=armv8.7-a -flto" } */ +#include +int main(void) +{ + data512_t d = __arm_ld64b ((const void *)0x1000); + __arm_st64b ((void *)0x2000, d); + uint64_t x = __arm_st64bv ((void *)0x3000, d); + x += __arm_st64bv0 ((void *)0x4000, d); +} diff --git a/gcc/testsuite/gcc.target/aarch64/acle/pr110132.c b/gcc/testsuite/gcc.target/aarch64/acle/pr110132.c new file mode 100644 index 00000000000..fb88d633dd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/pr110132.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.7-a" } */ + +/* Check that ls64 builtins can be invoked using a preprocesed testcase + without triggering bogus builtin warnings, see PR110132. + + Note that this is purely to test GCC internals and user code should + include arm_acle.h to make use of these builtins. */ + +#pragma GCC aarch64 "arm_acle.h" +typedef __arm_data512_t data512_t; +void f(void *p, data512_t d) +{ + __arm_st64b (p, d); +} diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 431a56f0be5..184fafb020f 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -10965,7 +10965,7 @@ proc check_effective_target_aarch64_tiny { } { # various architecture extensions via the .arch_extension pseudo-op. foreach { aarch64_ext } { "fp" "simd" "crypto" "crc" "lse" "dotprod" "sve" - "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" } { + "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" "ls64" } { eval [string map [list FUNC $aarch64_ext] { proc check_effective_target_aarch64_asm_FUNC_ok { } { if { [istarget aarch64*-*-*] } {