From patchwork Tue May 30 09:25:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takayuki 'January June' Suwa X-Patchwork-Id: 70300 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DE9963855885 for ; Tue, 30 May 2023 09:27:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DE9963855885 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685438865; bh=vvw3KiIH+XGVXHHJjJmaoBgainNyHkbVbpA5WWsomvQ=; h=Date:To:Cc:Subject:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=SIZv1CKyDrEyoki3iRypIh41rVW4n6ZfLPi5Gmuzbi3ifv7P7wtfv/MIJp5HY/eRG xOoOaQfpDT+rmUIJYHN08U30ME+VkhC60FD1YSryuD22RMx7/Ti0p6WgaO/NxpTOXd YdMklKbZw47boXTfnoU1fImbkonueg+gEsJISnbI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from omggw0013.mail.otm.ynwl.yahoo.co.jp (omggw0013.mail.otm.yahoo.co.jp [182.22.18.27]) by sourceware.org (Postfix) with ESMTPS id C31913858C00 for ; Tue, 30 May 2023 09:27:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C31913858C00 X-YMail-OSG: 8X2w0TsVM1nsBKr1CITLf.KA4ay2SLdmEdTYY_G_rT_rR_boWW5YegimyvdGCb0 wmd7s8ZJIm8_xM8w745cTcYJEs8zXG5xJxzi56GnsFrZr7JkB.ZubER3w96eA04f67ZiKFtYNmFi yqehyvUf7DRim9SUmfHnAfM4AjH_9FE0Isb8RywYZz.ZLlUyiMD8G115kBSq7PIcaOdFAgJhcNnX Pg95sFwl3nKpaf8vXVagLAwq5EMleSN_kv77987DNVE8YzC0wjbzeRxXo4iEFWDmSTEP2SL.0jnN 3tSFMKyhGMLDYgwP4oErHwWQ8FrSLcEa671K9Ug_XktUb0wk3GXz4ZwYwLedm_r0I9ZzAAYJWjHS 0_egMdzxIQDDrkaCwPU3c8rFoPUfRzxvm4xaRD6PXfj.voqtuy8uVypZ8v51.L48fpqBWsS.vzAM IsKsqrOzzVIwo9UOUUXbN7nHZWCIGmS4lMfiRfonymp5g59UC2iupX.fMudr7sk8lty2sQP4LuAV .wNlOiDWSiBHTUjyiOuKZtlhj35DXznEGHxO8XBBeKMIjtOdmI_65OaIBpPBkHLcAn6jf71EcLD6 axeGRgZIHwNjNh6yPmSztcSw3j52TTHK5XLaoMsSSJk_tszryq3vBlKThhjorzuPfHLM7Hvs.6vr mRgTB01cCihZgZFFRoLNHqsXS9mouZ932TxWD8KIdT06pC3SlWlX.KLw1Y8vJbGgmnlnN4043ghd mjwgxmJ0pSyj95BK2jJVESCKNp4AilXqw1jaA0fVZaY6RiXuMQuW5rravQ8tBKc2623A08V1dwi8 BzjfDMem.3aJZqLG07WAdgarHE8qGqiBsv2dZmxU7VLtjEYlFlwCO0R3R7vrpt.wm_DDcBRFa4uT lYMofD2lOegJVH4Twzk0oWPzH6wJjJpkc.xvzNaCFoyNspJvNmNvbzTvIIjWeENT2S8SfsUPzbJr dQrApUDhlegGCzKgr5zFswGtXnUCVOQmEKeylvUgooe2SYy2D1Od1mw4IVKFzhYQV8lo- Received: from sonicgw.mail.yahoo.co.jp by sonicconh6001.mail.ssk.yahoo.co.jp with HTTP; Tue, 30 May 2023 09:27:06 +0000 Received: by smtphe5007.mail.kks.ynwp.yahoo.co.jp (YJ Hermes SMTP Server) with ESMTPA ID 3cad198af2e9f658f090f8a7eb20f35f; Tue, 30 May 2023 18:27:03 +0900 (JST) Message-ID: Date: Tue, 30 May 2023 18:25:18 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 To: GCC Patches Cc: Max Filippov Subject: [PATCH 1/3] xtensa: Improve "*shlrd_reg" insn pattern and its variant References: X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_INVALID, DKIM_SIGNED, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_STOCKGEN, NML_ADSP_CUSTOM_MED, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The insn "*shlrd_reg" shifts two registers with a funnel shifter by the third register to get a single word result: reg0 = (reg1 SHIFT_OP0 reg3) BIT_JOIN_OP (reg2 SHIFT_OP1 (32 - reg3)) where the funnel left shift is SHIFT_OP0 := ASHIFT, SHIFT_OP1 := LSHIFTRT and its right shift is SHIFT_OP0 := LSHIFTRT, SHIFT_OP1 := ASHIFT, respectively. And also, BIT_JOIN_OP can be either PLUS or IOR in either shift direction. [(set (match_operand:SI 0 "register_operand" "=a") (match_operator:SI 6 "xtensa_bit_join_operator" [(match_operator:SI 4 "logical_shift_operator" [(match_operand:SI 1 "register_operand" "r") (match_operand:SI 3 "register_operand" "r")]) (match_operator:SI 5 "logical_shift_operator" [(match_operand:SI 2 "register_operand" "r") (neg:SI (match_dup 3))])]))] Although the RTL matching template can express it as above, there is no way of direcing that the operator (operands[6]) that combines the two individual shifts is commutative. Thus, if multiple insn sequences matching the above pattern appear adjacently, the combiner may accidentally mix them up and get partial results. This patch adds a new insn-and-split pattern with the two sides swapped representation of the bit-combining operation that was lacking and described above. And also changes the other "*shlrd" variants from previously describing the arbitraryness of bit-combining operations with code iterators to a combination of the match_operator and the predicate above. gcc/ChangeLog: * config/xtensa/predicates.md (xtensa_bit_join_operator): New predicate. * config/xtensa/xtensa.md (ior_op): Remove. (*shlrd_reg): Rename from "*shlrd_reg_", and add the insn_and_split pattern of the same name to express and capture the bit-combining operation with both sides swapped. In addition, replace use of code iterator with new operator predicate. (*shlrd_const, *shlrd_per_byte): Likewise regarding the code iterator. --- gcc/config/xtensa/predicates.md | 3 ++ gcc/config/xtensa/xtensa.md | 81 ++++++++++++++++++++++----------- 2 files changed, 58 insertions(+), 26 deletions(-) diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index 5faf1be8c15..a3575a68892 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -200,6 +200,9 @@ (define_predicate "xtensa_shift_per_byte_operator" (match_code "ashift,ashiftrt,lshiftrt")) +(define_predicate "xtensa_bit_join_operator" + (match_code "plus,ior")) + (define_predicate "tls_symbol_operand" (and (match_code "symbol_ref") (match_test "SYMBOL_REF_TLS_MODEL (op) != 0"))) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 57e50911f52..eda1353894b 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -87,9 +87,6 @@ ;; the same template. (define_mode_iterator HQI [HI QI]) -;; This code iterator is for *shlrd and its variants. -(define_code_iterator ior_op [ior plus]) - ;; Attributes. @@ -1682,21 +1679,22 @@ (set_attr "mode" "SI") (set_attr "length" "9")]) -(define_insn "*shlrd_reg_" +(define_insn "*shlrd_reg" [(set (match_operand:SI 0 "register_operand" "=a") - (ior_op:SI (match_operator:SI 4 "logical_shift_operator" + (match_operator:SI 6 "xtensa_bit_join_operator" + [(match_operator:SI 4 "logical_shift_operator" [(match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "register_operand" "r")]) - (match_operator:SI 5 "logical_shift_operator" - [(match_operand:SI 3 "register_operand" "r") - (neg:SI (match_dup 2))])))] + (match_operand:SI 3 "register_operand" "r")]) + (match_operator:SI 5 "logical_shift_operator" + [(match_operand:SI 2 "register_operand" "r") + (neg:SI (match_dup 3))])]))] "!optimize_debug && optimize && xtensa_shlrd_which_direction (operands[4], operands[5]) != UNKNOWN" { switch (xtensa_shlrd_which_direction (operands[4], operands[5])) { - case ASHIFT: return "ssl\t%2\;src\t%0, %1, %3"; - case LSHIFTRT: return "ssr\t%2\;src\t%0, %3, %1"; + case ASHIFT: return "ssl\t%3\;src\t%0, %1, %2"; + case LSHIFTRT: return "ssr\t%3\;src\t%0, %2, %1"; default: gcc_unreachable (); } } @@ -1704,14 +1702,42 @@ (set_attr "mode" "SI") (set_attr "length" "6")]) -(define_insn "*shlrd_const_" +(define_insn_and_split "*shlrd_reg" + [(set (match_operand:SI 0 "register_operand" "=a") + (match_operator:SI 6 "xtensa_bit_join_operator" + [(match_operator:SI 4 "logical_shift_operator" + [(match_operand:SI 1 "register_operand" "r") + (neg:SI (match_operand:SI 3 "register_operand" "r"))]) + (match_operator:SI 5 "logical_shift_operator" + [(match_operand:SI 2 "register_operand" "r") + (match_dup 3)])]))] + "!optimize_debug && optimize + && xtensa_shlrd_which_direction (operands[5], operands[4]) != UNKNOWN" + "#" + "&& 1" + [(set (match_dup 0) + (match_op_dup 6 + [(match_op_dup 5 + [(match_dup 2) + (match_dup 3)]) + (match_op_dup 4 + [(match_dup 1) + (neg:SI (match_dup 3))])]))] + "" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + + +(define_insn "*shlrd_const" [(set (match_operand:SI 0 "register_operand" "=a") - (ior_op:SI (match_operator:SI 5 "logical_shift_operator" + (match_operator:SI 7 "xtensa_bit_join_operator" + [(match_operator:SI 5 "logical_shift_operator" [(match_operand:SI 1 "register_operand" "r") (match_operand:SI 3 "const_int_operand" "i")]) - (match_operator:SI 6 "logical_shift_operator" + (match_operator:SI 6 "logical_shift_operator" [(match_operand:SI 2 "register_operand" "r") - (match_operand:SI 4 "const_int_operand" "i")])))] + (match_operand:SI 4 "const_int_operand" "i")])]))] "!optimize_debug && optimize && xtensa_shlrd_which_direction (operands[5], operands[6]) != UNKNOWN && IN_RANGE (INTVAL (operands[3]), 1, 31) @@ -1729,16 +1755,17 @@ (set_attr "mode" "SI") (set_attr "length" "6")]) -(define_insn "*shlrd_per_byte_" +(define_insn "*shlrd_per_byte" [(set (match_operand:SI 0 "register_operand" "=a") - (ior_op:SI (match_operator:SI 4 "logical_shift_operator" + (match_operator:SI 6 "xtensa_bit_join_operator" + [(match_operator:SI 4 "logical_shift_operator" [(match_operand:SI 1 "register_operand" "r") (ashift:SI (match_operand:SI 2 "register_operand" "r") (const_int 3))]) - (match_operator:SI 5 "logical_shift_operator" + (match_operator:SI 5 "logical_shift_operator" [(match_operand:SI 3 "register_operand" "r") (neg:SI (ashift:SI (match_dup 2) - (const_int 3)))])))] + (const_int 3)))])]))] "!optimize_debug && optimize && xtensa_shlrd_which_direction (operands[4], operands[5]) != UNKNOWN" { @@ -1753,32 +1780,34 @@ (set_attr "mode" "SI") (set_attr "length" "6")]) -(define_insn_and_split "*shlrd_per_byte__omit_AND" +(define_insn_and_split "*shlrd_per_byte_omit_AND" [(set (match_operand:SI 0 "register_operand" "=a") - (ior_op:SI (match_operator:SI 5 "logical_shift_operator" + (match_operator:SI 7 "xtensa_bit_join_operator" + [(match_operator:SI 5 "logical_shift_operator" [(match_operand:SI 1 "register_operand" "r") (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") (const_int 3)) (match_operand:SI 4 "const_int_operand" "i"))]) - (match_operator:SI 6 "logical_shift_operator" + (match_operator:SI 6 "logical_shift_operator" [(match_operand:SI 3 "register_operand" "r") (neg:SI (and:SI (ashift:SI (match_dup 2) (const_int 3)) - (match_dup 4)))])))] + (match_dup 4)))])]))] "!optimize_debug && optimize && xtensa_shlrd_which_direction (operands[5], operands[6]) != UNKNOWN && (INTVAL (operands[4]) & 0x1f) == 3 << 3" "#" "&& 1" [(set (match_dup 0) - (ior_op:SI (match_op_dup 5 + (match_op_dup 7 + [(match_op_dup 5 [(match_dup 1) (ashift:SI (match_dup 2) (const_int 3))]) - (match_op_dup 6 + (match_op_dup 6 [(match_dup 3) (neg:SI (ashift:SI (match_dup 2) - (const_int 3)))])))] + (const_int 3)))])]))] "" [(set_attr "type" "arith") (set_attr "mode" "SI") From patchwork Tue May 30 09:26:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takayuki 'January June' Suwa X-Patchwork-Id: 70301 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6D37C38558BE for ; Tue, 30 May 2023 09:27:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6D37C38558BE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685438866; bh=akS+33VrtzjVbOnJpZPAzRyp5jiK4kOtp4qxgbqDSHM=; h=Date:To:Cc:Subject:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=m1yL6M7mUkhYYtrW158Am4PKpjo8La4jEgMSusAqdDty4/OHLym7t56Q8BQweAhsZ ZTGKhpbbObUIRF34RXq4wUxJJSlkc7kzCW7HxejgG6gIQ0ZOuaXUr5xZ9h1CccC40B gtzezz0QrFSTM63H3FOAZV2rwWCKEh1LagNOWPQw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from omggw0015.mail.otm.ynwl.yahoo.co.jp (omggw0015.mail.otm.yahoo.co.jp [182.22.18.44]) by sourceware.org (Postfix) with ESMTPS id D53803858C1F for ; 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Tue, 30 May 2023 09:27:06 +0000 Received: by smtphe5002.mail.kks.ynwp.yahoo.co.jp (YJ Hermes SMTP Server) with ESMTPA ID 3d56fe2bdbf01fd0a78d52bd5afabfb6; Tue, 30 May 2023 18:27:04 +0900 (JST) Message-ID: <8defce68-dd50-5026-c87f-3d97a76898d6@yahoo.co.jp> Date: Tue, 30 May 2023 18:26:12 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 To: GCC Patches Cc: Max Filippov Subject: [PATCH 2/3] xtensa: Add 'adddi3' and 'subdi3' insn patterns References: <8defce68-dd50-5026-c87f-3d97a76898d6.ref@yahoo.co.jp> X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" More optimized than the default RTL generation. gcc/ChangeLog: * config/xtensa/xtensa.md (adddi3, subdi3): New RTL generation patterns implemented according to the instruc- tion idioms described in the Xtensa ISA reference manual (p. 600). --- gcc/config/xtensa/xtensa.md | 52 +++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index eda1353894b..7870fb0bfce 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -190,6 +190,32 @@ (set_attr "mode" "SI") (set_attr "length" "3")]) +(define_expand "adddi3" + [(set (match_operand:DI 0 "register_operand") + (plus:DI (match_operand:DI 1 "register_operand") + (match_operand:DI 2 "register_operand")))] + "" +{ + rtx_code_label *label = gen_label_rtx (); + rtx lo_dest, hi_dest, lo_op0, hi_op0, lo_op1, hi_op1; + lo_dest = gen_lowpart (SImode, operands[0]); + hi_dest = gen_highpart (SImode, operands[0]); + lo_op0 = gen_lowpart (SImode, operands[1]); + hi_op0 = gen_highpart (SImode, operands[1]); + lo_op1 = gen_lowpart (SImode, operands[2]); + hi_op1 = gen_highpart (SImode, operands[2]); + if (rtx_equal_p (lo_dest, lo_op1)) + FAIL; + emit_clobber (operands[0]); + emit_insn (gen_addsi3 (lo_dest, lo_op0, lo_op1)); + emit_insn (gen_addsi3 (hi_dest, hi_op0, hi_op1)); + emit_cmp_and_jump_insns (lo_dest, lo_op1, GEU, + const0_rtx, SImode, true, label); + emit_insn (gen_addsi3 (hi_dest, hi_dest, const1_rtx)); + emit_label (label); + DONE; +}) + (define_insn "addsf3" [(set (match_operand:SF 0 "register_operand" "=f") (plus:SF (match_operand:SF 1 "register_operand" "%f") @@ -237,6 +263,32 @@ (const_int 5) (const_int 6)))]) +(define_expand "subdi3" + [(set (match_operand:DI 0 "register_operand") + (minus:DI (match_operand:DI 1 "register_operand") + (match_operand:DI 2 "register_operand")))] + "" +{ + rtx_code_label *label = gen_label_rtx (); + rtx lo_dest, hi_dest, lo_op0, hi_op0, lo_op1, hi_op1; + lo_dest = gen_lowpart (SImode, operands[0]); + hi_dest = gen_highpart (SImode, operands[0]); + lo_op0 = gen_lowpart (SImode, operands[1]); + hi_op0 = gen_highpart (SImode, operands[1]); + lo_op1 = gen_lowpart (SImode, operands[2]); + hi_op1 = gen_highpart (SImode, operands[2]); + if (rtx_equal_p (lo_op0, lo_op1)) + FAIL; + emit_clobber (operands[0]); + emit_insn (gen_subsi3 (lo_dest, lo_op0, lo_op1)); + emit_insn (gen_subsi3 (hi_dest, hi_op0, hi_op1)); + emit_cmp_and_jump_insns (lo_op0, lo_op1, GEU, + const0_rtx, SImode, true, label); + emit_insn (gen_addsi3 (hi_dest, hi_dest, constm1_rtx)); + emit_label (label); + DONE; +}) + (define_insn "subsf3" [(set (match_operand:SF 0 "register_operand" "=f") (minus:SF (match_operand:SF 1 "register_operand" "f") From patchwork Tue May 30 09:26:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takayuki 'January June' Suwa X-Patchwork-Id: 70302 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2C08D385660A for ; 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Tue, 30 May 2023 09:27:07 +0000 Received: by smtphe5009.mail.kks.ynwp.yahoo.co.jp (YJ Hermes SMTP Server) with ESMTPA ID 6bc452069cfaf4935080d785fa79aad3; Tue, 30 May 2023 18:27:06 +0900 (JST) Message-ID: Date: Tue, 30 May 2023 18:26:45 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 To: GCC Patches Subject: [PATCH 3/3] xtensa: Optimize 'cstoresi4' insn pattern References: X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch introduces more optimized implementations for the 6 cstoresi4 insn comparison methods (eq/ne/lt/le/gt/ge, however, required TARGET_NSA for eq). gcc/ChangeLog: * config/xtensa/xtensa.cc (xtensa_expand_scc): Add dedicated optimization code for cstoresi4 (eq/ne/gt/ge/lt/le). * config/xtensa/xtensa.md (xtensa_ge_zero): Rename from '*signed_ge_zero', because it had to be called from 'xtensa_expand_scc()'. --- gcc/config/xtensa/xtensa.cc | 106 ++++++++++++++++++++++++++++++++---- gcc/config/xtensa/xtensa.md | 14 ++--- 2 files changed, 102 insertions(+), 18 deletions(-) diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc index 3b5d25b660a..64efd3d7287 100644 --- a/gcc/config/xtensa/xtensa.cc +++ b/gcc/config/xtensa/xtensa.cc @@ -991,24 +991,108 @@ xtensa_expand_conditional_move (rtx *operands, int isflt) int xtensa_expand_scc (rtx operands[4], machine_mode cmp_mode) { - rtx dest = operands[0]; - rtx cmp; - rtx one_tmp, zero_tmp; + rtx dest = operands[0], op0 = operands[2], op1 = operands[3]; + enum rtx_code code = GET_CODE (operands[1]); + rtx cmp, tmp0, tmp1; rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx); - if (!(cmp = gen_conditional_move (GET_CODE (operands[1]), cmp_mode, - operands[2], operands[3]))) - return 0; + /* Dedicated optimizations for cstoresi4. + a. In a magnitude comparison operator, swapping both sides and + inverting magnitude does not change the result, + eg. '(x >= y) != (y <= x)' is a constant of zero + (GE is changed to LE, not LT). + b. Due to room for further optimization, we use subtraction rather + than XOR (the default for RTL expansion of EQ/NE) as the binary + operation which is zero if both sides are the same and non-zero + otherwise. */ + if (cmp_mode == SImode) + switch (code) + { + /* EQ(op0, op1) := clz(op0 - op1) / 32 [requires TARGET_NSA] */ + case EQ: + if (!TARGET_NSA) + break; + /* EQ to EQZ conversion by subtracting op1 from op0. */ + emit_move_insn (dest, + expand_binop (SImode, sub_optab, op0, op1, + 0, 0, OPTAB_LIB_WIDEN)); + /* NSAU instruction will return 32 iff the source is zero, + zero through 31 otherwise (See Xtensa ISA Reference Manual, + p. 462) */ + emit_insn (gen_clzsi2 (dest, dest)); + emit_insn (gen_lshrsi3 (dest, dest, GEN_INT (5))); + return 1; + + /* NE(op0, op1) := (op0 - op1) == 0 ? 0 : 1 */ + case NE: + /* NE to NEZ conversion by subtracting op1 from op0. */ + emit_move_insn (tmp0 = gen_reg_rtx (SImode), + expand_binop (SImode, sub_optab, op0, op1, + 0, 0, OPTAB_LIB_WIDEN)); + emit_move_insn (dest, const_true_rtx); + emit_move_insn (dest, + gen_rtx_fmt_eee (IF_THEN_ELSE, SImode, + gen_rtx_fmt_ee (EQ, VOIDmode, + tmp0, const0_rtx), + tmp0, dest)); + return 1; + + case LE: + if (REG_P (op1)) + { + /* LE to GE conversion by swapping both sides. */ + tmp0 = op0, op0 = op1, op1 = tmp0; + goto case_GE_reg; + } + /* LE to LT conversion by adding one to op1. */ + op1 = GEN_INT (INTVAL (op1) + 1); + /* fallthru */ + + /* LT(op0, op1) := (unsigned)(op0 - op1) >> 31 */ + case LT: +case_LT: + /* LT to LTZ conversion by subtracting op1 from op0. */ + emit_move_insn (dest, + expand_binop (SImode, sub_optab, op0, op1, + 0, 0, OPTAB_LIB_WIDEN)); + emit_insn (gen_lshrsi3 (dest, dest, GEN_INT (31))); + return 1; + + case GE: + if (REG_P (op1)) + { +case_GE_reg: + /* GE to GEZ conversion by subtracting op1 from op0. */ + emit_move_insn (dest, + expand_binop (SImode, sub_optab, op0, op1, + 0, 0, OPTAB_LIB_WIDEN)); + /* Emitting the dedicated insn pattern. */ + emit_insn (gen_xtensa_ge_zero (dest, dest)); + return 1; + } + /* GE to GT conversion by subtracting one from op1. */ + op1 = GEN_INT (INTVAL (op1) - 1); + /* fallthru */ - one_tmp = gen_reg_rtx (SImode); - zero_tmp = gen_reg_rtx (SImode); - emit_insn (gen_movsi (one_tmp, const_true_rtx)); - emit_insn (gen_movsi (zero_tmp, const0_rtx)); + case GT: + /* GT to LT conversion by swapping both sides. */ + tmp0 = op0, op0 = op1, op1 = tmp0; + goto case_LT; + default: + break; + } + + if (! (cmp = gen_conditional_move (code, cmp_mode, op0, op1))) + return 0; + + tmp0 = force_reg (SImode, const0_rtx); + tmp1 = force_reg (SImode, const_true_rtx); gen_fn = (cmp_mode == SImode ? gen_movsicc_internal0 : gen_movsicc_internal1); - emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp)); + emit_insn (gen_fn (dest, XEXP (cmp, 0), tmp1, tmp0, cmp)); + return 1; } diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 7870fb0bfce..ebc305bd387 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -196,8 +196,8 @@ (match_operand:DI 2 "register_operand")))] "" { - rtx_code_label *label = gen_label_rtx (); rtx lo_dest, hi_dest, lo_op0, hi_op0, lo_op1, hi_op1; + rtx_code_label *label; lo_dest = gen_lowpart (SImode, operands[0]); hi_dest = gen_highpart (SImode, operands[0]); lo_op0 = gen_lowpart (SImode, operands[1]); @@ -209,8 +209,8 @@ emit_clobber (operands[0]); emit_insn (gen_addsi3 (lo_dest, lo_op0, lo_op1)); emit_insn (gen_addsi3 (hi_dest, hi_op0, hi_op1)); - emit_cmp_and_jump_insns (lo_dest, lo_op1, GEU, - const0_rtx, SImode, true, label); + emit_cmp_and_jump_insns (lo_dest, lo_op1, GEU, const0_rtx, + SImode, true, label = gen_label_rtx ()); emit_insn (gen_addsi3 (hi_dest, hi_dest, const1_rtx)); emit_label (label); DONE; @@ -269,8 +269,8 @@ (match_operand:DI 2 "register_operand")))] "" { - rtx_code_label *label = gen_label_rtx (); rtx lo_dest, hi_dest, lo_op0, hi_op0, lo_op1, hi_op1; + rtx_code_label *label; lo_dest = gen_lowpart (SImode, operands[0]); hi_dest = gen_highpart (SImode, operands[0]); lo_op0 = gen_lowpart (SImode, operands[1]); @@ -282,8 +282,8 @@ emit_clobber (operands[0]); emit_insn (gen_subsi3 (lo_dest, lo_op0, lo_op1)); emit_insn (gen_subsi3 (hi_dest, hi_op0, hi_op1)); - emit_cmp_and_jump_insns (lo_op0, lo_op1, GEU, - const0_rtx, SImode, true, label); + emit_cmp_and_jump_insns (lo_op0, lo_op1, GEU, const0_rtx, + SImode, true, label = gen_label_rtx ()); emit_insn (gen_addsi3 (hi_dest, hi_dest, constm1_rtx)); emit_label (label); DONE; @@ -3136,7 +3136,7 @@ (const_int 5) (const_int 6)))]) -(define_insn_and_split "*signed_ge_zero" +(define_insn_and_split "xtensa_ge_zero" [(set (match_operand:SI 0 "register_operand" "=a") (ge:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)))]