From patchwork Mon May 29 05:03:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 70203 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 878BB3858C31 for ; Mon, 29 May 2023 05:03:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 878BB3858C31 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685336634; bh=RffHZmBBt578A/5tIliBfLlHx213msvdPMetazu2AW4=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=YTDvDz3iX6xLeJcnCETMZzg++g5EgByEEE87vNyz9Zk5qJCwomAEzt3ky3am0Zv/R aiZaw14RD5RcEgl5gf4+GJc74cG4uzyfWFOK9tC4X8NwbLoT9igVq2JlkNVGLs/BVS EjQ88h0QIfvFXvwYGDR04KlY4/21E79Y/Ex2zqYw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 7327F3858CDA for ; Mon, 29 May 2023 05:03:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7327F3858CDA X-IronPort-AV: E=McAfee;i="6600,9927,10724"; a="418099711" X-IronPort-AV: E=Sophos;i="6.00,200,1681196400"; d="scan'208";a="418099711" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 May 2023 22:03:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10724"; a="818290994" X-IronPort-AV: E=Sophos;i="6.00,200,1681196400"; d="scan'208";a="818290994" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 28 May 2023 22:03:23 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 0FA511005674; Mon, 29 May 2023 13:03:23 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [committed 1/2] RISC-V: Fix ternary instruction attribute bug Date: Mon, 29 May 2023 13:03:20 +0800 Message-Id: <20230529050321.237236-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Juzhe-Zhong Fix bug of vector.md which generate incorrect information to VSETVL PASS when testing FMA auto vectorization ternop-3.c. Signed-off-by: Juzhe-Zhong gcc/ChangeLog: * config/riscv/vector.md: Fix vimuladd instruction bug. --- gcc/config/riscv/vector.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 15f66efaa48..cd696da5d89 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -388,7 +388,7 @@ (define_attr "avl_type" "" (symbol_ref "INTVAL (operands[7])")) (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\ - viwalu,viwmul,vnshift,vimuladd,vaalu,vsmul,vsshift,\ + viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\ vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\ vfsgnj,vfcmp,vfmuladd,vslideup,vslidedown,vislide1up,\ vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\ From patchwork Mon May 29 05:03:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 70204 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 629D23857729 for ; Mon, 29 May 2023 05:04:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 629D23857729 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685336692; bh=eFiA08SBccuwuEsrXuTSWfnJqcFS8fI92aDD53slA6c=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=iMEm/CMuL/Viyves3Y19MSjw2GNJfEIGzpAt9jix6sZ08VjEpCZ27+hbtmnXOgvln R1fqIld8b8OY/57YP+MWa+HeqoOewp4O82b/UFevvpRj/cbMjh3FhhSWclW1WbydoV +/ugnPkFHChmf/8KeJB31GpBVXNLEAJ998ngU3gc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 4C8A0385843E for ; Mon, 29 May 2023 05:03:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4C8A0385843E X-IronPort-AV: E=McAfee;i="6600,9927,10724"; a="418099720" X-IronPort-AV: E=Sophos;i="6.00,200,1681196400"; d="scan'208";a="418099720" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 May 2023 22:03:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10724"; a="818290997" X-IronPort-AV: E=Sophos;i="6.00,200,1681196400"; d="scan'208";a="818290997" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 28 May 2023 22:03:25 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 17F551005678; Mon, 29 May 2023 13:03:25 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [committed 2/2] RISC-V: Add RVV FMA auto-vectorization support Date: Mon, 29 May 2023 13:03:21 +0800 Message-Id: <20230529050321.237236-2-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529050321.237236-1-pan2.li@intel.com> References: <20230529050321.237236-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Juzhe-Zhong This patch support FMA auto-vectorization pattern. Let's RA decide vmacc or vmadd. Signed-off-by: Juzhe-Zhong gcc/ChangeLog: * config/riscv/autovec.md (fma4): New pattern. (*fma): Ditto. * config/riscv/riscv-protos.h (enum insn_type): New enum. (emit_vlmax_ternary_insn): New function. * config/riscv/riscv-v.cc (emit_vlmax_ternary_insn): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Add ternary tests * gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: New test. * gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: New test. * gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: New test. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: New test. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: New test. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: New test. --- gcc/config/riscv/autovec.md | 65 +++++++++++ gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv-v.cc | 20 ++++ .../riscv/rvv/autovec/ternop/ternop-1.c | 28 +++++ .../riscv/rvv/autovec/ternop/ternop-2.c | 34 ++++++ .../riscv/rvv/autovec/ternop/ternop-3.c | 33 ++++++ .../riscv/rvv/autovec/ternop/ternop_run-1.c | 84 ++++++++++++++ .../riscv/rvv/autovec/ternop/ternop_run-2.c | 104 ++++++++++++++++++ .../riscv/rvv/autovec/ternop/ternop_run-3.c | 104 ++++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 + 10 files changed, 476 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index b24867ae4d0..0314e7587d0 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -518,3 +518,68 @@ (define_expand "abs2" riscv_vector::RVV_UNOP_MU, ops); DONE; }) + +;; ========================================================================= +;; == Ternary arithmetic +;; ========================================================================= + +;; ------------------------------------------------------------------------- +;; ---- [INT] VMACC and VMADD +;; ------------------------------------------------------------------------- +;; Includes: +;; - vmacc +;; - vmadd +;; ------------------------------------------------------------------------- + +;; We can't expand FMA for the following reasons: +;; 1. Before RA, we don't know which multiply-add instruction is the ideal one. +;; The vmacc is the ideal instruction when operands[3] overlaps operands[0]. +;; The vmadd is the ideal instruction when operands[1|2] overlaps operands[0]. +;; 2. According to vector.md, the multiply-add patterns has 'merge' operand which +;; is the operands[5]. Since operands[5] should overlap operands[0], this operand +;; should be allocated the same regno as operands[1|2|3]. +;; 3. The 'merge' operand is always a real merge operand and we don't allow undefined +;; operand. +;; 4. The operation of FMA pattern needs VLMAX vsetlvi which needs a VL operand. +;; +;; In this situation, we design the codegen of FMA as follows: +;; 1. clobber a scratch in the expand pattern of FMA. +;; 2. Let's RA decide which input operand (operands[1|2|3]) overlap operands[0]. +;; 3. Generate instructions (vmacc or vmadd) according to the register allocation +;; result after reload_completed. +(define_expand "fma4" + [(parallel + [(set (match_operand:VI 0 "register_operand" "=vr") + (plus:VI + (mult:VI + (match_operand:VI 1 "register_operand" " vr") + (match_operand:VI 2 "register_operand" " vr")) + (match_operand:VI 3 "register_operand" " vr"))) + (clobber (match_scratch:SI 4))])] + "TARGET_VECTOR" + {}) + +(define_insn_and_split "*fma" + [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?&vr") + (plus:VI + (mult:VI + (match_operand:VI 1 "register_operand" " %0, vr, vr") + (match_operand:VI 2 "register_operand" " vr, vr, vr")) + (match_operand:VI 3 "register_operand" " vr, 0, vr"))) + (clobber (match_scratch:SI 4 "=r,r,r"))] + "TARGET_VECTOR" + "#" + "&& reload_completed" + [(const_int 0)] + { + PUT_MODE (operands[4], Pmode); + riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); + if (which_alternative == 2) + emit_insn (gen_rtx_SET (operands[0], operands[3])); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; + riscv_vector::emit_vlmax_ternary_insn (code_for_pred_mul_plus (mode), + riscv_vector::RVV_TERNOP, ops, operands[4]); + DONE; + } + [(set_attr "type" "vimuladd") + (set_attr "mode" "")]) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index c031354050d..0462f96c8d5 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -141,6 +141,7 @@ enum insn_type RVV_CMP_OP = 4, RVV_CMP_MU_OP = RVV_CMP_OP + 2, /* +2 means mask and maskoff operand. */ RVV_UNOP_MU = RVV_UNOP + 2, /* Likewise. */ + RVV_TERNOP = 5, }; enum vlmul_type { @@ -177,6 +178,7 @@ bool legitimize_move (rtx, rtx); void emit_vlmax_vsetvl (machine_mode, rtx); void emit_hard_vlmax_vsetvl (machine_mode, rtx); void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0); +void emit_vlmax_ternary_insn (unsigned, int, rtx *, rtx = 0); void emit_nonvlmax_insn (unsigned, int, rtx *, rtx); void emit_vlmax_merge_insn (unsigned, int, rtx *); void emit_vlmax_cmp_insn (unsigned, rtx *); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 6928c8d2797..a5715bb466c 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -362,6 +362,26 @@ emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, rtx vl) e.emit_insn ((enum insn_code) icode, ops); } +/* This function emits a {VLMAX, TAIL_ANY, MASK_ANY} vsetvli followed by the + * ternary operation which always has a real merge operand. */ +void +emit_vlmax_ternary_insn (unsigned icode, int op_num, rtx *ops, rtx vl) +{ + machine_mode dest_mode = GET_MODE (ops[0]); + machine_mode mask_mode = get_mask_mode (dest_mode).require (); + /* We have a maximum of 11 operands for RVV instruction patterns according to + * vector.md. */ + insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, + /*FULLY_UNMASKED_P*/ true, + /*USE_REAL_MERGE_P*/ true, /*HAS_AVL_P*/ true, + /*VLMAX_P*/ true, + /*DEST_MODE*/ dest_mode, /*MASK_MODE*/ mask_mode); + e.set_policy (TAIL_ANY); + e.set_policy (MASK_ANY); + e.set_vl (vl); + e.emit_insn ((enum insn_code) icode, ops); +} + /* This function emits a {NONVLMAX, TAIL_ANY, MASK_ANY} vsetvli followed by the * actual operation. */ void diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c new file mode 100644 index 00000000000..1996ca65108 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ + +#include + +#define TEST_TYPE(TYPE) \ + __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dst, \ + TYPE *__restrict a, \ + TYPE *__restrict b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] += a[i] * b[i]; \ + } + +#define TEST_ALL() \ + TEST_TYPE (int8_t) \ + TEST_TYPE (uint8_t) \ + TEST_TYPE (int16_t) \ + TEST_TYPE (uint16_t) \ + TEST_TYPE (int32_t) \ + TEST_TYPE (uint32_t) \ + TEST_TYPE (int64_t) \ + TEST_TYPE (uint64_t) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvmadd\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c new file mode 100644 index 00000000000..89eeaf6315f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ + +#include + +#define TEST_TYPE(TYPE) \ + __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dest1, \ + TYPE *__restrict dest2, \ + TYPE *__restrict dest3, \ + TYPE *__restrict src1, \ + TYPE *__restrict src2, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + dest1[i] += src1[i] * src2[i]; \ + dest2[i] += src1[i] * dest1[i]; \ + dest3[i] += src2[i] * dest2[i]; \ + } \ + } + +#define TEST_ALL() \ + TEST_TYPE (int8_t) \ + TEST_TYPE (uint8_t) \ + TEST_TYPE (int16_t) \ + TEST_TYPE (uint16_t) \ + TEST_TYPE (int32_t) \ + TEST_TYPE (uint32_t) \ + TEST_TYPE (int64_t) \ + TEST_TYPE (uint64_t) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvmacc\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c new file mode 100644 index 00000000000..127e701b187 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ + +#include + +#define TEST_TYPE(TYPE) \ + __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dest1, \ + TYPE *__restrict dest2, \ + TYPE *__restrict dest3, \ + TYPE *__restrict src1, \ + TYPE *__restrict src2, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + dest1[i] = src1[i] * src2[i] + dest2[i]; \ + dest2[i] += src1[i] * dest1[i]; \ + dest3[i] += src2[i] * dest2[i]; \ + } \ + } + +#define TEST_ALL() \ + TEST_TYPE (int8_t) \ + TEST_TYPE (uint8_t) \ + TEST_TYPE (int16_t) \ + TEST_TYPE (uint16_t) \ + TEST_TYPE (int32_t) \ + TEST_TYPE (uint32_t) \ + TEST_TYPE (int64_t) \ + TEST_TYPE (uint64_t) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvmv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c new file mode 100644 index 00000000000..1f69b694818 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c @@ -0,0 +1,84 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ + +#include "ternop-1.c" + +#define TEST_LOOP(TYPE, NUM) \ + { \ + TYPE array1_##NUM[NUM] = {}; \ + TYPE array2_##NUM[NUM] = {}; \ + TYPE array3_##NUM[NUM] = {}; \ + TYPE array4_##NUM[NUM] = {}; \ + for (int i = 0; i < NUM; ++i) \ + { \ + array1_##NUM[i] = (i & 1) + 5; \ + array2_##NUM[i] = i - NUM / 3; \ + array3_##NUM[i] = NUM - NUM / 3 - i; \ + array4_##NUM[i] = NUM - NUM / 3 - i; \ + asm volatile("" ::: "memory"); \ + } \ + ternop_##TYPE (array3_##NUM, array1_##NUM, array2_##NUM, NUM); \ + for (int i = 0; i < NUM; i++) \ + if (array3_##NUM[i] \ + != (TYPE) (array1_##NUM[i] * array2_##NUM[i] + array4_##NUM[i])) \ + __builtin_abort (); \ + } + +int __attribute__ ((optimize (0))) main () +{ + TEST_LOOP (int8_t, 7) + TEST_LOOP (uint8_t, 7) + TEST_LOOP (int16_t, 7) + TEST_LOOP (uint16_t, 7) + TEST_LOOP (int32_t, 7) + TEST_LOOP (uint32_t, 7) + TEST_LOOP (int64_t, 7) + TEST_LOOP (uint64_t, 7) + + TEST_LOOP (int8_t, 16) + TEST_LOOP (uint8_t, 16) + TEST_LOOP (int16_t, 16) + TEST_LOOP (uint16_t, 16) + TEST_LOOP (int32_t, 16) + TEST_LOOP (uint32_t, 16) + TEST_LOOP (int64_t, 16) + TEST_LOOP (uint64_t, 16) + + TEST_LOOP (int8_t, 77) + TEST_LOOP (uint8_t, 77) + TEST_LOOP (int16_t, 77) + TEST_LOOP (uint16_t, 77) + TEST_LOOP (int32_t, 77) + TEST_LOOP (uint32_t, 77) + TEST_LOOP (int64_t, 77) + TEST_LOOP (uint64_t, 77) + + TEST_LOOP (int8_t, 128) + TEST_LOOP (uint8_t, 128) + TEST_LOOP (int16_t, 128) + TEST_LOOP (uint16_t, 128) + TEST_LOOP (int32_t, 128) + TEST_LOOP (uint32_t, 128) + TEST_LOOP (int64_t, 128) + TEST_LOOP (uint64_t, 128) + + TEST_LOOP (int8_t, 15641) + TEST_LOOP (uint8_t, 15641) + TEST_LOOP (int16_t, 15641) + TEST_LOOP (uint16_t, 15641) + TEST_LOOP (int32_t, 15641) + TEST_LOOP (uint32_t, 15641) + TEST_LOOP (int64_t, 15641) + TEST_LOOP (uint64_t, 15641) + + TEST_LOOP (int8_t, 795) + TEST_LOOP (uint8_t, 795) + TEST_LOOP (int16_t, 795) + TEST_LOOP (uint16_t, 795) + TEST_LOOP (int32_t, 795) + TEST_LOOP (uint32_t, 795) + TEST_LOOP (int64_t, 795) + TEST_LOOP (uint64_t, 795) + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c new file mode 100644 index 00000000000..103b98acdf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c @@ -0,0 +1,104 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ + +#include "ternop-2.c" + +#define TEST_LOOP(TYPE, NUM) \ + { \ + TYPE array1_##NUM[NUM] = {}; \ + TYPE array2_##NUM[NUM] = {}; \ + TYPE array3_##NUM[NUM] = {}; \ + TYPE array4_##NUM[NUM] = {}; \ + TYPE array5_##NUM[NUM] = {}; \ + TYPE array6_##NUM[NUM] = {}; \ + TYPE array7_##NUM[NUM] = {}; \ + TYPE array8_##NUM[NUM] = {}; \ + for (int i = 0; i < NUM; ++i) \ + { \ + array1_##NUM[i] = (i & 1) + 5; \ + array2_##NUM[i] = i - NUM / 3; \ + array3_##NUM[i] = NUM - NUM / 3 - i; \ + array6_##NUM[i] = NUM - NUM / 3 - i; \ + array4_##NUM[i] = NUM - NUM / 2 + i; \ + array7_##NUM[i] = NUM - NUM / 2 + i; \ + array5_##NUM[i] = NUM + i * 7; \ + array8_##NUM[i] = NUM + i * 7; \ + asm volatile("" ::: "memory"); \ + } \ + ternop_##TYPE (array3_##NUM, array4_##NUM, array5_##NUM, array1_##NUM, \ + array2_##NUM, NUM); \ + for (int i = 0; i < NUM; i++) \ + { \ + array6_##NUM[i] \ + = (TYPE) (array1_##NUM[i] * array2_##NUM[i] + array6_##NUM[i]); \ + if (array3_##NUM[i] != array6_##NUM[i]) \ + __builtin_abort (); \ + array7_##NUM[i] \ + = (TYPE) (array1_##NUM[i] * array6_##NUM[i] + array7_##NUM[i]); \ + if (array4_##NUM[i] != array7_##NUM[i]) \ + __builtin_abort (); \ + array8_##NUM[i] \ + = (TYPE) (array2_##NUM[i] * array7_##NUM[i] + array8_##NUM[i]); \ + if (array5_##NUM[i] != array8_##NUM[i]) \ + __builtin_abort (); \ + } \ + } + +int __attribute__ ((optimize (0))) main () +{ + TEST_LOOP (int8_t, 7) + TEST_LOOP (uint8_t, 7) + TEST_LOOP (int16_t, 7) + TEST_LOOP (uint16_t, 7) + TEST_LOOP (int32_t, 7) + TEST_LOOP (uint32_t, 7) + TEST_LOOP (int64_t, 7) + TEST_LOOP (uint64_t, 7) + + TEST_LOOP (int8_t, 16) + TEST_LOOP (uint8_t, 16) + TEST_LOOP (int16_t, 16) + TEST_LOOP (uint16_t, 16) + TEST_LOOP (int32_t, 16) + TEST_LOOP (uint32_t, 16) + TEST_LOOP (int64_t, 16) + TEST_LOOP (uint64_t, 16) + + TEST_LOOP (int8_t, 77) + TEST_LOOP (uint8_t, 77) + TEST_LOOP (int16_t, 77) + TEST_LOOP (uint16_t, 77) + TEST_LOOP (int32_t, 77) + TEST_LOOP (uint32_t, 77) + TEST_LOOP (int64_t, 77) + TEST_LOOP (uint64_t, 77) + + TEST_LOOP (int8_t, 128) + TEST_LOOP (uint8_t, 128) + TEST_LOOP (int16_t, 128) + TEST_LOOP (uint16_t, 128) + TEST_LOOP (int32_t, 128) + TEST_LOOP (uint32_t, 128) + TEST_LOOP (int64_t, 128) + TEST_LOOP (uint64_t, 128) + + TEST_LOOP (int8_t, 15641) + TEST_LOOP (uint8_t, 15641) + TEST_LOOP (int16_t, 15641) + TEST_LOOP (uint16_t, 15641) + TEST_LOOP (int32_t, 15641) + TEST_LOOP (uint32_t, 15641) + TEST_LOOP (int64_t, 15641) + TEST_LOOP (uint64_t, 15641) + + TEST_LOOP (int8_t, 795) + TEST_LOOP (uint8_t, 795) + TEST_LOOP (int16_t, 795) + TEST_LOOP (uint16_t, 795) + TEST_LOOP (int32_t, 795) + TEST_LOOP (uint32_t, 795) + TEST_LOOP (int64_t, 795) + TEST_LOOP (uint64_t, 795) + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c new file mode 100644 index 00000000000..eac5408ce6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c @@ -0,0 +1,104 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ + +#include "ternop-3.c" + +#define TEST_LOOP(TYPE, NUM) \ + { \ + TYPE array1_##NUM[NUM] = {}; \ + TYPE array2_##NUM[NUM] = {}; \ + TYPE array3_##NUM[NUM] = {}; \ + TYPE array4_##NUM[NUM] = {}; \ + TYPE array5_##NUM[NUM] = {}; \ + TYPE array6_##NUM[NUM] = {}; \ + TYPE array7_##NUM[NUM] = {}; \ + TYPE array8_##NUM[NUM] = {}; \ + for (int i = 0; i < NUM; ++i) \ + { \ + array1_##NUM[i] = (i & 1) + 5; \ + array2_##NUM[i] = i - NUM / 3; \ + array3_##NUM[i] = NUM - NUM / 3 - i; \ + array6_##NUM[i] = NUM - NUM / 3 - i; \ + array4_##NUM[i] = NUM - NUM / 2 + i; \ + array7_##NUM[i] = NUM - NUM / 2 + i; \ + array5_##NUM[i] = NUM + i * 7; \ + array8_##NUM[i] = NUM + i * 7; \ + asm volatile("" ::: "memory"); \ + } \ + ternop_##TYPE (array3_##NUM, array4_##NUM, array5_##NUM, array1_##NUM, \ + array2_##NUM, NUM); \ + for (int i = 0; i < NUM; i++) \ + { \ + array6_##NUM[i] \ + = (TYPE) (array1_##NUM[i] * array2_##NUM[i] + array7_##NUM[i]); \ + if (array3_##NUM[i] != array6_##NUM[i]) \ + __builtin_abort (); \ + array7_##NUM[i] \ + = (TYPE) (array1_##NUM[i] * array6_##NUM[i] + array7_##NUM[i]); \ + if (array4_##NUM[i] != array7_##NUM[i]) \ + __builtin_abort (); \ + array8_##NUM[i] \ + = (TYPE) (array2_##NUM[i] * array7_##NUM[i] + array8_##NUM[i]); \ + if (array5_##NUM[i] != array8_##NUM[i]) \ + __builtin_abort (); \ + } \ + } + +int __attribute__ ((optimize (0))) main () +{ + TEST_LOOP (int8_t, 7) + TEST_LOOP (uint8_t, 7) + TEST_LOOP (int16_t, 7) + TEST_LOOP (uint16_t, 7) + TEST_LOOP (int32_t, 7) + TEST_LOOP (uint32_t, 7) + TEST_LOOP (int64_t, 7) + TEST_LOOP (uint64_t, 7) + + TEST_LOOP (int8_t, 16) + TEST_LOOP (uint8_t, 16) + TEST_LOOP (int16_t, 16) + TEST_LOOP (uint16_t, 16) + TEST_LOOP (int32_t, 16) + TEST_LOOP (uint32_t, 16) + TEST_LOOP (int64_t, 16) + TEST_LOOP (uint64_t, 16) + + TEST_LOOP (int8_t, 77) + TEST_LOOP (uint8_t, 77) + TEST_LOOP (int16_t, 77) + TEST_LOOP (uint16_t, 77) + TEST_LOOP (int32_t, 77) + TEST_LOOP (uint32_t, 77) + TEST_LOOP (int64_t, 77) + TEST_LOOP (uint64_t, 77) + + TEST_LOOP (int8_t, 128) + TEST_LOOP (uint8_t, 128) + TEST_LOOP (int16_t, 128) + TEST_LOOP (uint16_t, 128) + TEST_LOOP (int32_t, 128) + TEST_LOOP (uint32_t, 128) + TEST_LOOP (int64_t, 128) + TEST_LOOP (uint64_t, 128) + + TEST_LOOP (int8_t, 15641) + TEST_LOOP (uint8_t, 15641) + TEST_LOOP (int16_t, 15641) + TEST_LOOP (uint16_t, 15641) + TEST_LOOP (int32_t, 15641) + TEST_LOOP (uint32_t, 15641) + TEST_LOOP (int64_t, 15641) + TEST_LOOP (uint64_t, 15641) + + TEST_LOOP (int8_t, 795) + TEST_LOOP (uint8_t, 795) + TEST_LOOP (int16_t, 795) + TEST_LOOP (uint16_t, 795) + TEST_LOOP (int32_t, 795) + TEST_LOOP (uint32_t, 795) + TEST_LOOP (int64_t, 795) + TEST_LOOP (uint64_t, 795) + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index c0ab0dc0350..bf03570b9cc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -69,6 +69,8 @@ foreach op $AUTOVEC_TEST_OPTS { "" "$op" dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/unop/*.\[cS\]]] \ "" "$op" + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/ternop/*.\[cS\]]] \ + "" "$op" } # VLS-VLMAX tests