From patchwork Mon May 29 03:49:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 70200 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1030D385841D for ; Mon, 29 May 2023 03:49:44 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id 2E58D3858D32 for ; Mon, 29 May 2023 03:49:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2E58D3858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp86t1685332158t20gahbx Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 29 May 2023 11:49:17 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: y/6Sf3On8FuYOx8Cql2Zc4LKgVguJwxK5q8GoUefDN/80FtVRPzh72hztwGfp +Fv2Kp0KyAjxhbETNa/8+jEeHRidWihX6AambMigCtS/I6OCE2AT+RnJkPOGY3Sw1aeAP1z atWPzhCbwCzvwtCr+Yi9+PTd5qWyYbFdNBf1mGIVOVLhbU81Sfzx/5p3sP32N++yFuxYZ4K nKgb+bBvfMCgxJ+qcaAT7QEpOYnc66u4wlqogioso+XzSpR8M/aIG8I9s918odz51eQbHiw d9MHnV+804jxeCYurOWJQeq4n1YxB/Fsa32RvAuLbBCUs17aDvWihuR3qojt+mErOnGt4yn YrUAUvbTwgPHKlzi2jeu+yWRsQQwIC40RcUuTBNm0P6rM/SSSi5SI/xZGpACC59peq0Gjg7 berNvlzUczw= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5021235813801607266 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Add floating-point to integer conversion RVV auto-vectorization support Date: Mon, 29 May 2023 11:49:16 +0800 Message-Id: <20230529034916.4045904-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Juzhe-Zhong Even though we can't support floating-point operations which are depending on FRM yet, (for example vfadd support is blocked) since the RVV intrinsic doc is not updated and we can't support mode switching for this. We can support floating-point to integer conversion now since it's not depending on FRM and we don't need mode switching support for this ('rtz' conversions independent FRM). gcc/ChangeLog: * config/riscv/autovec.md (2): New pattern. * config/riscv/iterators.md: New attribute. * config/riscv/vector-iterators.md: New attribute. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: New test. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h: New test. --- gcc/config/riscv/autovec.md | 23 ++++++++ gcc/config/riscv/iterators.md | 4 +- gcc/config/riscv/vector-iterators.md | 5 ++ .../rvv/autovec/conversions/vfcvt_rtz-run.c | 52 +++++++++++++++++++ .../autovec/conversions/vfcvt_rtz-rv32gcv.c | 6 +++ .../autovec/conversions/vfcvt_rtz-rv64gcv.c | 6 +++ .../autovec/conversions/vfcvt_rtz-template.h | 15 ++++++ 7 files changed, 110 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index b24867ae4d0..3989ffb26ee 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -478,6 +478,29 @@ DONE; }) +;; ========================================================================= +;; == Conversions +;; ========================================================================= + +;; ------------------------------------------------------------------------- +;; ---- [INT<-FP] Conversions +;; ------------------------------------------------------------------------- +;; Includes: +;; - vfcvt.rtz.xu.f.v +;; - vfcvt.rtz.x.f.v +;; ------------------------------------------------------------------------- + +(define_expand "2" + [(set (match_operand: 0 "register_operand") + (any_fix: + (match_operand:VF 1 "register_operand")))] + "TARGET_VECTOR" +{ + insn_code icode = code_for_pred (, mode); + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands); + DONE; +}) + ;; ========================================================================= ;; == Unary arithmetic ;; ========================================================================= diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index 8afe98e4410..d374a10810c 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -225,7 +225,9 @@ (ss_minus "sssub") (us_minus "ussub") (sign_extend "extend") - (zero_extend "zero_extend")]) + (zero_extend "zero_extend") + (fix "fix_trunc") + (unsigned_fix "fixuns_trunc")]) ;; code attributes (define_code_attr or_optab [(ior "ior") diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 70fb5b80b1b..937ec3c7f67 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -1208,6 +1208,11 @@ (VNx1DF "VNx1DI") (VNx2DF "VNx2DI") (VNx4DF "VNx4DI") (VNx8DF "VNx8DI") (VNx16DF "VNx16DI") ]) +(define_mode_attr vconvert [ + (VNx1SF "vnx1si") (VNx2SF "vnx2si") (VNx4SF "vnx4si") (VNx8SF "vnx8si") (VNx16SF "vnx16si") (VNx32SF "vnx32si") + (VNx1DF "vnx1di") (VNx2DF "vnx2di") (VNx4DF "vnx4di") (VNx8DF "vnx8di") (VNx16DF "vnx16di") +]) + (define_mode_attr VNCONVERT [ (VNx1SF "VNx1HI") (VNx2SF "VNx2HI") (VNx4SF "VNx4HI") (VNx8SF "VNx8HI") (VNx16SF "VNx16HI") (VNx32SF "VNx32HI") (VNx1DI "VNx1SF") (VNx2DI "VNx2SF") (VNx4DI "VNx4SF") (VNx8DI "VNx8SF") (VNx16DI "VNx16SF") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c new file mode 100644 index 00000000000..b81814893dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c @@ -0,0 +1,52 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ + +#include "vfcvt_rtz-template.h" + +#define RUN(TYPE1, TYPE2, NUM) \ + TYPE1 src##TYPE1##TYPE2##NUM[NUM]; \ + TYPE2 dst##TYPE1##TYPE2##NUM[NUM]; \ + for (int i = 0; i < NUM; i++) \ + { \ + src##TYPE1##TYPE2##NUM[i] = i * 3.1315926 + 88932.947289; \ + } \ + vfcvt_##TYPE1##TYPE2 (dst##TYPE1##TYPE2##NUM, src##TYPE1##TYPE2##NUM, NUM); \ + for (int i = 0; i < NUM; i++) \ + if (dst##TYPE1##TYPE2##NUM[i] == (TYPE2) i) \ + __builtin_abort (); + +int +main () +{ + RUN (float, int32_t, 3) + RUN (float, int32_t, 4) + RUN (float, int32_t, 7) + RUN (float, int32_t, 99) + RUN (float, int32_t, 119) + RUN (float, int32_t, 128) + RUN (float, int32_t, 256) + RUN (float, int32_t, 279) + RUN (float, int32_t, 555) + RUN (float, int32_t, 1024) + RUN (float, int32_t, 1389) + RUN (float, int32_t, 2048) + RUN (float, int32_t, 3989) + RUN (float, int32_t, 4096) + RUN (float, int32_t, 5975) + + RUN (double, int64_t, 3) + RUN (double, int64_t, 4) + RUN (double, int64_t, 7) + RUN (double, int64_t, 99) + RUN (double, int64_t, 119) + RUN (double, int64_t, 128) + RUN (double, int64_t, 256) + RUN (double, int64_t, 279) + RUN (double, int64_t, 555) + RUN (double, int64_t, 1024) + RUN (double, int64_t, 1389) + RUN (double, int64_t, 2048) + RUN (double, int64_t, 3989) + RUN (double, int64_t, 4096) + RUN (double, int64_t, 5975) +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c new file mode 100644 index 00000000000..2f84631775f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ + +#include "vfcvt_rtz-template.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c new file mode 100644 index 00000000000..40e3e7a450d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable" } */ + +#include "vfcvt_rtz-template.h" + +/* { dg-final { scan-assembler-times {\tvfcvt\.rtz} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h new file mode 100644 index 00000000000..73bc1ad5591 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h @@ -0,0 +1,15 @@ +#include + +#define TEST(TYPE1, TYPE2) \ + __attribute__ ((noipa)) void vfcvt_##TYPE1##TYPE2 (TYPE2 *dst, TYPE1 *a, \ + int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = (TYPE1) a[i]; \ + } + +#define TEST_ALL() \ + TEST (float, int32_t) \ + TEST (double, int64_t) + +TEST_ALL ()