From patchwork Mon Apr 19 21:48:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 43053 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D46C43939C12; Mon, 19 Apr 2021 21:48:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D46C43939C12 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1618868902; bh=L8w7MMdYrpOlC08zviEtkGIinkBNY2qnt+qilIoabP4=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=akY/EolFpR9pvGTOIJ2l6a/67X3WrTIm8Ccdywex/xPkb8G/QhNUOVW7hMj7sm/pk zqCGWPy2os1FuamTLlmSLwLICOq2WIyNUe0uqPRplp46hy580jXruS/esB+Svo3QT2 UUuuhvvbEo4gnNbCUhh9Ia4fUzQnv7sg8NG+EFcM= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-qk1-x729.google.com (mail-qk1-x729.google.com [IPv6:2607:f8b0:4864:20::729]) by sourceware.org (Postfix) with ESMTPS id A36353857C60 for ; Mon, 19 Apr 2021 21:48:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org A36353857C60 Received: by mail-qk1-x729.google.com with SMTP id t17so8984022qkg.4 for ; Mon, 19 Apr 2021 14:48:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=L8w7MMdYrpOlC08zviEtkGIinkBNY2qnt+qilIoabP4=; b=fdLMfgtRQs1QgO4pX45Yx/ulRh/dFTiHfYrp8EuhBfj7rK5/ZAoxPRbZReEZjDQXhA TfYRnMGMMQJU6Y1+Ew9shbqh/QuErBYDgAY6xBFhplQ1/VwWAlwIGnyoIW4Ly+NAtllS KNgBiRNvVQozCHWLelCUxr6H98rejeaxmF7vsry+Wj9B1cefWHmt5v7TY/jfITVnH1Sc 81f/sZDgSXgIO8IN822AZugD45bcB1IBI7TV5GW+Jh+Vp3gHiMgEnsYfQNBasAlT4jEA WJPNoS+U7vSAP17jtPy8RRHWhzVAs9L+OqQcUa/mxSK2rnIWpqTwKxhod1IJV/zrCGlo Bbuw== X-Gm-Message-State: AOAM5324OtUEbSBSXR70mR3w+dbLq6/h/dnsoQkFFvqfSOfXurim//bI FG7+Tsl2XOk4LCfqThqa+hPWA8gRqL0= X-Google-Smtp-Source: ABdhPJy1nuD0/H/Z66ADsj5n0dxDMLd/yFj7QVO/0oKxZvl8znkggKOeRAhqB1wY5w9UYZNI5dvVjw== X-Received: by 2002:a37:6004:: with SMTP id u4mr14300313qkb.369.1618868899017; Mon, 19 Apr 2021 14:48:19 -0700 (PDT) Received: from localhost.localdomain (pool-71-245-178-39.pitbpa.fios.verizon.net. [71.245.178.39]) by smtp.googlemail.com with ESMTPSA id r5sm9905578qtp.75.2021.04.19.14.48.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 14:48:18 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH v5 1/2] x86: Optimize less_vec evex and avx512 memset-vec-unaligned-erms.S Date: Mon, 19 Apr 2021 17:48:10 -0400 Message-Id: <20210419214811.2852085-1-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" No bug. This commit adds optimized cased for less_vec memset case that uses the avx512vl/avx512bw mask store avoiding the excessive branches. test-memset and test-wmemset are passing. Signed-off-by: Noah Goldstein --- sysdeps/x86_64/multiarch/ifunc-impl-list.c | 40 ++++++++++----- sysdeps/x86_64/multiarch/ifunc-memset.h | 6 ++- .../multiarch/memset-avx512-unaligned-erms.S | 2 +- .../multiarch/memset-evex-unaligned-erms.S | 2 +- .../multiarch/memset-vec-unaligned-erms.S | 51 +++++++++++++++---- 5 files changed, 74 insertions(+), 27 deletions(-) diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c index 0b0927b124..c377cab629 100644 --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c @@ -204,19 +204,23 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, __memset_chk_avx2_unaligned_erms_rtm) IFUNC_IMPL_ADD (array, i, __memset_chk, (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW)), + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), __memset_chk_evex_unaligned) IFUNC_IMPL_ADD (array, i, __memset_chk, (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW)), + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), __memset_chk_evex_unaligned_erms) IFUNC_IMPL_ADD (array, i, __memset_chk, (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW)), + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), __memset_chk_avx512_unaligned_erms) IFUNC_IMPL_ADD (array, i, __memset_chk, (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW)), + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), __memset_chk_avx512_unaligned) IFUNC_IMPL_ADD (array, i, __memset_chk, CPU_FEATURE_USABLE (AVX512F), @@ -247,19 +251,23 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, __memset_avx2_unaligned_erms_rtm) IFUNC_IMPL_ADD (array, i, memset, (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW)), + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), __memset_evex_unaligned) IFUNC_IMPL_ADD (array, i, memset, (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW)), + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), __memset_evex_unaligned_erms) IFUNC_IMPL_ADD (array, i, memset, (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW)), + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), __memset_avx512_unaligned_erms) IFUNC_IMPL_ADD (array, i, memset, (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW)), + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), __memset_avx512_unaligned) IFUNC_IMPL_ADD (array, i, memset, CPU_FEATURE_USABLE (AVX512F), @@ -728,10 +736,14 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, && CPU_FEATURE_USABLE (RTM)), __wmemset_avx2_unaligned_rtm) IFUNC_IMPL_ADD (array, i, wmemset, - CPU_FEATURE_USABLE (AVX512VL), + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), __wmemset_evex_unaligned) IFUNC_IMPL_ADD (array, i, wmemset, - CPU_FEATURE_USABLE (AVX512VL), + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), __wmemset_avx512_unaligned)) #ifdef SHARED @@ -935,10 +947,14 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, CPU_FEATURE_USABLE (AVX2), __wmemset_chk_avx2_unaligned) IFUNC_IMPL_ADD (array, i, __wmemset_chk, - CPU_FEATURE_USABLE (AVX512VL), + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), __wmemset_chk_evex_unaligned) IFUNC_IMPL_ADD (array, i, __wmemset_chk, - CPU_FEATURE_USABLE (AVX512F), + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), __wmemset_chk_avx512_unaligned)) #endif diff --git a/sysdeps/x86_64/multiarch/ifunc-memset.h b/sysdeps/x86_64/multiarch/ifunc-memset.h index 502f946a84..eda5640541 100644 --- a/sysdeps/x86_64/multiarch/ifunc-memset.h +++ b/sysdeps/x86_64/multiarch/ifunc-memset.h @@ -54,7 +54,8 @@ IFUNC_SELECTOR (void) && !CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_AVX512)) { if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL) - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW)) + && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW) + && CPU_FEATURE_USABLE_P (cpu_features, BMI2)) { if (CPU_FEATURE_USABLE_P (cpu_features, ERMS)) return OPTIMIZE (avx512_unaligned_erms); @@ -68,7 +69,8 @@ IFUNC_SELECTOR (void) if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)) { if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL) - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW)) + && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW) + && CPU_FEATURE_USABLE_P (cpu_features, BMI2)) { if (CPU_FEATURE_USABLE_P (cpu_features, ERMS)) return OPTIMIZE (evex_unaligned_erms); diff --git a/sysdeps/x86_64/multiarch/memset-avx512-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-avx512-unaligned-erms.S index 22e7b187c8..8ad842fc2f 100644 --- a/sysdeps/x86_64/multiarch/memset-avx512-unaligned-erms.S +++ b/sysdeps/x86_64/multiarch/memset-avx512-unaligned-erms.S @@ -19,6 +19,6 @@ # define SECTION(p) p##.evex512 # define MEMSET_SYMBOL(p,s) p##_avx512_##s # define WMEMSET_SYMBOL(p,s) p##_avx512_##s - +# define USE_LESS_VEC_MASK_STORE 1 # include "memset-vec-unaligned-erms.S" #endif diff --git a/sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S index ae0a4d6e46..640f092903 100644 --- a/sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S +++ b/sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S @@ -19,6 +19,6 @@ # define SECTION(p) p##.evex # define MEMSET_SYMBOL(p,s) p##_evex_##s # define WMEMSET_SYMBOL(p,s) p##_evex_##s - +# define USE_LESS_VEC_MASK_STORE 1 # include "memset-vec-unaligned-erms.S" #endif diff --git a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S index 584747f1a1..08cfa49bd1 100644 --- a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S +++ b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S @@ -63,6 +63,8 @@ # endif #endif +#define PAGE_SIZE 4096 + #ifndef SECTION # error SECTION is not defined! #endif @@ -213,11 +215,38 @@ L(loop): cmpq %rcx, %rdx jne L(loop) VZEROUPPER_SHORT_RETURN + + .p2align 4 L(less_vec): /* Less than 1 VEC. */ # if VEC_SIZE != 16 && VEC_SIZE != 32 && VEC_SIZE != 64 # error Unsupported VEC_SIZE! # endif +# ifdef USE_LESS_VEC_MASK_STORE + /* Clear high bits from edi. Only keeping bits relevant to page + cross check. Note that we are using rax which is set in + MEMSET_VDUP_TO_VEC0_AND_SET_RETURN as ptr from here on out. + */ + andl $(PAGE_SIZE - 1), %edi + /* Check if VEC_SIZE store cross page. Mask stores suffer serious + performance degradation when it has to fault supress. */ + cmpl $(PAGE_SIZE - VEC_SIZE), %edi + ja L(cross_page) +# if VEC_SIZE > 32 + movq $-1, %rcx + bzhiq %rdx, %rcx, %rcx + kmovq %rcx, %k1 +# else + movl $-1, %ecx + bzhil %edx, %ecx, %ecx + kmovd %ecx, %k1 +# endif + vmovdqu8 %VEC(0), (%rax) {%k1} + VZEROUPPER_RETURN + + .p2align 4 +L(cross_page): +# endif # if VEC_SIZE > 32 cmpb $32, %dl jae L(between_32_63) @@ -234,36 +263,36 @@ L(less_vec): cmpb $1, %dl ja L(between_2_3) jb 1f - movb %cl, (%rdi) + movb %cl, (%rax) 1: VZEROUPPER_RETURN # if VEC_SIZE > 32 /* From 32 to 63. No branch when size == 32. */ L(between_32_63): - VMOVU %YMM0, -32(%rdi,%rdx) - VMOVU %YMM0, (%rdi) + VMOVU %YMM0, -32(%rax,%rdx) + VMOVU %YMM0, (%rax) VZEROUPPER_RETURN # endif # if VEC_SIZE > 16 /* From 16 to 31. No branch when size == 16. */ L(between_16_31): - VMOVU %XMM0, -16(%rdi,%rdx) - VMOVU %XMM0, (%rdi) + VMOVU %XMM0, -16(%rax,%rdx) + VMOVU %XMM0, (%rax) VZEROUPPER_RETURN # endif /* From 8 to 15. No branch when size == 8. */ L(between_8_15): - movq %rcx, -8(%rdi,%rdx) - movq %rcx, (%rdi) + movq %rcx, -8(%rax,%rdx) + movq %rcx, (%rax) VZEROUPPER_RETURN L(between_4_7): /* From 4 to 7. No branch when size == 4. */ - movl %ecx, -4(%rdi,%rdx) - movl %ecx, (%rdi) + movl %ecx, -4(%rax,%rdx) + movl %ecx, (%rax) VZEROUPPER_RETURN L(between_2_3): /* From 2 to 3. No branch when size == 2. */ - movw %cx, -2(%rdi,%rdx) - movw %cx, (%rdi) + movw %cx, -2(%rax,%rdx) + movw %cx, (%rax) VZEROUPPER_RETURN END (MEMSET_SYMBOL (__memset, unaligned_erms)) From patchwork Mon Apr 19 21:48:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 43054 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6825D3891C35; Mon, 19 Apr 2021 21:48:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6825D3891C35 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1618868904; bh=l8KD1Dg/i15zQMa9KC/JlAIgnqMBAQMlbAeTENg6zUg=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=ih195ONP/BQjqO6r9yKN21v81/YhdxVtlbrekAiLu3ams/Z1/0WuHpxuZsIrUDtzX jasdzjNbQ92Hr6OeKR/b9ms/qKhtPGv8MhPp/k6JIrslTOGjI1U1hU085zetAknKSX 44R4ozbAyKyswjXRKp0ksDfUfBSGHGIJFmQELMII= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-qk1-x732.google.com (mail-qk1-x732.google.com [IPv6:2607:f8b0:4864:20::732]) by sourceware.org (Postfix) with ESMTPS id 478EA3851C0B for ; Mon, 19 Apr 2021 21:48:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 478EA3851C0B Received: by mail-qk1-x732.google.com with SMTP id h13so18766992qka.2 for ; Mon, 19 Apr 2021 14:48:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l8KD1Dg/i15zQMa9KC/JlAIgnqMBAQMlbAeTENg6zUg=; b=JNFJ7UGcNZJsq081aErh7hKoEUDPRCMBoe0NgPViPp4P+pjVfZnDpxOVLFra7FSUMh 3ljNlPJyD/O34H4OPY5wOTaj3wO0o4y4NNkV0hAP33It6TZxWXfBcCnC5KFs4eZQfJfX zfafnXUfdQIhZPPge110NYEUZD+QxVOfVGl36WkXfruW3tdg23A6SjFpVWHk+u7oxFzp Cqdod3CltAvFzr93P6hMrIay3qA02c8qgszNQZkhx2ZokIPkfyzbwno28LsTTyk6L/g8 e1/ed1Q+/gfhglWlSVLInErs5Z3MZ6nzxLAf8SWIXHpeSTQgZk361osNgBQH8gOLcGg4 2VRw== X-Gm-Message-State: AOAM5319yfAuaKwf1vATHW/fS553HLl11ZLqhE7Q+v+JvkBFHQDQsgZI 8WAGwIYLopq6sTq3Osx2JG0OWXPCL6M= X-Google-Smtp-Source: ABdhPJzbenFbh1VaMzXafLgN+9ZDhmFl1vqz3XTJTYMZvtDEOBxoW9O52kgh6jmFHEWvKn5GBne1Gg== X-Received: by 2002:a37:9586:: with SMTP id x128mr13747318qkd.61.1618868900779; Mon, 19 Apr 2021 14:48:20 -0700 (PDT) Received: from localhost.localdomain (pool-71-245-178-39.pitbpa.fios.verizon.net. [71.245.178.39]) by smtp.googlemail.com with ESMTPSA id r5sm9905578qtp.75.2021.04.19.14.48.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 14:48:20 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH v5 2/2] x86: Expand test-memset.c and bench-memset.c Date: Mon, 19 Apr 2021 17:48:11 -0400 Message-Id: <20210419214811.2852085-2-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210419214811.2852085-1-goldstein.w.n@gmail.com> References: <20210419214811.2852085-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" No bug. This commit adds tests cases and benchmarks for page cross and for memset to the end of the page without crossing. As well in test-memset.c this commit adds sentinel on start/end of tstbuf to test for overwrites Signed-off-by: Noah Goldstein --- benchtests/bench-memset.c | 6 ++++-- string/test-memset.c | 20 +++++++++++++++----- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/benchtests/bench-memset.c b/benchtests/bench-memset.c index 1174900e88..d6619b4836 100644 --- a/benchtests/bench-memset.c +++ b/benchtests/bench-memset.c @@ -61,7 +61,7 @@ do_one_test (json_ctx_t *json_ctx, impl_t *impl, CHAR *s, static void do_test (json_ctx_t *json_ctx, size_t align, int c, size_t len) { - align &= 63; + align &= 4095; if ((align + len) * sizeof (CHAR) > page_size) return; @@ -110,9 +110,11 @@ test_main (void) { for (i = 0; i < 18; ++i) do_test (&json_ctx, 0, c, 1 << i); - for (i = 1; i < 32; ++i) + for (i = 1; i < 64; ++i) { do_test (&json_ctx, i, c, i); + do_test (&json_ctx, 4096 - i, c, i); + do_test (&json_ctx, 4095, c, i); if (i & (i - 1)) do_test (&json_ctx, 0, c, i); } diff --git a/string/test-memset.c b/string/test-memset.c index eb71517390..82bfcd6ad4 100644 --- a/string/test-memset.c +++ b/string/test-memset.c @@ -109,16 +109,24 @@ SIMPLE_MEMSET (CHAR *s, int c, size_t n) static void do_one_test (impl_t *impl, CHAR *s, int c __attribute ((unused)), size_t n) { - CHAR tstbuf[n]; + CHAR buf[n + 2]; + CHAR *tstbuf = buf + 1; + CHAR sentinel = c - 1; + buf[0] = sentinel; + buf[n + 1] = sentinel; #ifdef TEST_BZERO simple_bzero (tstbuf, n); CALL (impl, s, n); - if (memcmp (s, tstbuf, n) != 0) + if (memcmp (s, tstbuf, n) != 0 + || buf[0] != sentinel + || buf[n + 1] != sentinel) #else CHAR *res = CALL (impl, s, c, n); if (res != s || SIMPLE_MEMSET (tstbuf, c, n) != tstbuf - || MEMCMP (s, tstbuf, n) != 0) + || MEMCMP (s, tstbuf, n) != 0 + || buf[0] != sentinel + || buf[n + 1] != sentinel) #endif /* !TEST_BZERO */ { error (0, 0, "Wrong result in function %s", impl->name); @@ -130,7 +138,7 @@ do_one_test (impl_t *impl, CHAR *s, int c __attribute ((unused)), size_t n) static void do_test (size_t align, int c, size_t len) { - align &= 7; + align &= 4095; if ((align + len) * sizeof (CHAR) > page_size) return; @@ -245,9 +253,11 @@ test_main (void) { for (i = 0; i < 18; ++i) do_test (0, c, 1 << i); - for (i = 1; i < 32; ++i) + for (i = 1; i < 64; ++i) { do_test (i, c, i); + do_test (4096 - i, c, i); + do_test (4095, c, i); if (i & (i - 1)) do_test (0, c, i); }