From patchwork Fri May 26 03:01:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 70111 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4B5793857437 for ; Fri, 26 May 2023 03:01:43 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id F21C33858D39 for ; Fri, 26 May 2023 03:01:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F21C33858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1685070069tn4fm0ay Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 26 May 2023 11:01:08 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: CR3LFp2JE4mOllc7DrjAKKtWxI4bpokG6o5+k+Sc0o4nfaih8BlYkXyMC7YMT SamoqIhMpaIMfTKvvE8SvniWuYAZH84bqi783s3tF66wRuzenq0a28SkCQjAo/+Uz2btYrq KRD0ot98khCRddwtCO2EoF1c3TnHnui8YHZDJkzU1aO68ndj40ulsL9M0EdWR8vN3GYZnyL 2SK72+7ACy7zWp+zkADiFdeLQIQZ65TP+4LI+iDG98wHPha8R7VmFCd0FZDpQaZhRYJVRny DpNGMJR5VZ8AP4aND1qT3xQhgD6TvNubPjuSx8/uvgRbijRMA5uPZHZGLILd9eqe7z0Utie /0qNQ8YzH9vMmtnRr0yiLn70GxCpPGnqFdUzJ2y+841LPVtEL7ruI4cKanXVJ+EqvSprs03 MLHVVRgYOLU= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 1847569887317658485 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, pan2.li@intel.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization Date: Fri, 26 May 2023 11:01:07 +0800 Message-Id: <20230526030107.2567706-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Juzhe-Zhong Fix bug reported here: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109974 PR target/109974 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (source_equal_p): Fix ICE. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/pr109974.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 30 ++++++++++++++++++- .../gcc.target/riscv/rvv/vsetvl/pr109974.c | 17 +++++++++++ 2 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 9847d649d1d..fe55f4ccd30 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -1138,7 +1138,35 @@ source_equal_p (insn_info *insn1, insn_info *insn2) return false; if (!rtx_equal_p (SET_SRC (single_set1), SET_SRC (single_set2))) return false; - gcc_assert (insn1->uses ().size () == insn2->uses ().size ()); + /* RTL_SSA uses include REG_NOTE. Consider this following case: + + insn1 RTL: + (insn 41 39 42 4 (set (reg:DI 26 s10 [orig:159 loop_len_46 ] [159]) + (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201]) + (reg:DI 14 a4 [276]))) 408 {*umindi3} + (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201]) + (const_int 2 [0x2])) + (nil))) + The RTL_SSA uses of this instruction has 2 uses: + 1. (reg:DI 15 a5 [orig:201 _149 ] [201]) - twice. + 2. (reg:DI 14 a4 [276]) - once. + + insn2 RTL: + (insn 38 353 351 4 (set (reg:DI 27 s11 [orig:160 loop_len_47 ] [160]) + (umin:DI (reg:DI 15 a5 [orig:199 _146 ] [199]) + (reg:DI 14 a4 [276]))) 408 {*umindi3} + (expr_list:REG_EQUAL (umin:DI (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200]) + (const_int 2 [0x2])) + (nil))) + The RTL_SSA uses of this instruction has 3 uses: + 1. (reg:DI 15 a5 [orig:199 _146 ] [199]) - once + 2. (reg:DI 14 a4 [276]) - once + 3. (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200]) - once + + Return false when insn1->uses ().size () != insn2->uses ().size () + */ + if (insn1->uses ().size () != insn2->uses ().size ()) + return false; for (size_t i = 0; i < insn1->uses ().size (); i++) if (insn1->uses ()[i] != insn2->uses ()[i]) return false; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c new file mode 100644 index 00000000000..06a8562ebab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zbb -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3" } */ + +#include + +void +func (int8_t *__restrict x, int64_t *__restrict y, int n) +{ + for (int i = 0, j = 0; i < n; i++, j +=2 ) + { + x[i + 0] += 1; + y[j + 0] += 1; + y[j + 1] += 2; + } +} + +/* { dg-final { scan-assembler {vsetvli} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */