From patchwork Thu May 25 17:09:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georg-Johann Lay X-Patchwork-Id: 70096 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9F7163857722 for ; Thu, 25 May 2023 17:10:10 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mo4-p00-ob.smtp.rzone.de (mo4-p00-ob.smtp.rzone.de [85.215.255.20]) by sourceware.org (Postfix) with ESMTPS id 681733858D37 for ; Thu, 25 May 2023 17:09:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 681733858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=gjlay.de Authentication-Results: sourceware.org; spf=none smtp.mailfrom=gjlay.de ARC-Seal: i=1; a=rsa-sha256; t=1685034585; cv=none; d=strato.com; s=strato-dkim-0002; b=I7+Lvalfzz4+ypjBTrIYvmgapqKKIVyKiFxvpZCkGV9no56VyNojmn17OLWtOWXdya lBXIMDqFSbidHcEjgSykfJbUZQZ6mcJhMbiZWWQboBaDrooYjQMoWKPwd6QFugYCvt+T 9syb2+TNzId+UBLvqFAb9IVk+mQgLNUWYMbt1VR1g0DN1heOjAciHMao4X9jWNlP3LGZ KP1fHlvUPCB811px/ptweSlkppDeaEyBsVPwz113stqmVhF09XexBPBLUFWpt/9V/fL1 0DFMA4eIScw8xL9UlKEJ7fT8gg8edznrZL1iuO/EqKr1MlccfDYnw5832tJ6chwqmz8S 1fZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; t=1685034585; s=strato-dkim-0002; d=strato.com; h=Subject:From:To:Date:Message-ID:Cc:Date:From:Subject:Sender; bh=pQf0DgV1VGT1JNNK9X86jM8ZnsRZ2XfDuo9Ylx87P5E=; b=rBVpzNMY0r2qQDoQrmsHDgwdgC8iAxuF6I0cCNr/rHv9fvH1gZss88cl0dyOps37KK ZIHgCWQDyf7ZjTI1H0MUcnz9cfPdxYjMyq24K+jXR2dQj+IpN7SiEjineAOX7SJdAbYa k3oNp8fCnhjG6qpfRkVuRfdzGNoAY/ztx51rdZCv+cXKES3XX4bMzC9ofkmjYWLC5RBc qMWC+douxg/6jAdKcqI8d7A+JbJZACI/5IR3txorL0bmBSWpVsfPinn+nComBa8igVvu 6cPYHI6ij2jeI4mAG9ULrSr39R0V323E6wLj4Jw2sigKZRx2cILk3lWgKG/SzT+lPieA MovQ== ARC-Authentication-Results: i=1; strato.com; arc=none; dkim=none X-RZG-CLASS-ID: mo00 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1685034585; s=strato-dkim-0002; d=gjlay.de; h=Subject:From:To:Date:Message-ID:Cc:Date:From:Subject:Sender; bh=pQf0DgV1VGT1JNNK9X86jM8ZnsRZ2XfDuo9Ylx87P5E=; b=J5pFwmo8jK0GK5J83mhTQrWmi9NdA3vAfZJ8Gxw+bTyQcPV8jEPurJ3W6env0J0yMc OkDkeBU1w1Pk9sDDIeLBpSncJRaY4ctcwvTHvxVTnEkPw5lSVxF+pvySOD41TaUxgr7U w8Xc+KjuI+qawenIVwZkHaXYUSg54XZDUm5wlTp0B82/LGlMRc5A1Dp1fk3yd11/9F7A R02fFZkY9GB9No0o+vta5zKuAN1LXfecSVUuDMlDqC+m2kokDMSV77UjBn51ccxfGyDa spIcDvHFK6Zl8qSr99Iagk5c+SHsOp5o2UYDSmkEpu9+1TxfD1vXcK2Tm1UgxffbA8mq F1lg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; t=1685034585; s=strato-dkim-0003; d=gjlay.de; h=Subject:From:To:Date:Message-ID:Cc:Date:From:Subject:Sender; bh=pQf0DgV1VGT1JNNK9X86jM8ZnsRZ2XfDuo9Ylx87P5E=; b=kXQJGu6HHgIOHTn0eQLXEX++02jpc/ysifOwx7XJLA2TCDyBzRUyr8cnY2zitNFWE1 JeF95gynbpkAVuv7U7Cg== X-RZG-AUTH: ":LXoWVUeid/7A29J/hMvvT3koxZnKT7Qq0xotTetVnKkRmM69o2y+LiO3MutATA==" Received: from [192.168.2.102] by smtp.strato.de (RZmta 49.4.0 DYNA|AUTH) with ESMTPSA id z691f1z4PH9juOb (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate) for ; Thu, 25 May 2023 19:09:45 +0200 (CEST) Message-ID: <943d7018-5b82-00d3-8451-93f830049cb7@gjlay.de> Date: Thu, 25 May 2023 19:09:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Content-Language: en-US To: gcc-patches@gcc.gnu.org From: Georg-Johann Lay Subject: [avr,committed] PR82931: Improve single-bit transfers between registers. X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Applied this patch that makes one insn more generic so it can handle more bit positions than just 0. Johann --- target/82931: Make a pattern more generic to match more bit-transfers. There is already a pattern in avr.md that matches single-bit transfers from one register to another one, but it only handled bit 0 of 8-bit registers. This change makes that pattern more generic so it matches more of similar single-bit transfers. gcc/ PR target/82931 * config/avr/avr.md (*movbitqi.0): Rename to *movbit.0-6. Handle any bit position and use mode QISI. * config/avr/avr.cc (avr_rtx_costs_1) [IOR]: Return a cost of 2 insns for bit-transfer of respective style. gcc/testsuite/ PR target/82931 * gcc.target/avr/pr82931.c: New test. diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index 4fa6f5309b2..31706964eb1 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -10843,6 +10843,15 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code, *total += COSTS_N_INSNS (1); return true; } + if (IOR == code + && AND == GET_CODE (XEXP (x, 0)) + && AND == GET_CODE (XEXP (x, 1)) + && single_zero_operand (XEXP (XEXP (x, 0), 1), mode)) + { + // Open-coded bit transfer. + *total = COSTS_N_INSNS (2); + return true; + } *total = COSTS_N_INSNS (GET_MODE_SIZE (mode)); *total += avr_operand_rtx_cost (XEXP (x, 0), mode, code, 0, speed); if (!CONST_INT_P (XEXP (x, 1))) diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index a79c6824fad..371965938a6 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -9096,16 +9096,20 @@ (define_insn "*movbitqi.1-6.b" "bst %3,0\;bld %0,%4" [(set_attr "length" "2")]) -;; Move bit $3.0 into bit $0.0. -;; For bit 0, combiner generates slightly different pattern. -(define_insn "*movbitqi.0" - [(set (match_operand:QI 0 "register_operand" "=r") - (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0") - (match_operand:QI 2 "single_zero_operand" "n")) - (and:QI (match_operand:QI 3 "register_operand" "r") - (const_int 1))))] - "0 == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))" - "bst %3,0\;bld %0,0" +;; Move bit $3.x into bit $0.x. +(define_insn "*movbit.0-6" + [(set (match_operand:QISI 0 "register_operand" "=r") + (ior:QISI (and:QISI (match_operand:QISI 1 "register_operand" "0") + (match_operand:QISI 2 "single_zero_operand" "n")) + (and:QISI (match_operand:QISI 3 "register_operand" "r") + (match_operand:QISI 4 "single_one_operand" "n"))))] + "GET_MODE_MASK(mode) + == (GET_MODE_MASK(mode) & (INTVAL(operands[2]) ^ INTVAL(operands[4])))" + { + auto bitmask = GET_MODE_MASK (mode) & UINTVAL (operands[4]); + operands[4] = GEN_INT (exact_log2 (bitmask)); + return "bst %T3%T4" CR_TAB "bld %T0%T4"; + } [(set_attr "length" "2")]) ;; Move bit $2.0 into bit $0.7. diff --git a/gcc/testsuite/gcc.target/avr/pr82931.c b/gcc/testsuite/gcc.target/avr/pr82931.c new file mode 100644 index 00000000000..477284fa127 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr82931.c @@ -0,0 +1,29 @@ +/* { dg-options "-Os" } */ +/* { dg-final { scan-assembler-times "bst" 4 } } */ +/* { dg-final { scan-assembler-times "bld" 4 } } */ + +typedef __UINT8_TYPE__ uint8_t; +typedef __UINT16_TYPE__ uint16_t; + +#define BitMask (1u << 14) +#define Bit8Mask ((uint8_t) (1u << 4)) + +void merge1_8 (uint8_t *dst, const uint8_t *src) +{ + *dst = (*src & Bit8Mask) | (*dst & ~ Bit8Mask); +} + +void merge2_8 (uint8_t *dst, const uint8_t *src) +{ + *dst ^= (*dst ^ *src) & Bit8Mask; +} + +void merge1_16 (uint16_t *dst, const uint16_t *src) +{ + *dst = (*src & BitMask) | (*dst & ~ BitMask); +} + +void merge2_16 (uint16_t *dst, const uint16_t *src) +{ + *dst ^= (*dst ^ *src) & BitMask; +}