From patchwork Thu May 11 22:28:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 69183 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 69D943853576 for ; Thu, 11 May 2023 22:31:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id 40A313857027 for ; Thu, 11 May 2023 22:31:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 40A313857027 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1ab0c697c84so71049845ad.3 for ; Thu, 11 May 2023 15:31:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1683844297; x=1686436297; h=to:from:cc:content-transfer-encoding:mime-version:message-id:date :subject:from:to:cc:subject:date:message-id:reply-to; bh=dYXMT0m/LssqNVcXCFabquHzL5Q7FXD/2qO0BwZ+yms=; b=FLToj8u4Ua+lagE5WFSs/GrIepaPLw9sBUOPz5fwFMcIPEH5EnC+w3OmOkSU0u54Kg OhXUy7kNXyxIRxu1CiB9j88shPUF34ZhFVpy0FqtA/jG7/M2Ikm5SLHRgWDMgrK8W4rT 9l0mwwkLU5CWx/rRW9SOKHbvCZmG8ZPwVUWxZeVv4UeFr1iNUcR6hifeYPsROgZRUipO lV2XcYXVU6FplKCHuhT9OEKoD0erAbLAouJ1o+T/wdHep7QQfsou+e3Yx4ndwsYuXFsz bfoELhaspxu2CyGtNysrri6UIizv0NibvrpyeHuk0cjQexQzqGVBTTDTjxekSSTE+1wb h7dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683844297; x=1686436297; h=to:from:cc:content-transfer-encoding:mime-version:message-id:date :subject:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=dYXMT0m/LssqNVcXCFabquHzL5Q7FXD/2qO0BwZ+yms=; b=BkiGrLeFkG6q3jxPdx6/8eg8wZ1sNtrWZ2QGLYn7EYzuxuEsB8uBUmfM/Hew7p6YTo 5Psvmtf+A3cHdJZpI+qP/bAR3QSP5eGcwIA7TpHjhPrSVnxEFvcmiGvW+7jWeTpNbTNn aiUfuv/DYpNaeNAj7t9yrrc1laJVE15OUPPZCJRKVMBU8jADjoMDBYBfjKiVTFQbiUDV 7W6GwL0X+/646c5hfbfyiCh5reHx/W77BhP8Qwpmz7t0XPoJgelDny5V/XGEtYD0xLRN hYsZgPHWARItRFJK17ZKjkQ0L73N+3bFskOwyNweCeH3l+cUJxYUzdMS8qyzOnmOsV0v 7C1A== X-Gm-Message-State: AC+VfDyyEMNL+8eyhIgfq0c1QOv9Zi3ah7TDeHeKDxvbKzSayv6Ew/79 OFlqSgUVzr8Q/o8k5yB2EoWEAR5Wq2AeWS288yY= X-Google-Smtp-Source: ACHHUZ5d0S+ODDE9zJr1+R8XguA6AO2KXedrVedGHP5XdGv6sTBMfyvHGlxl+dlRTEsaOFhpGVVo1Q== X-Received: by 2002:a17:903:1d0:b0:1a6:7c83:e28e with SMTP id e16-20020a17090301d000b001a67c83e28emr23570498plh.68.1683844297185; Thu, 11 May 2023 15:31:37 -0700 (PDT) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id io12-20020a17090312cc00b001a64851087bsm6428686plb.272.2023.05.11.15.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 15:31:36 -0700 (PDT) Subject: [PATCH v2] RISC-V: Add vector_scalar_shift_operand Date: Thu, 11 May 2023 15:28:49 -0700 Message-Id: <20230511222848.15044-1-palmer@rivosinc.com> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 Cc: Palmer Dabbelt From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The vector shift immediates happen to have the same constraints as some of the CSR-related operands, but it's a different usage. This adds a name for them, so I don't get confused again next time. gcc/ChangeLog: * config/riscv/autovec.md (shifts): Use vector_scalar_shift_operand. * config/riscv/predicates.md (vector_scalar_shift_operand): New predicate. --- Still haven't built-tested it, my box is busy. Changes since v1 <20230511182555.26183-1-palmer@rivosinc.com>: * Change the name to "vector_scalar_shift_operand", as per Juzhe's suggestion. * Add a missing second ";" in the comment. --- gcc/config/riscv/autovec.md | 2 +- gcc/config/riscv/predicates.md | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index ac0c939d277..4561fcbe957 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -132,7 +132,7 @@ (define_expand "3" [(set (match_operand:VI 0 "register_operand") (any_shift:VI (match_operand:VI 1 "register_operand") - (match_operand: 2 "csr_operand")))] + (match_operand: 2 "vector_scalar_shift_operand")))] "TARGET_VECTOR" { if (!CONST_SCALAR_INT_P (operands[2])) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index e5adf06fa25..90e6f942c97 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -43,6 +43,11 @@ (define_predicate "csr_operand" (ior (match_operand 0 "const_csr_operand") (match_operand 0 "register_operand"))) +;; V has 32-bit unsigned immediates. This happens to be the same constraint as +;; the csr_operand, but it's not CSR related. +(define_predicate "vector_scalar_shift_operand" + (match_operand 0 "csr_operand")) + (define_predicate "sle_operand" (and (match_code "const_int") (match_test "SMALL_OPERAND (INTVAL (op) + 1)")))