From patchwork Thu May 11 18:25:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 69176 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8B1CE38560B8 for ; Thu, 11 May 2023 18:27:21 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by sourceware.org (Postfix) with ESMTPS id B45183858D1E for ; Thu, 11 May 2023 18:27:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B45183858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1a50cb65c92so64434165ad.0 for ; Thu, 11 May 2023 11:27:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1683829625; x=1686421625; h=to:from:cc:content-transfer-encoding:mime-version:message-id:date :subject:from:to:cc:subject:date:message-id:reply-to; bh=h7Fc2fqUkvyWPOVFTs4000teBebtCnVCEteZg52wHtc=; b=telQF+/TZnUd4tQi2s6zRBFlUmmuFLM+LiQbM6BK835V6gpehKVnZhMJUyXFZz7M+i uwIGaI/muV5wNe7vnTw9SUX9zfCX4qSym0/4gcESxJzf8hbQjv7c3k8UTrzIbBNpxUPL 6SIr4Dxw1aY6vGu45zhmt5ZDfc/2pgj882wiERH/MYk88ZLourTJgMaHMpBsCRLxwFCt Pcb+h/SBSpDHc+XdjCE+cQqT8jpB18V7CsCO8/HYIPKLS/eZ9cGP3DAYSIvIhG+dOklE OaaHK3TYwjxJbcc3OCZ4aJxjlJ12APCXfFYabEbzRBQkk0ji+X0N+cVvDW2klQJJ61lQ Cg/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683829625; x=1686421625; h=to:from:cc:content-transfer-encoding:mime-version:message-id:date :subject:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=h7Fc2fqUkvyWPOVFTs4000teBebtCnVCEteZg52wHtc=; b=ZemuhZkSKGeIQSvdu13J6xyU4bpHAVWILhy18XNnQDR/QBViP5HB7z+yuPY1itmbll 5rQbJsi7LhD7fU+QF1hTbXEDh58TbteuXzemabH/CAwKAzdUrBmGCdq5RcHCRTFiE70x 7ecU+Nu8fvNr6azhUbLmSSDN0BHJtpmZHdHr+CnVZYBYL7TOw8b/oz8UxxS7F1ulbu2c VWZDMQy09+5uv1fLN3CdYN3mOw/Q5VXO4rJsbuotgNrilfjb2dpJ0RRrefPOMDU+NQwr 0muMVUQY/spwuOTft9VbC2CfYcSQTofP/jB516Apw9dgL07Wvs3GaBiaqzuxdDHNRq0u XZBg== X-Gm-Message-State: AC+VfDznzOVhcSeK1ZNX0Co8leQLNsj54hNeeeYkn1GdXsh4ldrRzAT2 b3R79S2pN9OnYx9SyvwjpgjMiA== X-Google-Smtp-Source: ACHHUZ499G7Uq8Had6Q0MtqtOORmJX5QAUHiRLVKyB/LW6b4AS7GVKDQ7yT23RJmz3Aot85GEw47KQ== X-Received: by 2002:a17:903:48e:b0:1a2:a904:c438 with SMTP id jj14-20020a170903048e00b001a2a904c438mr21815448plb.58.1683829624602; Thu, 11 May 2023 11:27:04 -0700 (PDT) Received: from localhost ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id f12-20020a170902860c00b001ac6293577fsm6252617plo.110.2023.05.11.11.27.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 11:27:04 -0700 (PDT) Subject: [PATCH] RISC-V: Add v_uimm_operand Date: Thu, 11 May 2023 11:25:56 -0700 Message-Id: <20230511182555.26183-1-palmer@rivosinc.com> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 Cc: Palmer Dabbelt From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The vector shift immediates happen to have the same constraints as some of the CSR-related operands, but it's a different usage. This adds a name for them, so I don't get confused again next time. gcc/ChangeLog: * config/riscv/autovec.md (shifts): Use v_uimm_operand. * config/riscv/predicates.md (v_uimm_operand): New predicate. --- I haven't even build tested this one, I just saw it when reviewing some patch and figured I'd send it along. --- gcc/config/riscv/autovec.md | 2 +- gcc/config/riscv/predicates.md | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index ac0c939d277..daad51abbc2 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -132,7 +132,7 @@ (define_expand "3" [(set (match_operand:VI 0 "register_operand") (any_shift:VI (match_operand:VI 1 "register_operand") - (match_operand: 2 "csr_operand")))] + (match_operand: 2 "v_uimm_operand")))] "TARGET_VECTOR" { if (!CONST_SCALAR_INT_P (operands[2])) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index e5adf06fa25..62007d6c6e3 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -43,6 +43,11 @@ (define_predicate "csr_operand" (ior (match_operand 0 "const_csr_operand") (match_operand 0 "register_operand"))) +;; V has 32-bit unsigned immediates. This happens to be the same constraint as +; the csr_operand, but it's not CSR related. +(define_predicate "v_uimm_operand" + (match_operand 0 "csr_operand")) + (define_predicate "sle_operand" (and (match_code "const_int") (match_test "SMALL_OPERAND (INTVAL (op) + 1)")))