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([2601:681:8600:13d0::99f]) by smtp.gmail.com with ESMTPSA id n7-20020a6546c7000000b0051b7bcb6162sm3352588pgr.81.2023.05.06.12.52.57 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 06 May 2023 12:52:57 -0700 (PDT) Message-ID: Date: Sat, 6 May 2023 13:52:56 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Content-Language: en-US To: "gcc-patches@gcc.gnu.org" Subject: [committed] Partial revert of recent changes X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jeff Law via Gcc-patches From: Jeff Law Reply-To: Jeff Law Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" It turns out a couple of bits submitted by Michael had already been pushed to the trunk. These two patches removes the duplicated bits. Jeff commit b9b7981f3d6919518372daf4c7e8c40dfc58f49d Author: Jeff Law Date: Sat May 6 11:36:37 2023 -0600 Remove duplicated definition in risc-v vector support. gcc/ * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Remove duplicate definition. commit 4c05f966a098744db9fa1e73074d7c08ace446fd Author: Jeff Law Date: Sat May 6 13:28:33 2023 -0600 Delete duplicated riscv definition. gcc/ * config/riscv/riscv-v.cc (riscv_vector_preferred_simd_mode): Delete. diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 9d699d455b0..8c7f3206771 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -190,44 +190,6 @@ autovec_use_vlmax_p (void) || riscv_autovec_preference == RVV_FIXED_VLMAX); } -/* Return the vectorization machine mode for RVV according to LMUL. */ -machine_mode -riscv_vector_preferred_simd_mode (scalar_mode mode) -{ - /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128 && - riscv_autovec_lmul < RVV_M2. Since GCC loop vectorizer report ICE - when we enable -march=rv64gc_zve32* and -march=rv32gc_zve64*. - in the 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since we have - VNx1SImode in -march=*zve32* and VNx1DImode in -march=*zve64*, they are - enabled in targetm. vector_mode_supported_p and SLP vectorizer will try to - use them. Currently, we can support auto-vectorization in - -march=rv32_zve32x_zvl128b. Wheras, -march=rv32_zve32x_zvl32b or - -march=rv32_zve32x_zvl64b are disabled. */ - if (autovec_use_vlmax_p ()) - { - /* If TARGET_MIN_VLEN < 128, we don't allow LMUL < 2 - auto-vectorization since Loop Vectorizer may use VNx1SImode or - VNx1DImode to vectorize which will create ICE in the - 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. */ - if (TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2) - return word_mode; - /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and - riscv_autovec_lmul as multiply factor to calculate the the NUNITS to - get the auto-vectorization mode. */ - poly_uint64 nunits; - poly_uint64 vector_size - = BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul); - poly_uint64 scalar_size = GET_MODE_SIZE (mode); - gcc_assert (multiple_p (vector_size, scalar_size, &nunits)); - machine_mode rvv_mode; - if (get_vector_mode (mode, nunits).exists (&rvv_mode)) - return rvv_mode; - } - /* TODO: We will support minimum length VLS auto-vectorization in the future. - */ - return word_mode; -} - /* Emit an RVV unmask && vl mov from SRC to DEST. */ static void emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len, diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 6f8b4abf46d..9d699d455b0 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1015,17 +1015,6 @@ expand_tuple_move (machine_mode mask_mode, rtx *ops) } } -/* SCALABLE means that the vector-length is agnostic (run-time invariant and - compile-time unknown). FIXED meands that the vector-length is specific - (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing - auto-vectorization using VLMAX vsetvl configuration. */ -static bool -autovec_use_vlmax_p (void) -{ - return riscv_autovec_preference == RVV_SCALABLE - || riscv_autovec_preference == RVV_FIXED_VLMAX; -} - /* Return the vectorization machine mode for RVV according to LMUL. */ machine_mode preferred_simd_mode (scalar_mode mode)