From patchwork Thu Apr 6 15:36:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 67470 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A7EDA3857721 for ; Thu, 6 Apr 2023 15:37:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A7EDA3857721 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1680795424; bh=c7bO01MNUdiS2i/gEnEx9UFQeew5bjbCyGmuRGZ0h2Q=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=twbwiwXWRpRu19TlUbUj0KLHflgYTzDuQwxo3kjYd9vwtjqLZQxOsTbiDyXYomHpG lrOpO4uKGausuBMAGKzCMD5Q2vdXH65lTycTcMQLJIhdVVKrHmx/1ltVp9B0lfIJgx gm9FUsaS/ft7jlvnDW4xGmau7DRfh57fvlWJmoP8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 63DA23858D28 for ; Thu, 6 Apr 2023 15:36:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 63DA23858D28 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 157C9169E; Thu, 6 Apr 2023 08:37:19 -0700 (PDT) Received: from e126323.cambridge.arm.com (unknown [10.2.78.76]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6A5463F762; Thu, 6 Apr 2023 08:36:34 -0700 (PDT) To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [committed] arm: mve: fix auto-inc generation [PR107674] Date: Thu, 6 Apr 2023 16:36:20 +0100 Message-Id: <20230406153620.931820-1-rearnsha@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-15.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Earnshaw via Gcc-patches From: Richard Earnshaw Reply-To: Richard Earnshaw Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" My change r13-416-g485a0ae0982abe caused the compiler to stop generating auto-inc operations on mve loads and stores. The fix is to check whether there is a replacement register available when in strict mode and the register is still a pseudo. gcc: PR target/107674 * config/arm/arm.cc (arm_effective_regno): New function. (mve_vector_mem_operand): Use it. --- gcc/config/arm/arm.cc | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index a46627bc375..bf7ff9a9704 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -13639,6 +13639,19 @@ arm_coproc_mem_operand_no_writeback (rtx op) return arm_coproc_mem_operand_wb (op, 0); } +/* In non-STRICT mode, return the register number; in STRICT mode return + the hard regno or the replacement if it won't be a mem. Otherwise, return + the original pseudo number. */ +static int +arm_effective_regno (rtx op, bool strict) +{ + gcc_assert (REG_P (op)); + if (!strict || REGNO (op) < FIRST_PSEUDO_REGISTER + || !reg_renumber || reg_renumber[REGNO (op)] < 0) + return REGNO (op); + return reg_renumber[REGNO (op)]; +} + /* This function returns TRUE on matching mode and op. 1. For given modes, check for [Rn], return TRUE for Rn <= LO_REGS. 2. For other modes, check for [Rn], return TRUE for Rn < R15 (expect R13). */ @@ -13651,7 +13664,7 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict) /* Match: (mem (reg)). */ if (REG_P (op)) { - int reg_no = REGNO (op); + reg_no = arm_effective_regno (op, strict); return (((mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode) ? reg_no <= LAST_LO_REGNUM : reg_no < LAST_ARM_REGNUM) @@ -13662,7 +13675,7 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict) if (code == POST_INC || code == PRE_DEC || code == PRE_INC || code == POST_DEC) { - reg_no = REGNO (XEXP (op, 0)); + reg_no = arm_effective_regno (XEXP (op, 0), strict); return (((mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode) ? reg_no <= LAST_LO_REGNUM :(reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM)) @@ -13678,7 +13691,7 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict) || (reload_completed && code == PLUS && REG_P (XEXP (op, 0)) && GET_CODE (XEXP (op, 1)) == CONST_INT)) { - reg_no = REGNO (XEXP (op, 0)); + reg_no = arm_effective_regno (XEXP (op, 0), strict); if (code == PLUS) val = INTVAL (XEXP (op, 1)); else