From patchwork Mon Apr 3 10:21:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Schwab X-Patchwork-Id: 67207 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B6709385840A for ; Mon, 3 Apr 2023 10:22:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B6709385840A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680517326; bh=q6vrXVWaVt2hAYtOREEGiNThWBcBbPlCAP5bmvQ4JbU=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=q9XdblpqWfkILZfdy7iYR3jylhWn9+yIPBNqFYF1BCTOL7voTLXki6d9Yy0mhaw/e a46uuEqDXkQlZSaIKDD0L4W0bAI6Tq3CIUT1DupNO53BIH3tmzKgaEmKmxiX26lKQk ERfvhrNiAJJx+f6tDiAhpTMmBXy1Kg3ogjsRe0SY= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from smtp-out2.suse.de (smtp-out2.suse.de [IPv6:2001:67c:2178:6::1d]) by sourceware.org (Postfix) with ESMTPS id 33DE63858C5E for ; Mon, 3 Apr 2023 10:21:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 33DE63858C5E Received: from relay2.suse.de (relay2.suse.de [149.44.160.134]) by smtp-out2.suse.de (Postfix) with ESMTP id 3E1231FD8C for ; Mon, 3 Apr 2023 10:21:42 +0000 (UTC) Received: from hawking.suse.de (unknown [10.168.4.11]) by relay2.suse.de (Postfix) with ESMTP id 348BE2C14F for ; Mon, 3 Apr 2023 10:21:42 +0000 (UTC) Received: by hawking.suse.de (Postfix, from userid 17005) id 27E494A04C4; Mon, 3 Apr 2023 12:21:42 +0200 (CEST) To: libc-alpha@sourceware.org Subject: [PATCH] x86/dl-cacheinfo: remove unsused parameter from handle_amd X-Yow: Today, THREE WINOS from DETROIT sold me a framed photo of TAB HUNTER before his MAKEOVER! Date: Mon, 03 Apr 2023 12:21:42 +0200 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andreas Schwab via Libc-alpha From: Andreas Schwab Reply-To: Andreas Schwab Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" --- sysdeps/x86/dl-cacheinfo.h | 66 +++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 36 deletions(-) Reviewed-by: Adhemerval Zanella diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h index ab671487da..7e53d146ca 100644 --- a/sysdeps/x86/dl-cacheinfo.h +++ b/sysdeps/x86/dl-cacheinfo.h @@ -311,7 +311,7 @@ handle_intel (int name, const struct cpu_features *cpu_features) static long int __attribute__ ((noinline)) -handle_amd (int name, const struct cpu_features *cpu_features) +handle_amd (int name) { unsigned int eax; unsigned int ebx; @@ -334,24 +334,23 @@ handle_amd (int name, const struct cpu_features *cpu_features) switch (name) { - case _SC_LEVEL1_ICACHE_ASSOC: - case _SC_LEVEL1_DCACHE_ASSOC: - case _SC_LEVEL2_CACHE_ASSOC: - case _SC_LEVEL3_CACHE_ASSOC: - return ecx?((ebx >> 22) & 0x3ff) + 1 : 0; - case _SC_LEVEL1_ICACHE_LINESIZE: - case _SC_LEVEL1_DCACHE_LINESIZE: - case _SC_LEVEL2_CACHE_LINESIZE: - case _SC_LEVEL3_CACHE_LINESIZE: - return ecx?(ebx & 0xfff) + 1 : 0; - case _SC_LEVEL1_ICACHE_SIZE: - case _SC_LEVEL1_DCACHE_SIZE: - case _SC_LEVEL2_CACHE_SIZE: - case _SC_LEVEL3_CACHE_SIZE: - return ecx?(((ebx >> 22) & 0x3ff) + 1)*((ebx & 0xfff) + 1)\ - *(ecx + 1):0; - default: - assert (! "cannot happen"); + case _SC_LEVEL1_ICACHE_ASSOC: + case _SC_LEVEL1_DCACHE_ASSOC: + case _SC_LEVEL2_CACHE_ASSOC: + case _SC_LEVEL3_CACHE_ASSOC: + return ecx ? ((ebx >> 22) & 0x3ff) + 1 : 0; + case _SC_LEVEL1_ICACHE_LINESIZE: + case _SC_LEVEL1_DCACHE_LINESIZE: + case _SC_LEVEL2_CACHE_LINESIZE: + case _SC_LEVEL3_CACHE_LINESIZE: + return ecx ? (ebx & 0xfff) + 1 : 0; + case _SC_LEVEL1_ICACHE_SIZE: + case _SC_LEVEL1_DCACHE_SIZE: + case _SC_LEVEL2_CACHE_SIZE: + case _SC_LEVEL3_CACHE_SIZE: + return ecx ? (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1): 0; + default: + assert (! "cannot happen"); } return -1; } @@ -697,30 +696,25 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) } else if (cpu_features->basic.kind == arch_kind_amd) { - data = handle_amd (_SC_LEVEL1_DCACHE_SIZE, cpu_features); - core = handle_amd (_SC_LEVEL2_CACHE_SIZE, cpu_features); - shared = handle_amd (_SC_LEVEL3_CACHE_SIZE, cpu_features); + data = handle_amd (_SC_LEVEL1_DCACHE_SIZE); + core = handle_amd (_SC_LEVEL2_CACHE_SIZE); + shared = handle_amd (_SC_LEVEL3_CACHE_SIZE); - level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE, cpu_features); - level1_icache_linesize - = handle_amd (_SC_LEVEL1_ICACHE_LINESIZE, cpu_features); + level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE); + level1_icache_linesize = handle_amd (_SC_LEVEL1_ICACHE_LINESIZE); level1_dcache_size = data; - level1_dcache_assoc - = handle_amd (_SC_LEVEL1_DCACHE_ASSOC, cpu_features); - level1_dcache_linesize - = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE, cpu_features); + level1_dcache_assoc = handle_amd (_SC_LEVEL1_DCACHE_ASSOC); + level1_dcache_linesize = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE); level2_cache_size = core; - level2_cache_assoc = handle_amd (_SC_LEVEL2_CACHE_ASSOC, cpu_features); - level2_cache_linesize - = handle_amd (_SC_LEVEL2_CACHE_LINESIZE, cpu_features); + level2_cache_assoc = handle_amd (_SC_LEVEL2_CACHE_ASSOC); + level2_cache_linesize = handle_amd (_SC_LEVEL2_CACHE_LINESIZE); level3_cache_size = shared; - level3_cache_assoc = handle_amd (_SC_LEVEL3_CACHE_ASSOC, cpu_features); - level3_cache_linesize - = handle_amd (_SC_LEVEL3_CACHE_LINESIZE, cpu_features); + level3_cache_assoc = handle_amd (_SC_LEVEL3_CACHE_ASSOC); + level3_cache_linesize = handle_amd (_SC_LEVEL3_CACHE_LINESIZE); if (shared <= 0) /* No shared L3 cache. All we have is the L2 cache. */ - shared = core; + shared = core; } cpu_features->level1_icache_size = level1_icache_size;